Chip stacking structure, electronic equipment and preparation method of chip stacking structure
By setting up electronic devices in the chip stack structure and using a hybrid bonding structure for electrical connection, the problems of low space utilization and resource waste of die are solved, and efficient space utilization and low power consumption are achieved.
Patent Information
- Application Number
- CN202310955207.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-31
- Publication Date
- 2025-02-14
AI Technical Summary
In the existing chip stacking structure, the gap between the dies causes low space utilization, and the stress during Cu filling during bonding processing leads to warping of the wafer, which wastes a lot of resources.
The gap area and virtual contact pad structure are fully utilized by providing electronic devices, such as capacitors, within the gap between the dies and using a hybrid bonding structure to electrically connect the electronic devices to the circuit structure.
This improves the space utilization of the chip stack structure, achieves a 3D chip architecture with higher bandwidth and lower power consumption, while avoiding the problems of resource waste and wafer warping.
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Figure CN119447125A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a chip stacking structure, an electronic device, and a method for preparing the chip stacking structure. Background Art
[0002] As the demand for computing power for high-speed data communications and artificial intelligence surges, chip integration is further improved, and three-dimensional stacking technology of multi-layer chips is widely adopted.
[0003] Figure 1 A chip on wafer stack (CoW) structure is given as an example, and two chips 2 are integrated on a wafer. Figure 1 In the CoW stacking structure, the gaps between chips result in low space utilization.
[0004] In addition, if Figure 1 As shown, both chips 2 can be integrated on the wafer using bonding technology. In order to balance the stress when filling Cu during the bonding process and avoid wafer warping, the additional processing of Cu between the two chips also causes a certain degree of resource waste. Summary of the invention
[0005] The present application provides a chip stacking structure, an electronic device and a method for preparing the chip stacking structure, with the purpose of fully utilizing the gap area between dies and fully utilizing the idle virtual contact pad structure located in the gap between the dies.
[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:
[0007] On the one hand, the present application provides a chip stacking structure, which is a multi-chip module packaging structure.
[0008] The bare chip packaging structure may include: a circuit structure, at least two bare chips integrated on the circuit structure, for example, including a first bare chip and a second bare chip; the first bare chip and the second bare chip are arranged side by side on the same side of the circuit structure; an electronic device is arranged in the gap between the first bare chip and the second bare chip, and the electronic device is electrically connected to the circuit structure through a first bonding structure; the first bonding structure includes at least one first contact pad and at least one second contact pad arranged face to face, and the first contact pad and the second contact pad are electrically connected.
[0009] In the chip stacking structure provided in the present application, there will be a gap between the first bare chip and the second bare chip integrated on the circuit structure. One or more electronic devices, such as passive devices, can be arranged in the gap. The passive device can be at least one of a capacitor, a resistor, an inductor, etc. In this way, the gap area can be fully utilized to improve the space utilization of the bare chip packaging structure; and the electronic device and the circuit structure are interconnected through a bonding structure located at the interface between the electronic device and the circuit structure, thereby fully utilizing the idle virtual contact pad structure located at the gap between the bare chips.
[0010] In one achievable manner, the first contact pad and the second contact pad are bonded to form a hybrid bonding structure.
[0011] By utilizing the hybrid bonding structure, heterogeneous integration of chips of different sizes can be achieved, providing a 3D chip architecture with higher bandwidth and lower power consumption.
[0012] In one achievable manner, at least one first contact pad is disposed in the first dielectric layer; at least one second contact pad is disposed in the second dielectric layer; and the first dielectric layer and the second dielectric layer are bonded to each other at their opposite surfaces.
[0013] In the hybrid bonding structure, in addition to the contact pads bonding to each other, other non-conductive parts at the interface can also be bonded. In the hybrid bonding structure, there is no gap between the bare die and the circuit structure, and between the electronic device and the circuit structure, and no epoxy resin is needed to fill them.
[0014] In one achievable manner, the electronic device may be a passive device, and the passive device may be at least one of a capacitor, a resistor, an inductor, and the like.
[0015] In one achievable manner, the electronic device includes a capacitor, a power supply circuit is provided in the circuit structure, and the capacitor is electrically connected to the power supply circuit via a first bonding structure.
[0016] By placing the capacitor electrically connected to the power supply circuit in the gap between the bare chips, a higher capacitance decoupling capacitor can be achieved to meet the noise reduction requirements of the power supply circuit.
[0017] In one achievable manner, the capacitor includes a first electrode and a second electrode; at least one first contact pad is arranged on a side of the capacitor facing the circuit structure, and at least one second contact pad is arranged on a surface of the circuit structure facing the electronic device; at least one first contact pad includes a first electrode contact pad and a second electrode contact pad; the first electrode is electrically connected to the first electrode contact pad through a first conductive via, and the second electrode is electrically connected to the second electrode contact pad through a second conductive via.
[0018] The above example is a MIM capacitor structure, and each electrode in the MIM capacitor structure can be electrically connected to a contact pad through a conductive via (eg, a through silicon via TSV) penetrating a dielectric layer.
[0019] In one achievable manner, the capacitor further includes a third electrode, and the first electrode, the second electrode, and the third electrode are arranged along a first direction; at least one first contact pad further includes a third electrode contact pad; the third electrode is electrically connected to the third electrode contact pad through a third conductive through hole; and the first direction is parallel to a stacking direction of the first bare chip and the circuit structure.
[0020] In some examples, more electrodes may be included to form multiple parallel capacitors, thereby increasing the capacitance.
[0021] In one achievable manner, a dielectric layer is provided in the gap between the first die and the second die, and the electronic device is arranged in the dielectric layer; the first die and the dielectric layer are bonded to each other at their opposite surfaces; and the second die and the dielectric layer are bonded to each other at their opposite surfaces.
[0022] In this way, the strength and reliability of the entire chip stacking structure can be improved.
[0023] In one achievable manner, the first die and the second die are both electrically connected to the circuit structure via a second bonding structure; the second bonding structure includes a third contact pad and a fourth contact pad arranged face to face, and the third contact pad and the fourth contact pad are electrically connected.
[0024] The first bare chip and the second bare chip may also be electrically connected to the circuit structure by using a bonding structure.
[0025] In one achievable manner, the third contact pad and the fourth contact pad are bonded to form a hybrid bonding structure.
[0026] That is, both the first bare chip and the second bare chip are electrically connected to the circuit structure using a hybrid bonding structure.
[0027] In one possible implementation, the circuit structure is a wafer, a packaging substrate, a redistribution layer, or an intermediate layer.
[0028] On the other hand, the present application also provides a method for preparing a chip stacking structure, the preparation method comprising:
[0029] placing the first die and the second die on a carrier;
[0030] disposing an electronic device in a gap between the first die and the second die;
[0031] A bonding structure is used to electrically connect the first bare chip, the second bare chip and the electronic device to the circuit structure. The first bare chip, the electronic device and the second bare chip are located on the same side of the circuit structure. The bonding structure includes at least one first contact pad and at least one second contact pad arranged face to face. The first contact pad and the second contact pad are electrically connected.
[0032] In the preparation method of the chip stacking structure given in the present application, an electronic device is arranged in the gap between the first bare chip and the second bare chip to fully utilize the bare chip gap area and improve the space utilization of the bare chip packaging structure; and the electronic device is electrically connected to the circuit structure through a bonding structure, which also fully utilizes the virtual contact pad structure on the circuit structure.
[0033] In one possible implementation, the electronic device is electrically connected to the circuit structure using a bonding structure, including:
[0034] At least one first contact pad is arranged on the side of the electronic device away from the carrier, at least one second contact pad is arranged on the surface of the circuit structure, the first contact pad and the second contact pad are directly bonded to form a hybrid bonding structure; and the carrier is removed.
[0035] The electronic device is electrically connected to the circuit structure through the hybrid bonding structure.
[0036] In one implementation, an electronic device is provided in a gap between a first die and a second die, including:
[0037] A first electrode, a second electrode, a first conductive via and a second conductive via are arranged in the gap, so that the first electrode is connected to the first contact pad through the first conductive via and the second electrode is connected to another first contact pad through the second conductive via.
[0038] In this example, the electronic device is a capacitor, and the circuit structure may include a power supply circuit electrically connected to the capacitor, so that a decoupling capacitor with a higher capacitance value can be implemented to meet the noise reduction requirements of the power supply circuit.
[0039] In one possible implementation, an electronic device is arranged in a gap between the first die and the second die, further comprising:
[0040] A third electrode and a third conductive via are arranged in the gap, the first electrode, the second electrode and the third electrode are arranged along a first direction, and the third electrode is connected to another first contact pad through the third conductive via; the first direction is parallel to the stacking direction of the first bare chip and the circuit structure.
[0041] In this implementation process, multiple capacitors can be manufactured, thereby increasing the capacitance.
[0042] On the other hand, the present application also provides an electronic device, which includes a circuit board, and a chip stacking structure of any of the above-mentioned implementations, or a chip stacking structure manufactured using the preparation method, wherein the chip stacking structure is arranged on the circuit board.
[0043] In the electronic device provided in the present application, since the gaps between the bare chips in the chip stacking structure are occupied by electronic devices, the space in the gap area is fully utilized, and the idle virtual contact pad structure is also fully utilized. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 It is a structural schematic diagram of a chip stacking structure in the prior art;
[0045] Figure 2 A schematic diagram of a structure including a PCB and a chip stacking structure in an electronic device provided in an embodiment of the present application;
[0046] Figure 3 A schematic diagram of a chip stacking structure provided in an embodiment of the present application;
[0047] Figure 4A A schematic diagram of a circuit structure in a chip stacking structure provided in an embodiment of the present application;
[0048] Figure 4B A schematic diagram of another circuit structure in a chip stacking structure provided in an embodiment of the present application;
[0049] Figure 4C A schematic diagram of another circuit structure in the chip stacking structure provided in an embodiment of the present application;
[0050] Figure 5 A schematic diagram of the structure of a capacitor provided in an embodiment of the present application;
[0051] Figure 6 A schematic diagram of the structure of another capacitor provided in an embodiment of the present application;
[0052] Figure 7 A schematic diagram of a chip stacking structure provided in an embodiment of the present application;
[0053] Figure 8 A schematic diagram of a chip stacking structure provided in an embodiment of the present application;
[0054] Fig. 9 A flowchart of a method for preparing a chip stacking structure provided in an embodiment of the present application;
[0055] FIG. 10A to FIG. 10FA schematic diagram of the corresponding structure after each step is completed in the manufacturing process of a chip stacking structure provided in an embodiment of the present application.
[0056] Reference numerals:
[0057] 100-PCB;
[0058] 200- electrical connection structure;
[0059] 300- chip packaging structure;
[0060] 400-Radiator;
[0061] 1a-Packaging substrate;
[0062] 1b-Rewiring layer;
[0063] 1c-intermediary layer;
[0064] 111-core material;
[0065] 112-Laminated circuit;
[0066] 113-conductive through hole;
[0067] 114- dielectric layer;
[0068] 1- Circuit structure;
[0069] 2- bare die; 21- first bare die; 22- second bare die;
[0070] 3- Gap;
[0071] 41, 42 - contact pads;
[0072] 411 - first electrode contact pad; 412 - second electrode contact pad; 413 - third electrode contact pad;
[0073] 511 - first electrode; 512 - second electrode; 515 - third electrode;
[0074] 513 - first conductive via; 514 - second conductive via; 516 - third conductive via;
[0075] 61-first dielectric layer; 62-second dielectric layer;
[0076] 7- dielectric layer;
[0077] 8-filling layer;
[0078] 9-Carrier. DETAILED DESCRIPTION
[0079] The embodiment of the present application provides an electronic device. The electronic device may include a mobile phone, a tablet computer (pad), a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR), or a household appliance or other device. The embodiment of the present application does not impose any special restrictions on the specific form of the above-mentioned electronic device.
[0080] like Figure 2 As shown, the electronic device may include a circuit board, such as a printed circuit board (PCB) 100, and a chip packaging structure 300. The chip packaging structure 300 is electrically connected to the PCB 100 through an electrical connection structure 200, so that the chip packaging structure 300 can achieve signal interconnection with other chips or other electronic modules on the PCB 100.
[0081] In addition, Figure 2 As shown, the electronic device may further include a heat sink 400, which covers the chip packaging structure 300 and other electronic modules on the PCB 100 and is fixedly connected to the PCB 100. The heat sink 400 here is a heat dissipation structure that can dissipate heat and cool the chip packaging structure 300 and other electronic modules on the PCB 100. In addition, the heat sink 400 can also play a physical protection role for the chip packaging structure 300.
[0082] In an alternative embodiment, the electrical connection structure 200 may include a plurality of solder balls, such as a ball grid array (BGA), or a plurality of metal pillars.
[0083] The chip packaging structure 300 may be a chip packaged structure. For example, the chip packaging structure 300 may be a processor including a memory and a system on chip (SOC), or may include a system on chip SOC and an analog chip, or may include an analog chip and other digital chips.
[0084] The structure of the chip packaging structure 300 is described in detail below.
[0085] Figure 3 A cross-sectional schematic diagram of a chip stacking structure in a chip packaging structure 300 provided in an embodiment of the present application, the chip stacking structure includes: multiple bare chips, the multiple bare chips are all integrated on a circuit structure 1, and the multiple bare chips are located on the same side of the circuit structure 1. Figure 3 It is exemplified that the first die 21 and the second die 22 are integrated on the circuit structure 1 .
[0086] Figure 3 This is only an exemplary structure, and more bare chips may be arranged on the circuit structure 1, for example, three, four, etc. Such a packaging structure may be referred to as a multi-chip packaging structure.
[0087] The present application relates to a bare chip integrated on a circuit structure 1, which may be a single bare chip or a plurality of bare chips stacked in three dimensions. For example, Figure 3 The first die 21 in the figure may refer to one die, and the second die 22 may include a plurality of die stacked in three dimensions. The three-dimensional stacking here refers to stacking in a direction perpendicular to the circuit structure 1 .
[0088] Figure 3 An exemplary die may be a chip that is cut from a wafer but not packaged.
[0089] The circuit structure 1 involved in the present application has a variety of structures that can be realized.
[0090] For example, the circuit structure 1 may be a wafer.
[0091] As another example, the circuit structure 1 may be configured as follows: Figure 4A The package substrate 1 a shown includes a core material 111 and a laminated circuit 112 located on the upper surface of the core material 111 .
[0092] As another example, the circuit structure 1 may be Figure 4B The redistribution layer (RDL) 1b made by the redistribution process is shown, and RDL1b includes one or more layers of metal wiring and multiple dielectric layers, and each two adjacent layers of metal wiring are separated by a dielectric layer. In order to electrically connect the metal wirings on different layers, a conductive channel can be made in the dielectric layer so that the metal wirings on different layers are electrically connected through the conductive channel. When RDL1b is used as a circuit structure, flexibility can also be improved and the warping degree of the package can be suppressed.
[0093] As another example, the circuit structure 1 may be Figure 4C An interposer 1c is shown, and the interposer 1c includes a dielectric layer 114, a redistribution layer 1b integrated on the dielectric layer 114, and a conductive via 113 penetrating the dielectric layer 114, wherein the conductive via 113 is electrically connected to the redistribution layer 1b.
[0094] There are many ways to bond any one of the first die 21 and the second die 22 to the circuit structure 1. For example, Figure 3The first die 21 and the second die 22 are interconnected with the circuit structure 1 using a hybrid bonding structure. A contact pad 41 is provided at the interface of the first die 21 for bonding with the circuit structure 1, and a contact pad 42 is provided at the interface of the circuit structure 1 for bonding with the first die 21. The contact pads 41 and the contact pads 42 are directly bonded and attached together to form a hybrid bonding structure 4. This bonding structure can also be called a direct bond interconnect (DBI).
[0095] In some examples, the contact pad includes, but is not limited to, an alloy formed from one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene, or carbon nanotubes.
[0096] like Figure 3 The hybrid bonding structure shown enables heterogeneous integration of chips of different sizes to provide a 3D chip architecture with higher bandwidth and lower power consumption.
[0097] In some other examples, the electrical connection between the first die 21 and the circuit structure 1 may be achieved through solder bumps or micro bumps.
[0098] like Figure 3 In this example, the second die 22 or other more dies may be used Figure 3 A hybrid bonding structure or integrated on the circuit structure 1 using a ball implant bonding process.
[0099] When the bare chip is set on the circuit structure 1, in some examples, the active surface (active surface) of the bare chip can face the circuit structure 1, and the passive surface (also called the passive surface) of the bare chip is away from the circuit structure 1, and the active surface of the bare chip is set on the circuit structure 1 through the bonding structure 4.
[0100] After the first die 21 and the second die 22 are arranged on the circuit structure 1, there will be a gap between the two die. Figure 3 The gap 3 shown. In some examples, the width dimension d of the gap 3 may be 50 μm to 100 μm, and the length dimension of the gap 3 may be 10 mm to 50 mm, where the length dimension is the dimension in a direction perpendicular to the width dimension. In this way, there is a larger die gap area between the first die 21 and the second die 22.
[0101] When the first die 21 and the second die 22 are bonded on the circuit structure 1 , in order to prevent the circuit structure 1 from warping, an idle, virtual contact pad 42 is processed on the surface of the circuit structure 1 and located at the gap 3 between the first die 21 and the second die 22 .
[0102] In order to fully utilize the gap 3 between the first die 21 and the second die 22, and to fully utilize the idle, virtual contact pads 42, as shown in FIG. Figure 3 The chip stacking structure of the example of the present application also includes: an electronic device 5 arranged in the gap 3 between the first bare chip 21 and the second bare chip 22, and the electronic device 5 is interconnected with the circuit structure 1 through a bonding structure 4 located between the interface of the circuit structure 1 and the electronic device 5.
[0103] In this way, the gap 3 between the first die 21 and the second die 22 is fully utilized, and the virtual contact pad 42 is fully utilized.
[0104] In some examples, the electronic device 5 may be a passive device, for example, at least one of a capacitor, a resistor, an inductor, etc. Figure 3 In the figure, the electronic device 5 is shown as an example including a capacitor.
[0105] like Figure 5 , Figure 5 The structure of a capacitor is exemplarily shown, and the capacitor includes a first electrode 511 and a second electrode 512, and the first electrode 511 and the second electrode 512 are separated by a dielectric layer. Such a capacitor may be called a MIM capacitor.
[0106] The first electrode 511 and the second electrode 512 are arranged along the P direction. The P direction (which may be referred to as the first direction) may be understood as the above Figure 3 The stacking direction of the first bare chip 21 and the circuit structure 1 in FIG.
[0107] The contact pad 41 located at the interface between the capacitor and the circuit structure 1 includes: a first electrode contact pad 411 electrically connected to the first electrode 511 , and a second electrode contact pad 412 electrically connected to the second electrode 512 .
[0108] In some examples, the first electrode 511 can be interconnected with the first electrode contact pad 411 through a first conductive via 513 (e.g., through silicon via TSV) penetrating the dielectric layer, and the second electrode 512 can be interconnected with the second electrode contact pad 412 through a second conductive via 514 (e.g., through silicon via TSV).
[0109] Figure 5 A capacitor is shown as an example. In some structures, more capacitors can be arranged in the gap 3. For example, a multilayer electrode structure including more than two layers can be provided. Figure 6As shown, a third electrode 515 may also be included. The first electrode 511, the second electrode 512 and the third electrode 515 are arranged along the stacking direction P, where the stacking direction P is parallel to the stacking direction of the bare chip and the circuit structure. Each electrode is electrically connected to the corresponding contact pad through a conductive through hole. For example, the third electrode 515 is interconnected with the third electrode contact pad 413 through a third conductive through hole 516. Figure 6 In the example, the first electrode 511 and the second electrode 512 form a MIM capacitor, and the first electrode 511 and the third electrode 515 form another MIM capacitor. This structure forms two capacitors in parallel, thereby increasing the capacitance value.
[0110] In some examples, a power supply circuit may be formed in the circuit structure 1, and the power supply circuit may supply power to at least one of the first die 21 and the second die 22. For example, when the first die 21 is a dynamic random access memory (DRAM), the power supply circuit may be used to supply power to the DRAM.
[0111] Figure 3 In the example, the capacitor disposed in the gap between the dies can be electrically connected to the power supply circuit in the circuit structure 1 through the bonding structure 4 .
[0112] In some examples, capacitors can be integrated into the back-end metal interconnect structure of circuit structure 1. In this case, there needs to be sufficient space between metal layers to allow capacitors with a certain density to be integrated therein, and the coupling interference between the capacitors and surrounding interconnects or electronic devices needs to be minimized as much as possible. This may result in the integration density of the capacitors or the capacitance being limited.
[0113] like Figure 3 In the present application example, the capacitor is set in the gap 3 between the bare chips, and the spacing between the two electrodes can be adjusted according to the capacitance value, and the phenomenon that the capacitance value of the capacitor in the back-end process is limited will basically not occur. In addition, the capacitor is set in an independent space between the first bare chip 21 and the second bare chip 22, and is basically not affected by the coupling interference of other electronic devices, thereby improving the performance of the capacitor, realizing a higher capacitance decoupling capacitor, and meeting the noise reduction requirements of the complex power supply network.
[0114] like Figure 7 When the first bare chip 21 , the second bare chip 22 and the electronic device 5 are integrated on the circuit structure 1 using a hybrid bonding structure, the contact pad 41 is disposed in the first dielectric layer 61 , and the contact pad 42 is disposed in the second dielectric layer 62 .
[0115] At the face-to-face position between the first bare chip 21 and the circuit structure 1 , not only the contact pad 41 is attached to the contact pad 42 , but also the first dielectric layer 61 is attached to the second dielectric layer 62 .
[0116] At the face-to-face position between the second bare chip 22 and the circuit structure 1 , not only the contact pads 41 are attached to the contact pads 42 , but also the first dielectric layer 61 is attached to the second dielectric layer 62 .
[0117] At the face-to-face position between the electronic device 5 and the circuit structure 1 , not only the contact pad 41 is in contact with the contact pad 42 , but also the first dielectric layer 61 is in contact with the second dielectric layer 62 .
[0118] Continue reading Figure 7 A dielectric layer 7 is filled in the gap between the first die 21 and the second die 22 , and the electronic device 5 is arranged in the dielectric layer 7 .
[0119] The first die 21 and the dielectric layer 7 are bonded to each other at their opposite surfaces, and the second die 22 and the dielectric layer 7 are bonded to each other at their opposite surfaces. This can improve the strength of the entire die packaging structure.
[0120] In some chip stacking structures, such as Figure 8 , including not only the first die 21 and the second die 22 , but also the third die 23 . The first die 21 , the second die 22 and the third die 23 are located on the same side of the circuit structure 1 , and the third die 23 is electrically connected to the circuit structure 1 through the bonding structure 4 .
[0121] In some examples, such as Figure 8 There is no dummy contact pad 42 in the gap between the third die 23 and the first die 21 , so that the gap between the first die 21 and the third die 23 can be filled with the filling layer 8 .
[0122] The filling layer 8 may include at least one of SiO 2 , epoxy resin, and the like.
[0123] The present application also provides a method for preparing a chip stacking structure. Fig. 9 As shown, Fig. 9 A flowchart of a method for preparing a chip stacking structure is exemplarily shown, wherein the preparation method comprises:
[0124] S1: placing a first die and a second die on a carrier.
[0125] The first die or the second die may be one die, or may be a plurality of stacked dies.
[0126] S2: Arrange an electronic device in the gap between the first die and the second die.
[0127] S3: A bonding structure is used to electrically connect the first bare chip, the second bare chip and the electronic device to the circuit structure. The first bare chip, the electronic device and the second bare chip are located on the same side of the circuit structure. The bonding structure includes at least one first contact pad and at least one second contact pad arranged face to face. The first contact pad and the second contact pad are electrically connected.
[0128] In the chip stacking structure prepared by the above method, the gap area between the bare chips is fully utilized, thereby improving the space utilization rate of the chip stacking structure. In addition, the electronic devices arranged in the gap between the bare chips can also use the virtual contact pad structure on the circuit structure to interconnect with the circuit structure, without causing the waste of virtual contact pad resources.
[0129] The specific process flow involved in the method for preparing the above chip stacking structure is introduced below in conjunction with the accompanying drawings.
[0130] FIG. 10A to FIG. 10F The process structure after each step of the process of preparing a chip stacking structure according to an embodiment of the present application is given.
[0131] like Fig. 10A As shown, a plurality of bare chips are arranged on a carrier 9. For example, Fig. 10A The first die 21 and the second die 22 are arranged on the same side of the carrier 9. There is a gap 3 between the first die 21 and the second die 22.
[0132] Wherein, a contact pad 41 is disposed on a side of either the first die 21 or the second die 22 away from the carrier 9. The contact pad 41 is disposed in the dielectric layer.
[0133] like Fig. 10B As shown, an electronic device 5 is arranged in the gap 3 between the first die 21 and the second die 22 , for example, a capacitor may be arranged.
[0134] For example, a plurality of stacked electrodes may be formed by etching in the gap, and a capacitor is formed between two adjacent electrodes, thereby forming a plurality of parallel capacitors.
[0135] Compared with setting capacitors in the interconnection layer of the back-end process, setting capacitors in the gap between the bare chips is not limited by the spacing between metal layers. In the method exemplified in the present application, the spacing between electrodes can be adjusted according to the capacitance value. Moreover, setting capacitors in the gap will not be affected by coupling interference from metal wiring or other devices.
[0136] Since the capacitor needs to be electrically connected to the peripheral circuit, such as Fig. 10B , a conductive through hole can be set in the dielectric layer so that the conductive through hole is electrically connected to the corresponding electrode.
[0137] like Fig. 10C , a contact pad 41 may be formed on one side of the capacitor such that the contact pad 41 is interconnected with the electrode through a conductive via.
[0138] Contact pads 41 that are electrically connected to the capacitor are also located in the dielectric layer.
[0139] In this way, a plurality of dies and electronic devices located in the gaps between the dies are integrated on the carrier 9 .
[0140] like Fig. 10D , providing a circuit structure 1, which may be one of a wafer, an interposer or a redistribution layer, and the like.
[0141] A contact pad 42 is disposed on the surface of the circuit structure 1 , and the contact pad 42 is located in the second dielectric layer 62 .
[0142] In the circuit structure 1, a power supply circuit can be set up, which can supply power to the first bare chip or the second bare chip. The capacitor located in the gap between the bare chips is electrically connected to the power supply circuit through a hybrid bonding structure, so as to realize a decoupling capacitor with a higher capacitance value and meet the noise reduction requirements of more complex power supply circuits.
[0143] like Fig. 10E A hybrid bonding process may be used to bond the contact pad 41 and the contact pad 42 , and the first dielectric layer 61 and the second dielectric layer 62 are also bonded together.
[0144] like Fig.10F , remove the carrier 9. Thus, a three-dimensionally stacked package including the first die 21, the second die 22, the electronic device 5 and the circuit structure 1 is obtained.
[0145] Combination FIG. 10A to FIG. 10F In the obtained bare chip packaging structure, not only the bare chip gap is fully utilized, but also the virtual contact pad on the circuit structure 1 is fully utilized.
[0146] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.
[0147] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A chip stacking structure, characterized in that: include: Circuit structure; a first die and a second die, wherein the first die and the second die are arranged side by side on a same side of the circuit structure; An electronic device is disposed in the gap between the first die and the second die, and the electronic device is electrically connected to the circuit structure through a first bonding structure; The first bonding structure includes at least one first contact pad and at least one second contact pad disposed face to face, and the first contact pad and the second contact pad are electrically connected.
2. The chip stacking structure according to claim 1, characterized in that: The first contact pad and the second contact pad are bonded to form a hybrid bonding structure.
3. The chip stacking structure according to claim 1 or 2, characterized in that: The at least one first contact pad is disposed in the first dielectric layer; The at least one second contact pad is disposed in the second dielectric layer; The surfaces of the first dielectric layer and the second dielectric layer facing each other are bonded.
4. The chip stacking structure according to any one of claims 1 to 3, characterized in that: The electronic device includes a capacitor, a power supply circuit is provided in the circuit structure, and the capacitor is electrically connected to the power supply circuit through the first bonding structure.
5. The chip stacking structure according to claim 4, characterized in that: The capacitor comprises a first electrode and a second electrode; The at least one first contact pad is disposed on a side of the capacitor facing the circuit structure; The at least one first contact pad includes a first electrode contact pad and a second electrode contact pad; The first electrode is electrically connected to the first electrode contact pad through a first conductive via, and the second electrode is electrically connected to the second electrode contact pad through a second conductive via.
6. The chip stacking structure according to claim 5, characterized in that: The capacitor further includes a third electrode, and the first electrode, the second electrode and the third electrode are arranged along a first direction; The at least one first contact pad further comprises a third electrode contact pad; The third electrode is interconnected with the third electrode contact pad through a third conductive via; The first direction is parallel to a stacking direction of the first die and the circuit structure.
7. The chip stacking structure according to any one of claims 1 to 6, characterized in that: A dielectric layer is provided in the gap between the first die and the second die, and the electronic device is arranged in the dielectric layer; The first bare chip and the dielectric layer are bonded to each other at surfaces facing each other; The second die and the dielectric layer are bonded to each other at their opposite surfaces.
8. The chip stacking structure according to any one of claims 1 to 7, characterized in that: The first die and the second die are both electrically connected to the circuit structure via a second bonding structure; The second bonding structure includes a third contact pad and a fourth contact pad disposed face to face; The third contact pad and the fourth contact pad are bonded to form a hybrid bonding structure.
9. The chip stacking structure according to any one of claims 1 to 8, characterized in that: The circuit structure is a wafer, a packaging substrate, a redistribution layer or an intermediate layer.
10. A method for preparing a chip stacking structure, characterized in that: The preparation method comprises: placing the first die and the second die on a carrier; disposing an electronic device in a gap between the first die and the second die; A bonding structure is used to electrically connect the first bare chip, the second bare chip and the electronic device to a circuit structure. The first bare chip, the electronic device and the second bare chip are located on the same side of the circuit structure. The bonding structure includes at least one first contact pad and at least one second contact pad arranged face to face. The first contact pad and the second contact pad are electrically connected.
11. The method for preparing a chip stacking structure according to claim 10, characterized in that: The method of electrically connecting the electronic device to the circuit structure by using a bonding structure comprises: At least one first contact pad is arranged on a side of the electronic device facing away from the carrier, and at least one second contact pad is arranged on a surface of the circuit structure, wherein the first contact pad and the second contact pad are directly bonded to form a hybrid bonding structure; The carrier is removed.
12. The method for preparing a chip stacking structure according to claim 10 or 11, characterized in that: An electronic device is arranged in a gap between the first die and the second die, comprising: A first electrode, a second electrode, a first conductive via and a second conductive via are arranged in the gap, so that the first electrode is connected to the first contact pad through the first conductive via, and the second electrode is connected to another first contact pad through the second conductive via.
13. The method for preparing a chip stacking structure according to claim 12, characterized in that: An electronic device is arranged in a gap between the first die and the second die, and further comprising: A third electrode and a third conductive via are arranged in the gap, the first electrode, the second electrode and the third electrode are arranged along a first direction, and the third electrode is connected to another first contact pad through the third conductive via; the first direction is parallel to the stacking direction of the first bare chip and the circuit structure.
14. An electronic device, characterized in that: include: Circuit boards; The chip stacking structure according to any one of claims 1 to 9, or the chip stacking structure obtained by the method for preparing the chip stacking structure according to any one of claims 10 to 13; Wherein, the chip stacking structure is arranged on the circuit board.