Multi-chip packaging structure and method
By using chip embedded substrate and rewiring layer design in multi-chip packaging structures, the problems of large area occupied by traditional packaging structures and unstable interfaces of heterogeneous materials are solved, and higher reliability and electrical properties are achieved Performance and miniaturization design.
Patent Information
- Application Number
- CN202310973537.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-04
- Publication Date
- 2025-02-14
AI Technical Summary
The existing multi-chip packaging structures occupy a large area, and the interface between heterogeneous materials is prone to shedding or delamination, affecting the reliability of the components and signal transmission.
The chip embedded substrate is adopted. By designing the rewiring layer and the packaging layer, the chip is fixed on the substrate, and the homogeneous materials (such as copper) are electrically connected to reduce the packaging resistance and thermal resistance.
It improves the reliability and electrical properties of the components, reduces thermal resistance, increases the freedom of packaging design, and realizes the miniaturization of the product.
Smart Images
Figure CN119447126A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to chip packaging, and in particular to a multi-chip packaging structure and method. Background Art
[0002] The design of today's electronic products places great emphasis on user needs, such as multiple functions, miniaturization, and portability. However, in a traditional multi-chip package structure, multiple chips are arranged horizontally to occupy a large printed circuit board area, which is not conducive to product design and development.
[0003] Furthermore, in the existing three-dimensional or stacked packaging structures, the stacked chips are mostly electrically connected and fixed to the components of other layers through heterogeneous materials such as high-lead solder, silver paste, solder balls, etc. However, it is easier for the heterogeneous materials to fall off or delaminate at the interface between each other and the interface between the conductive material and the packaging material, resulting in poor reliability of the components, and the heterogeneous material interface also has an adverse effect on the transmission of energy or signals. Summary of the invention
[0004] In view of this, the present invention proposes a multi-chip packaging structure and method to effectively solve the above problems encountered in the prior art.
[0005] According to a specific embodiment of the present invention, a multi-chip packaging structure is provided. In this embodiment, the multi-chip packaging structure includes a chip-embedded substrate, an integrated circuit chip, a conductive structure and a packaging layer. The chip-embedded substrate has a first surface and a second surface relative to each other, and the chip-embedded substrate includes a first rewiring layer, a second rewiring layer and a first power chip, the first rewiring layer is adjacent to the first surface and exposed to the first surface, and the second rewiring layer is adjacent to the second surface. The first power chip is arranged between the first rewiring layer and the second rewiring layer and is electrically connected to at least one of the first rewiring layer and the second rewiring layer. The integrated circuit chip is electrically insulated and connected to the second surface of the chip-embedded substrate. The conductive structure electrically connects the integrated circuit chip and the chip-embedded substrate. The packaging layer covers the integrated circuit chip and at least part of the conductive structure.
[0006] In one embodiment, the chip embedded substrate further includes a first conductor disposed between the first redistribution layer and the second redistribution layer.
[0007] In one embodiment, the chip-embedded substrate also includes a second power chip, which is arranged between the first re-wiring layer and the second re-wiring layer. The second power chip is separated from the first power chip by a gap, and the integrated circuit chip overlaps with part of the first power chip, part of the second power chip and at least part of the gap from a top-down perspective.
[0008] In one embodiment, the second redistribution layer is electrically connected to the first power chip and the integrated circuit chip.
[0009] In one embodiment, the conductive structure is at least one of a rewiring layer, a conductive column, a connecting line, a conductive clip, or an aluminum tape, or a combination thereof.
[0010] In one embodiment, the packaging layer has a third surface away from the chip embedded substrate, the third surface exposes a portion of the conductive structure, and the packaging structure further includes a heat dissipation structure electrically insulated and contacting the conductive structure exposed on the third surface.
[0011] Another specific embodiment of the present invention is a multi-chip packaging structure. In this embodiment, the multi-chip packaging structure includes a first packaging part and a second packaging part. The first packaging part has a first surface and a second surface opposite to each other. The first surface of the first packaging part is provided with a first rewiring layer, and the second surface of the first packaging part is provided with a second rewiring layer. The first packaging part includes a first power chip. The first power chip is provided between the first rewiring layer and the second rewiring layer and is respectively connected to the first rewiring layer and the second rewiring layer. The second packaging part has a first surface and a second surface opposite to each other. The first surface of the second packaging part is provided with a third rewiring layer. The second surface of the second packaging part is connected face to face with the second surface of the first packaging part. The second packaging part includes an integrated circuit chip and a plurality of first conductive pillars. The integrated circuit chip has a first surface and a second surface opposite to each other. The second surface of the integrated circuit chip faces the second surface of the second packaging part, and the first surface of the integrated circuit chip is electrically connected to the first rewiring layer. The second surface of the integrated circuit chip is provided with an insulating layer. The plurality of first conductive pillars are respectively electrically connected to the third rewiring layer. The first power chip is electrically connected to the second packaging part through at least one of the first rewiring layer and the second rewiring layer.
[0012] In one embodiment, the first packaging part further includes a second power chip. The second power chip has a first surface and a second surface opposite to each other, is disposed between the first redistribution layer and the second redistribution layer, and is electrically connected to the first redistribution layer and the second redistribution layer respectively.
[0013] In one embodiment, the second packaging portion further includes at least one second conductive pillar electrically connecting the first redistribution layer and the second redistribution layer.
[0014] Another specific embodiment of the present invention is a multi-chip packaging method. In this embodiment, the multi-chip packaging method includes the following steps: providing a chip embedded substrate, the chip embedded substrate having a first surface and a second surface opposite to each other and including a first redistribution layer, a second redistribution layer and a first power chip, the first redistribution layer being adjacent to the first surface and exposed to the first surface, the first power chip being disposed between the first redistribution layer and the second redistribution layer and electrically connected to at least one of the first redistribution layer and the second redistribution layer. Disposing an integrated circuit chip on the second surface of the chip embedded substrate in an electrically insulated manner.
[0015] In one embodiment, the chip-embedded substrate further includes a second power chip. The packaging method further includes: electrically connecting the second power chip between the first redistribution layer and the third redistribution layer and separating the second power chip from the first power chip with a gap.
[0016] In one embodiment, the packaging method further includes: providing a conductive structure to electrically connect the integrated circuit chip and the chip embedded substrate.
[0017] In one embodiment, the packaging method further includes: providing a packaging material to cover the integrated circuit chip and at least a portion of the conductive structure.
[0018] Compared with the prior art, the multi-chip packaging structure and method proposed in the present invention have the following advantages and effects:
[0019] (1) Improved reliability of components: Compared with conventional three-dimensional packaging or stacked packaging that uses heterogeneous materials such as solder and contact pads to connect the chip to other layers of components, the present invention uses the same polymer material as the packaging material to fix the chip on the chip-embedded substrate, thereby increasing the reliability between the chip and the component;
[0020] (2) Improving the electrical and thermal conductivity of components: Compared with the traditional wire bonding or clip connection method that requires the use of heterogeneous materials such as solder, the present invention further reduces the package resistance by connecting the rewiring layer (e.g., copper) of the same material as the wire bonding and clip to the conductor material inside the package. On the other hand, the large area of the rewiring layer is designed to contact the heat dissipation component, which can reduce the thermal resistance;
[0021] (3) Increased freedom of package design: Compared with the prior art, the present invention can configure larger or more chips within the same package area to improve product performance or functionality, and can provide more functional pin configuration space within the original package area; and
[0022] (4) Realizing product miniaturization: The packaging structure of the present invention adopts a multi-chip top-bottom layout design to reduce the packaging area, and at the same time reduces the area of the required printed circuit board, which is conducive to the development of product miniaturization.
[0023] The advantages and spirit of the present invention may be further understood through the following specific embodiments and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The accompanying drawings of the present invention are described as follows:
[0025] Figure 1 FIG. 1 is a schematic diagram of a multi-chip package structure 1 according to an embodiment of the present invention.
[0026] FIG. 2A to FIG. 2E They are Figure 1 Schematic diagram of different manufacturing stages of a multi-chip package structure 1.
[0027] Figure 3 FIG. 4 is a schematic diagram of a multi-chip packaging structure 3 according to an embodiment of the present invention.
[0028] Figure 4 FIG. 4 is a schematic diagram of a multi-chip package structure 4 according to an embodiment of the present invention.
[0029] Figure 5 FIG. 5 is a schematic diagram of a multi-chip packaging structure 5 according to an embodiment of the present invention.
[0030] Figure 6 FIG. 4 is a schematic diagram of a multi-chip package structure 6 according to an embodiment of the present invention.
[0031] Figure 7 It is a schematic diagram showing that an insulating heat-conducting layer LH is further provided on the multi-chip packaging structure 7 of the present invention.
[0032] Figure 8 It is a schematic diagram showing that a heat dissipation element EH is further provided on the multi-chip packaging structure 8 of the present invention.
[0033] Fig. 9 FIG. 4 is a flow chart of a multi-chip packaging method according to an embodiment of the present invention.
[0034] Description of main component symbols:
[0035] 1…Multi-chip packaging structure
[0036] DES…Chip Embedded Substrate
[0037] R1~R3…rewiring layer
[0038] S1~S3…Surface
[0039] MOS1…The first power chip
[0040] IC…Integrated Circuit Chip
[0041] MOS2…The second power chip
[0042] CU1…First conductor
[0043] CU2…Second conductor
[0044] S…Source
[0045] G…Gate
[0046] D…Drain
[0047] GAP…Gap
[0048] DL…Insulation layer
[0049] PKG…Package layer
[0050] S20~S24…stage
[0051] 3…Multi-chip packaging structure
[0052] 4…Multi-chip packaging structure
[0053] P1…First packaging unit
[0054] P2…Second packaging unit
[0055] P11…First surface
[0056] P12…Second surface
[0057] P21…First surface
[0058] P22…Second surface
[0059] DIE1…The first power chip
[0060] DIE2…Integrated Circuit Chip
[0061] D11…First surface
[0062] D12…Second surface
[0063] D21…First surface
[0064] D22…Second surface
[0065] CB1…First conductive column
[0066] CB2…Second conductive column
[0067] 5…Multi-chip packaging structure
[0068] BD…Bonding
[0069] 6…Multi-chip packaging structure
[0070] CL…Clip
[0071] 7…Multi-chip packaging structure
[0072] DIE3…The second power chip
[0073] D31…First surface
[0074] D32…Second surface
[0075] S80~S84…stage
[0076] 9…Multi-chip packaging structure
[0077] LH…Insulation and thermal conductivity layer
[0078] 10…Multi-chip packaging structure
[0079] EH…Cooling element DETAILED DESCRIPTION
[0080] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Elements / components using the same or similar reference numerals in the drawings and embodiments are intended to represent the same or similar parts.
[0081] According to a specific embodiment of the present invention, a multi-chip packaging structure is provided. In this embodiment, the multi-chip packaging structure uses a rewiring layer and an external circuit structure with homogeneous materials (such as copper) to improve the reliability of the components, and uses a multi-chip top-bottom layout design to reduce the packaging area and the area of the required printed circuit board. Compared with the traditional SMT process, the chip packaged using the rewiring layer process (copper-copper connection process) is less likely to be displaced and tilted, which can effectively improve the process stability.
[0082] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the packaging structure of the multi-chip in this embodiment. Figure 1 As shown, the multi-chip packaging structure 1 includes a chip-embedded substrate DES, an integrated circuit chip IC, a third rewiring layer R3, a second conductor CU2 and a packaging layer PKG. The packaging layer PKG encapsulates the integrated circuit chip IC, the third rewiring layer R3 and the second conductor CU2. The chip-embedded substrate DES includes a first rewiring layer R1, a first power chip MOS1, a second power chip MOS2, a second rewiring layer R2 and a first conductor CU1. The chip-embedded substrate DES has a first surface S1 and a second surface S2, and the first surface S1 exposes a portion of the first rewiring layer R1. The packaging layer PKG has a third surface S3.
[0083] The chip-embedded substrate DES also includes a second power chip MOS2, which is separated from the first power chip MOS1 by a gap GAP. The first power chip MOS1 and the second power chip MOS2 are arranged between the first rewiring layer R1 and the second rewiring layer R2, and are electrically connected to the first rewiring layer R1 and the second rewiring layer R2 respectively. The source S and the gate G of the first power chip MOS1 are electrically connected to the first rewiring layer R1, and the drain D thereof is electrically connected to the second rewiring layer R2. The source S and the gate G of the second power chip MOS2 are electrically connected to the third rewiring layer R3, and the drain D thereof is electrically connected to the first rewiring layer R1. The first conductor CU1 is electrically connected between the second rewiring layer R2 and the first rewiring layer R1.
[0084] The integrated circuit chip IC is fixed to the second surface S2 through an insulating layer DL that is the same as the packaging material or has a higher bonding strength. The third rewiring layer R3 is disposed on the integrated circuit chip IC. The second conductor CU2 is electrically connected between the second rewiring layer R2 and the third rewiring layer R3. The third rewiring layer R3 and the second conductor CU2 form a conductive structure to electrically connect the integrated circuit chip IC to the chip embedded substrate DES.
[0085] It should be noted that the integrated circuit chip IC is a single-sided electrical grain (such as IC or horizontal MOS), that is, the top surface of the integrated circuit chip IC is electrically connected to the third rewiring layer R3 located above it, and the bottom surface of the integrated circuit chip IC is electrically insulated and connected to the chip embedded substrate DES, that is, the bottom surface of the integrated circuit chip IC is electrically insulated from the second surface S2 of the chip embedded substrate DES.
[0086] In addition, in the implementation of the three-chip package, the chip with a larger area (such as the integrated circuit chip IC) is separately arranged to achieve the best spatial configuration and the best heat dissipation configuration. At this time, a portion of the integrated circuit chip IC will be located above the first power chip MOS1 and another portion will be located above the second power chip MOS2. In other words, from a top-down angle, the integrated circuit chip IC overlaps with a portion of the first power chip MOS1, a portion of the second power chip MOS2, and at least a portion of the gap GAP. As a result, the multi-chip packaging structure 1 has a three-dimensional structure with multiple chips arranged up and down, so the packaging area can be greatly reduced and the area of the required printed circuit board can be reduced at the same time.
[0087] The first rewiring layer R1, the second rewiring layer R2, the third rewiring layer R3, the first conductor CU1 and the second conductive layer CU2 in the multi-chip packaging structure 1 are all made of homogeneous materials (such as copper) and are connected to each other over a large area, so the packaging resistance and thermal resistance can be effectively reduced.
[0088] Please refer to FIG. 2A to FIG. 2E, FIG. 2A to FIG. 2E Draw in sequence Figure 1 Schematic diagram of various stages of a multi-chip packaging structure 1.
[0089] like Figure 2A As shown, in stage S20, the first conductor CU1, the first power chip MOS1 and the second power chip MOS2 are fixed on a substrate (e.g., a tape) and a first redistribution layer R1 and a second redistribution layer R2 are respectively formed on the bottom and top surfaces of the chip-embedded substrate DES to produce a chip-embedded substrate DES including the first power chip MOS1, the second power chip MOS2, the first redistribution layer R1, the second redistribution layer R2 and the first conductor CU1.
[0090] like Figure 2B As shown, in stage S21, the integrated circuit chip IC is fixed on the chip embedded substrate DES by using insulating material (insulating glue) and a part of the integrated circuit chip IC is located above the first power chip MOS1 and another part of the integrated circuit chip IC is located above the second power chip MOS2.
[0091] like Figure 2C As shown, in stage S22 , the packaging material is pressed / filled again to cover the integrated circuit chip IC and a second conductor CU2 is provided to electrically connect the integrated circuit chip IC and the first conductor CU1 of the chip embedded substrate DES.
[0092] like Figure 2D As shown, in stage S23, a third redistribution layer R3 is formed on the integrated circuit chip IC and the second conductive body CU2, and the integrated circuit chip IC and the second conductive body CU2 are electrically connected to the third redistribution layer R3.
[0093] like Figure 2E As shown, in stage S24, the packaging material is filled to complete Figure 1 Multi-chip packaging structure 1.
[0094] Please refer to Figure 3 The multi-chip packaging structure 3 includes a chip embedded substrate DES, an integrated circuit chip IC, a second redistribution layer R2 and a second conductor CU2. The chip embedded substrate DES includes a first redistribution layer R1, a first power chip MOS1, a second power chip MOS2 and a third redistribution layer R3.
[0095] The second power chip MOS2 is separated from the first power chip MOS1 by a gap GAP and is configured in the chip embedded substrate DES. The first power chip MOS1 is electrically connected between the first rewiring layer R1 and the second rewiring layer R2. The source S, drain D and gate G of the first power chip MOS1 are electrically connected to the second rewiring layer R2. The second power chip MOS2 is electrically connected between the first rewiring layer R1 and the second rewiring layer R2. The source S, drain D and gate G of the second power chip MOS2 are electrically connected to the second rewiring layer R2. The first conductor CU1 is electrically connected between the second rewiring layer R2 and the first rewiring layer R1.
[0096] The third rewiring layer R3 is disposed on the integrated circuit chip IC and is electrically connected to the integrated circuit chip IC. The top surface of the integrated circuit chip IC is electrically connected to the third rewiring layer R3 located above it, and the bottom surface of the integrated circuit chip IC is electrically insulated and disposed on the chip embedded substrate DES. The second conductor CU2 is electrically connected between the second rewiring layer R2 and the third rewiring layer R3.
[0097] Please refer to Figure 3 ,and Figure 1 The difference is that Figure 3 The first power chip MOS1 and the second power chip MOS2 in the package structure 3 are horizontal power chips. Figure 1 The multi-chip package structure 1 is soldered on a printed circuit board (not shown) in a flip-chip manner. Figure 3 The pins in the circuit will be located on the top surface of the integrated circuit chip IC, namely the third rewiring layer R3.
[0098] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the packaging structure of the multi-chip in this embodiment. Figure 4 As shown, the multi-chip packaging structure 4 includes a first packaging part P1 and a second packaging part P2 arranged one above the other. The first packaging part P1 has a first surface P11 and a second surface P12 opposite to each other. The second packaging part P2 has a first surface P21 and a second surface P22 opposite to each other. The second surface P12 of the first packaging part P1 and the second surface P22 of the second packaging part P2 are adjacent to each other.
[0099] The first surface P11 of the first packaging part P1 is provided with a first rewiring layer R1. The first packaging part P1 includes a first power chip DIE1 and a first conductive pillar CB1. The first power chip DIE1 has a first surface D11 and a second surface D12 opposite to each other. The first surface D11 of the first power chip DIE1 is electrically connected to the first rewiring layer R1. The second surface D12 of the first power chip DIE1 faces the second surface P12 of the first packaging part P1. The first conductive pillar CB1 is provided between the first rewiring layer R1 and the second surface P12 of the first packaging part P1. The first conductive pillar CB1 is electrically connected to the first rewiring layer R1.
[0100] The first surface P21 of the second packaging part P2 is provided with a third rewiring layer R3. The second packaging part P2 includes an integrated circuit chip DIE2 and a second conductive pillar CB2. The third rewiring layer R3 and the second conductive pillar CB2 constitute a conductive structure. The integrated circuit chip DIE2 has a first surface D21 and a second surface D22 opposite to each other. The first surface D21 of the integrated circuit chip DIE2 is electrically connected to the third rewiring layer R3. The second conductive pillar CB2 is provided between the third rewiring layer R3 and the second surface P22 of the second packaging part P2. The second conductive pillar CB2 is electrically connected to the second rewiring layer R2.
[0101] It should be noted that the integrated circuit chip DIE2 of the second packaging part P2 must be a single-sided electrical grain (such as IC or horizontal MOS), that is, it is only electrically connected to the third rewiring layer R3 located on the first surface P21 of the second packaging part P2 through the first surface D21, and its second surface D22 is electrically insulated.
[0102] Since the second surface P12 of the first package part P1 and the second surface P22 of the second package part P2 are adjacent to each other, the first conductive pillar CB1 of the first package part P1 and the second conductive pillar CB2 of the second package part P2 are electrically connected to each other. Thus, the integrated circuit chip DIE2 of the second package part P2 can be electrically connected to the first power chip DIE1 of the first package part P1 through the third rewiring layer R3, the second conductive pillar CB2, the first conductive pillar CB1 and the first rewiring layer R1.
[0103] In another embodiment, if Figure 5 and Figure 6 As shown in the multi-chip package structure 5 and package structure 6, the conductive structure can be a wire bond BD or a conductive clip CL. The integrated circuit chip DIE2 is electrically connected to the first conductive pillar CB1 of the first package part P1, and then electrically connected to the first power chip DIE1 of the first package part P1 through the first rewiring layer R1.
[0104] Please refer to Figure 7In one embodiment, an insulating thermal conductive layer LH is further disposed above the first surface P21 of the second packaging portion P2 in the multi-chip packaging structure 7, and the insulating thermal conductive layer LH is in contact with the third rewiring layer R3, but is not limited thereto.
[0105] Please refer to Figure 8 In another embodiment, a heat dissipation element EH (such as a heat dissipation fin, but not limited thereto) is further disposed above the insulating heat conductive layer LH in the multi-chip packaging structure 8. The insulating heat conductive layer LH contacts the third redistribution layer R3 and the heat dissipation element EH contacts the insulating heat conductive layer LH to discharge the heat inside the multi-chip packaging structure 8, but not limited thereto.
[0106] Another specific embodiment of the present invention is a multi-chip packaging method. Fig. 9 , Fig. 9 This is a flow chart of the multi-chip packaging method in this embodiment. Fig. 9 As shown, the multi-chip packaging method includes the following steps:
[0107] Step S10: providing a chip-embedded substrate, wherein the chip-embedded substrate has a first surface and a second surface opposite to each other and comprises a first redistribution layer, a second redistribution layer and a first power chip, wherein the first redistribution layer is adjacent to the first surface and exposed to the first surface, and the first power chip is disposed between the first redistribution layer and the second redistribution layer and electrically connected to at least one of the first redistribution layer and the second redistribution layer;
[0108] Step S12: Disposing the integrated circuit chip on the second surface of the chip embedded substrate in an electrically insulated manner;
[0109] Step S14: disposing a third rewiring layer on the integrated circuit chip and electrically connecting the integrated circuit chip; and
[0110] Step S16: electrically connecting the second conductor between the second redistribution layer and the third redistribution layer.
[0111] In one embodiment, the chip embedded substrate may further include a second power chip. The packaging method may further include: electrically connecting the second power chip between the first redistribution layer and the third redistribution layer and separating the second power chip from the first power chip with a gap.
[0112] In another embodiment, the packaging method may further include: disposing another portion of the integrated circuit chip above the second power chip; and positioning the integrated circuit chip above the gap and covering the gap.
[0113] In another embodiment, the packaging method may further include: disposing an insulating heat-conductive layer on the third re-distribution layer and contacting the third re-distribution layer; and disposing a heat dissipation element on the insulating heat-conductive layer.
[0114] Compared with the prior art, the multi-chip packaging structure and method proposed in the present invention can provide the following advantages and effects:
[0115] (1) Improved reliability of components: Compared with conventional three-dimensional packaging or stacked packaging that uses heterogeneous materials such as solder and contact pads to connect the chip to other layers of components, the present invention uses the same polymer material as the packaging material to fix the chip on the chip-embedded substrate, thereby increasing the reliability between the chip and the component;
[0116] (2) Improving the electrical and thermal conductivity of components: Compared with the traditional wire bonding or clip connection method that requires the use of heterogeneous materials such as solder, the present invention further reduces the package resistance by connecting the rewiring layer (e.g., copper) of the same material as the wire bonding and clip to the conductor material inside the package. On the other hand, the large area of the rewiring layer is designed to contact the heat dissipation component, which can reduce the thermal resistance;
[0117] (3) Increased freedom of package design: Compared with the prior art, the present invention can configure larger or more chips within the same package area to improve product performance or functionality, and can provide more functional pin configuration space within the original package area; and
[0118] (4) Realizing product miniaturization: The packaging structure of the present invention adopts a multi-chip top-bottom layout design to reduce the packaging area, and at the same time reduces the area of the required printed circuit board, which is conducive to the development of product miniaturization.
Claims
1. A multi-chip packaging structure, characterized in that: The packaging structure comprises: A chip-embedded substrate having a first surface and a second surface opposite to each other, the chip-embedded substrate comprising a first redistribution layer, a second redistribution layer and a first power chip, wherein the first redistribution layer is adjacent to the first surface and exposed to the first surface, the second redistribution layer is adjacent to the second surface, and the first power chip is disposed between the first redistribution layer and the second redistribution layer and electrically connected to at least one of the first redistribution layer and the second redistribution layer; an integrated circuit chip electrically insulated and connected to the second surface of the chip embedded substrate; a conductive structure electrically connecting the integrated circuit chip and the chip embedded substrate; and A packaging layer covers the integrated circuit chip and at least a portion of the conductive structure.
2. The multi-chip packaging structure according to claim 1, characterized in that: The chip embedded substrate further includes a first conductor disposed between the first rewiring layer and the second rewiring layer.
3. The multi-chip packaging structure according to claim 1, characterized in that: The chip-embedded substrate further comprises: A second power chip is arranged between the first rewiring layer and the second rewiring layer. The second power chip is separated from the first power chip by a gap, and the integrated circuit chip overlaps with part of the first power chip, part of the second power chip and at least part of the gap from a top view.
4. The multi-chip packaging structure according to claim 1, wherein: The second rewiring layer electrically connects the first power chip and the integrated circuit chip.
5. The multi-chip packaging structure according to claim 1, wherein: The conductive structure is at least one of a rewiring layer, a conductive column, a connecting line, a conductive clip or an aluminum tape, or a combination thereof.
6. The multi-chip packaging structure according to claim 1, characterized in that: The packaging layer has a third surface away from the chip embedded substrate, the third surface exposes a portion of the conductive structure, and the packaging structure further includes a heat dissipation structure electrically insulated and in contact with the conductive structure exposed on the third surface.
7. A multi-chip packaging structure, characterized in that: The packaging structure includes a first packaging part and a second packaging part. The first packaging part has a first surface and a second surface opposite to each other, the first surface of the first packaging part is provided with a first rewiring layer, the second surface of the first packaging part is provided with a second rewiring layer, and the first packaging part includes: a first power chip, disposed between the first rewiring layer and the second rewiring layer and connected to the first rewiring layer and the second rewiring layer respectively; and The second packaging part has a first surface and a second surface opposite to each other, the first surface of the second packaging part is provided with a third rewiring layer, the second surface of the second packaging part is connected face to face with the second surface of the first packaging part, and the second packaging part comprises: an integrated circuit chip having a first surface and a second surface opposite to each other, wherein the second surface of the integrated circuit chip faces the second surface of the second packaging portion, and the first surface of the integrated circuit chip is electrically connected to the first rewiring layer, and an insulating layer is disposed on the second surface of the integrated circuit chip; and A plurality of first conductive pillars, electrically connected to the third rewiring layer respectively; The first power chip is electrically connected to the second packaging portion through at least one of the first rewiring layer and the second rewiring layer.
8. The multi-chip packaging structure according to claim 7, characterized in that: The first packaging unit further includes: A second power chip has a first surface and a second surface opposite to each other, is disposed between the first rewiring layer and the second rewiring layer and is electrically connected to the first rewiring layer and the second rewiring layer respectively.
9. The multi-chip packaging structure according to claim 7, characterized in that: The second packaging portion further includes at least one second conductive column electrically connecting the first redistribution layer and the second redistribution layer.
10. A multi-chip packaging method, characterized in that: The packaging method comprises the following steps: A chip-embedded substrate is provided, wherein the chip-embedded substrate has a first surface and a second surface opposite to each other and includes a first redistribution layer, a second redistribution layer and a first power chip, wherein the first redistribution layer is adjacent to the first surface and exposed to the first surface, and the first power chip is disposed between the first redistribution layer and the second redistribution layer and electrically connected to at least one of the first redistribution layer and the second redistribution layer; as well as An integrated circuit chip is electrically insulated and disposed on the second surface of the chip embedded substrate.
11. The multi-chip packaging method according to claim 10, characterized in that: The packaging method further comprises: A conductive structure is provided to electrically connect the integrated circuit chip and the chip embedded substrate.
12. The multi-chip packaging method according to claim 11, wherein: The packaging method further comprises: A packaging material is provided to cover the integrated circuit chip and at least a portion of the conductive structure.