Integrated chip packaging structure and manufacturing method thereof

Abstract

The invention discloses an integrated chip packaging structure and a manufacturing method thereof, and belongs to the technical field of semiconductors. The packaging structure comprises a first adapter plate and a second adapter plate, and the first adapter plate and the second adapter plate are oppositely arranged and are bonded through a connection bonding pad; the first chip and the second chip are arranged on one side, far away from the second adapter plate, of the first adapter plate in parallel; the capacitor is arranged between the first adapter plate and the second adapter plate, the capacitor comprises a first polar plate and a second polar plate, the first polar plate is arranged on the first adapter plate, and the second polar plate is arranged on the second adapter plate; and the first insulating layer is filled among the connecting bonding pad, the first polar plate and the second polar plate. According to the integrated chip packaging structure and the manufacturing method thereof provided by the invention, the capacitance area can be greatly increased, the distance from the capacitor to a power supply network is shortened, and the performance of the packaging structure is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to an integrated chip packaging structure and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, the requirements for miniaturization and lightweighting of chips are becoming increasingly higher. In the traditional packaging structure, each module is independently packaged and finally connected to each other through a substrate to form a system. It is a two-dimensional system, which leads to a large size of the packaging structure and does not meet the demand for increased integration. In the packaging structure, capacitors are provided for energy storage, filtering, tuning and decoupling. However, in the current packaging structure, the capacitors and the chip are often laid flat on a substrate, and the capacitors are connected to the chip through the substrate. There are problems such as large occupied area, long distance from the power supply network, and inability to integrate large capacitors. It cannot meet the requirements of high density, short distance, high current, etc., which limits the integration of semiconductor packaging structures. Summary of the Invention

[0003] The purpose of the present invention is to provide an integrated chip packaging structure and a manufacturing method thereof. Through the integrated chip packaging structure and the manufacturing method provided by the present invention, chips with multiple functions can be packaged together in one package body, and a capacitor structure is innovatively added between the bonding surfaces of the two adapter plates, which can greatly increase the capacitance area, shorten the distance from the capacitor to the power supply network, and improve the performance of the packaging structure.

[0004] To solve the above technical problems, the present invention provides an integrated chip packaging structure, comprising at least:

[0005] A first adapter plate and a second adapter plate, wherein the first adapter plate and the second adapter plate are arranged opposite to each other and are bonded to each other via connection pads;

[0006] A first chip and a second chip are arranged side by side on a side of the first adapter board away from the second adapter board;

[0007] a capacitor disposed between the first adapter plate and the second adapter plate, the capacitor comprising a first electrode plate and a second electrode plate, the first electrode plate being disposed on the first adapter plate, and the second electrode plate being disposed on the second adapter plate; and

[0008] The first insulating layer is filled between the connecting pad, the first electrode plate and the second electrode plate.

[0009] In one embodiment of the present invention, a first solder pad is provided on a side of the first adapter board away from the second adapter board, a first solder ball is provided on the first solder pad, the first chip and the second chip are bonded to the first adapter board through the first solder ball, and a plastic packaging substrate is provided on the bonding surface.

[0010] In one embodiment of the present invention, the first adapter plate includes a plurality of first connection structures, and a first connection pad is provided on the first adapter plate, wherein the first connection pad is connected to the first connection structures at both ends. In one embodiment of the present invention, the first electrode plate is located between the first connection pads, and the first electrode plate is connected to a portion of the first connection structures.

[0011] In one embodiment of the present invention, the second adapter plate includes a plurality of second connection structures, and second connection pads are provided on the second adapter plate, and the second connection pads are connected to the second connection structures at both ends. In one embodiment of the present invention, the second electrode plate is located between the second connection pads, and the second electrode plate is connected to a portion of the second connection structures.

[0012] In one embodiment of the present invention, the first electrode plate and the second electrode plate have the same thickness and area, and the thickness of the first electrode plate or the second electrode plate is 20% to 50% of the thickness of the connecting pad.

[0013] In one embodiment of the present invention, a plastic package base is provided between the first chip and the first adapter board, and between the second chip and the first adapter board, and a second insulating layer is provided on the first chip, the second chip, and the first adapter board.

[0014] In one embodiment of the present invention, a second solder ball is provided on a side of the second adapter plate away from the first adapter plate, a second solder pad is provided between the second solder ball and the second adapter plate, and the second solder ball is provided on the second solder pad.

[0015] The present invention also provides a method for manufacturing an integrated chip packaging structure, which comprises at least the following steps:

[0016] providing a first adapter plate and a second adapter plate;

[0017] forming a first electrode plate and a first connecting pad on one side of the first adapter plate;

[0018] forming a second electrode plate and a second connecting pad on opposite sides of the second adapter plate and the first adapter plate;

[0019] The first adapter plate and the second adapter plate are bonded via the first connecting pad and the second connecting pad, and the first adapter plate and the second adapter plate are arranged opposite to each other;

[0020] Filling a first insulating layer between the connecting pad, the first electrode plate, and the second electrode plate to form a capacitor between the first adapter plate and the second adapter plate, the capacitor including the first electrode plate and the second electrode plate; and

[0021] A first chip and a second chip are bonded and connected to each other on a side of the first transfer board away from the second transfer board.

[0022] In summary, the present invention provides an integrated chip packaging structure and a manufacturing method thereof. By adopting a system-level packaging structure, chips with multiple functions are packaged together in one package body. The packaging structure is the same size as the connecting board, but is smaller in size, thinner in thickness, more integrated in the system, and has better market prospects. A capacitor structure is innovatively added between the bonding surfaces of the two adapter plates, and the capacitors are integrated in three dimensions to ensure that the package size is smaller, the system is more integrated, and the device performance is more superior. The innovative addition of a capacitor structure between the bonding surfaces of the two adapter plates can greatly increase the capacitor area and improve the capacity. The capacitor is closer to the chip itself, shortening the distance from the capacitor to the power supply network, and improving the performance of the packaging structure. A 2.5-dimensional packaging structure is obtained through the bonding between the chip and the adapter plate. The interconnection of signals is achieved through the connection structure in the adapter plate, and the signal is led to the back of the packaging structure, which can simplify the subsequent connection of the integrated chip packaging structure.

[0023] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 FIG. 4 is a schematic diagram of a first adapter board in an embodiment of the present invention.

[0026] Figure 2 Schematic diagram of an embodiment of the present invention and a second adapter board.

[0027] Figure 3 FIG. 1 is a schematic diagram of a thinned first adapter plate according to an embodiment of the present invention.

[0028] Figure 4 FIG. 1 is a schematic diagram of a thinned second adapter plate according to an embodiment of the present invention.

[0029] Figure 5Schematic diagram of forming a first electrode plate and a first connecting pad on a first adapter plate in one embodiment of the present invention.

[0030] Figure 6 Schematic diagram of forming a second electrode plate and a second connecting pad on a second adapter plate in one embodiment of the present invention.

[0031] Figure 7 FIG. 1 is a schematic diagram of forming a capacitor after bonding the first transfer plate and the second transfer plate in one embodiment of the present invention.

[0032] Figure 8 FIG. 1 is a schematic diagram of an integrated chip packaging structure according to an embodiment of the present invention.

[0033] Description of labels:

[0034] 100, first chip; 200, second chip; 10, first adapter board; 20, second adapter board; 101, first connection structure; 102, first solder pad; 103, first electrode; 104, first connection pad; 111, first surface; 112, second surface; 201, second connection structure; 202, second solder pad; 203, second electrode; 204, second connection pad; 211, first surface; 212, second surface; 300, capacitor; 11, first insulating layer; 12, first solder ball; 13, second solder ball; 14, plastic package base; 15, second insulating layer. DETAILED DESCRIPTION

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0036] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0037] In the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like indicate positions or locations based on those shown in the accompanying drawings. These terms are intended solely to facilitate the description of the present application and simplify the description, and are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present application. Furthermore, the terms "first" and "second" are used solely for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0038] See also Figure 8 As shown, the present invention provides an integrated chip packaging structure, comprising at least a first chip 100, a second chip 200, a first adapter plate 10, a second adapter plate 20, and a capacitor 300. The first adapter plate 10 and the second adapter plate 20 are disposed opposite each other and connected via connection pads. The first chip 100 and the second chip 200 are disposed side by side on a side of the first adapter plate 10 away from the second adapter plate 20. The capacitor 300 is disposed between the first adapter plate 10 and the second adapter plate 20, and the first electrode plate 103 of the capacitor 300 is disposed on the first adapter plate 10, and the second electrode plate 203 is disposed on the second adapter plate 20. Both ends of the first electrode plate 103 and the second electrode plate 203 are at a predetermined distance from the first connection pad 104. A first insulating layer 11 is filled between the first electrode plate 103, the second electrode plate 203, and the first connection pad 104. The present invention adopts a system-level packaging structure, where chips with multiple functions are packaged together in one package to form a 2.5-dimensional packaging structure, making the system of the packaging structure more integrated and smaller in size. In addition, a capacitor structure is innovatively added between the bonding surfaces of the two adapter plates, which can greatly increase the capacitor area and improve the capacitance value. The capacitor is closer to the device itself, which can better improve the performance of the device. Specifically, the specific structure of the integrated chip packaging structure of the present application and the manufacturing method of the integrated chip packaging structure are as follows: Figures 1 to 8 The integrated chip packaging structure and its manufacturing method provided in this application can improve the performance of the integrated chip packaging structure and the integration of the packaging system. The integrated chip packaging structure can be widely used in various emerging industries such as information, energy, and communications.

[0039] See also Figure 1 As shown, in one embodiment of the present invention, a first adapter plate 10 is provided. The first adapter plate 10 includes a first surface 111 and a second surface 112. A plurality of first connection structures 101 are provided inside the first adapter plate 10. The first connection structures 101 extend from the first surface 111 into the first adapter plate 10 and have a preset distance from the second surface 112. Figure 1The number and positions of the first connection structures 101 are for example purposes only. The first connection structures 101 may include a conductive material, such as copper, aluminum, or tungsten, or an alloy thereof. A plurality of first solder pads 102 are provided on the first surface 111 of the first adapter board 10. The first solder pads 102 are provided on and connected to the first connection structures 101, and may be made of a conductive material, such as copper, aluminum, or tungsten, or an alloy thereof.

[0040] See also Figure 2 As shown, in one embodiment of the present invention, the present invention further provides a second adapter plate 20, which includes a first surface 211 and a second surface 212. A plurality of second connection structures 201 are provided inside the second adapter plate 20. The second connection structures 201 extend from the first surface 211 into the second adapter plate 20 and have a preset distance from the second surface 212. Figure 2 The number and position of the first connection structures 101 are only for example. The second connection structure 201, for example, includes a conductive material, and the conductive material is, for example, a conductive material or alloy such as copper, aluminum or tungsten. A plurality of second solder pads 202 are provided on the first surface 211 of the second adapter board 20, and the second solder pads 202 are, for example, provided on the second connection structure 201 and connected to the second connection structure 201, wherein the second solder pads 202 are, for example, selected from a conductive material, and for example, a conductive material or alloy such as copper, aluminum or tungsten. Among them, the first adapter board 10 and the second adapter board 20 are, for example, organic adapter boards, silicon-based adapter boards or glass adapter boards, etc., respectively. The present application does not specifically limit the specific types of the first adapter board 10 and the second adapter board 20, as long as the interconnection between signals can be achieved.

[0041] See also Figures 1 to 4As shown, in one embodiment of the present invention, the first adapter plate 10 and the second adapter plate 20 are thinned. Specifically, a temporary carrier (not shown in the figure) is bonded to the first surface 111 of the first adapter plate 10, and wafer thinning is performed from the second surface 112 of the first adapter plate 10 until the first connection structure 101 is exposed. A temporary carrier (not shown in the figure) is bonded to the first surface 211 of the second adapter plate 20, and wafer thinning is performed from the second surface 212 of the second adapter plate 20 until the second connection structure 201 is exposed. The adapter plate is thinned, for example, by etching, mechanical grinding, or chemical mechanical polishing (CMP) and other processes to ensure that the first connection structure 101 and the second connection structure 201 are exposed, so as to facilitate the subsequent interconnection of signals. After thinning, the first connection structure 101 or the second connection structure 201 is flush with the structures on both sides thereof, that is, the second surface 112 of the first adapter plate 10 is flush, and the second surface 212 of the second adapter plate 20 is flush. By bonding a temporary carrier to the first adapter plate 10 and the second adapter plate 20, the strength of the adapter plate can be increased during the thinning process, reducing the possibility of fragmentation. At the same time, after thinning, the mechanical strength of the adapter plate can be enhanced to facilitate subsequent processes.

[0042] See also Figure 3 and Figure 5As shown, in one embodiment of the present invention, after thinning the first adapter plate 10, a first electrode plate 103 and a first connecting pad 104 are formed on the second surface 112 of the first adapter plate 10, and the first electrode plate 103 and the first connecting pad 104 are spaced apart. In this embodiment, the first connecting pad 104 is, for example, located at both ends of the first adapter plate 10, and the first electrode plate 103 is, for example, located between the first connecting pads 104. The first electrode plate 103 and the first connecting pad 104 are, for example, made of the same material, such as copper or other metal materials. The thickness of the first electrode plate 103 is less than the thickness of the first connecting pad 104, and the thickness of the first electrode plate 103 is, for example, 20% to 50% of the thickness of the first connecting pad 104. Specifically, a metal layer (not shown in the figure) is deposited on the second surface 112, and a patterned photoresist layer (not shown in the figure) is formed on the metal layer. For example, a portion of the metal layer is etched to the second surface 112 by dry etching or other methods, and then the etching is stopped. The metal layer is segmented, the patterned photoresist layer is removed, and a new patterned photoresist layer (not shown in the figure) is formed. For example, the metal layer in the middle portion is thinned by dry etching or other methods, thereby forming the first electrode 103 and the first connecting pad 104. In another embodiment of the present invention, for example, after the metal layer is deposited, a photoresist layer is formed on the metal layer, and by controlling the exposure amount at different positions, the thickness of the photoresist layer retained at different positions on the metal layer is different. Therefore, through one etching, part of the metal layer is completely etched, part of the metal layer is etched to a partial thickness, and part of the metal layer is not etched, thereby forming the first electrode 103 and the first connecting pad 104. In another embodiment of the present invention, if the first electrode plate 103 and the first connection pad 104 are made of different materials, they can be prepared by depositing two photoresist layers separately. This application does not limit the specific method of forming the first electrode plate and the connection pad, which can be selected according to manufacturing requirements.

[0043] See also Figure 4 and Figure 6As shown, in one embodiment of the present invention, after thinning the second adapter plate 20, a second electrode plate 203 and a second connecting pad 204 are formed on the second surface 212 of the second adapter plate 20, and the second electrode plate 203 and the second connecting pad 204 are spaced apart. In this embodiment, the second connecting pad 204 is, for example, located at both ends of the second adapter plate 20, and the second electrode plate 203 is, for example, located between the second connecting pads 204. The second electrode plate 203 and the second connecting pad 204 are made of, for example, the same material, such as copper or other metal materials. The thickness of the second electrode plate 203 is less than the thickness of the second connecting pad 204, and the thickness of the second electrode plate 203 is, for example, 20% to 50% of the thickness of the second connecting pad 204. In this embodiment, the thickness of the second electrode plate 203 is, for example, equal to the thickness of the first electrode plate 103, and the second electrode plate 203 and the first electrode plate 103 have the same area. The method for forming the second electrode plate 203 and the second connecting pad 204 on the second adapter plate 20 is, for example, the same as the method for forming the first electrode plate 103 and the first connecting pad 104 on the first adapter plate 10 , and will not be elaborated herein.

[0044] See also Figure 5 and Figure 6 As shown, in one embodiment of the present invention, on the first adapter plate 10, the first connecting pad 104 is connected to the first connecting structure 101 at both ends of the first adapter plate 10, and the first electrode 103 is connected to the first connecting structure 101 in the middle. On the second adapter plate 20, the second connecting pad 204 is connected to the second connecting structure 201 at both ends of the second adapter plate 20, and the second electrode 203 is connected to the second connecting structure 201 in the middle. After subsequent bonding, the first adapter plate 10 and the second adapter plate 20 are bonded through the first connecting pad 104 and the second connecting pad 204, so that signal communication between the subsequently bonded chips can be achieved, and part of the connection structure completes the control of the capacitance.

[0045] See also Figures 5 to 7As shown, in one embodiment of the present invention, after forming the electrode plate and the connecting pad, the first adapter plate 10 and the second adapter plate 20 are placed opposite to each other on the side with the connecting pad, that is, the second surface 112 and the second surface 212, for bonding. The first connecting pad 104 on the first adapter plate 10 and the second connecting pad 204 on the second adapter plate 20 are electrically connected to complete the bonding between the adapter plates. After the bonding is completed, the temporary carriers on the first adapter plate 10 and the second adapter plate 20 are removed. The first adapter plate 10 and the second adapter plate 20 are bonded, for example, by a wafer-to-wafer bonding method. After the first adapter plate 10 and the second adapter plate 20 are bonded, an insulating material with a high dielectric constant is filled between the second adapter plate 20 and the first adapter plate 10 to form a first insulating layer 11. The opposing surfaces of the first adapter plate 10 and the second adapter plate 20 are completely sealed in the first insulating layer 11. The first insulating layer 11 may comprise, for example, ABF (Ajinomoto Build-up Film) material, a low-fill chip filler, or other thermoplastic material, which exhibits a certain degree of fluidity upon heating. The thinner metal layers at the first and second electrode plates 103 and 203 ensure that the fluid three-dimensional insulating material can completely fill the gap between the first and second adapter plates 10 and 20, and finally solidify to form the first insulating layer 11. The present invention bonds the two adapter plates together through wafer bonding to form a large capacitor structure.

[0046] See also Figure 7 As shown, in one embodiment of the present invention, after forming the first insulating layer 11, the first electrode 103, the second electrode 203 and the first insulating layer 11 between the electrodes constitute a capacitor 300. Among them, the first electrode 103 of the capacitor 300 is arranged on the first adapter plate 10, and the second electrode 203 is arranged on the second adapter plate 20. The two ends of the first electrode 103 and the second electrode 203 have a preset distance from the first connecting pad 104. The first electrode 103 and the second electrode 204 are placed in an area where the power supply is concentrated to shorten the distance between the capacitor and the power supply network. In the present invention, an innovative capacitor structure is added between the bonding surfaces of the two adapter plates. The entire capacitor 300 is formed inside the package between the chips. The capacitor is integrated in a three-dimensional direction to ensure that the package size is smaller, the system is more integrated, and the device performance is more superior. The capacitance area can be greatly increased and the capacity can be improved. The capacitor is closer to the chip itself, shortening the distance from the capacitor to the power supply network and improving the performance of the packaging structure. By bonding between the adapter plates, the large capacitor is located between the adapter plates. The entire packaging structure is the same size as the adapter plate, but is smaller in size, thinner in thickness, and has better market prospects.

[0047] See also Figures 7 and 8As shown, in one embodiment of the present invention, after forming the first insulating layer 11, a first solder ball 12 is formed on the first pad 102 of the first adapter board 10. The first solder ball 12 is, for example, a tin-silver ball. The first solder ball 12 is located at the center of the first pad 102, and the first solder ball 12 corresponds to the first pad 102 one-to-one, and the first solder ball 12 is adapted to be electrically connected to the first pad 102. A second solder ball 13 is formed on the second pad 202 of the second adapter board 20. The second solder ball 13 is located at the center of the second pad 202, and the second solder ball 13 corresponds to the second pad 202 one-to-one, and the second solder ball 13 is adapted to be electrically connected to the second pad 202. In this embodiment, the second solder ball 13 is, for example, a tin-silver ball, so as to be used for connecting the integrated chip packaging structure with the subsequent substrate.

[0048] See also Figures 7 and 8 As shown, in one embodiment of the present invention, a first chip 100 is bonded to a portion of the first solder balls 12, and the first chip 100 and the first adapter board 10 are bonded, for example, by a wafer-to-wafer or chip-to-wafer bonding method. A second chip 200 is bonded to a portion of the first solder balls 12 on one side of the first chip 100, and the second chip 200 and the first adapter board 10 are bonded, for example, by a wafer-to-wafer or chip-to-wafer bonding method. The present application does not limit the bonding order of the first chip 100 and the second chip 200. For example, the first chip 100 and the second chip 200 are bonded to the first adapter board 10 at the same time. The present invention does not limit the specific types of the first chip 100 and the second chip 200, and they can be selected according to needs or uses. In this embodiment, the first chip 100 is, for example, a memory chip, and the second chip 200 is, for example, a power chip. In the present application, the first chip 100 and the second chip 200 are arranged side by side on the side of the first adapter board 10 away from the second adapter board 20 to form a 2.5D chip packaging structure. The capacitor 300 is arranged between the first adapter board 10 and the second adapter board 20, that is, the capacitor 300 is integrated in the three-dimensional direction, which can ensure that the package size is smaller, the system is more integrated, and the device performance is more superior. Compared with the traditional SIP (System In a Package) packaging, the packaging structure size of the present application is reduced and the market prospects are better.

[0049] See also Figures 7 and 8As shown, in one embodiment of the present invention, after the first chip 100 and the second chip 200 are bonded to the first adapter board 10, a plastic encapsulation compound is filled between the first adapter board 10, the first chip 100, and the second chip 200 and cured to form a plastic encapsulation matrix 14. The plastic encapsulation matrix 14 may include, for example, epoxy resin, silicone encapsulation compound, or polyurethane encapsulation compound. After the plastic encapsulation matrix 14 is formed, a second insulating layer 15 is formed on the first chip 100, the second chip 200, and the first adapter board 10. The second insulating layer 15 may be, for example, an organic plastic encapsulation material, such as epoxy resin, polyethylene, polypropylene, or polyimide, to prevent circuit short circuits, provide mechanical support, and protect the integrated chip packaging structure from the external environment. The present invention is based on a 2.5-dimensional packaging structure. Corresponding capacitor plates are manufactured between the adapter plates. The two adapter plates are then bonded together through wafer bonding. The capacitor structure is integrated into the packaging structure to obtain a larger capacitance value. At the same time, the signal in the chip is led to the back of the packaging structure through the connection structure and is used as the final output through the second solder ball. This can simplify the subsequent connection of the integrated chip packaging structure and obtain a high-performance, highly integrated chip packaging structure.

[0050] In summary, the present invention provides an integrated chip packaging structure and a manufacturing method thereof. By adopting a system-level packaging structure, chips with multiple functions are packaged together in one package body. The packaging structure is the same size as the connecting board, but is smaller in size, thinner in thickness, more integrated in the system, and has better market prospects. A capacitor structure is innovatively added between the bonding surfaces of the two adapter plates, and the capacitors are integrated in three dimensions to ensure that the package size is smaller, the system is more integrated, and the device performance is more superior. The innovative addition of a capacitor structure between the bonding surfaces of the two adapter plates can greatly increase the capacitor area and improve the capacity. The capacitor is closer to the chip itself, shortening the distance from the capacitor to the power supply network, and improving the performance of the packaging structure. A 2.5-dimensional packaging structure is obtained through the bonding between the chip and the adapter plate. The interconnection of signals is achieved through the connection structure in the adapter plate, and the signal is led to the back of the packaging structure, which can simplify the subsequent connection of the integrated chip packaging structure.

[0051] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the inventive concept, such as the technical solutions formed by the mutual replacement of the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

[0052] Except for the technical features described in the specification, the remaining technical features are known technologies to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be described here in detail.

Claims

1. An integrated chip packaging structure, characterized in that: At least: A first adapter plate and a second adapter plate, wherein the first adapter plate and the second adapter plate are arranged opposite to each other, and the first adapter plate and the second adapter plate are bonded via a connecting pad; A first chip and a second chip are arranged side by side on a side of the first adapter board away from the second adapter board; A capacitor is arranged between the first adapter plate and the second adapter plate, and the capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is arranged on the first adapter plate, and the second electrode plate is arranged on the second adapter plate; as well as The first insulating layer is filled between the connecting pad, the first electrode plate and the second electrode plate.

2. The integrated chip packaging structure according to claim 1, characterized in that: A first solder pad is provided on a side of the first adapter board away from the second adapter board, a first solder ball is provided on the first solder pad, the first chip and the second chip are bonded to the first adapter board via the first solder ball, and a plastic package substrate is provided on the bonding surface.

3. The integrated chip packaging structure according to claim 1, characterized in that: The first adapter board includes a plurality of first connection structures. A first connection pad is disposed on the first adapter board. The first connection pad is connected to the first connection structures at two ends.

4. The integrated chip packaging structure according to claim 3, characterized in that: The first electrode plate is located between the first connecting pads, and the first electrode plate is connected to a portion of the first connecting structure.

5. The integrated chip packaging structure according to claim 1, characterized in that: The second adapter board includes a plurality of second connection structures. The second adapter board is provided with second connection pads, and the second connection pads are connected to the second connection structures at two ends.

6. The integrated chip packaging structure according to claim 5, characterized in that: The second electrode plate is located between the second connecting pads, and the second electrode plate is connected to a portion of the second connecting structure.

7. The integrated chip packaging structure according to claim 1, characterized in that: The first electrode plate and the second electrode plate have the same thickness and area, and the thickness of the first electrode plate or the second electrode plate is 20% to 50% of the thickness of the connecting pad.

8. The integrated chip packaging structure according to claim 1, characterized in that: A plastic package substrate is provided between the first chip and the first adapter board, and between the second chip and the first adapter board, and a second insulating layer is provided on the first chip, the second chip and the first adapter board.

9. The integrated chip packaging structure according to claim 1, characterized in that: A second solder ball is arranged on a side of the second adapter board away from the first adapter board, a second solder pad is arranged between the second solder ball and the second adapter board, and the second solder ball is arranged on the second solder pad.

10. A method for manufacturing an integrated chip packaging structure, characterized in that: At least the following steps are included: Providing a first adapter plate and a second adapter plate; forming a first electrode plate and a first connecting pad on one side of the first adapter plate; forming a second electrode plate and a second connection pad on opposite sides of the second adapter plate and the first adapter plate; The first adapter plate and the second adapter plate are bonded via the first connection pad and the second connection pad, and the first adapter plate and the second adapter plate are arranged opposite to each other; Filling a first insulating layer between the connection pad, the first electrode plate, and the second electrode plate to form a capacitor between the first adapter plate and the second adapter plate, the capacitor comprising the first electrode plate and the second electrode plate; and A first chip and a second chip are bonded and connected to each other on a side of the first adapter board away from the second adapter board.

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