Rapid topology analysis method and system for deflection of single-ended element switch

Abstract

The invention discloses a rapid topology analysis method for single-ended element switch deflection, which comprises the following steps: acquiring a CIM file, analyzing the CIM file into a vertex and edge data set oriented to a graph database, and constructing a node switch graph model of a power grid; solving a network topology by applying a graph division technology to construct a bus branch graph model; acquiring real-time equipment state data, updating the node switch graph model to a real-time state, and traversing associated equipment; if the associated equipment is a single-ended element, generating a first topological node, and mapping the first topological node to a bus branch graph model node by using an optimized graph topology analysis algorithm; if other functional elements are associated, a traditional topology analysis method is used for judgment, a second topology node is generated, and the second topology node is mapped to a bus branch diagram model node; and mapping the first topological node and the second topological node in the bus branch diagram model to the corresponding transmission line and the series compensator node, thereby providing accurate topological information for the operation state of the power grid.

Description

Technical Field

[0001] The present invention relates to the technical field of power topology analysis, and in particular to a method and system for rapid topology analysis of a single-ended element switch position change. Background Art

[0002] In a substation, a single-ended component refers to a device that has only one connection port to other components of the power grid, such as loads, generators, etc. For a single-ended component, the change in its switch state only involves the change in its own connection state, and does not affect the connection state of other devices. The switch devices in the substation node switch graph model are usually operated independently, that is, they can be opened or closed individually without being directly affected by the state of other devices. Therefore, when a switch state changes, the state of other devices is independent of this change. In the power system, the device status is usually updated synchronously, that is, the status is updated at a certain moment, rather than updating different devices at different time points. This makes it possible to directly remove the device with a state change from the overall topology for the status at a specific point in time without having to perform complex in-station topology analysis.

[0003] The topological analysis within a station may involve a large number of devices and complex electrical relationships. However, when dealing with changes in the state of a single device, the calculation can be simplified by considering only the components directly connected to the device, without having to consider the electrical relationships within the entire station. From the perspective of the spatiotemporal changes in the power system, there are usually certain real-time requirements for the response to state changes. Based on the topology of a certain provincial power grid and the statistical analysis of the continuous-time operating state, it can be found that the number of single-ended components associated with the switch state changes accounts for 80%-90% of all switch position devices. In order to respond quickly and accurately to changes in the state of the equipment, the proposed simplified processing method helps to improve the real-time performance of the system. Summary of the invention

[0004] In view of the above-mentioned problems, the present invention is proposed.

[0005] Therefore, the technical problem solved by the present invention is: the present invention solves the complexity of the topological analysis of the switch displacement of a single-ended component. The traditional power system topological analysis needs to consider a large number of devices and complex electrical connection relationships, resulting in high calculation costs, and the existing topological analysis methods cannot meet the real-time requirements and have a high topological error rate.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a method for rapid topological analysis of a single-ended element switch position change, comprising:

[0008] Obtain a CIM file, parse the CIM file into vertex and edge data sets for a graph database, and construct a node switch graph model of a power grid based on the vertex and edge data sets;

[0009] Based on the node switch graph model, the graph partitioning technology is applied to solve the network topology, and the bus branch graph model is constructed according to the solution result;

[0010] Acquire real-time device status data, and update the node switch graph model to a real-time state according to the real-time device status data, so that the structure of the bus branch graph model changes synchronously, and traverse the associated devices with switch status changes;

[0011] If the associated device is a single-ended component, a first topological node is generated, and the first topological node is mapped to a bus branch graph model node using an optimized graph topology analysis algorithm;

[0012] If other functional elements are associated, a traditional topological analysis method is used to make a judgment, generate a second topological node, and map the second topological node to a bus branch graph model node;

[0013] The first and second topological nodes in the bus branch diagram model are mapped to corresponding transmission lines and series compensator nodes.

[0014] As a preferred solution of the single-ended element switch position fast topology analysis method of the present invention, the application of graph partitioning technology to solve the network topology includes:

[0015] Calculating busbar search and island search separately includes:

[0016] Computational bus search: Starting from the node switch graph, the node switch graph is divided into multiple subgraphs using the graph partitioning algorithm. In the process of node switch graph partitioning, the key edges connecting different subgraphs are identified as computational buses;

[0017] Electrical island search: Starting from the computing bus, a set of computing buses connected by computing branches is constructed, that is, the network model of each computing bus subgraph. The network structure and connection characteristics of each computing bus subgraph are analyzed, and electrical islands are identified based on the network structure and connection characteristics.

[0018] As a preferred solution of the single-ended element switch position rapid topology analysis method of the present invention, the bus branch diagram model includes:

[0019] Select all devices and name each device as a local variable of the topology node. The value of the topology node is equal to the connection node number. Each connection node number is unique.

[0020] Select all connected nodes connected to all devices and name each connected node as a local variable of the topology node;

[0021] Loop through all devices and connection nodes and process them. In each loop, if the devices are connected through connection nodes, the values ​​of the topological nodes of the devices and connection nodes are the same.

[0022] If the devices are not connected through the connection node, set the value of the topology node that is different between the device and the connection node;

[0023] The bus branch model is obtained based on the results.

[0024] As a preferred solution of the single-ended element switch position fast topology analysis method of the present invention, wherein: updating the node switch graph model to a real-time state according to the real-time device state data comprises:

[0025] For the node switch graph model of all substations, the transmission lines, transformers, and series compensators are processed in turn, each unprocessed transmission line or each transformer and series compensator is identified, and a first judgment is made on the connection status of both ends.

[0026] As a preferred solution of the single-ended element switch position fast topology analysis method of the present invention, the first judgment includes:

[0027] If each untreated transmission line or both ends of each transformer and series compensator are connected, the relevant substations are evaluated based on the untreated busbars and connected nodes in the node switch graph model;

[0028] If there are unprocessed busbars, the neighboring nodes of each unprocessed busbar are identified, and if the neighboring nodes are circuit breakers or disconnectors, the type of equipment remotely associated with the neighboring nodes is determined.

[0029] As a preferred solution of the single-ended component switch position rapid topology analysis method of the present invention, if the associated device is a single-ended component, it includes:

[0030] If the remote associated device is a single-ended component, the single-ended component generates a unique first topology node for the bus and maps the topology node to a bus branch graph model node.

[0031] As a preferred solution of the single-ended component switch position rapid topology analysis method of the present invention, if other functional components are associated, the associated functional components include:

[0032] If the remote device is another functional element, then evaluate whether the connection relationship between the node and the bus is closed or whether the node is a connection node;

[0033] If it is closed or the node is a connection node, the topological node ID of the bus node is copied to this node;

[0034] If the node is disconnected or not connected, a traditional graph topology analysis method is used to make a judgment, generate a unique second topology node for the corresponding device, and map the second topology node to the bus branch graph model node.

[0035] In a second aspect, the present invention provides a system for rapid topological analysis of switch position changes of a single-ended element, comprising:

[0036] A node switch graph model construction module is used to obtain a CIM file, parse the CIM file into vertex and edge data sets for a graph database, and construct a node switch graph model of a power grid based on the vertex and edge data sets;

[0037] A bus branch graph model construction module is used to solve the network topology based on the node switch graph model by applying the graph partitioning technology, and to construct the bus branch graph model according to the solution result;

[0038] A traversal module is used to obtain real-time device status data, and update the node switch graph model to a real-time state according to the real-time device status data, so that the structure of the bus branch graph model changes synchronously, and the associated devices with the switch status changes are traversed;

[0039] A first mapping module, configured to generate a first topological node if the associated device is a single-ended component, and map the first topological node to a bus branch graph model node using an optimized graph topology analysis algorithm;

[0040] A second mapping module is used to use a traditional topological analysis method to make a judgment if other functional elements are associated, generate a second topological node, and map the second topological node to a bus branch graph model node;

[0041] The third mapping module is used to map the first topological node and the second topological node in the bus branch diagram model to corresponding transmission lines and series compensator nodes.

[0042] In a third aspect, the present invention provides a computing device, comprising:

[0043] Memory and processor;

[0044] The memory is used to store computer executable instructions, and the processor is used to execute the computer executable instructions. When the computer executable instructions are executed by the processor, the steps of the single-ended component switch position fast topology analysis method are implemented.

[0045] In a fourth aspect, the present invention provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the steps of the single-ended element switch position fast topology analysis method.

[0046] Beneficial effects of the present invention: The single-ended element switch position fast topology analysis method proposed in the present invention pays special attention to the functional consideration of the element when maintaining the dynamic graph, ensuring that the number of nodes and edges of the busbar branch graph model remains stable during the state change of the element, thereby optimizing the accuracy and execution efficiency of the topology analysis. In this way, the algorithm can efficiently capture the time sequence changes of the switch state, adapt to the characteristics of different types of elements in the power system, and provide accurate topology information for the operating status of the power grid. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0048] Figure 1 An overall flow chart of a method for rapid topological analysis of a single-ended element switch position change provided by the present invention;

[0049] Figure 2 A schematic diagram of a node switch graph model of a single-ended element switch position rapid topology analysis method provided by the present invention;

[0050] Figure 3 A schematic diagram of a busbar routing diagram model for a single-ended element switch position rapid topology analysis method provided by the present invention. DETAILED DESCRIPTION

[0051] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0052] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0053] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0054] The present invention is described in detail with reference to schematic diagrams. When describing the embodiments of the present invention, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0055] At the same time, in the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "upper, lower, inner and outer" are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present invention. In addition, the terms "first, second or third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0056] In the present invention, unless otherwise clearly specified and limited, the terms "install, connect, connect" should be understood in a broad sense, for example: it can be a fixed connection, a detachable connection or an integral connection; it can also be a mechanical connection, an electrical connection or a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0057] Example 1

[0058] Reference Figure 1-3 , as an embodiment of the present invention, provides a single-ended element switch position change fast topology analysis method, comprising:

[0059] S100: Acquire a CIM file, parse the CIM file into vertex and edge data sets for a graph database, and build a node switch graph model of a power grid based on the vertex and edge data sets;

[0060] Specifically, data model loading includes data conversion and import of CIM files, automatically parsing CIM files into vertex and edge data sets for the graph database, storing them in the graph database, and automatically loading to generate a node switch graph model of the power grid. According to the model definition, data sets of various vertices such as region, reference voltage, plant station, voltage level, bus segment synchronous generator, AC line, AC line segment, AC line endpoint, DC line, DC line endpoint, converter, load, transformer, transformer winding, transformer tap type, shunt compensator, series compensator, interval, etc. can be directly extracted from the CIM file, and each type of vertex data set forms an independent data file.

[0061] For example, Figure 2 As shown, a data set represented by a regional power grid graph model G=(V,E), where V is a vertex set, each vertex represents a node in the power grid, and E is an edge set, where each edge represents a power connection between two nodes.

[0062] It should be noted that the automated data conversion and import process reduces manual operations, improves the efficiency of data processing, ensures data consistency and accuracy, stores data in a graph database, facilitates complex network analysis and query, and independent data files make data easier to manage and update.

[0063] S200: Based on the node switch graph model, the graph partitioning technology is applied to solve the network topology, and the bus branch graph model is constructed according to the solution result;

[0064] In the embodiment of the present application, respectively calculating the bus search and the electrical island search includes:

[0065] Computational bus search: Starting from the node switch graph, the node switch graph is divided into multiple subgraphs using the graph partitioning algorithm. In the process of node switch graph partitioning, the key edges connecting different subgraphs are identified as computational buses;

[0066] Electrical island search: Starting from the computing bus, a set of computing buses connected by computing branches is constructed, that is, the network model of each computing bus subgraph. The network structure and connection characteristics of each computing bus subgraph are analyzed, and electrical islands are identified based on the network structure and connection characteristics.

[0067] Specifically, the graph partitioning technology is applied to solve the network topology, and the computational bus search and electrical island search are completed respectively. The computational bus is a subgraph of G. Each vertex in the subgraph can be connected through the edges where the closed switches and knife switches are located, and cannot cross branch components such as transformers and lines. The electrical island is a collection of computational buses connected by computational branches, and is also a subgraph of the computational bus model graph.

[0068] In the embodiment of the present application, all devices are selected, and a local variable named as a topological node is given to each device. The value of the topological node is equal to the connection node number, and the number of each connection node is unique;

[0069] Select all connected nodes connected to all devices and name each connected node as a local variable of the topology node;

[0070] Loop through all devices and connection nodes and process them. In each loop, if the devices are connected through connection nodes, the values ​​of the topological nodes of the devices and connection nodes are the same.

[0071] If the devices are not connected through the connection node, set the value of the topology node that is different between the device and the connection node;

[0072] The bus branch model is obtained based on the results.

[0073] Specifically, Figure 3 As shown, the calculation bus is connected through branch elements such as transformers and lines. Starting from the transformer and line vertices, the node vertices at both ends are searched along the outgoing edge, and the corresponding calculation bus vertices are found. The edges of the corresponding calculation branch types are added to the graph database, and the vertices on both sides of the edge are the obtained calculation buses.

[0074] First, the calculated busbars are extracted from the node switch diagram, and then these calculated busbars are connected through branch elements such as transformers and lines to form the final busbar branch model diagram.

[0075] Specifically, the bus branch graph model uses custom topological nodes and topological connection structures to store the attributes required for analysis and calculation. The topological nodes include topological analysis related attributes, including topological ID, external ID (used to calculate bus sorting), island flag and bus name.

[0076] Attributes related to the power flow state estimation calculation include bus type, weight of voltage state estimation, voltage level, and measurement and estimation information (including voltage amplitude, voltage phase angle, generator active power, generator reactive power, load active power, load reactive power, bus active injection, bus reactive injection).

[0077] Topology connectivity is available for all device types, storing properties such as initial and final topology node IDs, resistance, reactance, nanometers, class 1-3 capacities, transformer turns ratios, and line measurements and estimates.

[0078] It should be noted that when maintaining dynamic graphs, special attention is paid to component functionality considerations to ensure that the number of nodes and edges in the bus branch graph model remains stable as the component states change, thereby optimizing the accuracy and execution efficiency of topological analysis.

[0079] S300: Acquire real-time device status data, and update the node switch graph model to the real-time state according to the real-time device status data, so that the structure of the bus branch graph model changes synchronously, and traverse the associated devices with the switch status change;

[0080] In the embodiment of the present application, for the node switch graph model of all substations, the transmission lines, transformers, and series compensators are processed in sequence, each unprocessed transmission line or each transformer and series compensator is identified, and a first judgment is made on the connection status of both ends;

[0081] The first judgment includes: if both ends of each untreated transmission line or each transformer and series compensator are connected, evaluating the relevant substation according to the untreated busbar and the connected node in the node switch graph model;

[0082] If there are unprocessed buses, identify the neighboring nodes of each unprocessed bus, and if the neighboring node is a circuit breaker or a disconnector, determine the type of equipment remotely associated with the neighboring node;

[0083] Specifically, according to the time-series changes of the grid switch state, the grid node switch graph model is updated to the real-time state, the generated bus branch graph model structure will change, and the associated devices with the switch state changes will be traversed;

[0084] Initialize the node switch graph model, update the switch status according to the real-time device status data, synchronize with the node switch graph model, and initialize the definition of the bus branch graph model to be generated;

[0085] It should be noted that by updating the power grid model in real time, potential problems can be discovered and dealt with in a timely manner, reducing the risk of failures. The use of real-time data can help power grid operators manage the power grid more effectively, such as optimizing load distribution, reducing energy waste, quickly identifying fault points and affected equipment, and speeding up fault handling and power grid recovery.

[0086] S400: If the associated device is a single-ended component, generate a first topology node, and map the first topology node to a bus branch graph model node using an optimized graph topology analysis algorithm;

[0087] In an embodiment of the present application, if the remote associated device is a single-ended component, the single-ended component generates a unique first topological node for the bus and maps the topological node to a bus branch graph model node.

[0088] Specifically, for single-ended components, the algorithm directly maps its associated bus to the topological nodes of the bus branch graph model, avoiding the complexity of traditional topological analysis of the state changes of such components.

[0089] S500: If other functional elements are associated, a traditional topology analysis method is used to make a judgment, generate a second topology node, and map the second topology node to a bus branch diagram model node.

[0090] Specifically, for other functional elements, the algorithm uses traditional graph topology analysis methods for judgment, conversion and mapping.

[0091] S600: Mapping a first topological node and a second topological node in the bus branch diagram model to corresponding transmission lines and series compensator nodes;

[0092] It should be noted that the algorithm pays special attention to the functional consideration of components when maintaining the dynamic graph, ensuring that the number of nodes and edges of the bus branch graph model remains stable during the state change of the components, thereby optimizing the accuracy and execution efficiency of the topological analysis. In this way, the algorithm can efficiently capture the temporal changes of the switch state, adapt to the characteristics of different types of components in the power system, and provide accurate topological information for the operating status of the power grid.

[0093] The above is a schematic scheme of a method for rapid topological analysis of a single-ended component switch position change in this embodiment. It should be noted that the technical scheme of the device for rapid topological analysis of a single-ended component switch position change and the technical scheme of the method for rapid topological analysis of a single-ended component switch position change belong to the same concept, and the details of the technical scheme of the device for rapid topological analysis of a single-ended component switch position change in this embodiment that are not described in detail can all be referred to the description of the technical scheme of the method for rapid topological analysis of a single-ended component switch position change.

[0094] The device for rapid topological analysis of switch position change of a single-ended element in this embodiment includes:

[0095] A node switch graph model construction module is used to obtain a CIM file, parse the CIM file into vertex and edge data sets for a graph database, and construct a node switch graph model of a power grid based on the vertex and edge data sets;

[0096] A bus branch graph model construction module is used to solve the network topology based on the node switch graph model by applying the graph partitioning technology, and to construct the bus branch graph model according to the solution result;

[0097] A traversal module is used to obtain real-time device status data, and update the node switch graph model to a real-time state according to the real-time device status data, so that the structure of the bus branch graph model changes synchronously, and the associated devices with the switch status changes are traversed;

[0098] A first mapping module, configured to generate a first topological node if the associated device is a single-ended component, and map the first topological node to a bus branch graph model node using an optimized graph topology analysis algorithm;

[0099] A second mapping module is used to use a traditional topological analysis method to make a judgment if other functional elements are associated, generate a second topological node, and map the second topological node to a bus branch graph model node;

[0100] The third mapping module is used to map the first topological node and the second topological node in the bus branch diagram model to corresponding transmission lines and series compensator nodes.

[0101] This embodiment also provides a computing device suitable for fast topological analysis of single-ended element switch position changes, including:

[0102] A memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute computer executable instructions to implement the method for fast topological analysis of single-ended element switch displacement as proposed in the above embodiment.

[0103] This embodiment also provides a storage medium on which a computer program is stored. When the program is executed by a processor, the method for realizing fast topological analysis of switch displacement of a single-ended element as proposed in the above embodiment is implemented.

[0104] The storage medium proposed in this embodiment and the method for realizing fast topological analysis of single-ended element switch position change proposed in the above embodiment belong to the same inventive concept. The technical details not fully described in this embodiment can be referred to the above embodiment, and this embodiment has the same beneficial effects as the above embodiment.

[0105] Through the above description of the implementation methods, the technicians in the relevant field can clearly understand that the present invention can be implemented by means of software and necessary general hardware, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ReadOnly, Memory, ROM), random access memory (RandomAccess Memory, RAM), flash memory (FLASH), hard disk or optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform the methods of various embodiments of the present invention.

[0106] Example 2

[0107] Referring to Table 1-2, different from the first embodiment, a verification test of a single-ended component switch displacement rapid topology analysis method is provided to verify and illustrate the technical effects adopted in the method.

[0108] Based on the original data provided by a provincial grid, a certain time section was selected for verification analysis. The probability of unit and load topology errors in the original data was 6.26% and 13%, respectively, as shown in Table 1.

[0109] Table 1 Original topology error identification

[0110] unit load Total number of devices 703 47723 Connection Error 44 6204 Error rate 6.26％ 13.0％

[0111] Using the algorithm proposed in this method to perform topology verification and correction, the topology error rate can be reduced to 1.28% and 3.61%, as shown in Table 2;

[0112] Table 2 Error identification after fast topological analysis of switch position change

[0113] unit load Total number of devices 703 47723 Connection Error 9 1723 Error rate 1.28％ 3.61％

[0114] From Table 1 and Table 2, we can see that after using the algorithm, the topology error rate of the unit is reduced to 1.28%, the number of errors is reduced from 44 to 9, and the topology error rate of the load is reduced to 3.61%, and the number of errors is reduced from 6204 to 1723.

[0115] Through algorithm verification and correction, the topology error rates of both units and loads have been significantly reduced, which helps improve the operating efficiency and reliability of the power grid. The lower error rate means less manual intervention is required to identify and repair topology errors, thereby reducing maintenance costs.

[0116] The current correction algorithm repairs the topology error by operating the switches and circuit breakers connected to the single-ended element that produces the mismatch between telesignaling and telemetering. If the single-ended element (unit, load) has measurement but the switch is disconnected, the switch or circuit breaker connected to it can be merged to repair the error. If the error does not come from the telesignal error of the switching switch of the single-ended element, but from the topology error on the high-voltage side of the transformer, it cannot be repaired by only correcting the telesignal of the switching switch. Therefore, correcting the telesignal status of the switching switch device can solve most topology errors, but cannot solve complex topology errors on the high-voltage side.

[0117] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A method for rapid topological analysis of switch displacement of a single-ended element, characterized in that: include: Obtain a CIM file, parse the CIM file into vertex and edge data sets for a graph database, and construct a node switch graph model of a power grid based on the vertex and edge data sets; Based on the node switch graph model, the graph partitioning technology is applied to solve the network topology, and the bus branch graph model is constructed according to the solution result; Acquire real-time device status data, and update the node switch graph model to a real-time state according to the real-time device status data, so that the structure of the bus branch graph model changes synchronously, and traverse the associated devices with switch status changes; If the associated device is a single-ended component, a first topological node is generated, and the first topological node is mapped to a bus branch graph model node using an optimized graph topology analysis algorithm; If other functional elements are associated, a traditional topological analysis method is used to make a judgment, generate a second topological node, and map the second topological node to a bus branch graph model node; The first and second topological nodes in the bus branch diagram model are mapped to corresponding transmission lines and series compensator nodes.

2. The single-ended element switch displacement fast topology analysis method according to claim 1, characterized in that: Applying graph partitioning technology to solve network topology includes: Calculating busbar search and island search separately includes: Computational bus search: Starting from the node switch graph, the node switch graph is divided into multiple subgraphs using the graph partitioning algorithm. In the process of node switch graph partitioning, the key edges connecting different subgraphs are identified as computational buses; Electrical island search: Starting from the computing bus, a set of computing buses connected by computing branches is constructed, that is, the network model of each computing bus subgraph. The network structure and connection characteristics of each computing bus subgraph are analyzed, and electrical islands are identified based on the network structure and connection characteristics.

3. The single-ended element switch displacement fast topology analysis method according to claim 2, characterized in that: The bus branch diagram model includes: Select all devices and name each device as a local variable of the topology node. The value of the topology node is equal to the connection node number. Each connection node number is unique. Select all connected nodes connected to all devices and name each connected node as a local variable of the topology node; Loop through all devices and connection nodes and process them. In each loop, if the devices are connected through connection nodes, the values ​​of the topological nodes of the devices and connection nodes are the same. If the devices are not connected through the connection node, set the value of the topology node that is different between the device and the connection node; The bus branch model is obtained based on the results.

4. The single-ended element switch displacement fast topology analysis method according to claim 3, characterized in that: Updating the node switch graph model to a real-time state according to the real-time device state data comprises: For the node switch graph model of all substations, the transmission lines, transformers, and series compensators are processed in turn, each unprocessed transmission line or each transformer and series compensator is identified, and a first judgment is made on the connection status of both ends.

5. The single-ended element switch displacement fast topology analysis method according to claim 4, characterized in that: The first judgment includes: If each untreated transmission line or both ends of each transformer and series compensator are connected, the relevant substations are evaluated based on the untreated busbars and connected nodes in the node switch graph model; If there are unprocessed busbars, the neighboring nodes of each unprocessed busbar are identified, and if the neighboring nodes are circuit breakers or disconnectors, the type of equipment remotely associated with the neighboring nodes is determined.

6. The single-ended element switch displacement rapid topology analysis method according to claim 5, characterized in that: If the associated device is a single-ended component, it includes: If the remote associated device is a single-ended component, the single-ended component generates a unique first topology node for the bus and maps the topology node to a bus branch graph model node.

7. The single-ended element switch displacement rapid topology analysis method according to claim 5 or 6, characterized in that: If other functional elements are associated, they include: If the remote device is another functional element, then evaluate whether the connection relationship between the node and the bus is closed or whether the node is a connection node; If it is closed or the node is a connection node, the topological node ID of the bus node is copied to this node; If the node is disconnected or not connected, a traditional graph topology analysis method is used to make a judgment, generate a unique second topology node for the corresponding device, and map the second topology node to the bus branch graph model node.

8. A system for a fast topological analysis method of a single-ended element switch displacement, characterized in that: include: A node switch graph model construction module is used to obtain a CIM file, parse the CIM file into vertex and edge data sets for a graph database, and construct a node switch graph model of a power grid based on the vertex and edge data sets; A bus branch graph model construction module is used to solve the network topology based on the node switch graph model by applying the graph partitioning technology, and to construct the bus branch graph model according to the solution result; A traversal module is used to obtain real-time device status data, and update the node switch graph model to a real-time state according to the real-time device status data, so that the structure of the bus branch graph model changes synchronously, and the associated devices with the switch status changes are traversed; A first mapping module, configured to generate a first topological node if the associated device is a single-ended component, and map the first topological node to a bus branch graph model node using an optimized graph topology analysis algorithm; A second mapping module is used to use a traditional topological analysis method to make a judgment if other functional elements are associated, generate a second topological node, and map the second topological node to a bus branch graph model node; The third mapping module is used to map the first topological node and the second topological node in the bus branch diagram model to corresponding transmission lines and series compensator nodes.

9. An electronic device, characterized in that: The device comprises: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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