Driving circuit, power conversion circuit and power tube driver

Abstract

The invention relates to the technical field of driving circuits, in particular to a driving circuit, a power conversion circuit and a power tube driver. The driving circuit comprises a first transistor, a second transistor, a third transistor, a driving control circuit and a voltage refresh circuit. The drive control circuit outputs a first control signal and a second control signal to control the first transistor and the second transistor to be alternately turned on and turned off, so that the voltage of the control electrode of the third transistor is controlled to be increased or decreased, and the third transistor is controlled to be turned on and turned off. The voltage refresh circuit pulls down the voltages at the control electrodes of the first transistor and the second transistor respectively to release charges accumulated at the control electrodes of the first transistor and the second transistor due to ringing, so that the voltages at the control electrodes of the first transistor and the second transistor are refreshed to target values. Therefore, the first control signal and the second control signal can accurately control the action of the third transistor so as to ensure the normal work of the driving circuit.

Description

Technical Field

[0001] The present application relates to the technical field of drive circuits, and in particular to a drive circuit, a power conversion circuit, and a power tube driver. Background Art

[0002] In the technical field of power conversion circuits, a driving circuit is usually required to drive the high-side power tube to be turned on and off, so as to adjust the output power of the power conversion circuit.

[0003] In the related art, since parasitic inductance usually exists in the circuit, ringing phenomenon will occur in the driving circuit during the current signal transmission process, and the ringing phenomenon will cause a certain amount of charge accumulation in the driving circuit. When the charge accumulates to a certain extent, the amount of charge stored in the driving circuit exceeds the charge change brought by the control signal, that is, the potential adjustment amount of the control signal on a certain control node will be affected by the accumulated charge, resulting in the voltage value of the control node cannot be accurately adjusted to the target voltage value, thereby affecting the control accuracy of the driving circuit, making the driving work of the driving circuit invalid, and ultimately causing the circuit to malfunction. Summary of the invention

[0004] The present application provides a driving circuit, a power conversion circuit and a power tube driver to solve the technical problem in the related art that the ringing phenomenon affects the control accuracy of the driving circuit, and realizes continuous refreshing of the potential of the control node, so that the potential of the control node is always clamped to the target voltage value, thereby ensuring that the control signal can accurately control the normal operation of each device, thereby ensuring the normal operation of the circuit.

[0005] In a first aspect, the present application provides a driving circuit, the driving circuit comprising: a first transistor, a second transistor, a third transistor, a driving control circuit and a voltage refresh circuit;

[0006] The drive control circuit comprises an input terminal, a first output terminal and a second output terminal, wherein the input terminal of the drive control circuit is used to receive a drive control signal, the drive control circuit is used to perform signal processing on the drive control signal to generate a first control signal and a second control signal with opposite logical states, and the first output terminal and the second output terminal are used to output the first control signal and the second control signal, respectively;

[0007] The first output terminal of the drive control circuit is connected to the first electrode of the first transistor, and the second electrode of the first transistor is used to be connected to the output terminal of the power supply circuit; the second output terminal of the drive control circuit is connected to the first electrode of the second transistor, and the second electrode of the second transistor is also used to be connected to the output terminal of the power supply circuit; the first output terminal of the drive control circuit is also connected to the control electrode of the second transistor, and the second output terminal of the drive control circuit is also connected to the control electrode of the first transistor;

[0008] The second output terminal of the drive control circuit is also connected to the control electrode of the third transistor, the first electrode of the third transistor is used to be connected to the output terminal of the power supply circuit, and the second electrode of the third transistor is used to output a switch control signal;

[0009] The voltage refresh circuit includes a refresh control circuit, a first current source branch and a second current source branch; the input end of the first current source branch is connected to the first electrode of the first transistor, and the input end of the second current source branch is connected to the first electrode of the second transistor;

[0010] The refresh control circuit is used to collect the driving voltage signal and the switch control signal on the control electrode of the third transistor, and determine whether the voltage difference between the driving voltage signal and the switch control signal is greater than or equal to the threshold voltage of the third transistor, and if so, generate a first refresh control signal; if not, generate a second refresh control signal;

[0011] The first refresh control signal is used to control the first current source branch to be turned on to form a current loop, thereby pulling the voltage at the first pole of the first transistor down to a first voltage value; the second refresh control signal is used to control the second current source branch to be turned on to form a current loop, thereby pulling the voltage at the first pole of the second transistor down to a second voltage value.

[0012] In one possible design, the refresh control circuit includes a comparator and a control unit;

[0013] The non-inverting input terminal of the comparator is connected to the control electrode of the third transistor to collect the driving voltage signal on the control electrode of the third transistor; the inverting input terminal of the comparator is connected to the second electrode of the third transistor to collect the switch control signal; the comparator is used to compare whether the voltage difference between the driving voltage signal and the switch control signal is greater than or equal to the threshold voltage of the third transistor, and output a first comparison signal;

[0014] The control unit is used to generate the first refresh control signal or the second refresh control signal according to the logic state of the first comparison signal.

[0015] In one possible design, the drive control circuit includes a first inverter, a second inverter, a buffer, a first capacitor, and a second capacitor;

[0016] The output end of the first inverter is connected to the input end of the buffer, the output end of the buffer is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the first electrode of the first transistor; the input end of the first inverter is the input end of the drive control circuit, and the second end of the first capacitor is the first output end of the drive control circuit;

[0017] The output end of the first inverter is also connected to the input end of the second inverter, the output end of the second inverter is connected to the first end of the second capacitor, the second end of the second capacitor is connected to the first electrode of the second transistor, and the second end of the second capacitor is the second output end of the drive control circuit.

[0018] In one possible design, the refresh control circuit includes a first control signal output terminal and a second control signal output terminal;

[0019] The first control signal output terminal is used to output a first refresh control signal, and the second control signal output terminal is used to output the second refresh control signal.

[0020] In one possible design, the first current source branch includes a first current source and a first switch tube; the output end of the first current source is grounded, the input end of the first current source is connected to the first electrode of the first switch tube, the second electrode of the first switch tube is the input end of the first current source branch, and the second electrode of the first switch tube is connected to the first electrode of the first transistor; the first control signal output end is connected to the control electrode of the first switch tube.

[0021] In one possible design, the second current source branch includes a second current source and a second switch tube; the output end of the second current source is grounded, the input end of the second current source is connected to the first electrode of the second switch tube, the second electrode of the second switch tube is the input end of the second current source branch, and the second electrode of the second switch tube is connected to the first electrode of the second transistor; the second control signal output end is connected to the control electrode of the second switch tube.

[0022] In one possible design, the driving circuit includes a power supply circuit, an input end of the power supply circuit is used to connect to a power supply, and an output end of the power supply circuit is used to output a power supply voltage.

[0023] In a second aspect, the present application also provides a power conversion circuit, which includes the driving circuit as described above.

[0024] In a third aspect, the present application also provides a power tube driver, which includes the driving circuit as described above.

[0025] In a fourth aspect, the present application also provides a power conversion device, which includes the driving circuit as described above.

[0026] Through the driving circuit provided by the first aspect above, the first control signal and the second control signal are outputted respectively through the driving control circuit to control the first transistor and the second transistor to be alternately turned on and off, so as to control the voltage of the control electrode of the third transistor to be pulled up or down, so as to control the third transistor to be turned on and off. In each working cycle, the voltage refresh circuit can pull down the voltage at the control electrode of the first transistor and the second transistor respectively to release the charge accumulated at the control electrode of the first transistor and the second transistor due to ringing, so as to ensure that in each cycle, the voltage at the control electrode of the first transistor and the second transistor is refreshed to the target value, so as to ensure that the first control signal and the second control signal can accurately control the action of the third transistor, so as to ensure the normal operation of the driving circuit.

[0027] The beneficial effects provided in the above-mentioned second aspect and various possible designs of the above-mentioned second aspect can refer to the beneficial effects brought about by the above-mentioned first aspect and various possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of a driving circuit structure provided for the related technology of the embodiment of the present application;

[0029] Figure 2 One of the waveform diagrams of the voltage signal and current signal inside the driving circuit provided in the present application;

[0030] Figure 3 A schematic diagram of a driving circuit structure provided in an embodiment of the present application;

[0031] Figure 4 This is the second waveform diagram of each voltage signal and current signal inside the driving circuit of the present application. DETAILED DESCRIPTION

[0032] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0033] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0034] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0035] The transistor in the present application is a three-terminal transistor, and its three terminals are a control electrode, a first electrode, and a second electrode. The transistor can be a bipolar transistor or a field effect transistor, etc. For example, when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or collector of the bipolar transistor; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor. In addition, the switch tube in the present application may also be a three-terminal switch tube, whose three terminals are a control electrode, a first electrode and a second electrode. When the switch tube is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, and the corresponding second electrode may be the emitter or collector of the bipolar transistor; when the switch tube is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, and the corresponding second electrode may be the source or drain of the field effect transistor.

[0036] Ringing refers to a periodic oscillation phenomenon that occurs in a circuit or system, usually with multiple harmonic components, a certain amplitude and frequency. This phenomenon is often caused by the presence of a feedback loop in the circuit or system, which causes the signal to be repeatedly amplified and act on the input end again after passing through the loop, resulting in oscillation and distortion of the output signal. The appearance of ringing can affect the normal operation of the circuit or system, leading to problems such as signal distortion, increased errors, and reduced system stability.

[0037] Ringing phenomenon can usually be caused by a variety of factors, the most common of which is parasitic inductance. Parasitic inductance usually exists in the circuit, so during the current signal transmission, ringing phenomenon will occur in the driving circuit. The ringing phenomenon will cause a certain amount of charge accumulation in the driving circuit. When the charge accumulates to a certain extent, the amount of charge stored in the driving circuit exceeds the amount of charge change caused by the control signal, resulting in the voltage value of the control node cannot be accurately adjusted to the target voltage value, thereby affecting the control accuracy of the driving circuit.

[0038] In order to overcome the impact of ringing on the circuit, the relevant technology usually adopts the method of optimizing the layout of various components on the circuit board. For example, in the case of a long transmission line or a large number of high-speed logic gate circuits in the circuit, the occurrence of ringing can be reduced by optimizing the PCB (Printed Circuit Board) layout, such as strengthening the power supply and grounding, shortening the signal transmission line, etc. In addition, for digital controllers, the ringing phenomenon can be eliminated by parameter selection method or ringing factor elimination method. For example, the inertia time constant and sampling period of the expected closed-loop transfer function can be reasonably selected, or the factors that cause the ringing phenomenon in the digital controller can be found and these factors can be artificially eliminated to change the dynamic characteristics of the digital controller, thereby suppressing the ringing phenomenon.

[0039] However, after testing in actual application scenarios, it was found that the method of optimizing PCB layout provided in the relevant technology has a limited effect on eliminating ringing phenomena. In a complex circuit structure, the method of optimizing PCB layout still cannot solve the way of charge accumulation in the circuit. As a result, after the circuit has worked for multiple cycles, when the charge accumulates to a certain level, it will still affect the voltage of the control node in the circuit, thereby affecting the regulation of the control node potential, causing the driving circuit to fail and ultimately causing the circuit to malfunction.

[0040] Figure 1 A schematic diagram of a driving circuit structure provided by the related technology of the embodiment of the present application is shown in FIG. Figure 1As shown, the driving circuit includes a transistor M1, a transistor M2, a transistor M3, an inverter INV11, an inverter INV12, a buffer Buf10, a capacitor C10 and a capacitor C20. The power supply terminal PAD_V0 is connected to an external power supply, L1 is a parasitic inductance in the circuit, and V0 is a power supply terminal inside the driving circuit, and the power supply terminal V0 is used to connect internal components. The output end of the control signal receiving terminal HSD_VIN is connected to the input end of the inverter INV11, the output end of the inverter INV11 is connected to the input end of the buffer Buf10, the output end of the buffer Buf10 is connected to the first electrode of the transistor M1 through the capacitor C10, and the second electrode of the transistor M1 is connected to the power supply terminal V0. The output end of the inverter INV11 is also connected to the input end of the inverter INV12, the output end of the inverter INV12 is connected to the first electrode of the transistor M2 through the capacitor C20, and the second electrode of the transistor M2 is connected to the power supply terminal V0. The output end of the inverter INV12 is also connected to the control electrode of the transistor M1 through the capacitor C20, and the output end of the buffer Buf10 is connected to the control electrode of the transistor M2 through the capacitor C10. The output end of the inverter INV12 is also connected to the control electrode of the transistor M3 through the capacitor C20. The first electrode of the transistor M3 is used to output the switch control signal S1, and the second electrode of the transistor M3 is also connected to the power supply terminal V0.

[0041] Among them, the control signal receiving terminal HSD_VIN receives an input control signal, and the control signal is used to control the conduction or shutdown of the transistor M3. Assuming that the control signal is a high-low level signal, the high-level signal is used to control the turn-on of the transistor M3, and the low-level signal is used to control the turn-off of the transistor M3. Assume that in this application, the power supply voltages of the inverter INV11 and the inverter INV12 are both VCC, and the power supply voltage on the power supply terminal V0 is V0. See Figure 1 As shown, since there are parasitic diodes on both transistors M1 and M2, assuming that the conduction voltage drop of the parasitic diodes in this embodiment is Vdiode, when transistors M1 and M2 are turned off, since the parasitic diodes are passages, Figure 1 The voltages at points A and C can be expressed as (V0-Vdiode). When it is necessary to control transistor M3 to turn on, a high-level signal is input to the signal receiving terminal HSD_VI. At this time, the voltage of the C potential will become (V0-Vdiode+VCC). At this time, transistors M1 and M3 are turned on, and transistor M2 is turned off. At this time, the voltages at point B and the switch control signal S1 are both V0. When it is necessary to turn off transistor M3, a low-level signal is input to the signal receiving terminal HSD_VI. At this time, the voltage at point B will become (V0+VCC). At this time, transistor M2 is turned on, biasing the voltage value at point C to V0, and turning off transistor M3.

[0042] It can be understood that when the voltage difference between the control electrode and the first electrode of the transistor M3 is greater than the threshold voltage of the transistor M3, the transistor M3 is turned on, and when the voltage difference between the control electrode and the first electrode is less than the threshold voltage, the transistor M3 is turned off. Figure 1 In the driving circuit, when the transistor M3 is turned off, the voltage of the switch control signal S1 is V0, and the voltage value of point C is also V0. At this time, the voltage difference between the control electrode and the first electrode of M3 is 0; when the transistor M3 is turned on, the voltage of the switch control signal S1 is V0, and the voltage value of point C is (V0-Vdiode+VCC). At this time, the voltage difference between the control electrode and the first electrode of the transistor M3 is (VCC-Vdiode). In order to turn on the transistor M3, in the actual circuit, according to the parameters of each device, it is necessary to set the voltage difference (VCC-Vdiode) greater than the conduction threshold of the transistor M3.

[0043] Please continue to see Figure 1 As shown, the current inside the driving circuit comes from the power supply terminal PAD_V0. Due to the presence of parasitic inductance L1 in the circuit, in actual operation, when the current flows from the power supply terminal PAD_V0 to the internal power supply terminal V0, when the slope of the current changes, the current will generate ringing on the parasitic inductance L1.

[0044] Figure 2 One of the waveform diagrams of the voltage signal and current signal inside the driving circuit provided in this application, see Figure 2 As shown, Figure 2 In the equation, Vc is Figure 1 The voltage signal on the receiving terminal HSD_VIN is I1. Figure 1 The current signal on the parasitic inductor L1, V0 is the voltage signal on the power supply terminal V0, and Vb is Figure 1 The voltage signal V1 at point B is the voltage difference between the control electrode and the first electrode of the transistor M3.

[0045] See also Figure 2 As shown in the figure, in a switching cycle, at time t0, the voltage signal Vc on HSD_VIN changes from a low level to a high level, and the voltage difference V1 between the control electrode and the first electrode of the transistor M3 changes from 0 to greater than the threshold voltage, and the transistor M3 is turned on. At the same time, at time t0, the slope of the current signal I1 on the parasitic inductance L1 changes, and the voltage signal V0 rings, which will cause Figure 1 Charge accumulation occurs at point B, so Figure 1The voltage signal at point B accumulates a voltage difference of ΔV. Since a voltage difference of ΔV is generated each time a ringing phenomenon occurs, after multiple cycles, the voltage signal Vb at point B accumulates multiple voltage differences, which will cause the voltage value of the voltage signal Vb to increase. When the sum of the accumulated voltage differences at point B exceeds the voltage change caused by the voltage signal Vc after multiple ringing phenomena occur, then Figure 1 The voltage at point B in the circuit will always be higher than (V0+VCC). At this time, even if the voltage signal Vc changes from a low level to a high level, the voltage at point B cannot be pulled down to below (V0+VCC), and the transistor M2 will always be turned on, making Figure 1 The voltage at point C is always equal to V0, that is, the voltage of the control electrode of transistor M1 is always V0 at this time, so transistor M1 cannot be turned on, that is, the voltage at point B cannot be refreshed to the normal voltage V0, which in turn causes transistor M3 to be unable to be turned off normally, that is, the drive circuit cannot be modulated according to the normal duty cycle signal, and the drive circuit cannot meet the volt-second balance, thereby affecting the control accuracy of the drive circuit, causing the drive circuit to fail and causing circuit failure.

[0046] In another working condition, if the ringing phenomenon has a greater impact on the voltage value at point C, the voltage signal at point C will accumulate multiple voltage differences, which will cause the voltage value of the voltage signal at point C to be always high, causing transistor M1 to be always in the on state, causing transistor M2 to be unable to turn on, and causing transistor M3 to be always on, that is, transistor M3 cannot be turned off normally. This will also cause the drive circuit to fail and cause circuit failure.

[0047] In order to overcome the deficiencies in the above-mentioned related technologies, the present application provides a driving circuit, which includes: a first transistor, a second transistor, a third transistor, a driving control circuit and a voltage refresh circuit. Among them, the first output end of the driving control circuit is connected to the first pole of the first transistor, and the second pole of the first transistor is used to connect to the output end of the power supply circuit; the second output end of the driving control circuit is connected to the first pole of the second transistor, and the second pole of the second transistor is also used to connect to the output end of the power supply circuit; the first output end of the driving control circuit is also connected to the control pole of the second transistor, and the second output end of the driving control circuit is also connected to the control pole of the first transistor; the second output end of the driving control circuit is also connected to the control pole of the third transistor, the first pole of the third transistor is used to connect to the output end of the power supply circuit, and the second pole of the third transistor is used to output a switch control signal. In a working cycle, the driving control circuit outputs the first control signal and the second control signal respectively to control the first transistor and the second transistor to be alternately turned on and off, so as to control the voltage of the control pole of the third transistor to be pulled up or down to control the third transistor to be turned on and off. In each working cycle, the voltage refresh circuit can pull down the voltage at the control electrode of the first transistor and the second transistor respectively to release the charge accumulated at the control electrode of the first transistor and the second transistor due to ringing, thereby ensuring that in each cycle, the voltage at the control electrode of the first transistor and the second transistor is refreshed to the target value, thereby ensuring that the first control signal and the second control signal can accurately control the action of the third transistor, thereby ensuring the normal operation of the drive circuit.

[0048] Figure 3 For a schematic diagram of the driving circuit structure provided in the embodiment of the present application, please refer to Figure 3 As shown, the driving circuit includes: a first transistor Q1, a second transistor Q2, a third transistor Q3, a driving control circuit 10 and a voltage refresh circuit 20.

[0049] The drive control circuit 10 includes an input terminal, a first output terminal, and a second output terminal. The input terminal of the drive control circuit 10 is used to receive a drive control signal. The drive control circuit is used to perform signal processing on the drive control signal to generate a first control signal and a second control signal with opposite logic states. The first output terminal and the second output terminal of the drive control circuit 10 are used to output the first control signal and the second control signal, respectively. In this embodiment, the opposite logic states of the first control signal and the second control signal refer to, for example, if the logic state of the first control signal is a high-level pulse signal, the logic state of the second control signal is a low-level pulse signal; or, if the logic state of the first control signal is a low-level pulse signal, the logic state of the second control signal is a high-level pulse signal. Since the first control signal and the second control signal are used to control the conduction or shutoff of the first transistor Q1 and the second transistor Q2, respectively, in order to achieve periodic control of the first transistor Q1 and the second transistor Q2 to alternately turn on and off, in this embodiment, the logic states of the first control signal and the second control signal are set to be opposite to achieve the above purpose.

[0050] The first output terminal of the driving control circuit 10 is connected to the first electrode of the first transistor Q1, and the second electrode of the first transistor Q1 is used to connect to the output terminal of the power supply circuit; the second output terminal of the driving control circuit 10 is connected to the first electrode of the second transistor Q2, and the second electrode of the second transistor Q2 is also used to connect to the output terminal of the power supply circuit; the first output terminal of the driving control circuit 10 is also connected to the control electrode of the second transistor Q2, and the second output terminal of the driving control circuit 10 is also connected to the control electrode of the first transistor Q1. In this way, the first control signal and the second control signal outputted from the first output terminal and the second output terminal of the driving control circuit 10 can control the first transistor Q1 and the second transistor Q2 to be alternately turned on or off.

[0051] The second output terminal of the drive control circuit 10 is also connected to the control electrode of the third transistor Q3, the first electrode of the third transistor Q3 is used to be connected to the output terminal of the power supply circuit, and the second electrode of the third transistor Q3 is used to output the switch control signal. In this way, the first control signal and the second control signal output by the drive control circuit 10 can control the first transistor Q1 and the second transistor Q2 to be alternately turned on or off, so as to increase or decrease the voltage of the control electrode of the third transistor Q3, thereby controlling the conduction and shutoff of the third transistor Q3, so as to achieve the purpose of controlling the drive circuit to be turned on and off.

[0052] The voltage refresh circuit 20 includes a refresh control circuit, a first current source branch 201 and a second current source branch 202; the input end of the first current source branch 201 is connected to the first electrode of the first transistor Q1, and the input end of the second current source branch 202 is connected to the first electrode of the second transistor Q2.

[0053] The refresh control circuit is used to collect the driving voltage signal and the switch control signal on the control electrode of the third transistor Q3, and determine whether the voltage difference between the driving voltage signal and the switch control signal is greater than or equal to the threshold voltage of the third transistor Q3. If so, a first refresh control signal is generated; if not, a second refresh control signal is generated. The first refresh control signal is used to control the first current source branch 201 to be turned on to form a current loop, so that the formed current loop can consume the charge accumulated at the first electrode of the first transistor Q1, thereby pulling the voltage at the first electrode of the first transistor Q1 down to the first voltage value; the second refresh control signal is used to control the second current source branch 202 to be turned on to form a current loop, so that the formed current loop can consume the charge accumulated at the first electrode of the second transistor Q2, thereby pulling the voltage at the first electrode of the second transistor Q2 down to the second voltage value.

[0054] It can be seen that, by using the driving circuit provided in this embodiment, the first control signal and the second control signal are outputted respectively through the driving control circuit to control the first transistor and the second transistor to be alternately turned on and off, so as to control the voltage of the control electrode of the third transistor to be pulled up or down, so as to control the third transistor to be turned on and off. Moreover, in each working cycle, the voltage refresh circuit can generate the corresponding first refresh control signal or the second refresh control signal according to the voltage difference between the driving voltage signal and the switch control signal, so as to control the first current source branch 201 or the second current source branch 202 to form a conduction loop, so that the voltage at the control electrode of the first transistor and the second transistor can be pulled down respectively, so as to release the charge accumulated at the control electrode of the first transistor and the second transistor due to ringing, so as to ensure that in each cycle, the voltage at the control electrode of the first transistor and the second transistor is refreshed to the target value, so as to ensure that the first control signal and the second control signal can accurately control the action of the third transistor, so as to ensure the normal operation of the driving circuit.

[0055] Please continue to refer to Figure 3 As shown, in some embodiments, the refresh control circuit includes a comparator COMP and a control unit 203. The non-inverting input terminal of the comparator COMP is connected to the control electrode of the third transistor Q3 to collect the driving voltage signal on the control electrode of the third transistor Q3; the inverting input terminal of the comparator COMP is connected to the second electrode of the third transistor Q3 to collect the switch control signal SW output by the second electrode of the third transistor Q3; the comparator COMP is used to compare whether the voltage difference between the driving voltage signal and the switch control signal is greater than or equal to the threshold voltage of the third transistor Q3, and output a first comparison signal through the output terminal F; the control unit 203 is used to generate a first refresh control signal or a second refresh control signal according to the logic state of the first comparison signal.

[0056] In some embodiments, the first comparison signal may have different logic states, for example, the first comparison signal may be a high level pulse signal or a low level pulse signal in a digital circuit. When the first comparison signal is in different logic states, it indicates that the comparison results of the voltage difference between the driving voltage signal and the switch control signal SW and the threshold voltage of the third transistor Q3 are different. For example, if the output first comparison signal is a high level pulse signal, it is determined that the voltage difference between the driving voltage signal and the switch control signal SW is greater than or equal to the threshold voltage of the third transistor Q3, and the control unit 203 generates a first refresh control signal; if the output first comparison signal is a low level pulse signal, it is determined that the voltage difference between the driving voltage signal and the switch control signal is less than the threshold voltage of the third transistor Q3, and the control unit 203 generates a second refresh control signal.

[0057] In some embodiments, the drive control circuit 10 includes a first inverter INV1, a second inverter INV2, a buffer Buf1, a first capacitor C1, and a second capacitor C2. The input terminal HSD_ON of the drive control circuit 10 is connected to the input terminal of the first inverter INV1, that is, the input terminal of the first inverter INV1 is the input terminal of the drive control circuit 10, the output terminal of the first inverter INV1 is connected to the input terminal of the buffer Buf1, the output terminal of the buffer Buf1 is connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is connected to the first electrode of the first transistor Q1; the second terminal of the first capacitor C1 is the first output terminal of the drive control circuit 10, and the potential corresponding to the first output terminal of the drive control circuit 10 is Figure 3 The voltage at point A, i.e., the first output terminal of the drive control circuit 10, is Figure 3 In addition, the output end of the first inverter INV1 is also connected to the input end of the second inverter INV2, the output end of the second inverter INV2 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the first electrode of the second transistor Q2. The second end of the second capacitor C2 is the second output end of the drive control circuit 10.

[0058] It can be understood that, in the present embodiment, the driving control circuit 10 makes the first output terminal and the second output terminal output the first control signal and the second control signal with opposite logic states through the combination of the first inverter INV1, the second inverter INV2, and the buffer Buf1. Assume that the power supply voltage of the first inverter INV1, the second inverter INV2 and the buffer Buf1 is VCC, when the first control signal is a high-level pulse signal, the power supply voltage VCC charges the first capacitor C1, so that the voltage at the second end of the first capacitor C1 is VCC; or, when the second control signal is a high-level pulse signal, the power supply voltage VCC charges the second capacitor C2, so that the voltage at the second end of the second capacitor C2 is VCC. Then, according to whether the first transistor Q1 and the second transistor Q2 are turned on, it can be determined Figure 3 The voltage values ​​at point A and point HSD determine whether the third transistor Q3 is turned on.

[0059] In some embodiments, see Figure 3 As shown, the refresh control circuit includes a first control signal output terminal E and a second control signal output terminal D; the first control signal output terminal E is used to output a first refresh control signal, and the second control signal output terminal D is used to output a second refresh control signal. Specifically, the control unit 203 is provided with a first control signal output terminal E and a second control signal output terminal D to output the first refresh control signal and the second refresh control signal.

[0060] Please continue to see Figure 3 As shown, in some embodiments, the first current source branch 201 includes a first current source IDC1 and a first switch tube K1; the output end of the first current source IDC1 is grounded GND, the input end of the first current source IDC1 is connected to the first electrode of the first switch tube K1, the second electrode of the first switch tube K1 is the input end of the first current source branch 201, and the second electrode of the first switch tube K1 is connected to the first electrode of the first transistor Q1; the first control signal output end E is connected to the control electrode of the first switch tube K1. In this way, the first control signal output end E can output a first refresh control signal to control the conduction and shutoff of the first switch tube K1, thereby controlling whether the first current source branch 201 is turned on to form a current loop.

[0061] Please continue to see Figure 3As shown, in some embodiments, the second current source branch 202 includes a second current source IDC2 and a second switch tube K2; the output end of the second current source IDC2 is grounded GND, the input end of the second current source IDC2 is connected to the first electrode of the second switch tube K2, the second electrode of the second switch tube K2 is the input end of the second current source branch 202, and the second electrode of the second switch tube K2 is connected to the first electrode of the second transistor Q2; the second control signal output end is connected to the control electrode of the second switch tube K2. In this way, the second control signal output end D can output a second refresh control signal to control the conduction and shutoff of the second switch tube K2, thereby controlling whether the second current source branch 202 is turned on to form a current loop.

[0062] Please continue to see Figure 3 As shown, in some embodiments, the driving circuit includes a power supply circuit, an input terminal PAD_VIN of the power supply circuit is used to connect to a power supply, and an output terminal of the power supply circuit is used to output a power supply voltage VIN, and the power supply voltage VIN is used to power various devices inside the circuit.

[0063] It can be understood that the input terminal PAD_VIN of the power supply circuit is generally connected to the external total power supply terminal, and then the power supply circuit processes the input electrical signal to obtain electrical signals suitable for various devices, and outputs these electrical signals from the output terminal. There will be a parasitic inductance PAR_IND between the input terminal PAD_VIN and the output terminal of the power supply circuit. When the slope of the current in the circuit changes, the current will produce ringing on the parasitic inductance PAR_IND, thereby affecting the voltage values ​​of points A and HSD.

[0064] In some embodiments, the driving circuit further includes a transistor LSD and a voltage output terminal VOUT. When the transistor LSD is controlled to be turned on, the switch control signal SW is pulled down to a low level, and the voltage output terminal VOUT is used to output a discharge voltage signal to the outside.

[0065] Figure 4 This is the second waveform diagram of each voltage signal and current signal in the driving circuit of this application, please refer to Figure 4 As shown, Figure 4 HSD_ON in Figure 3 A schematic diagram of a voltage waveform on the input terminal HSD_ON of the drive control circuit 10;

[0066] Figure 4 V2 is a schematic diagram of the voltage difference signal waveform between the driving voltage signal and the switch control signal SW. In other words, V2 is Figure 3 A schematic diagram of a voltage difference signal waveform between the control electrode and the first electrode of the third transistor Q3; Figure 4 IND Figure 3Schematic diagram of the current signal waveform on the parasitic inductance PAR_IND; Figure 4 The VIN in Figure 3 A schematic diagram of a waveform of a voltage signal at an output end of a power supply circuit; Figure 4 The F in Figure 3 A schematic diagram of a waveform of a first comparison signal at an output terminal of the comparator COMP; Figure 4 The E in Figure 3 A schematic diagram of a waveform of a first refresh control signal outputted by the first control signal output terminal E; Figure 4 D in Figure 3 A schematic diagram of a waveform of a second refresh control signal outputted from a second control signal output terminal D;

[0067] Figure 4 A in Figure 3 FIG. 1 is a schematic diagram of a waveform of a voltage signal on the control electrode of the second transistor Q2 in FIG. Figure 4 A in Figure 3 Schematic diagram of the waveform of the voltage signal on the first electrode of the first transistor Q1.

[0068] Please continue to see Figure 3 and Figure 4 As shown, in a switching cycle, at time t1, when the voltage signal on HSD_ON changes from a low level to a high level, the first transistor Q1 is controlled to be turned on, and the second transistor Q2 is controlled to be turned off. Then, the voltage difference between the driving voltage signal and the switch control signal SW is greater than the threshold voltage of the third transistor Q3, that is, the voltage difference V2 between the control electrode and the first electrode of the third transistor Q3 changes from 0V to greater than the threshold voltage of the third transistor Q3, and the third transistor Q3 is turned on. Correspondingly, when the voltage signal on HSD_ON changes from a high level to a low level, the first transistor Q1 is controlled to be turned off, and the second transistor Q2 is controlled to be turned on. Then, the voltage difference between the driving voltage signal and the switch control signal SW is 0V, that is, the voltage difference between the driving voltage signal and the switch control signal SW is less than the threshold voltage of the third transistor Q3, and the third transistor Q3 is controlled to be turned off.

[0069] At the same time, at time t1, the slope of the current signal IND on the parasitic inductance PAR_IND changes, and at this time, the power supply voltage signal VIN rings, which will cause Figure 3 Charge accumulation occurs at point A, so Figure 3The voltage signal at point A accumulates a voltage difference of ΔV. Since a voltage difference of ΔV is generated at point A every time a ringing phenomenon occurs, after multiple cycles, the voltage signal at point A accumulates multiple voltage differences, which will cause the voltage value of the voltage signal to increase. When the sum of the accumulated voltage differences at point A exceeds the voltage change caused by the power supply voltage VCC of the first inverter INV1 after multiple ringing phenomena occur, then Figure 3 The voltage at point A in the circuit will always be higher than (VIN+VCC). At this time, even if the driving control signal HSD_ON changes from a low level to a high level, the voltage at point A cannot be pulled down to below (VIN+VCC), and the second transistor Q2 will always be turned on, making Figure 3 The voltage at the HSD point is always equal to VIN, that is, the voltage of the control electrode of the first transistor Q1 is always VIN at this time, so the first transistor Q1 cannot be controlled to be turned on, that is, the voltage at point A cannot be refreshed to the normal voltage VIN, which causes the third transistor Q3 to be unable to be turned off normally, that is, the drive circuit cannot be modulated according to the normal duty cycle signal, and the drive circuit cannot meet the volt-second balance, thereby affecting the control accuracy of the drive circuit, causing the drive circuit to fail and causing circuit failure. In another working condition, correspondingly, if the ringing phenomenon has a greater impact on the voltage value of the HSD point, then after the voltage signal at the HSD point accumulates multiple voltage differences, the voltage value of the voltage signal at the HSD point will be always high, which will cause the first transistor Q1 to be always in the on state, causing the second transistor Q2 to be unable to open, and the third transistor Q3 to be always on, that is, the third transistor Q3 cannot be turned off normally. This will also cause the drive circuit to fail and cause circuit failure.

[0070] According to the driving circuit provided in this embodiment, the driving circuit includes a voltage refresh circuit. Please continue to refer to Figure 3 As shown, in the first half of a working cycle, at time t1, when the driving control signal HSD_ON is switched from a low level signal to a high level signal, when the first transistor Q1 is turned on, the third transistor Q3 is controlled to be turned on. The voltage value at point A is (VIN-Vdiode+VCC), and at this time, the voltage difference between the control electrode and the first electrode of the third transistor Q3 is (VCC-Vdiode). Due to signal hysteresis, at time t2, the voltage difference signal F output by the comparator COMP changes from 0V to a high level signal, and the control unit 203 outputs the first refresh control signal E, that is, the first refresh control signal E is switched from a low level signal to a high level signal to control the first switch tube K1 to be turned on, thereby controlling the first current source branch 201 to be turned on to form a current loop, so as to release the accumulated charge at point A, that is, to pull the voltage at point A down to VIN, thereby ensuring that in the next cycle, the second control signal can be output to control the second transistor Q2 to be normally turned off, thereby driving the third transistor Q3 to be turned on.

[0071] Wherein, Vdiode is the conduction voltage drop of the freewheeling diode in the second transistor Q2 or the third transistor Q3. It can be understood that in the circuit of this embodiment, the second transistor Q2 and the third transistor Q3 can use transistors of the same specification, so the freewheeling diodes in the second transistor Q2 and the third transistor Q3 have the same voltage drop.

[0072] Please continue to refer to Figure 3 As shown, in the second half of a working cycle, when the driving control signal HSD_ON is switched from a high level signal to a low level signal, the first transistor Q1 is controlled to be turned off. At this time, the control electrode of the second transistor Q2 is at a high level, and the second transistor Q2 is turned on. At this time, the voltage of the control electrode of the third transistor Q3 is pulled down to VIN, and the third transistor Q3 is controlled to be turned off. At this time, the voltage difference between the control electrode and the first electrode of the third transistor Q3 is at a high level, that is, the voltage difference signal F output by the comparator COMP also changes from 0V to a high level signal, and the control unit 203 outputs a second refresh control signal, that is, the second refresh control signal D is switched from a low level signal to a high level signal to control the second switch tube K2 to be turned on, thereby controlling the second current source branch 202 to be turned on to form a current loop to release the accumulated charge at the HSD point, that is, to pull the voltage at the HSD point down to VIN, thereby ensuring that in the next cycle, the first control signal can be output to control the first transistor Q1 to be normally turned off, and then drive the third transistor Q3 to be turned off.

[0073] It should be noted that the duration of the first current source branch 201 and the second current source branch 202 being turned on by the control unit 203 can be set according to the parameter characteristics of the circuit, and the duration of the first current source branch 201 and the second current source branch 202 being turned on represents the duration of releasing the accumulated charge. Therefore, the duration of the first current source branch 201 and the second current source branch 202 being turned on should be set to ensure that the accumulated charge is released, and since the first current source branch 201 and the second current source branch 202 are controlled to be turned on in each cycle to release the accumulated charge, the duration of the first current source branch 201 and the second current source branch 202 being turned on should not be too long to affect the working efficiency of the circuit. The control unit 203 can be a control chip.

[0074] In some embodiments, Figure 3Taking the driving circuit shown as an example, assuming that the voltage difference caused by the accumulated charge at point A is ΔV, the capacitance of the first capacitor C1 and the second capacitor C2 are both C, and the current value of the first current source IDC1 and the second current source IDC2 is I2, then C*ΔV=I2*t3, t3 is the conduction time of the first current source branch 201 and the second current source branch 202, then the conduction time t3 of the first current source branch 201 and the second current source branch 202 can be calculated by the above theoretical formula, and based on the conduction time t3, the ringing effect can be eliminated while ensuring the working efficiency of the driving circuit.

[0075] It can be seen from the above analysis that in each working cycle, the voltage refresh circuit can generate a corresponding first refresh control signal or a second refresh control signal according to the voltage difference between the driving voltage signal and the switch control signal, so as to respectively control the first current source branch 201 or the second current source branch 202 to form a conduction loop, so that the voltage at the control electrode of the first transistor and the second transistor can be pulled down respectively to release the charge accumulated at the control electrode of the first transistor and the second transistor due to ringing, thereby ensuring that in each cycle, the voltage at the control electrode of the first transistor and the second transistor are refreshed to the target value, thereby ensuring that the first control signal and the second control signal can accurately control the action of the third transistor, thereby ensuring the normal operation of the driving circuit.

[0076] In addition, according to the drive circuit provided in this embodiment, the voltage VIN provided by the output end of the power supply circuit can be a higher voltage, generally tens of volts, while the power supply of the components in the drive control circuit 10 and the voltage refresh circuit 20 is low voltage, and the general power supply voltage is several volts. Therefore, according to this embodiment, there is no need to consider the technical problem of high voltage resistance of the components in the drive control circuit 10 and the voltage refresh circuit 20, and only the technical problem of high voltage resistance of the first capacitor C1, the second capacitor C2, the first transistor Q1, the second transistor Q2 and the third transistor Q3 needs to be considered. In this way, the drive circuit provided in this embodiment can be widely used in high voltage environments, making the application range wider.

[0077] In this embodiment, the supply voltage of the first inverter INV1, the second inverter INV2 and the buffer Buf1 can be set to 5 V. Therefore, there is no need to consider the technical problem of high voltage resistance of the first inverter INV1, the second inverter INV2 and the buffer Buf1, and only the voltage resistance of the first capacitor C1 and the second capacitor C2 needs to be considered.

[0078] Based on the driving circuit provided in the above embodiment, this embodiment also provides a power conversion circuit, which includes multiple transistors and also includes a driving circuit as provided in the above embodiment. The driving circuit can accurately control the conduction and shutdown of each transistor in the power conversion circuit to ensure the working accuracy and stability of the power conversion circuit.

[0079] Based on the driving circuit provided in the above embodiment, this embodiment further provides a power tube driver, which includes the driving circuit provided in the above embodiment. The power tube driver can accurately control the on and off of the power tube to ensure the working accuracy and stability of the circuit.

[0080] Based on the driving circuit provided in the above embodiment, this embodiment further provides a power conversion device, which includes the driving circuit as described above. The driving circuit can accurately control the on and off of each transistor in the power conversion device to ensure the working accuracy and stability of the power conversion device.

[0081] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A driving circuit, characterized in that: include: A first transistor, a second transistor, a third transistor, a drive control circuit and a voltage refresh circuit; The drive control circuit comprises an input terminal, a first output terminal and a second output terminal, wherein the input terminal of the drive control circuit is used to receive a drive control signal, the drive control circuit is used to perform signal processing on the drive control signal to generate a first control signal and a second control signal with opposite logical states, and the first output terminal and the second output terminal are used to output the first control signal and the second control signal, respectively; The first output terminal of the drive control circuit is connected to the first electrode of the first transistor, and the second electrode of the first transistor is used to be connected to the output terminal of the power supply circuit; the second output terminal of the drive control circuit is connected to the first electrode of the second transistor, and the second electrode of the second transistor is also used to be connected to the output terminal of the power supply circuit; the first output terminal of the drive control circuit is also connected to the control electrode of the second transistor, and the second output terminal of the drive control circuit is also connected to the control electrode of the first transistor; The second output terminal of the drive control circuit is also connected to the control electrode of the third transistor, the first electrode of the third transistor is used to be connected to the output terminal of the power supply circuit, and the second electrode of the third transistor is used to output a switch control signal; The voltage refresh circuit includes a refresh control circuit, a first current source branch and a second current source branch; the input end of the first current source branch is connected to the first electrode of the first transistor, and the input end of the second current source branch is connected to the first electrode of the second transistor; The refresh control circuit is used to collect the driving voltage signal and the switch control signal on the control electrode of the third transistor, and determine whether the voltage difference between the driving voltage signal and the switch control signal is greater than or equal to the threshold voltage of the third transistor, and if so, generate a first refresh control signal; if not, generate a second refresh control signal; The first refresh control signal is used to control the first current source branch to be turned on to form a current loop, thereby pulling down the voltage at the first electrode of the first transistor to a first voltage value; The second refresh control signal is used to control the second current source branch to be turned on to form a current loop, thereby pulling the voltage at the first electrode of the second transistor down to a second voltage value.

2. The driving circuit according to claim 1, characterized in that: The refresh control circuit includes a comparator and a control unit; The non-inverting input terminal of the comparator is connected to the control electrode of the third transistor to collect the driving voltage signal on the control electrode of the third transistor; the inverting input terminal of the comparator is connected to the second electrode of the third transistor to collect the switch control signal; the comparator is used to compare whether the voltage difference between the driving voltage signal and the switch control signal is greater than or equal to the threshold voltage of the third transistor, and output a first comparison signal; The control unit is used to generate the first refresh control signal or the second refresh control signal according to the logic state of the first comparison signal.

3. The driving circuit according to claim 1 or 2, characterized in that: The drive control circuit includes a first inverter, a second inverter, a buffer, a first capacitor and a second capacitor; The output end of the first inverter is connected to the input end of the buffer, the output end of the buffer is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the first electrode of the first transistor; the input end of the first inverter is the input end of the drive control circuit, and the second end of the first capacitor is the first output end of the drive control circuit; The output end of the first inverter is also connected to the input end of the second inverter, the output end of the second inverter is connected to the first end of the second capacitor, the second end of the second capacitor is connected to the first electrode of the second transistor, and the second end of the second capacitor is the second output end of the drive control circuit.

4. The driving circuit according to claim 1 or 2, characterized in that: The refresh control circuit includes a first control signal output terminal and a second control signal output terminal; The first control signal output terminal is used to output a first refresh control signal, and the second control signal output terminal is used to output the second refresh control signal.

5. The driving circuit according to claim 4, characterized in that: The first current source branch includes a first current source and a first switch tube; the output end of the first current source is grounded, the input end of the first current source is connected to the first electrode of the first switch tube, the second electrode of the first switch tube is the input end of the first current source branch, and the second electrode of the first switch tube is connected to the first electrode of the first transistor; the first control signal output end is connected to the control electrode of the first switch tube.

6. The driving circuit according to claim 4, characterized in that: The second current source branch includes a second current source and a second switch tube; the output end of the second current source is grounded, the input end of the second current source is connected to the first electrode of the second switch tube, the second electrode of the second switch tube is the input end of the second current source branch, and the second electrode of the second switch tube is connected to the first electrode of the second transistor; the second control signal output end is connected to the control electrode of the second switch tube.

7. The driving circuit according to claim 1 or 2, characterized in that: The driving circuit comprises a power supply circuit, an input end of the power supply circuit is used to connect to a power supply, and an output end of the power supply circuit is used to output a power supply voltage.

8. A power conversion circuit, characterized in that: Comprising the driving circuit as described in any one of claims 1-7.

9. A power tube driver, characterized in that: Comprising the driving circuit as described in any one of claims 1-7.

10. A power conversion device, characterized in that: Comprising the driving circuit as described in any one of claims 1-7.

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