Inverter circuit, chip and electronic equipment

Abstract

The invention discloses an inverter circuit, a chip and electronic equipment, and relates to the technical field of electronic equipment. The inverter circuit comprises a booster circuit, an inverter and a reference voltage generation circuit, the input end of the booster circuit is coupled with a power supply; the first input end of the inverter is coupled with the output end of the booster circuit, and the output end of the inverter is used for coupling a load; the input end of the reference voltage generation circuit is coupled with the output end of the booster circuit, and the output end of the reference voltage generation circuit is coupled with the second input end of the inverter; the reference voltage generation circuit is used for receiving a voltage signal output by the output end of the booster circuit, the reference voltage generation circuit is further used for sampling the voltage signal, generating reference voltage and outputting the reference voltage to the second input end of the inverter, and the reference voltage comprises voltage generated according to the minimum sampling voltage. According to the scheme, fidelity high-voltage sine driving signals can be obtained through the inverter circuit.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and in particular to inverter circuits, chips and electronic equipment. Background Art

[0002] As electronic devices such as mobile phones, smart wearable products, and personal computers (PCs) gradually develop towards being lighter and smaller, higher requirements are placed on the performance and volume of the heat dissipation modules of electronic devices. Since liquid cooling has a better heat dissipation effect, liquid cooling can usually be used to dissipate heat from electronic devices. The liquid cooling module may include: a pump and a working fluid. The working substance can be understood as a carrier that realizes the mutual conversion of thermal energy and mechanical energy. The pump can serve as a power source for the working substance and provide power for the flow of the working substance. The working substance can serve as a carrier for heat transfer during the flow process, so that the liquid cooling module can achieve the effect of heat dissipation.

[0003] A typical liquid cooling module uses a piezoelectric liquid pump as the power source of the working fluid. However, the piezoelectric liquid pump requires a high-voltage sinusoidal wave drive. Therefore, how to obtain a high-fidelity high-voltage sinusoidal drive signal becomes a problem that needs to be solved. Summary of the invention

[0004] The present application discloses an inverter circuit, a chip and an electronic device, which can obtain a high-fidelity high-voltage sinusoidal driving signal through the inverter circuit.

[0005] In the first aspect, an inverter circuit is provided. The inverter circuit includes: a boost circuit, an inverter, and a reference voltage generating circuit; the input end of the boost circuit is used to couple a power source; the first input end of the inverter is coupled to the output end of the boost circuit, and the output end of the inverter is used to couple a load; the input end of the reference voltage generating circuit is coupled to the output end of the boost circuit, and the output end of the reference voltage generating circuit is coupled to the second input end of the inverter; the reference voltage generating circuit is used to receive a voltage signal output from the output end of the boost circuit, and the reference voltage generating circuit is also used to sample the voltage signal to generate a reference voltage to output to the second input end of the inverter, wherein the reference voltage is a voltage generated according to the minimum sampling voltage of the voltage signal. Since the input end of the boost circuit is used to couple a power source; the first input end of the inverter is coupled to the output end of the boost circuit, the DC voltage U input to the power source can be adjusted by the boost circuit. in Boost the voltage to get the voltage signal U boost (With DC bias voltage U offset The steamed bun wave) and the voltage signal U boost Output to the inverter, thereby achieving the inverter output voltage U o The amplitude is greater than the input DC voltage U in In addition, the reference voltage generating circuit can be used for the voltage signal Uboost Sampling and generating the reference voltage U ref Output to the inverter, because the reference voltage U ref According to the voltage signal U boost The voltage generated by the minimum sampling voltage can be boost The lowest point is taken as the reference voltage U ref (corresponding to the minimum sampling voltage, that is, the steamed bun wave U boost The DC bias voltage U offset ), the reference voltage U ref As the reference ground of the H-bridge inverter to U boost When turning, you can eliminate U boost With a DC bias voltage U offset , obtain the high-voltage sinusoidal driving signal U o In addition, since the inverter circuit does not involve a filter circuit, it occupies a smaller volume or area, which is more conducive to the miniaturization of the device.

[0006] In one possible implementation, the reference voltage generating circuit includes: a voltage tracking circuit coupled between an input terminal and an output terminal of the reference voltage generating circuit; the voltage tracking circuit includes: an analog-to-digital converter, a first memory, a second memory, a comparator, an AND gate circuit, and a digital-to-analog converter; the analog-to-digital converter is coupled between the input terminal of the reference voltage generating circuit and the first memory, the first memory is coupled to the first input terminal of the comparator and the first input terminal of the AND gate circuit; the second memory is coupled to the output terminal of the AND gate circuit, the digital-to-analog converter, and the second input terminal of the comparator; the output terminal of the comparator is coupled to the second input terminal of the AND gate circuit; the output terminal of the digital-to-analog converter is coupled to the output terminal of the reference voltage generating circuit.

[0007] In a possible implementation, an analog-to-digital converter is used to convert a second sampled voltage of a voltage signal into a second digital signal; a first memory is used to store the second digital signal; a second memory is used to store a first digital signal, wherein the first digital signal is a digital signal corresponding to the first sampled voltage of the voltage signal; a comparator is used to compare the first digital signal and the second digital signal to generate a comparison result; an AND gate circuit is used to perform an AND operation on the first digital signal and the comparison result, and output the operation result, wherein when the voltage corresponding to the first digital signal is greater than the voltage corresponding to the second digital signal, a first operation result is generated; or when the voltage corresponding to the first digital signal is less than the voltage corresponding to the second digital signal, a second operation result is generated; the second memory is used to store the second digital signal according to the first operation result, or to keep storing the first digital signal according to the second operation result; a digital-to-analog converter is used to convert the first digital signal or the second digital signal into an analog voltage, wherein the reference voltage generating circuit generates the reference voltage according to the analog voltage. In some examples, the first memory may adopt a first in first out (FIFO) memory, and the second memory may adopt a register. Exemplarily, the voltage signal U is converted by the analog-to-digital converter ADC. boost The sampled voltage is converted into analog-to-digital (AD) to obtain a digital signal B, which is stored in the FIFO memory; wherein the value in the register is recorded as the digital signal A, and the digital signal A can be the voltage signal U boost The digital signal obtained by sampling the voltage for the first time before sampling the digital signal B, or it can also be a default initial value set in the register based on experience; then, the register sends the digital signal A to the comparator, and the FIFO memory sends the digital signal B to the comparator, the comparator compares the digital signal A and the digital signal B, and generates a comparison result; the FIFO memory sends the digital signal B to the AND gate circuit, and the comparator sends the comparison result to the AND gate circuit, the AND gate circuit performs an AND operation on the digital signal B and the comparison result, and outputs the operation result; wherein, when the voltage corresponding to the digital signal A is greater than the voltage corresponding to the digital signal B, a first operation result is generated; or when the voltage corresponding to the digital signal A is less than the voltage corresponding to the digital signal B, a second operation result is generated. The register stores the digital signal B according to the first operation result, or stores the digital signal A according to the second operation result. Then, the digital-to-analog converter DAC converts the digital signal (A or B) stored in the register into an analog voltage; finally, the reference voltage generating circuit 404 generates a reference voltage Uref according to the analog voltage; in this way, after the voltage signal U boost After one or more cycles of sampling, the digital signal stored in the register is updated to a digital signal corresponding to the minimum sampling voltage.

[0008] In a possible implementation, the reference voltage generating circuit further includes: a selection switch; a common end of the selection switch coupled to the output end of the analog-to-digital converter, a first selection end of the selection switch coupled to the first memory; and a second selection end of the selection switch coupled to the second memory. boost When sampling, the common end of the selection switch can be controlled to be connected to the second selection end to transmit the obtained digital signal A to the register; then the common end of the selection switch is connected to the first selection end, and the generated digital signal is transmitted to the FIFO memory in sequence during the subsequent voltage sampling process.

[0009] In a possible implementation, it also includes: a voltage sampling circuit and a voltage amplifying circuit; the voltage sampling circuit is coupled between the input end of the reference voltage generating circuit and the voltage tracking circuit; the voltage amplifying circuit is coupled between the voltage tracking circuit and the output end of the reference voltage generating circuit; the voltage sampling circuit has a first sampling ratio, the voltage amplifying circuit has a first amplification ratio, and the product of the first amplification ratio and the first sampling ratio is 1. The voltage sampling circuit generates a voltage signal U output by the boost circuit. boost When sampling, sampling can be performed at a sampling ratio k1. boost The sampling is performed, and the sampling ratio k1 of the voltage sampling circuit is boost The voltage amplitude of the voltage sampling circuit is reduced to a certain extent, so it is necessary to use a voltage amplifier circuit to compensate the reduction caused by the voltage sampling circuit in the form of gain with a certain amplification ratio k2. Therefore, the sampling ratio k1 and the amplification ratio k2 have the following relationship: k1*k2=1.

[0010] In a possible implementation, it further includes: an impedance matching circuit coupled between the voltage amplifier circuit and the output end of the reference voltage generating circuit. The impedance matching circuit is mainly used to match the resistance impedance between the voltage amplifier circuit and the impedance of the inverter to ensure that the system line impedance is matched and the voltage can be transmitted normally. In some examples, the impedance matching circuit can use a voltage follower.

[0011] In a possible implementation, a voltage sampling circuit includes: a first resistor and a second resistor; a first end of the first resistor is coupled to an input end of a reference voltage generating circuit, a second end of the first resistor is coupled to a first end of a second resistor, and the second end of the first resistor is also coupled to a voltage tracking circuit; and a second end of the second resistor is coupled to ground. The above sampling ratio k1 = first resistor R1 / second resistor R2.

[0012] In a possible implementation, the amplifier circuit includes a positive feedback amplifier circuit or a negative feedback amplifier circuit.

[0013] In a possible implementation, the voltage boost circuit includes: a boost circuit.

[0014] In a possible implementation, the inverter includes: an H-bridge inverter.

[0015] In a second aspect, a chip is provided, including a substrate and an inverter circuit arranged on the substrate, wherein the inverter circuit includes the inverter circuit provided in the first aspect and possible implementations thereof.

[0016] In a third aspect, an electronic device is provided, comprising a pump and an inverter circuit as described in the first aspect and possible implementations thereof; the inverter circuit is connected to the pump.

[0017] In a possible implementation, the electronic device includes a liquid cooling module, the liquid cooling module includes the pump and a cavity, and the pump is used to drive the working medium to flow in the cavity.

[0018] In a possible implementation manner, the cavity is disposed in a housing of the electronic device.

[0019] Among them, the technical problems solved by the second to third aspects and their possible implementation methods and the technical effects achieved can be referred to the description in the first aspect and its possible implementation methods, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of a driving method of a piezoelectric fluid pump provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of the structure of an inverter circuit provided in an embodiment of the present application;

[0023] Figure 4 A schematic structural diagram of an inverter circuit provided in another embodiment of the present application;

[0024] Figure 5 A U provided in an embodiment of the present application boost Waveform diagram of ;

[0025] Figure 6 A schematic structural diagram of an inverter circuit provided in yet another embodiment of the present application;

[0026] Figure 7 A schematic diagram of the duty cycle of Q1 and Q2 provided in an embodiment of the present application;

[0027] Figure 8A schematic diagram of the conduction state of Q3-Q6 provided in an embodiment of the present application;

[0028] Fig. 9 A schematic diagram of a voltage tracking circuit provided in an embodiment of the present application;

[0029] Fig.10 A schematic diagram of the structure of a voltage tracking circuit provided in another embodiment of the present application;

[0030] Fig.11 A schematic diagram of the structure of a voltage tracking circuit provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0032] Herein, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "multiple" means two or more. In addition, herein, directional terms such as "upper" and "lower" are defined relative to the orientation of the schematic placement of the structure in the accompanying drawings. It should be understood that these directional terms are relative concepts, which are used for description and clarification relative to each other, and may change accordingly according to changes in the orientation of the placement of the structure.

[0033] When used to describe a three-port switch (also called a switch device, such as a switch tube, a switch transistor), the "first end" and the "second end" may refer to the connection ends of the switch, respectively, and the "control end" may refer to the control end of the switch. For example, for a MOS (metal-oxide-semiconductor) tube, the control end may refer to the gate of the MOS tube, the first end may refer to the source of the MOS tube, and the second end may refer to the drain of the MOS tube, or the first end may refer to the drain of the MOS tube, and the second end may refer to the source of the MOS tube. In an embodiment of the present application, each switch may include a switch transistor, but in order to minimize the increase in internal resistance caused by the switches in series on the line, each switch may also include two or more switch transistors in parallel.

[0034] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0035] The electronic devices involved in the embodiments of the present application may include, but are not limited to: mobile phones, tablet computers, laptop computers, ultra-mobile personal computers (UMPCs), handheld computers, netbooks, personal digital assistants (PDAs), wearable electronic devices, virtual reality devices, and other electronic devices that require battery charging.

[0036] Reference Figure 1 As shown, a schematic diagram of the structure of an electronic device 10 is provided. Taking a mobile phone as an example, it can be seen that the electronic device 10 includes: a housing 100 and an electronic functional component (not shown in the figure) located in the housing 100. In the embodiment of the present application, the mobile phone may be a folding device or a straight device. The electronic functional components of the electronic device 10 include, but are not limited to: a processor, an internal memory, a charging management module, a power management module, a battery, an antenna, a communication module, a camera, an audio module, a speaker, a receiver, a microphone, a sensor module, a motor, and an indicator, etc. Among them, the electronic device 10 may have more or fewer electronic functional components than described above. Various electronic functional components can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application-specific integrated circuits.

[0037] The electronic functional components release heat when they are in working state. When the temperature inside the electronic device 10 is too high, it will affect the working efficiency of the electronic functional components and the service life of the electronic device 10. Therefore, it is necessary to set a liquid cooling module 200 to control the temperature rise of the electronic functional components. Based on the above considerations, in some feasible implementations, the liquid cooling module 200 is located between the housing 100 and the electronic functional components to achieve temperature control of the electronic functional components. Exemplarily, the liquid cooling module 200 can be located on the side of the housing 100 adjacent to the electronic functional components. The liquid cooling module 200 can achieve temperature control of the electronic functional components. In some feasible implementations, the liquid cooling module 200 can also be used as a part of the electronic functional component package to achieve temperature control of the electronic functional component. Exemplarily, the liquid cooling module can be encapsulated in the battery as a part of the battery, and the temperature of the battery can be controlled.

[0038] The structure of the liquid cooling module 200 is described as follows:

[0039] Reference Figure 1, the liquid cooling module 200 may include: a cavity 201, a pump 202 and a working fluid (not shown in the figure). The working fluid is filled in the cavity 201. The pump 202 is connected to the cavity 201, and the pump 202 can serve as a power source for the working fluid in the cavity 201, providing power for the flow of the working fluid. During the flow process, the working fluid can serve as a carrier for heat transfer, taking the heat away from the electronic functional components, thereby achieving the control of the temperature of the electronic functional components. In the embodiment of the present application, the cavity 201 provides a flow track / place for the flow of the working fluid, and the cavity 201 can be arranged in the housing 100 of the electronic device. The embodiment of the present application does not specifically limit the type of the pump 202. In some feasible implementation methods, the pump 202 can adopt a micro piezoelectric liquid pump, the micro piezoelectric liquid pump has an amplitude of ≤50um, is ultra-thin, small in size, simple in structure, high in pressure and small in flow, no electromagnetic interference, and low in working noise. It can achieve precise fluid delivery and control, and is particularly suitable for electronic devices such as mobile phones, watches, and accessories.

[0040] Usually, piezoelectric pumps need to be driven by high-voltage AC power. In order to reduce the noise generated by the piezoelectric pumps, high-voltage sinusoidal AC power is usually used. Figure 2 As shown, since the power supply 300 of the electronic device 10 can usually only provide a direct current (DC) voltage of 3-5V, it is necessary to convert the DC voltage output by the power supply 300 into a high-voltage sinusoidal AC power (such as Figure 2 , the peak-to-peak value of the high-voltage sinusoidal AC in the example is 200 Vpp) to drive the piezoelectric fluid pump 202.

[0041] Reference Figure 3 As shown, a specific circuit structure of an inverter circuit 400 is provided. The inverter circuit 400 includes a boost circuit 401, an inverter 402 and a filter circuit 403. The input voltage U in For a DC voltage, a boost circuit 401 (for example, Figure 3 The boost circuit is used in the input voltage U in Boost the voltage to get a high voltage DC voltage U boost ; The high voltage DC voltage U boost As the inverter 402 ( Figure 3 The H-bridge inverter is used as the input, and the inverter 402 adopts a sinusoidal pulse width modulation (SPWM) strategy, and the output SPWM wave is filtered by the filter circuit 403 ( Figure 3 The LC filter circuit is used in the circuit) to obtain high voltage sinusoidal AC as the drive of the load (piezoelectric fluid pump). For details, refer to Figure 3As shown, the boost circuit 401 includes an inductor L1, a switch Q1 and a switch Q2. The first end of the inductor L1 is coupled to the positive electrode (+) of the power supply, the second end of the inductor L1 is coupled to the first end of the switch Q1, the second end of the switch Q1 is coupled to the negative electrode (-) of the power supply, and the negative electrode (-) of the power supply is coupled to the ground GND. The second end of the switch Q2 is coupled to the first end of the switch Q1, and the first end of the switch Q2 serves as the output end of the boost circuit. The switches Q1 and Q2 are turned on or off at a constant switching frequency through pulse width modulation (PWM), and a stable U is achieved by adjusting the duty cycle of the pulse width modulation signal. boost Output; In order to ensure the stability of the output voltage of the boost circuit, a capacitor C1 is usually coupled between the first end of the switch Q2 and the ground GND. The inverter 402 includes an H-bridge inverter composed of a switch Q3, a switch Q4, a switch Q5 and a switch Q6; wherein the first end of the switch Q3 is coupled to the output end of the boost circuit 401, the second end of the switch Q3 is coupled to the first end of the switch Q4, the second end of the switch Q4 is coupled to the ground GND, the first end of the switch Q5 is coupled to the output end of the boost circuit 401, the second end of the switch Q5 is coupled to the first end of the switch Q6, and the second end of the switch Q6 is coupled to the ground GND; the inverter 402 adopts a sinusoidal pulse width SPWM modulation strategy to control the conduction duty cycle of the switches Q3, Q4, Q5 and Q6, and outputs an SPWM wave (wherein the SPWM wave is a rectangular wave) between the second end of the switch Q3 and the second end of the switch Q5. The filter circuit 403 includes an inductor L2, an inductor L3, a capacitor C2 and a capacitor C3, wherein the first end of the inductor L2 is coupled to the second end of the switch Q3, and the second end of the inductor L2 is coupled to the first end of the load; the first end of the inductor L3 is coupled to the second end of the switch Q5, and the second end of the inductor L3 is coupled to the second end of the load; the capacitor C2 is coupled between the second end of the inductor L2 and the ground GND, and the capacitor C3 is coupled between the second end of the inductor L3 and the ground GND. In this way, the SPWM wave is filtered into a high-voltage sinusoidal AC current U by the filtering action of the filter circuit 403. o Among them, due to Figure 3 The inverter circuit 400 shown includes a filter circuit 403, and the filter circuit 403 is mainly composed of an inductor and a capacitor, which occupies a large volume or area, which is not conducive to the miniaturization of electronic equipment; in addition, the boost circuit and the six switches of the H-bridge inverter all operate in a high-frequency switching state throughout the entire process, resulting in large switching losses and low efficiency.

[0042] In another example, referring to Figure 4 As shown in FIG. 1 , a specific circuit structure of an inverter circuit 400 is provided. The inverter circuit 400 includes a boost circuit 401 and an inverter 402. The boost circuit 401 adopts Figure 3 The specific connection relationship of the boost circuit in can be referred to Figure 3The description is not repeated here; the inverter 402 adopts an H-bridge inverter. The specific connection relationship can be referred to Figure 3 The description of Figure 3 The difference between the inverter circuit shown is that the second ends of the switch Q4 and the switch Q6 are both coupled to the power supply U in The positive electrode (+) of the power supply is connected to the positive electrode (+) of the power supply, and the capacitor C1 is coupled between the first end of the switch Q2 and the second end of the switch Q4, and the second ends of the switches Q4 and Q6 are directly coupled to the two ends of the load. in For a DC voltage, a boost circuit 401 (for example, Figure 4 The boost circuit is used in the input voltage U in Boost to generate a DC bias voltage U offset The steamed bun wave U boost (Refer to Figure 5 As shown), the steamed bun wave U boost As the inverter 402 ( Figure 2 The H-bridge inverter is used as the input. The function of the H-bridge inverter is to boost Turn the direction and make the bun wave U boost Converted to sine wave, U in As the reference ground of the H-bridge inverter, it can approximately eliminate the steamed bun wave U boost A DC bias is applied to obtain a high voltage sinusoidal wave drive signal. Figure 3 The scheme shown, due to Figure 4 The inverter circuit shown in the figure no longer needs to be provided with a filter circuit, so it occupies a smaller volume and area. In addition, since the H-bridge inverter is only used for the steamed bun wave U boost Therefore, compared with the SPWM strategy control, the switching frequency of Q3-Q6 can be reduced, thereby reducing the switching loss. However, it can be understood that the device L1, switch Q1 and switch Q2 in the boost circuit usually have on-resistance, so the DC bias voltage U offset Usually not equal to U in , in some examples, refer to Figure 5 As shown, U in May be greater than the DC bias voltage U offset , then use U in As the reference ground of the H-bridge inverter, the steamed bun wave U boost When the direction is reversed, there is a large distortion near the zero crossing, and a standard sine wave cannot be generated. Therefore, how to obtain a high-voltage sine drive signal with high fidelity through the inverter circuit becomes a problem that needs to be solved.

[0043] In order to solve the above problems, an embodiment of the present application provides an inverter circuit 400, referring to Figure 6As shown, it includes: a boost circuit 401 , an inverter 402 and a reference voltage generating circuit 404 .

[0044] The input end of the boost circuit 401 is used to couple the power supply; the first input end of the inverter 402 is coupled to the output end of the boost circuit 401, and the output end of the inverter 402 is used to couple the load; the input end of the reference voltage generating circuit 404 is coupled to the output end of the boost circuit 401, and the output end of the reference voltage generating circuit 404 is coupled to the second input end of the inverter 402; the reference voltage generating circuit 404 is used to receive the voltage signal output by the output end of the boost circuit 401, and the reference voltage generating circuit 404 is also used to sample the voltage signal to generate a reference voltage U ref Output to the second input terminal of the inverter 402, wherein the reference voltage U ref Includes voltage generated from minimum sampled voltage.

[0045] For example, refer to Figure 6 As shown, the boost circuit 401 can adopt a boost circuit. The specific structure of the boost circuit can refer to Figure 3 The inverter 402 can be an H-bridge inverter, and the specific structure can be referred to Figure 3 As shown, no further details will be given. Figure 4 The difference is that Figure 6 In the embodiment, a first terminal of the reference voltage generating circuit 404 is coupled to a first terminal of the switch Q2, and a second terminal of the reference voltage generating circuit 404 is coupled to second terminals of the switch Q4 and the switch Q6.

[0046] In this way, the function of the boost circuit 401 is to make the output voltage amplitude of the inverter 402 greater than the input DC voltage U in The main module of the controller is to input DC voltage U in Boost to generate a DC bias voltage (U offset )'s steamed bun wave U boost , the DC bias voltage is recorded as V offset . Reference Figure 6 The structure of the boost circuit 401 is shown, and the expression of the output voltage of the boost circuit 401 is:

[0047] U offset is the DC bias voltage, U m For U boost The maximum value max.

[0048] The switches Q1 and Q2 of the boost circuit 401 are turned on alternately and complementary, and the output voltage U boost The relationship between the duty cycle D of the switch Q1 is:

[0049]

[0050] The controller dynamically changes U by adjusting the duty cycle D. boost The size of the modulation strategy (SPWM) and the output voltage U of the boost circuit 401 boost Schematic diagram as Figure 7 As shown, U boost That is, with a DC bias voltage U offset The steamed bun wave.

[0051] The function of the reference voltage generation circuit is to sample the voltage signal U boost , after processing, we get U boost The lowest point is taken as the reference voltage U ref (corresponding to the minimum sampling voltage), that is, the DC bias voltage U of the steamed bun wave offset The reference voltage U ref As the reference ground of the H-bridge inverter to U boost Flipping can eliminate U boost With a DC bias voltage U offset , obtain a high-voltage sinusoidal drive signal U with high fidelity o For details, please refer to Figure 8 As shown, the operating frequency of the H-bridge inverter is set to be equal to U o The frequency is the same, Q3 and Q6 are in the same conduction state (on or off), Q4 and Q5 are in the same conduction state, and Q3 and Q4 are alternately turned on and off. ref , the reference voltage U ref The value of U offset are equal, so U boost The DC bias voltage U can be eliminated offset After flipping, it becomes a sine wave output.

[0052] Reference Fig. 9 and Fig.10As shown, a specific structure of a reference voltage generating circuit 404 is provided. The reference voltage generating circuit 404 includes: a voltage tracking circuit 4042 coupled between an input terminal and an output terminal of the reference voltage generating circuit 404. The voltage tracking circuit 4042 includes: an analog-digital converter (ADC), a first memory S1, a second memory S2, a comparator OA1, an AND gate circuit &, and a digital-analog converter (DAC); the analog-digital converter ADC is coupled between the input terminal of the reference voltage generating circuit 404 and the first memory S1, the first memory S1 is coupled to the first input terminal of the comparator OA1 and the first input terminal of the AND gate circuit &; the second memory S2 is coupled to the output terminal of the AND gate circuit &, the digital-analog converter DAC, and the second input terminal of the comparator OA1; the output terminal of the comparator OA1 is coupled to the second input terminal of the AND gate circuit &; the output terminal of the digital-analog converter DAC is coupled to the output terminal of the reference voltage generating circuit 404. In some examples, the first memory S1 may be a first in first out (FIFO) memory, and the second memory S2 may be a register.

[0053] In addition, refer to Fig. 9 and Fig.10 As shown, the reference voltage generating circuit 404 also includes: a voltage sampling circuit 4041 and a voltage amplifying circuit 4043; the voltage sampling circuit 4041 is coupled between the input end of the reference voltage generating circuit 404 and the voltage tracking circuit 4042; the voltage amplifying circuit 4043 is arranged between the voltage tracking circuit 4042 and the output end of the reference voltage generating circuit 404; the voltage sampling circuit 4041 has a first sampling ratio, the voltage amplifying circuit 4043 has a first amplifying ratio, and the product of the first amplifying ratio and the first sampling ratio is 1.

[0054] Combination Fig.10 As shown, the voltage sampling circuit 4041 includes: a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is coupled to the input end of the reference voltage generating circuit 404, and is used to receive the voltage U output by the boost circuit 401 boost The second end of the first resistor R1 is coupled to the first end of the second resistor R2, and the second end of the first resistor R1 is also coupled to the voltage tracking circuit 4042; the second end of the second resistor R2 is coupled to the ground GND. The voltage amplifier circuit 4043 includes a positive feedback amplifier circuit or a negative feedback amplifier circuit. Fig.10As shown, a negative feedback amplifier circuit is provided, which includes an operational amplifier OA2, the positive terminal (+) of the operational amplifier OA2 is coupled to the voltage tracking circuit 4042 through a resistor R3; the negative terminal (-) of the operational amplifier OA2 is coupled to the ground GND through a resistor R4; the output terminal of the operational amplifier OA2 is coupled to the negative terminal (-) of the operational amplifier OA2 through a resistor R5. boost Therefore, the sampling ratio of the voltage sampling circuit 4041 (ie, R1 / R2) has an influence on U boost The voltage amplitude of the voltage sampling circuit is reduced to a certain extent. Therefore, the voltage amplifier circuit 4043 needs to be used to amplify the reduction caused by the voltage sampling circuit in the form of gain at a certain amplification ratio.

[0055] Reference Fig. 9 and Fig.10 As shown, the reference voltage generating circuit 404 also includes: an impedance matching circuit 4044 arranged between the voltage amplifier circuit 4043 and the output end of the reference voltage generating circuit 404. Among them, the impedance matching circuit 4044 is mainly used to match the resistance impedance between the voltage amplifier circuit 4043 and the impedance of the H-bridge inverter to ensure the impedance matching of the system line and the normal transmission of the voltage. In some examples, the impedance matching circuit 4044 can adopt a voltage follower OA3. The voltage follower OA3 includes a positive terminal (+) and a reverse terminal (-), the positive terminal (+) of the voltage follower is coupled to the output terminal of the operational amplifier OA2, and the output terminal of the voltage follower is coupled to the reverse terminal (-) of the voltage follower OA3.

[0056] Based on the above Fig. 9 and Fig.10 The reference voltage generating circuit 404 shown has its functions specifically described as follows:

[0057] First, the voltage sampling circuit 4041 detects the voltage signal U output by the boost circuit 401. boost Sampling is performed, for example, the sampling ratio of the voltage sampling circuit 4041 is k1 (ie, R1 / R2=k1).

[0058] Then, the ADC performs analog-to-digital (AD) conversion on the sampled voltage to obtain a digital signal B, which is stored in the FIFO memory S1; wherein the value in the register S2 is recorded as the digital signal A, wherein the digital signal A can be the voltage signal U boost The digital signal obtained by sampling the voltage for the first time before sampling the digital signal B, or a default initial value set in the register S2 based on experience, it should be noted that, referring to Fig.11As shown, the voltage tracking circuit 4042 may include: a selection switch K1; a common end of the selection switch K1 coupled to the output end of the analog-to-digital converter ADC; a first selection end of the selection switch K1 coupled to the first memory S1; and a second selection end of the selection switch K1 coupled to the second memory S2. In this way, when determining whether the voltage signal U is first boost When sampling, the common end of the selection switch K1 can be controlled to be connected to the second selection end to transmit the obtained digital signal A to the register S2; then the common end of the selection switch K1 is connected to the first selection end, and the generated digital signal is transmitted to the FIFO memory S1 in sequence during the subsequent voltage sampling process.

[0059] Afterwards, register S2 sends digital signal A to comparator OA1, FIFO memory S1 sends digital signal B to comparator OA1, comparator OA1 compares digital signal A and digital signal B to generate a comparison result; FIFO memory S1 sends digital signal B to AND gate circuit &, and comparator OA1 sends the comparison result to AND gate circuit &, AND gate circuit & performs AND operation on digital signal B and the comparison result, and outputs the operation result, wherein, when the voltage corresponding to digital signal A is greater than the voltage corresponding to digital signal B, the comparison result may be logic "1", then AND gate circuit & performs AND operation on digital signal B and logic "1", and generates a first operation result, wherein the first operation result includes digital signal B; or, when the voltage corresponding to digital signal A is less than the voltage corresponding to digital signal B, the comparison result may be logic "0", then AND gate circuit & performs AND operation on digital signal B and logic "0", and generates a second operation result, which may include logic "0". Register S2 stores digital signal B according to the first operation result, or keeps storing digital signal A according to the second operation result. Afterwards, the digital-to-analog converter DAC converts the digital signal (A or B) stored in the register S2 into an analog voltage; finally, the reference voltage generating circuit 404 generates a reference voltage U according to the analog voltage. ref ; In this way, the voltage signal U boost After one or more cycles of sampling, the digital signal stored in the register is updated to a digital signal corresponding to the minimum sampling voltage. The reference voltage generating circuit 404 generates a reference voltage Uref according to the analog voltage, including: the analog voltage is amplified by the voltage amplifier circuit 4043, the amplification ratio of the voltage amplifier circuit 4043 is k2, and the following relationship exists: k1*k2=1; the amplified analog signal is impedance matched by the impedance matching circuit 4044 to generate the reference voltage U ref The output serves as the reference ground for the H-bridge inverter.

[0060] Optionally, an embodiment of the present application further provides a chip, including a substrate and an inverter circuit fabricated on the substrate.

[0061] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An inverter circuit, characterized in that: include: A boost circuit, wherein an input end of the boost circuit is used for coupling a power supply; An inverter, wherein a first input end of the inverter is coupled to an output end of the boost circuit, and an output end of the inverter is used to couple to a load; a reference voltage generating circuit, wherein an input end of the reference voltage generating circuit is coupled to an output end of the boost circuit, and an output end of the reference voltage generating circuit is coupled to a second input end of the inverter; The reference voltage generating circuit is used to receive the voltage signal output by the output end of the boost circuit; The reference voltage generating circuit is further used for sampling the voltage signal to generate a reference voltage to be output to the second input terminal of the inverter, wherein the reference voltage is a voltage generated according to a minimum sampling voltage of the voltage signal.

2. The inverter circuit according to claim 1, characterized in that: The reference voltage generating circuit comprises: a voltage tracking circuit coupled between an input terminal and an output terminal of the reference voltage generating circuit; The voltage tracking circuit comprises: an analog-to-digital converter, a first memory, a second memory, a comparator, an AND gate circuit and a digital-to-analog converter; The analog-to-digital converter is coupled between the input end of the reference voltage generating circuit and the first memory, the first memory is coupled to the first input end of the comparator and the first input end of the AND gate circuit; the second memory is coupled to the output end of the AND gate circuit, the digital-to-analog converter and the second input end of the comparator; the output end of the comparator is coupled to the second input end of the AND gate circuit; the output end of the digital-to-analog converter is coupled to the output end of the reference voltage generating circuit.

3. The inverter circuit according to claim 2, characterized in that: The analog-to-digital converter is used to convert the second sampled voltage of the voltage signal into a second digital signal; The first memory is used to store the second digital signal; The second memory is used to store a first digital signal, where the first digital signal is a digital signal corresponding to a first sampling voltage of the voltage signal; The comparator is used to compare the first digital signal and the second digital signal to generate a comparison result; The AND gate circuit is used to perform an AND operation on the first digital signal and the comparison result, and output an operation result, wherein when the voltage corresponding to the first digital signal is greater than the voltage corresponding to the second digital signal, a first operation result is generated; or when the voltage corresponding to the first digital signal is less than the voltage corresponding to the second digital signal, a second operation result is generated; The second memory is used to store the second digital signal according to the first operation result, or to keep storing the first digital signal according to the second operation result; The digital-to-analog converter is used to convert the first digital signal or the second digital signal into an analog voltage, wherein the reference voltage generating circuit generates the reference voltage according to the analog voltage.

4. The inverter circuit according to claim 3, characterized in that: The reference voltage generating circuit further includes: a selection switch; The common end of the selection switch is coupled to the output end of the analog-to-digital converter, the first selection end of the selection switch is coupled to the first memory, and the second selection end of the selection switch is coupled to the second memory.

5. The inverter circuit according to any one of claims 2 to 4, characterized in that: Also includes: Voltage sampling circuit and voltage amplifying circuit; The voltage sampling circuit is coupled between the input terminal of the reference voltage generating circuit and the voltage tracking circuit; The voltage amplifying circuit is coupled between the voltage tracking circuit and the output end of the reference voltage generating circuit; The voltage sampling circuit has a first sampling ratio, the voltage amplifying circuit has a first amplifying ratio, and the product of the first amplifying ratio and the first sampling ratio is 1.

6. The inverter circuit according to claim 5, characterized in that: Also includes: The impedance matching circuit is coupled between the voltage amplifying circuit and the output end of the reference voltage generating circuit.

7. The inverter circuit according to claim 5, characterized in that: The voltage sampling circuit comprises: a first resistor and a second resistor; The first end of the first resistor is coupled to the input end of the reference voltage generating circuit. The second end of the first resistor is coupled to the first end of the second resistor, and the second end of the first resistor is also coupled to the voltage tracking circuit; the second end of the second resistor is coupled to the ground.

8. The inverter circuit according to claim 5, characterized in that: The voltage amplifier circuit includes a positive feedback amplifier circuit or a negative feedback amplifier circuit.

9. The inverter circuit according to claim 6, characterized in that: The impedance matching circuit includes a voltage follower.

10. The inverter circuit according to any one of claims 1 to 9, characterized in that: The voltage boost circuit includes: a boost circuit.

11. The inverter circuit according to any one of claims 1 to 10, characterized in that: The inverter includes: an H-bridge inverter.

12. A chip, characterized in that: It comprises a substrate, and an inverter circuit as claimed in any one of claims 1 to 11 arranged on the substrate.

13. An electronic device, characterized in that: It comprises a pump and an inverter circuit as described in any one of claims 1 to 11; the inverter circuit is connected to the pump.

14. The electronic device according to claim 13, characterized in that: The electronic device comprises a liquid cooling module, the liquid cooling module comprises the pump and a cavity, and the pump is used to drive the working medium to flow in the cavity.

15. The electronic device according to claim 14, characterized in that: The cavity is arranged in the housing of the electronic device.

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