Hysteresis comparator

Abstract

The invention provides a hysteresis comparator, which comprises a bias voltage providing module, a switch control module, a hysteresis amount adjusting module and a hysteresis comparison module, and is characterized in that the switch control module outputs multiple paths of intermediate switch signals to the hysteresis amount adjusting module to control the on-off of currents of multiple branches in the hysteresis amount adjusting module; therefore, a current signal with an adjustable numerical value is provided for the hysteresis comparison module, and the larger the numerical value of the current signal is, the larger the hysteresis voltage interval of the hysteresis comparator is, so that the hysteresis voltage interval of the hysteresis comparator can be flexibly adjusted.

Description

Technical Field

[0001] The present application relates to the technical field of comparator integrated circuits, and in particular to a hysteresis comparator. Background Art

[0002] A hysteresis comparator, also known as a hysteresis comparator or a Schmitt trigger, belongs to the field of electronic technology, and plays an important role in the design of analog circuits and digital circuits.

[0003] The core characteristic of the hysteresis comparator is the hysteresis characteristic. The hysteresis comparator has a hysteresis region, that is, the output signal will change state only when the input signal reaches two different thresholds (a high threshold and a low threshold). The hysteresis characteristic makes the hysteresis comparator more stable and reliable when processing noise and fluctuating signals. Furthermore, the hysteresis comparator has a comparison function, which can compare the input signal with the reference level, determine whether the input signal is higher or lower than the reference level, and generate a corresponding output signal accordingly. The comparison function of the hysteresis comparator is particularly important in applications such as signal detection and signal synchronization. In addition, the hysteresis comparator also has the ability to convert continuous analog signals into binary digital signals (digital signal conversion function), which has been widely used in digital signal processing circuits such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).

[0004] At present, the traditional hysteresis comparator mainly realizes its hysteresis characteristics through positive feedback, which makes the output state of the comparator flip after the input signal reaches a certain threshold, and maintains the current output state before the input signal returns to another threshold, thereby forming a hysteresis interval (also called hysteresis window). However, the hysteresis interval of the traditional hysteresis comparator cannot be adjusted when the feedback network is fixed. In addition, the power supply of the digital logic circuit and the analog logic circuit in most traditional hysteresis comparators is not separated, resulting in mutual interference between the digital logic circuit and the analog logic circuit, affecting the accuracy of the output. Summary of the invention

[0005] The present application provides a hysteresis comparator that can solve at least one of the following problems: the hysteresis interval (hysteresis voltage interval) of the traditional hysteresis comparator cannot be adjusted; the digital logic circuit and the analog logic circuit in the hysteresis comparator interfere with each other, thereby affecting the output accuracy.

[0006] The embodiment of the present application provides a hysteresis comparator, comprising: a bias voltage providing module, a switch control module, a hysteresis adjustment module and a hysteresis comparison module, wherein:

[0007] The bias voltage providing module is used to provide bias voltages to multiple branches in the hysteresis adjustment module, and to provide bias voltages to multiple branches in the hysteresis comparison module;

[0008] The switch control module is used to receive multiple control signals input from the outside, and perform internal logic processing according to the multiple control signals to output multiple intermediate switch signals to the hysteresis adjustment module to control the on and off of currents of multiple branches in the hysteresis adjustment module;

[0009] The hysteresis adjustment module is used to provide a current signal with adjustable value to the hysteresis comparison module according to the intermediate switch signal;

[0010] The hysteresis comparison module is used to receive an externally input differential signal, perform signal amplification and comparison processing according to the differential signal and the current signal, and output a first voltage signal and a second voltage signal to a subsequent circuit.

[0011] Optionally, in the hysteresis comparator, the hysteresis comparator also includes: a first power supply module and a second power supply module, wherein the first power supply module is connected to the hysteresis adjustment module to supply power to the hysteresis adjustment module; and the second power supply module is connected to the hysteresis comparison module to supply power to the hysteresis comparison module.

[0012] Optionally, in the hysteresis comparator, the bias voltage providing module includes: transistor Q1, transistor Q2, transistor Q3, transistor Q4, transistor Q5, transistor Q23, transistor Q24, transistor Q27, resistor R1, resistor R2, resistor R3, resistor R6, resistor R7 and resistor R8, wherein,

[0013] One end of the resistor R6 is connected to the positive electrode of the second power supply module, and the other end of the resistor R6 is connected to the collector of the transistor Q23, the base of the transistor Q23 is connected to the collector of the transistor Q23, the emitter of the transistor Q23 is connected to the collector of the transistor Q24, the base of the transistor Q24 is connected to the collector of the transistor Q24, the emitter of the transistor Q24 is connected to the collector of the transistor Q27, the base of the transistor Q27 is connected to the collector of the transistor Q27, the emitter of the transistor Q27 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the collector of the transistor Q1, and the The emitter of the transistor Q1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the negative electrode of the second power module, the base of the transistor Q1 is also connected to the base of the transistor Q2, the collector of the transistor Q2 is connected to the emitter of the transistor Q5, the collector of the transistor Q5 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to the positive electrode of the first power module, the emitter of the transistor Q2 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the negative electrode of the second power module, and the base of the transistor Q2 is also connected to the hysteresis comparison module to provide bias voltage for multiple branches in the hysteresis comparison module;

[0014] The resistor R7 is connected between the base of the transistor Q5 and the base of the transistor Q3, the collector of the transistor Q3 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the positive electrode of the first power module, the emitter of the transistor Q3 is connected to the base of the transistor Q3, the emitter of the transistor Q3 is also connected to the collector of the transistor Q4, the emitter of the transistor Q4 is connected to the negative electrode of the first power module, the base of the transistor Q4 is connected to the series node between the transistor Q5 and the transistor Q2, and the base of the transistor Q3 is also connected to the hysteresis adjustment module to provide bias voltage to multiple branches in the hysteresis adjustment module.

[0015] Optionally, in the hysteresis comparator, the hysteresis adjustment module includes: first to fifth branches, wherein:

[0016] The first branch includes: a resistor R4, a transistor Q6, a transistor Q7 and a first switch unit M5, wherein one end of the resistor R4 is connected to the positive electrode of the first power module, the other end of the resistor R4 is connected to the collector of the transistor Q6, the emitter of the transistor Q6 is connected to the collector of the transistor Q7, the collector of the transistor Q7 is also connected to the first end of the first switch unit M5, the second end of the first switch unit M5 is connected to the negative electrode of the first power module, and the third end of the first switch unit M5 is connected to the first output end of the switch control module to receive the first intermediate switch signal of the switch control module;

[0017] The second branch includes: a resistor R5, a transistor Q8, a transistor Q9 and a second switch unit M4, wherein one end of the resistor R5 is connected to the positive electrode of the first power module, the other end of the resistor R5 is connected to the collector of the transistor Q8, the emitter of the transistor Q8 is connected to the collector of the transistor Q9, the collector of the transistor Q9 is also connected to the first end of the second switch unit M4, the second end of the second switch unit M4 is connected to the negative electrode of the first power module, and the third end of the second switch unit M4 is connected to the second output end of the switch control module to receive the second intermediate switch signal of the switch control module;

[0018] The third branch includes: a resistor R9, a transistor Q10, a transistor Q11 and a third switch unit M3, wherein one end of the resistor R9 is connected to the positive electrode of the first power module, the other end of the resistor R9 is connected to the collector of the transistor Q10, the emitter of the transistor Q10 is connected to the collector of the transistor Q11, the collector of the transistor Q11 is also connected to the first end of the third switch unit M3, the second end of the third switch unit M3 is connected to the negative electrode of the first power module, and the third end of the third switch unit M3 is connected to the third output end of the switch control module to receive the third intermediate switch signal of the switch control module;

[0019] The fourth branch includes: a resistor R10, a transistor Q12, a transistor Q13 and a fourth switch unit M2, wherein one end of the resistor R10 is connected to the positive electrode of the first power module, the other end of the resistor R10 is connected to the collector of the transistor Q12, the emitter of the transistor Q12 is connected to the collector of the transistor Q13, the collector of the transistor Q13 is also connected to the first end of the fourth switch unit M2, the second end of the fourth switch unit M2 is connected to the negative electrode of the first power module, and the third end of the fourth switch unit M2 is connected to the fourth output end of the switch control module to receive the fourth intermediate switch signal of the switch control module;

[0020] The fifth branch includes: a resistor R11, a transistor Q14, a transistor Q15 and a fifth switch unit M1, wherein one end of the resistor R11 is connected to the positive electrode of the first power module, the other end of the resistor R11 is connected to the collector of the transistor Q14, the emitter of the transistor Q14 is connected to the collector of the transistor Q15, the collector of the transistor Q15 is also connected to the first end of the fifth switch unit M1, the second end of the fifth switch unit M1 is connected to the negative electrode of the first power module, and the third end of the fifth switch unit M1 is connected to the fifth output end of the switch control module to receive the fifth intermediate switch signal of the switch control module;

[0021] Among them, the base of the transistor Q15, the base of the transistor Q13, the base of the transistor Q11, the base of the transistor Q9 and the base of the transistor Q7 are all connected to the negative electrode of the first power supply module; the emitter of the transistor Q15, the emitter of the transistor Q13, the emitter of the transistor Q11, the emitter of the transistor Q9 and the emitter of the transistor Q7 are connected and then connected to the hysteresis comparison module to provide the hysteresis comparison module with a current signal with adjustable value.

[0022] Optionally, in the hysteresis comparator, the first switch unit M5, the second switch unit M4, the third switch unit M3, the fourth switch unit M2 and the fifth switch unit M1 are all NMOS tubes, wherein the first end of the first switch unit M5 is the drain end of the NMOS tube, the second end of the first switch unit M5 is the source end of the NMOS tube, and the third end of the first switch unit M5 is the gate end of the NMOS tube; the first end of the second switch unit M4 is the drain end of the NMOS tube, the second end of the second switch unit M4 is the source end of the NMOS tube, and the third end of the second switch unit M4 is the gate end of the NMOS tube. the gate terminal of the third switch unit M3; the first end of the third switch unit M3 is the drain terminal of the NMOS tube, the second end of the third switch unit M3 is the source terminal of the NMOS tube, and the third end of the third switch unit M3 is the gate terminal of the NMOS tube; the first end of the fourth switch unit M2 is the drain terminal of the NMOS tube, the second end of the fourth switch unit M2 is the source terminal of the NMOS tube, and the third end of the fourth switch unit M2 is the gate terminal of the NMOS tube; the first end of the fifth switch unit M1 is the drain terminal of the NMOS tube, the second end of the fifth switch unit M1 is the source terminal of the NMOS tube, and the third end of the fifth switch unit M1 is the gate terminal of the NMOS tube.

[0023] Optionally, in the hysteresis comparator, the hysteresis comparison module includes: resistor R13, resistor R14, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, resistor R22, resistor R23, resistor R24, resistor R25, transistor Q18, transistor Q19, transistor Q20, transistor Q21, transistor Q25, transistor Q26, transistor Q28, transistor Q29, transistor Q30, transistor Q31, transistor Q32, transistor Q33, transistor Q34, transistor Q35, transistor Q36, transistor Q37 and transistor Q38, wherein,

[0024] The collector of the transistor Q18 is connected to the emitter of the transistor Q15, the base of the transistor Q18 is connected to the collector of the transistor Q18, the emitter of the transistor Q18 is connected to the collector of the transistor Q20, the emitter of the transistor Q20 is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the negative electrode of the second power module, the base of the transistor Q18 is also connected to the base of the transistor Q19, the emitter of the transistor Q19 is connected to the collector of the transistor Q21, the base of the transistor Q21 is respectively connected to the base of the transistor Q20 and the collector of the transistor Q21, the emitter of the transistor Q21 is connected to one end of the resistor R14, the other end of the resistor R14 is connected to the negative electrode of the second power module, and the collector of the transistor Q19 is connected to the emitter of the transistor Q25;

[0025] The base of the transistor Q25 is connected to the emitter of the transistor Q25, the collector of the transistor Q25 is connected to one end of the resistor R16, the other end of the resistor R16 is connected to the positive electrode of the second power module, the base of the transistor Q25 is also connected to the base of the transistor Q26, the collector of the transistor Q26 is connected to one end of the resistor R17, the other end of the resistor R17 is connected to the positive electrode of the second power module, and the emitter of the transistor Q26 is connected to the base of the transistor Q26. The collector of the transistor Q28, the emitter of the transistor Q28 is connected to one end of the resistor R19, the other end of the resistor R19 is connected to the negative electrode of the second power module, the resistor R18 is connected between the base of the transistor Q28 and the base of the transistor Q29, the collector of the transistor Q28 is connected to the base of the transistor Q29, the emitter of the transistor Q29 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the negative electrode of the second power module;

[0026] The emitter of the transistor Q30 is connected to the emitter of the transistor Q31 and then connected to the collector of the transistor Q32. The emitter of the transistor Q32 is connected to one end of the resistor R21, and the other end of the resistor R21 is connected to the negative electrode of the second power module. The collector of the transistor Q30 is connected to one end of the resistor R22, and the other end of the resistor R22 is connected to the positive electrode of the second power module. The collector of the transistor Q31 is connected to one end of the resistor R23, and the other end of the resistor R23 is connected to the positive electrode of the second power module. The base of the transistor Q30 and the base of the transistor Q31 receive a pair of differential signals input from the outside.

[0027] The collector of the transistor Q30 is also connected to the base of the transistor Q38, the collector of the transistor Q38 is connected to the positive electrode of the second power module, the emitter of the transistor Q38 is connected to the collector of the transistor Q34, the emitter of the transistor Q34 is connected to one end of the resistor R25, and the other end of the resistor R25 is connected to the negative electrode of the second power module;

[0028] The collector of the transistor Q37 is connected to the positive electrode of the second power module, the emitter of the transistor Q37 is connected to the collector of the transistor Q33, the emitter of the transistor Q33 is connected to one end of the resistor R24, and the other end of the resistor R24 ​​is connected to the negative electrode of the second power module;

[0029] The emitter of the transistor Q35 is connected to the emitter of the transistor Q36 and then connected to the collector of the transistor Q29. The emitter of the transistor Q29 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the negative electrode of the second power module. The collector of the transistor Q35 is connected to the collector of the transistor Q30, and the collector of the transistor Q36 is connected to the collector of the transistor Q31. The base of the transistor Q35 is connected to the emitter of the transistor Q37, and the base of the transistor Q36 is connected to the emitter of the transistor Q38.

[0030] The base of the transistor Q32, the base of the transistor Q33 and the base of the transistor Q34 are all connected to the base of the transistor Q2 to receive the bias voltage provided by the bias voltage providing module;

[0031] Among them, transistors Q18 to Q21, resistor R13 and resistor R14 constitute a first current mirror; transistors Q25, Q26, Q28, Q29, resistor R19 and resistor R20 constitute a second current mirror; the transistor Q30 and the transistor Q31 constitute a first differential pair; the transistor Q35 and the transistor Q36 constitute a second differential pair.

[0032] Optionally, in the hysteresis comparator, the switch control module includes: first to third control signal input terminals, first to fifth switch signal output terminals, first to third inverters, first to seventh NAND gates, first NOR gates and second NOR gates, the first control signal input terminal is respectively connected to the first terminal of the first NAND gate, the input terminal of the second inverter and the first input terminal of the second NOR gate; the second control signal input terminal is respectively connected to the input terminal of the first inverter, the second input terminal of the second NAND gate, the first input terminal of the first NOR gate and the second input terminal of the second NOR gate; the third control signal input terminal is respectively connected to the input terminal of the third inverter, the second input terminal of the seventh NAND gate, the second input terminal of the first NOR gate and the third input terminal of the second NOR gate; the output terminal of the first inverter is respectively connected to the second input terminal of the first NAND gate and the second input terminal of the fourth NAND gate; The output end of the second inverter is respectively connected to the first input end of the second NAND gate, the first input end of the third NAND gate and the first input end of the fourth NAND gate, and the output end of the third inverter is connected to the second input end of the third NAND gate; the output ends of the first NAND gate are respectively connected to the first end of the fifth NAND gate and the first input end of the sixth NAND gate; the output end of the second NAND gate is connected to the second input end of the fifth NAND gate; the output end of the third NAND gate is connected to the second input end of the sixth NAND gate; the output end of the fourth NAND gate is connected to the first input end of the seventh NAND gate; the output end of the fifth NAND gate is connected to the first switch signal output end, the output end of the sixth NAND gate is connected to the second switch signal output end, the output end of the seventh NAND gate is connected to the fourth switch signal output end, the output end of the first NOR gate is connected to the third switch signal output end, and the output end of the second NOR gate is connected to the fifth switch signal output end.

[0033] The technical solution of this application has at least the following advantages:

[0034] The present application provides a hysteresis comparator, comprising: a bias voltage providing module, a switch control module, a hysteresis amount adjustment module and a hysteresis comparison module. The present application outputs multiple intermediate switch signals to the hysteresis amount adjustment module through the switch control module to control the on and off of currents in multiple branches in the hysteresis amount adjustment module, thereby providing the hysteresis comparison module with a current signal whose value can be adjusted, and realizing positive feedback through the current. The larger the value of the current signal, the larger the hysteresis voltage range of the hysteresis comparator, thereby making the hysteresis voltage range of the hysteresis comparator flexibly adjustable.

[0035] Furthermore, the present application utilizes a first power supply module to power a hysteresis adjustment module (digital logic circuit) and utilizes a second power supply module to power a hysteresis comparison module (analog logic circuit), wherein the power supply of the hysteresis comparison module (analog logic circuit) can be adjusted according to the input common mode range without affecting the power supply of the hysteresis adjustment module (digital logic circuit). The present application separates the power supply of the digital logic circuit and the analog logic circuit, thereby effectively reducing the interference between the two and improving the accuracy of the device output results. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 is a schematic diagram of the circuit structure of a hysteresis comparator according to an embodiment of the present invention;

[0038] Figure 2 is a schematic diagram of the circuit structure of a switch control module according to an embodiment of the present invention;

[0039] The reference numerals are described as follows:

[0040] 10 - bias voltage providing module, 20 - switch control module, 30 - hysteresis adjustment module, 40 - hysteresis comparison module. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0042] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0043] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0044] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0045] The present application embodiment provides a hysteresis comparator, referring to Figure 1 , Figure 1 is a circuit structure diagram of a hysteresis comparator according to an embodiment of the present invention, wherein the hysteresis comparator comprises: a bias voltage providing module 10, a switch control module 20, a hysteresis amount adjusting module 30 and a hysteresis comparing module 40, wherein:

[0046] The bias voltage providing module 10 is used to provide bias voltages to multiple branches in the hysteresis adjustment module 30, and to provide bias voltages to multiple branches in the hysteresis comparison module 40;

[0047] The switch control module 20 is used to receive multiple control signals input from the outside, and perform internal logic processing according to the multiple control signals to output multiple intermediate switch signals to the hysteresis adjustment module 30 to control the on and off of the currents of multiple branches in the hysteresis adjustment module 30;

[0048] The hysteresis adjustment module 30 is used to provide a current signal with adjustable value to the hysteresis comparison module 40 according to the intermediate switch signal;

[0049] The hysteresis comparison module 40 is used to receive a differential signal input from the outside, perform signal amplification and comparison processing according to the differential signal and the current signal, and output a first voltage signal and a second voltage signal to a subsequent circuit.

[0050] Furthermore, the hysteresis comparator may also include: a first power supply module and a second power supply module, wherein the first power supply module is connected to the hysteresis adjustment module 30 to supply power to the hysteresis adjustment module 30; and the second power supply module is connected to the hysteresis comparison module 40 to supply power to the hysteresis comparison module 40.

[0051] In this embodiment, the positive electrode of the first power module is VDD, and the negative electrode is DGND; the positive electrode of the second power module is VCC, and the negative electrode is VEE.

[0052] In the present application, the first power supply module is used to power the hysteresis adjustment module (digital logic circuit) and the second power supply module is used to power the hysteresis comparison module (analog logic circuit), wherein the power supply of the hysteresis comparison module (analog logic circuit) can be adjusted according to the input common mode range without affecting the power supply of the hysteresis adjustment module (digital logic circuit). The present application separates the power supply of the digital logic circuit and the analog logic circuit, effectively reducing the interference between the two and improving the accuracy of the device output results.

[0053] Preferably, the bias voltage providing module 10 includes: transistor Q1, transistor Q2, transistor Q3, transistor Q4, transistor Q5, transistor Q23, transistor Q24, transistor Q27, resistor R1, resistor R2, resistor R3, resistor R6, resistor R7 and resistor R8.

[0054] Among them, one end of the resistor R6 is connected to the positive electrode VCC of the second power supply module, and the other end of the resistor R6 is connected to the collector of the transistor Q23, the base of the transistor Q23 is connected to the collector of the transistor Q23, the emitter of the transistor Q23 is connected to the collector of the transistor Q24, the base of the transistor Q24 is connected to the collector of the transistor Q24, the emitter of the transistor Q24 is connected to the collector of the transistor Q27, the base of the transistor Q27 is connected to the collector of the transistor Q27, the emitter of the transistor Q27 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the collector of the transistor Q1, and the transistor The emitter of Q1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the negative electrode VEE of the second power module, the base of the transistor Q1 is also connected to the base of the transistor Q2, the collector of the transistor Q2 is connected to the emitter of the transistor Q5, the collector of the transistor Q5 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to the positive electrode VDD of the first power module, the emitter of the transistor Q2 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the negative electrode VEE of the second power module, and the base of the transistor Q2 is also connected to the hysteresis comparison module 40 to provide bias voltage to multiple branches in the hysteresis comparison module 40;

[0055] The resistor R7 is connected between the base of the transistor Q5 and the base of the transistor Q3, the collector of the transistor Q3 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the positive electrode VDD of the first power module, the emitter of the transistor Q3 is connected to the base of the transistor Q3, the emitter of the transistor Q3 is also connected to the collector of the transistor Q4, the emitter of the transistor Q4 is connected to the negative electrode DGND of the first power module, the base of the transistor Q4 is connected to the series node between the transistor Q5 and the transistor Q2, and the base of the transistor Q3 is also connected to the hysteresis adjustment module 30 to provide bias voltage to multiple branches in the hysteresis adjustment module 30.

[0056] In this embodiment, transistors Q1 , Q2 , Q23 , Q24 , and Q27 are all NPN transistors; and transistors Q3 , Q4 , and Q5 are all PNP transistors.

[0057] For further reference, Figure 2 , Figure 2: is a schematic diagram of the circuit structure of the switch control module of the embodiment of the present invention, the switch control module 20 includes: first to third control signal input terminals HYST0~HYST2, first to fifth switch signal output terminals U5~U1, first to third inverters X1~X3, first to seventh NAND gates D1~D3, first NOR gate N1 and second NOR gate N2, the first control signal input terminal HYST0 is respectively connected to the first end of the first NAND gate D1, the input end of the second inverter X2 and the first input end of the second NOR gate N2; the second control signal input terminal HYST1 is respectively connected to the input end of the first inverter X1, the second input end of the second NAND gate D2, the first input end of the first NOR gate N1 and the second input end of the second NOR gate N2, the third control signal input terminal HYST2 is respectively connected to the input end of the third inverter X3, the second input end of the seventh NAND gate D7, the second input end of the first NOR gate N1 and the third input end of the second NOR gate N2; the output end of the first inverter X1 is respectively connected to the second input end of the first NAND gate D1 The output end of the second inverter X2 is connected to the first input end of the second NAND gate D2, the first input end of the third NAND gate D3 and the first input end of the fourth NAND gate D4 respectively, and the output end of the third inverter X3 is connected to the second input end of the third NAND gate D3; the output end of the first NAND gate D1 is connected to the first end of the fifth NAND gate D5 and the first input end of the sixth NAND gate D6 respectively; the output end of the second NAND gate D2 is connected to the second input end of the fifth NAND gate D5; the output end of the third NAND gate D3 is connected to the second input end of the sixth NAND gate D6; the output end of the fourth NAND gate D4 is connected to the first input end of the seventh NAND gate D7; the output end of the fifth NAND gate D5 is connected to the first switch signal output end U5, the output end of the sixth NAND gate D6 is connected to the second switch signal output end U4, the output end of the seventh NAND gate D7 is connected to the fourth switch signal output end U2, the output end of the first NOR gate N1 is connected to the third switch signal output end U3, and the output end of the second NOR gate N2 is connected to the fifth switch signal output end U1.

[0058] Preferably, the hysteresis adjustment module 30 includes: first to fifth branches, wherein:

[0059] The first branch includes: a resistor R4, a transistor Q6, a transistor Q7 and a first switch unit M5, wherein one end of the resistor R4 is connected to the positive electrode VDD of the first power module, the other end of the resistor R4 is connected to the collector of the transistor Q6, the emitter of the transistor Q6 is connected to the collector of the transistor Q7, the collector of the transistor Q7 is also connected to the first end of the first switch unit M5, the second end of the first switch unit M5 is connected to the negative electrode DGND of the first power module, and the third end of the first switch unit M5 is connected to the first output end U5 of the switch control module to receive the first intermediate switch signal of the switch control module;

[0060] The second branch includes: a resistor R5, a transistor Q8, a transistor Q9 and a second switch unit M4, wherein one end of the resistor R5 is connected to the positive electrode VDD of the first power module, the other end of the resistor R5 is connected to the collector of the transistor Q8, the emitter of the transistor Q8 is connected to the collector of the transistor Q9, the collector of the transistor Q9 is also connected to the first end of the second switch unit M4, the second end of the second switch unit M4 is connected to the negative electrode DGND of the first power module, and the third end of the second switch unit M4 is connected to the second output end U4 of the switch control module to receive the second intermediate switch signal of the switch control module;

[0061] The third branch includes: a resistor R9, a transistor Q10, a transistor Q11 and a third switch unit M3, wherein one end of the resistor R9 is connected to the positive electrode VDD of the first power module, the other end of the resistor R9 is connected to the collector of the transistor Q10, the emitter of the transistor Q10 is connected to the collector of the transistor Q11, the collector of the transistor Q11 is also connected to the first end of the third switch unit M3, the second end of the third switch unit M3 is connected to the negative electrode DGND of the first power module, and the third end of the third switch unit M3 is connected to the third output end U3 of the switch control module to receive the third intermediate switch signal of the switch control module;

[0062] The fourth branch includes: a resistor R10, a transistor Q12, a transistor Q13 and a fourth switch unit M2, wherein one end of the resistor R10 is connected to the positive electrode VDD of the first power module, the other end of the resistor R10 is connected to the collector of the transistor Q12, the emitter of the transistor Q12 is connected to the collector of the transistor Q13, the collector of the transistor Q13 is also connected to the first end of the fourth switch unit M2, the second end of the fourth switch unit M2 is connected to the negative electrode DGND of the first power module, and the third end of the fourth switch unit M2 is connected to the fourth output end U2 of the switch control module to receive the fourth intermediate switch signal of the switch control module;

[0063] The fifth branch includes: a resistor R11, a transistor Q14, a transistor Q15 and a fifth switch unit M1, wherein one end of the resistor R11 is connected to the positive electrode VDD of the first power module, the other end of the resistor R11 is connected to the collector of the transistor Q14, the emitter of the transistor Q14 is connected to the collector of the transistor Q15, the collector of the transistor Q15 is also connected to the first end of the fifth switch unit M1, the second end of the fifth switch unit M1 is connected to the negative electrode DGND of the first power module, and the third end of the fifth switch unit M1 is connected to the fifth output end U1 of the switch control module to receive the fifth intermediate switch signal of the switch control module;

[0064] Among them, the base of the transistor Q15, the base of the transistor Q13, the base of the transistor Q11, the base of the transistor Q9 and the base of the transistor Q7 are all connected to the negative electrode DGND of the first power supply module; the emitter of the transistor Q15, the emitter of the transistor Q13, the emitter of the transistor Q11, the emitter of the transistor Q9 and the emitter of the transistor Q7 are connected and then connected to the hysteresis comparison module 40 to provide the hysteresis comparison module 40 with a current signal I6 with adjustable value.

[0065] In this embodiment, transistors Q6 , Q7 , Q8 , Q9 , Q10 , Q11 , Q12 , Q13 , Q14 , and Q15 are all PNP transistors.

[0066] Further, the first switch unit M5, the second switch unit M4, the third switch unit M3, the fourth switch unit M2 and the fifth switch unit M1 are all NMOS tubes, wherein the first end of the first switch unit M5 is the drain end of the NMOS tube, the second end of the first switch unit M5 is the source end of the NMOS tube, and the third end of the first switch unit M5 is the gate end of the NMOS tube; the first end of the second switch unit M4 is the drain end of the NMOS tube, the second end of the second switch unit M4 is the source end of the NMOS tube, and the third end of the second switch unit M4 is the gate end of the NMOS tube; The first end of the third switch unit M3 is the drain end of the NMOS tube, the second end of the third switch unit M3 is the source end of the NMOS tube, and the third end of the third switch unit M3 is the gate end of the NMOS tube; the first end of the fourth switch unit M2 is the drain end of the NMOS tube, the second end of the fourth switch unit M2 is the source end of the NMOS tube, and the third end of the fourth switch unit M2 is the gate end of the NMOS tube; the first end of the fifth switch unit M1 is the drain end of the NMOS tube, the second end of the fifth switch unit M1 is the source end of the NMOS tube, and the third end of the fifth switch unit M1 is the gate end of the NMOS tube.

[0067] In this embodiment, HYST0, HYST1, and HYST2 are three control signals inputted from the external part of the switch control module 20, and are processed by the internal logic of the switch control module 20 to generate five intermediate switch signals U5 to U1 for controlling the first to fifth switch units (M5 to M1) to be turned on or off, wherein according to Figure 2 The circuit structure of the switch control module 20, the truth table of the switch control module 20 is shown in Table 1, and the switch control module 20 outputs U1~U5, wherein U1~U5=low level "0" or high level "1", low level "0" represents that the corresponding connected switch unit (one of M1~M5) is controlled to be turned off, and high level "1" represents that the corresponding connected switch unit (one of M1~M5) is controlled to be turned on.

[0068] Table 1

[0069]

[0070]

[0071] Further, the hysteresis comparison module 40 includes: resistor R13, resistor R14, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, resistor R22, resistor R23, resistor R24, resistor R25, transistor Q18, transistor Q19, transistor Q20, transistor Q21, transistor Q25, transistor Q26, transistor Q28, transistor Q29, transistor Q30, transistor Q31, transistor Q32, transistor Q33, transistor Q34, transistor Q35, transistor Q36, transistor Q37 and transistor Q38.

[0072] Wherein, the collector of the transistor Q18 is connected to the emitter of the transistor Q15, the base of the transistor Q18 is connected to the collector of the transistor Q18, the emitter of the transistor Q18 is connected to the collector of the transistor Q20, the emitter of the transistor Q20 is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the negative electrode VEE of the second power module, the base of the transistor Q18 is also connected to the base of the transistor Q19, the emitter of the transistor Q19 is connected to the collector of the transistor Q21, the base of the transistor Q21 is respectively connected to the base of the transistor Q20 and the collector of the transistor Q21, the emitter of the transistor Q21 is connected to one end of the resistor R14, the other end of the resistor R14 is connected to the negative electrode VEE of the second power module, and the collector of the transistor Q19 is connected to the emitter of the transistor Q25;

[0073] The base of the transistor Q25 is connected to the emitter of the transistor Q25, the collector of the transistor Q25 is connected to one end of the resistor R16, the other end of the resistor R16 is connected to the positive electrode of the second power module, the base of the transistor Q25 is also connected to the base of the transistor Q26, the collector of the transistor Q26 is connected to one end of the resistor R17, the other end of the resistor R17 is connected to the positive electrode VCC of the second power module, and the emitter of the transistor Q26 is connected to the base of the transistor Q26. The collector of the transistor Q28 is connected to the collector of the transistor Q28, the emitter of the transistor Q28 is connected to one end of the resistor R19, the other end of the resistor R19 is connected to the negative electrode VEE of the second power module, the resistor R18 is connected between the base of the transistor Q28 and the base of the transistor Q29, the collector of the transistor Q28 is connected to the base of the transistor Q29, the emitter of the transistor Q29 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the negative electrode VEE of the second power module;

[0074] The emitter of the transistor Q30 is connected to the emitter of the transistor Q31 and then connected to the collector of the transistor Q32. The emitter of the transistor Q32 is connected to one end of the resistor R21, and the other end of the resistor R21 is connected to the negative electrode VEE of the second power module. The collector of the transistor Q30 is connected to one end of the resistor R22, and the other end of the resistor R22 is connected to the positive electrode VCC of the second power module. The collector of the transistor Q31 is connected to one end of the resistor R23, and the other end of the resistor R23 is connected to the positive electrode VCC of the second power module. The base of the transistor Q30 and the base of the transistor Q31 receive a pair of differential signals VP and VN input from the outside.

[0075] The collector of the transistor Q30 is also connected to the base of the transistor Q38, the collector of the transistor Q38 is connected to the positive electrode VCC of the second power module, the emitter of the transistor Q38 is connected to the collector of the transistor Q34, the emitter of the transistor Q34 is connected to one end of the resistor R25, and the other end of the resistor R25 is connected to the negative electrode VEE of the second power module;

[0076] The collector of the transistor Q37 is connected to the positive electrode VCC of the second power module, the emitter of the transistor Q37 is connected to the collector of the transistor Q33, the emitter of the transistor Q33 is connected to one end of the resistor R24, and the other end of the resistor R24 ​​is connected to the negative electrode VEE of the second power module;

[0077] The emitter of the transistor Q35 is connected to the emitter of the transistor Q36 and then connected to the collector of the transistor Q29. The emitter of the transistor Q29 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the negative electrode VEE of the second power module. The collector of the transistor Q35 is connected to the collector of the transistor Q30, and the collector of the transistor Q36 is connected to the collector of the transistor Q31. The base of the transistor Q35 is connected to the emitter of the transistor Q37, and the base of the transistor Q36 is connected to the emitter of the transistor Q38.

[0078] The base of the transistor Q32, the base of the transistor Q33 and the base of the transistor Q34 are all connected to the base of the transistor Q2 to receive the bias voltage provided by the bias voltage providing module 10;

[0079] Among them, transistor Q18, transistor Q19, transistor Q20, transistor Q21, resistor R13 and resistor R14 constitute a first current mirror; transistor Q25, transistor Q26, transistor Q28, transistor Q29, resistor R19 and resistor R20 constitute a second current mirror; the transistor Q30 and the transistor Q31 constitute a first differential pair; the transistor Q35 and the transistor Q36 constitute a second differential pair;

[0080] The collector potential of transistor Q34 is V OUT1 The potential V at the collector of transistor Q33 is output as the first voltage signal to the subsequent circuit. OUT2 The second voltage signal is output to the subsequent circuit.

[0081] In this embodiment, transistor Q18, transistor Q19, transistor Q20, transistor Q21, transistor Q28, transistor Q29, transistor Q30, transistor Q31, transistor Q32, transistor Q33, transistor Q34, transistor Q35, transistor Q36, transistor Q37 and transistor Q38 are all NPN transistors; transistor Q25 and transistor Q26 are all PNP transistors.

[0082] In this embodiment, taking the negative electrode DGND of the first power module as the ground terminal (0V) and the negative electrode VEE of the second power module as the ground terminal (0V) as an example, the working principle is explained using the fifth branch of the switch control module 20: resistor R11, transistor Q14, transistor Q15, and fifth switch unit M1. The working principles of the remaining branches from the first branch to the fourth branch are the same. U5, U4, U3, U2, and U1 are five intermediate switch signals output from the first to fifth output terminals of the switch control module 20. Assuming that U2~U5="1", I2~I5 pass through M2~M5 to the ground. If U1="1", the NMOS tube M1 is turned on, the current I1 flowing through the fifth branch flows through the NMOS tube M1 to the negative electrode DGND (ground terminal) of the first power module, the transistor Q15 has no current, and the current of the transistors Q18~Q21 remains unchanged, which will not affect the subsequent analog logic; if U1="0", the NMOS tube M1 is turned off, the current I1 flowing through the fifth branch flows through the transistor Q15 to the first current mirror Q18~Q21, and then passes through the second current mirror Q25, Q26, Q28, and Q29 to affect the analog logic.

[0083] The working principle of the hysteresis comparison module 40 (analog logic) is as follows:

[0084] Since the triodes Q18, Q19, Q20, Q21, resistor R13 and resistor R14 form a first current mirror (improved Wilson current mirror); the triodes Q25, Q26, Q28, Q29, resistor R19, resistor R20 form a second current mirror, so I6 = I7 = I8 = I9;

[0085] A pair of differential signals VP and VN input externally are the input signals of the differential pair of the first differential pair transistors Q30, Q31. When VP - VN > 0, the differential logic is high level "1"; when VP - VN < 0, the differential logic is low level "0".

[0086] It is assumed that the physical characteristics of the triodes Q30 and Q31 are exactly the same;

[0087] It is assumed that the differential mode signal of the differential pair is Vdiff = VP - VN, and the common mode signal is Vcm = (VP + VN) / 2;

[0088] 1. When M1 to M5 are all conducting and I9 = 0,

[0089] 1.1) The differential mode signal Vdiff < 0, IC1 < IC2, V1 = VCC - IC1 * R22, V2 = VCC - IC2 * R23, so V1 > V2, V OUT1 > V OUT2 ;

[0090] 1.2) The differential mode signal Vdiff = 0, IC1 = IC2, V1 = V2, V OUT1 = V OUT2 ;

[0091] 1.3) The differential mode signal Vdiff > 0, IC1 > IC2, V1 < V2, V OUT1 < V OUT2 .

[0092] 2. When at least one of M1 to M5 is turned off and I9 > 0,

[0093] 2.1) The differential mode signal Vdiff < 0, IC1 < IC2, V1 > V2, V OUT1 > V OUT2 , causing the triode Q36 to conduct, V2 = VCC - (I9 + IC2) * R23, V1 is equivalent to the value when I9 = 0, and V1 is VCC - IC1 * R22;

[0094] 2.2) When Vdiff gradually increases to Vdiff = 0, IC1 = IC2, from 1), it can be seen that V1 > V2, V OUT1 > V OUT2 , and the output result remains unchanged;

[0095] 2.3) When Vdiff continues to increase, let V OUT1 =V OUT2 , V1=V2, and we get IC1=I9+IC2. According to the transistor transfer characteristic formula, VP=VCOM+VT*ln((IC2+I9) / IS), VN=VCOM+VT*ln(IC2 / IS), Vdiff=VP-VN=VT*ln(1+I9 / IC2), and Vdiff at this time can be called Vtrip+. Only when Vdiff>Vtrip+, V1 <V2,V OUT1 <V OUT2 , the output result is flipped;

[0096] 2.4) Similarly, in the process of Vdiff changing from large to small, Vtrip- can be obtained. In a completely symmetrical structure, ideally Vtrip+=|Vtrip-|=Vtrip, and the hysteresis interval is (Vtrip+)-(Vtrip-), that is, the hysteresis interval is 2Vtrip.

[0097] 3. Obviously, Vtrip can be changed by changing the size of I9. The hysteresis comparator structure provided in this application has different logic selections (different control signals HYST0, HYST1, and HYST2) corresponding to different hysteresis intervals. Since resistor R3, transistor Q3, resistor R4, and transistor Q6 constitute a current source; resistor R3, transistor Q3, resistor R5, and transistor Q8 constitute a current source; resistor R3, transistor Q3, resistor R9, and transistor Q10 constitute a current source; resistor R3, transistor Q3, resistor R10, and transistor Q12 constitute a current source; resistor R3, transistor Q3, resistor R11, and transistor Q14 constitute a current source, so this application can adjust resistor R4, resistor R5, resistor R9, resistor R10, and The resistance value of resistor R11 makes I5, I4, I3, I2, and I1 proportional, wherein the specific values ​​(proportional values) of R4: R5: R9: R10: R11 need to be combined with the IC1 current of transistor Q30 and the IC2 current of transistor Q31, and the specific proportional values ​​of R4: R5: R9: R10: R11 can be set according to the actual circuit debugging. It can be seen that the present application can adjust the resistance values ​​of resistors R4, R5, R9, R10, and R11 to achieve linear increase or decrease of the hysteresis interval;

[0098] Among them, I1 is the current flowing through transistor Q14; I2 is the current flowing through transistor Q12; I3 is the current flowing through transistor Q10; I4 is the current flowing through transistor Q8; I5 is the current flowing through transistor Q6; I6 is the current flowing through transistor Q18; I7 is the current flowing through transistor Q19; I8 is the current flowing through transistor Q28; I9 is ​​the current flowing through transistor Q29; IC1 is the current flowing through transistor Q30. flow; IC2 is the current flowing through the transistor Q31; IS is the transistor transfer characteristic constant; V1 is the potential of the node between the resistor R22 and the collector of the transistor Q30; V2 is the potential of the node between the resistor R23 and the collector of the transistor Q31; VCOM is the potential at the collector position of the transistor Q32; VCC is the supply voltage of the second power supply module; R22 is the resistance value of the resistor R22; R23 is the resistance value of the resistor R23; V OUT1 is the voltage value of the first voltage signal; V OUT2 is the voltage value of the second voltage signal.

[0099] In this embodiment, according to actual conditions, in combination with the IC1 current of the transistor Q30 and the IC2 current of the transistor Q31, the specific values ​​(proportional values) of R4: R5: R9: R10: R11 are adjusted, and the hysteresis interval of the hysteresis comparison module 40 can be adjusted to linearly increase. The hysteresis interval of the hysteresis comparison module 40 changes according to the three control signals HYST0, HYST1, and HYST2 of the external input of the switch control module 20 as shown in Table 2 below. It is worth noting that in Table 2 below, as the current signal value I6 changes, the linear increase of the value of the comparator hysteresis interval is only an example.

[0100] Table 2

[0101]

[0102] In the present application, a switch control module outputs multiple intermediate switch signals to the hysteresis adjustment module to control the on and off of the currents of multiple branches in the hysteresis adjustment module, thereby providing the hysteresis comparison module with a current signal I6 whose value can be adjusted. The larger the value of the current signal I6, the larger the hysteresis voltage range of the hysteresis comparator, so that the hysteresis voltage range of the hysteresis comparator can be flexibly adjusted. Furthermore, the hysteresis range can be linearly increased or decreased by adjusting the resistance values ​​of resistors R4, R5, R9, R10 and R11.

[0103] The hysteresis comparator provided in the present application is an important electronic component in the field of electronic technology. Due to its unique hysteresis characteristics and powerful comparison function, it plays a key role in signal processing, waveform generation, digital signal conversion and other aspects. It has been widely used in many fields, including but not limited to: power management, data conversion, sensor interface, communication system and medical electronics.

[0104] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A hysteresis comparator, characterized in that: include: A bias voltage providing module, a switch control module, a hysteresis adjustment module and a hysteresis comparison module, wherein: The bias voltage providing module is used to provide bias voltages to multiple branches in the hysteresis adjustment module, and to provide bias voltages to multiple branches in the hysteresis comparison module; The switch control module is used to receive multiple control signals input from the outside, and perform internal logic processing according to the multiple control signals to output multiple intermediate switch signals to the hysteresis adjustment module to control the on and off of currents of multiple branches in the hysteresis adjustment module; The hysteresis adjustment module is used to provide a current signal with adjustable value to the hysteresis comparison module according to the intermediate switch signal; The hysteresis comparison module is used to receive an externally input differential signal, perform signal amplification and comparison processing according to the differential signal and the current signal, and output a first voltage signal and a second voltage signal to a subsequent circuit.

2. The hysteresis comparator according to claim 1, characterized in that: The hysteresis comparator also includes: a first power supply module and a second power supply module, wherein the first power supply module is connected to the hysteresis adjustment module to supply power to the hysteresis adjustment module; the second power supply module is connected to the hysteresis comparison module to supply power to the hysteresis comparison module.

3. The hysteresis comparator according to claim 2, characterized in that: The bias voltage providing module includes: transistor Q1, transistor Q2, transistor Q3, transistor Q4, transistor Q5, transistor Q23, transistor Q24, transistor Q27, resistor R1, resistor R2, resistor R3, resistor R6, resistor R7 and resistor R8, wherein, One end of the resistor R6 is connected to the positive electrode of the second power supply module, and the other end of the resistor R6 is connected to the collector of the transistor Q23, the base of the transistor Q23 is connected to the collector of the transistor Q23, the emitter of the transistor Q23 is connected to the collector of the transistor Q24, the base of the transistor Q24 is connected to the collector of the transistor Q24, the emitter of the transistor Q24 is connected to the collector of the transistor Q27, the base of the transistor Q27 is connected to the collector of the transistor Q27, the emitter of the transistor Q27 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the collector of the transistor Q1, and the The emitter of the transistor Q1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the negative electrode of the second power module, the base of the transistor Q1 is also connected to the base of the transistor Q2, the collector of the transistor Q2 is connected to the emitter of the transistor Q5, the collector of the transistor Q5 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to the positive electrode of the first power module, the emitter of the transistor Q2 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the negative electrode of the second power module, and the base of the transistor Q2 is also connected to the hysteresis comparison module to provide bias voltage for multiple branches in the hysteresis comparison module; The resistor R7 is connected between the base of the transistor Q5 and the base of the transistor Q3, the collector of the transistor Q3 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the positive electrode of the first power module, the emitter of the transistor Q3 is connected to the base of the transistor Q3, the emitter of the transistor Q3 is also connected to the collector of the transistor Q4, the emitter of the transistor Q4 is connected to the negative electrode of the first power module, the base of the transistor Q4 is connected to the series node between the transistor Q5 and the transistor Q2, and the base of the transistor Q3 is also connected to the hysteresis adjustment module to provide bias voltage to multiple branches in the hysteresis adjustment module.

4. The hysteresis comparator according to claim 2, characterized in that: The hysteresis adjustment module includes: first to fifth branches, wherein: The first branch includes: a resistor R4, a transistor Q6, a transistor Q7 and a first switch unit M5, wherein one end of the resistor R4 is connected to the positive electrode of the first power module, the other end of the resistor R4 is connected to the collector of the transistor Q6, the emitter of the transistor Q6 is connected to the collector of the transistor Q7, the collector of the transistor Q7 is also connected to the first end of the first switch unit M5, the second end of the first switch unit M5 is connected to the negative electrode of the first power module, and the third end of the first switch unit M5 is connected to the first output end of the switch control module to receive the first intermediate switch signal of the switch control module; The second branch includes: a resistor R5, a transistor Q8, a transistor Q9 and a second switch unit M4, wherein one end of the resistor R5 is connected to the positive electrode of the first power module, the other end of the resistor R5 is connected to the collector of the transistor Q8, the emitter of the transistor Q8 is connected to the collector of the transistor Q9, the collector of the transistor Q9 is also connected to the first end of the second switch unit M4, the second end of the second switch unit M4 is connected to the negative electrode of the first power module, and the third end of the second switch unit M4 is connected to the second output end of the switch control module to receive the second intermediate switch signal of the switch control module; The third branch includes: a resistor R9, a transistor Q10, a transistor Q11 and a third switch unit M3, wherein one end of the resistor R9 is connected to the positive electrode of the first power module, the other end of the resistor R9 is connected to the collector of the transistor Q10, the emitter of the transistor Q10 is connected to the collector of the transistor Q11, the collector of the transistor Q11 is also connected to the first end of the third switch unit M3, the second end of the third switch unit M3 is connected to the negative electrode of the first power module, and the third end of the third switch unit M3 is connected to the third output end of the switch control module to receive the third intermediate switch signal of the switch control module; The fourth branch includes: a resistor R10, a transistor Q12, a transistor Q13 and a fourth switch unit M2, wherein one end of the resistor R10 is connected to the positive electrode of the first power module, the other end of the resistor R10 is connected to the collector of the transistor Q12, the emitter of the transistor Q12 is connected to the collector of the transistor Q13, the collector of the transistor Q13 is also connected to the first end of the fourth switch unit M2, the second end of the fourth switch unit M2 is connected to the negative electrode of the first power module, and the third end of the fourth switch unit M2 is connected to the fourth output end of the switch control module to receive the fourth intermediate switch signal of the switch control module; The fifth branch includes: a resistor R11, a transistor Q14, a transistor Q15 and a fifth switch unit M1, wherein one end of the resistor R11 is connected to the positive electrode of the first power module, the other end of the resistor R11 is connected to the collector of the transistor Q14, the emitter of the transistor Q14 is connected to the collector of the transistor Q15, the collector of the transistor Q15 is also connected to the first end of the fifth switch unit M1, the second end of the fifth switch unit M1 is connected to the negative electrode of the first power module, and the third end of the fifth switch unit M1 is connected to the fifth output end of the switch control module to receive the fifth intermediate switch signal of the switch control module; Among them, the base of the transistor Q15, the base of the transistor Q13, the base of the transistor Q11, the base of the transistor Q9 and the base of the transistor Q7 are all connected to the negative electrode of the first power supply module; the emitter of the transistor Q15, the emitter of the transistor Q13, the emitter of the transistor Q11, the emitter of the transistor Q9 and the emitter of the transistor Q7 are connected and then connected to the hysteresis comparison module to provide the hysteresis comparison module with a current signal with adjustable value.

5. The hysteresis comparator according to claim 4, characterized in that: The first switch unit M5, the second switch unit M4, the third switch unit M3, the fourth switch unit M2 and the fifth switch unit M1 are all NMOS tubes, wherein the first end of the first switch unit M5 is the drain end of the NMOS tube, the second end of the first switch unit M5 is the source end of the NMOS tube, and the third end of the first switch unit M5 is the gate end of the NMOS tube; the first end of the second switch unit M4 is the drain end of the NMOS tube, the second end of the second switch unit M4 is the source end of the NMOS tube, and the third end of the second switch unit M4 is the gate end of the NMOS tube; The first end of the third switch unit M3 is the drain end of the NMOS tube, the second end of the third switch unit M3 is the source end of the NMOS tube, and the third end of the third switch unit M3 is the gate end of the NMOS tube; the first end of the fourth switch unit M2 is the drain end of the NMOS tube, the second end of the fourth switch unit M2 is the source end of the NMOS tube, and the third end of the fourth switch unit M2 is the gate end of the NMOS tube; the first end of the fifth switch unit M1 is the drain end of the NMOS tube, the second end of the fifth switch unit M1 is the source end of the NMOS tube, and the third end of the fifth switch unit M1 is the gate end of the NMOS tube.

6. The hysteresis comparator according to claim 1, characterized in that: The hysteresis comparison module includes: a resistor R13, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a transistor Q18, a transistor Q19, a transistor Q20, a transistor Q21, a transistor Q25, a transistor Q26, a transistor Q28, a transistor Q29, a transistor Q30, a transistor Q31, a transistor Q32, a transistor Q33, a transistor Q34, a transistor Q35, a transistor Q36, a transistor Q37 and a transistor Q38, wherein: The collector of the transistor Q18 is connected to the emitter of the transistor Q15, the base of the transistor Q18 is connected to the collector of the transistor Q18, the emitter of the transistor Q18 is connected to the collector of the transistor Q20, the emitter of the transistor Q20 is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the negative electrode of the second power module, the base of the transistor Q18 is also connected to the base of the transistor Q19, the emitter of the transistor Q19 is connected to the collector of the transistor Q21, the base of the transistor Q21 is respectively connected to the base of the transistor Q20 and the collector of the transistor Q21, the emitter of the transistor Q21 is connected to one end of the resistor R14, the other end of the resistor R14 is connected to the negative electrode of the second power module, and the collector of the transistor Q19 is connected to the emitter of the transistor Q25; The base of the transistor Q25 is connected to the emitter of the transistor Q25, the collector of the transistor Q25 is connected to one end of the resistor R16, the other end of the resistor R16 is connected to the positive electrode of the second power module, the base of the transistor Q25 is also connected to the base of the transistor Q26, the collector of the transistor Q26 is connected to one end of the resistor R17, the other end of the resistor R17 is connected to the positive electrode of the second power module, and the emitter of the transistor Q26 is connected to the base of the transistor Q26. The collector of the transistor Q28, the emitter of the transistor Q28 is connected to one end of the resistor R19, the other end of the resistor R19 is connected to the negative electrode of the second power module, the resistor R18 is connected between the base of the transistor Q28 and the base of the transistor Q29, the collector of the transistor Q28 is connected to the base of the transistor Q29, the emitter of the transistor Q29 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the negative electrode of the second power module; The emitter of the transistor Q30 is connected to the emitter of the transistor Q31 and then connected to the collector of the transistor Q32. The emitter of the transistor Q32 is connected to one end of the resistor R21, and the other end of the resistor R21 is connected to the negative electrode of the second power module. The collector of the transistor Q30 is connected to one end of the resistor R22, and the other end of the resistor R22 is connected to the positive electrode of the second power module. The collector of the transistor Q31 is connected to one end of the resistor R23, and the other end of the resistor R23 is connected to the positive electrode of the second power module. The base of the transistor Q30 and the base of the transistor Q31 receive a pair of differential signals input from the outside. The collector of the transistor Q30 is also connected to the base of the transistor Q38, the collector of the transistor Q38 is connected to the positive electrode of the second power module, the emitter of the transistor Q38 is connected to the collector of the transistor Q34, the emitter of the transistor Q34 is connected to one end of the resistor R25, and the other end of the resistor R25 is connected to the negative electrode of the second power module; The collector of the transistor Q37 is connected to the positive electrode of the second power module, the emitter of the transistor Q37 is connected to the collector of the transistor Q33, the emitter of the transistor Q33 is connected to one end of the resistor R24, and the other end of the resistor R24 ​​is connected to the negative electrode of the second power module; The emitter of the transistor Q35 is connected to the emitter of the transistor Q36 and then connected to the collector of the transistor Q29. The emitter of the transistor Q29 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the negative electrode of the second power module. The collector of the transistor Q35 is connected to the collector of the transistor Q30, and the collector of the transistor Q36 is connected to the collector of the transistor Q31. The base of the transistor Q35 is connected to the emitter of the transistor Q37, and the base of the transistor Q36 is connected to the emitter of the transistor Q38. The base of the transistor Q32, the base of the transistor Q33 and the base of the transistor Q34 are all connected to the base of the transistor Q2 to receive the bias voltage provided by the bias voltage providing module; Among them, transistors Q18 to Q21, resistor R13 and resistor R14 constitute a first current mirror; transistors Q25, Q26, Q28, Q29, resistor R19 and resistor R20 constitute a second current mirror; the transistor Q30 and the transistor Q31 constitute a first differential pair; the transistor Q35 and the transistor Q36 constitute a second differential pair.

7. The hysteresis comparator according to claim 1, characterized in that: The switch control module includes: first to third control signal input terminals, first to fifth switch signal output terminals, first to third inverters, first to seventh NAND gates, first NOR gates and second NOR gates, wherein the first control signal input terminal is respectively connected to the first terminal of the first NAND gate, the input terminal of the second inverter and the first input terminal of the second NOR gate; the second control signal input terminal is respectively connected to the input terminal of the first inverter, the second input terminal of the second NAND gate, the first input terminal of the first NOR gate and the second input terminal of the second NOR gate; the third control signal input terminal is respectively connected to the input terminal of the third inverter, the second input terminal of the seventh NAND gate, the second input terminal of the first NOR gate and the third input terminal of the second NOR gate; the output terminal of the first inverter is respectively connected to the second input terminal of the first NAND gate and the second input terminal of the fourth NAND gate; the output terminal of the second ... The output ends are respectively connected to the first input end of the second NAND gate, the first input end of the third NAND gate and the first input end of the fourth NAND gate, and the output end of the third inverter is connected to the second input end of the third NAND gate; the output ends of the first NAND gate are respectively connected to the first end of the fifth NAND gate and the first input end of the sixth NAND gate; the output end of the second NAND gate is connected to the second input end of the fifth NAND gate; the output end of the third NAND gate is connected to the second input end of the sixth NAND gate; the output end of the fourth NAND gate is connected to the first input end of the seventh NAND gate; the output end of the fifth NAND gate is connected to the first switch signal output end, the output end of the sixth NAND gate is connected to the second switch signal output end, the output end of the seventh NAND gate is connected to the fourth switch signal output end, the output end of the first NOR gate is connected to the third switch signal output end, and the output end of the second NOR gate is connected to the fifth switch signal output end.

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