Analog-to-digital converter and analog-to-digital conversion method

Abstract

The invention discloses an analog-to-digital converter and an analog-to-digital conversion method, and relates to the field of integrated circuits, and the analog-to-digital converter comprises a small loop which comprises at least one pipeline stage; a major cycle including at least one minor cycle; the assembly line stages are connected in series, and the small cycles are connected in series; the assembly line stage comprises a sampling and holding module, a sub analog-to-digital conversion module, a sub digital-to-analog conversion module and a residual error generator module which are connected in sequence, and further comprises an amplifier which can be arranged behind any one of the modules. An analog-to-digital converter assembly line architecture is designed into a large cycle composed of a plurality of small cycles, each small cycle is composed of multiple stages of assembly lines, and the positions of amplifiers in the stages of assembly lines are different, so that dynamic ranges of different stages are flexibly matched, and signal distortion is prevented.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an analog-to-digital converter and an analog-to-digital conversion method. Background Art

[0002] In current electronic systems, the performance requirements of analog-to-digital converters (ADCs) are getting higher and higher for applications that require high-speed and high-precision analog-to-digital conversion, especially in the fields of medical imaging, communications, and scientific instruments. High-speed CT (continuous time) analog-to-digital conversion is a key technology that enables fast and accurate digitization of analog signals. In traditional ADC design, the amplifier is usually placed after the residual generator. Its purpose is to amplify the residual signal after analog-to-digital conversion to increase the amplitude of the signal, thereby optimizing the dynamic range and signal-to-noise ratio of the system. However, for stages such as the sample-and-hold module, sub-ADC, and sub-DAC, if their dynamic range is small, placing the amplifier only after the residual generator will not be able to fully utilize the overall dynamic range of the system, resulting in a mismatch in the dynamic range of different stages. Therefore, it is necessary to provide a high-speed CT analog-to-digital conversion method that can adapt to different signal characteristics to flexibly optimize dynamic atmosphere matching and achieve low noise and low distortion. Summary of the invention

[0003] In view of the above problems existing in the prior art, the present invention is proposed.

[0004] To solve the above technical problems, in a first aspect, the present invention provides the following technical solutions: an analog-to-digital converter, comprising a small loop, which includes at least one pipeline stage; a large loop, which includes at least one small loop; the pipeline stages are connected in series with each other, and the small loops are connected in series with each other; the pipeline stage includes a sampling and holding module, a sub-analog-to-digital conversion module, a sub-digital-to-analog conversion module and a residual generator module connected in sequence, and also includes an amplifier that can be arranged after any of the above modules.

[0005] As a preferred solution of the analog-to-digital converter of the present invention, the structure of each of the small cycles is the same.

[0006] As a preferred solution of the analog-to-digital converter of the present invention, wherein: one of the small loops includes four pipeline stages connected in sequence, the positions of the amplifiers in the four pipeline stages are different from each other, and the four pipeline stages are respectively a first pipeline stage, a second pipeline stage, a third pipeline stage and a fourth pipeline stage.

[0007] As a preferred solution of the analog-to-digital converter of the present invention, the first pipeline stage includes the sampling and holding module, the amplifier, the sub-analog-to-digital conversion module, the sub-digital-to-analog conversion module and the residual generator module connected in sequence.

[0008] As a preferred solution of the analog-to-digital converter of the present invention, the second pipeline stage includes the sampling and holding module, the sub-analog-to-digital conversion module, the amplifier, the sub-digital-to-analog conversion module and the residual generator module connected in sequence.

[0009] As a preferred solution of the analog-to-digital converter of the present invention, the third pipeline stage includes the sampling and holding module, the sub-analog-to-digital conversion module, the sub-digital-to-analog conversion module, the amplifier and the residual generator module connected in sequence.

[0010] As a preferred solution of the analog-to-digital converter of the present invention, the fourth pipeline stage includes the sampling and holding module, the sub-analog-to-digital conversion module, the sub-digital-to-analog conversion module, the residual generator module and the amplifier connected in sequence.

[0011] In a second aspect, the present invention provides an analog-to-digital conversion method, which is applicable to the above-mentioned analog-to-digital converter, the method comprising: sampling and holding an input analog signal through a sampling and holding module to obtain a held signal; quantizing the held signal through a sub-analog-to-digital conversion module and obtaining a quantization result; converting the quantization result into a feedback signal through a sub-digital-to-analog conversion module; converting the input analog signal and the feedback signal into a residual signal through a residual generator module; and amplifying any one of the held signal, the quantization result, the feedback signal and the residual signal through an amplifier.

[0012] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the above method when executing the computer program.

[0013] A computer-readable storage medium having a computer program stored thereon, characterized in that when the computer program is executed by a processor, the steps of the above method are implemented

[0014] The beneficial effects of the present invention are as follows: by designing the analog-to-digital converter pipeline architecture as a large cycle composed of multiple small cycles, each small cycle is composed of multiple stages of pipelines, and the amplifier positions in each stage of the pipeline are set differently, so as to flexibly match the dynamic range of different stages and prevent signal distortion. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 Schematic diagram of the large loop architecture of the analog-to-digital converter.

[0017] Figure 2 Schematic diagram of the small loop architecture of the analog-to-digital converter. DETAILED DESCRIPTION

[0018] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

[0019] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0020] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor is it an embodiment that is mutually exclusive with other embodiments, either individually or selectively.

[0021] Example 1

[0022] Reference Figure 1 and Figure 2 , which is the first embodiment of the present invention, provides an analog-to-digital converter, which includes a small cycle 100 and a large cycle 200.

[0023] Specifically, the small loop 100 includes a plurality of pipeline stages 101, and each pipeline stage 101 is connected end to end to form a series connection.

[0024] The large loop 200 includes a plurality of small loops 100, and each of the small loops 100 is connected end to end to form a series connection.

[0025] Preferably, each pipeline stage 101 comprises a sampling and holding module 101a, a sub-analog-to-digital conversion module 101b, a sub-digital-to-analog conversion module 101c and a residual amplifier module 101d connected in sequence, wherein the amplifier 101e is arranged after any one of the above four modules.

[0026] That is, the entire analog-to-digital converter has a small cycle 100 composed of N pipeline stages 101 and a large cycle 200 composed of M small cycles 100. And the components of each small cycle 100 are composed and arranged in the same manner.

[0027] Among them, the structure of using N pipeline stages 101 to form a small loop 100 and M small loops 100 to form a large loop 200 can realize parallel processing of input signals. This helps to improve the speed and efficiency of the entire system and adapt to the requirements of high-speed ADC. Each pipeline stage 101 contains a group of similar components. This modular design improves the maintainability and scalability of the system. If you need to increase the resolution or change the system scale, you only need to simply increase or decrease the pipeline stage. The composition and order of the components in each large loop 200 are the same, ensuring the consistency of the entire system. This helps to simplify the design and debugging process of the system, reduce complexity, and improve the stability of the system. The amplifier 101e is set in each pipeline stage 101 and can be optionally placed after different components, providing flexible processing of signals at different stages. This design flexibility enables the system to perform differentiated processing of signals according to specific needs, thereby optimizing system performance. The existence of the amplifier 101e enables the amplitude of the signal to be dynamically adjusted at each stage, which helps to match the dynamic range of different stages. This ensures that the entire system can make full use of the dynamic range when processing the input signal to prevent signal distortion.

[0028] Preferably, refer to Figure 2 , each small loop 100 includes four pipeline stages 101, and M small loops 100 include 4M pipeline stages 101 in total. The four pipeline stages 101 are respectively the first pipeline stage 101-1, the second pipeline stage 101-2, the third pipeline stage 101-3, and the fourth pipeline stage 101-4. For the convenience of explanation, the pipeline stages 101 in the first small loop 100 are named as the 11th pipeline stage, the 12th pipeline stage, the 13th pipeline stage, and the 14th pipeline stage; the pipeline stages 101 in the second small loop 100 are named as the 21st pipeline stage, the 22nd pipeline stage, the 23rd pipeline stage, and the 24th pipeline stage. By analogy, the pipeline stages 101 in the Mth small loop 100 are named the M1th pipeline stage, the M2th pipeline stage, the M3th pipeline stage and the M4th pipeline stage respectively.

[0029] Preferably, the 11th pipeline stage includes a sampling and holding module 101a, an amplifier 101e, a sub-analog-to-digital conversion module 101b, a sub-digital-to-analog conversion module 101c and a residual amplifier module 101d which are connected in sequence.

[0030] The sampling and holding module 101a samples and holds the analog input signal, obtains a holding signal, and transmits it to the amplifier 101e and the residual generator module 101d of the current pipeline stage respectively;

[0031] The amplifier 101e amplifies the held signal and transmits it to the sub-analog-to-digital conversion module 101b;

[0032] The sub-analog-to-digital conversion module 101b quantizes the held signal and obtains a quantization result, and the quantization result is transmitted to the sub-digital-to-analog conversion module 101c of the current pipeline stage;

[0033] The sub-digital-to-analog conversion module 101c generates a feedback signal according to the quantization result and transmits it to the residual amplifier module 101d;

[0034] The residual amplifier module 101d subtracts the received hold signal from the feedback signal to obtain a residual signal, and transmits the residual signal to the sampling and holding module 101a of the next pipeline stage.

[0035] Among them, the sampling and holding module 101a first samples and holds the analog input signal, ensuring the orderly processing of the signal in each pipeline stage 101. This sequential processing helps to improve the stability and controllability of the system. The amplifier 101e follows the sampling and holding module 101a to amplify the held signal. Such a design can be adjusted according to the amplitude of the input signal to ensure that the signal has an appropriate amplitude when it is passed to the subsequent steps, thereby avoiding signal distortion and loss. The signal output by the amplifier 101e is transmitted to the sub-analog-to-digital conversion module 101b for quantization. Through this step, the signal can be digitized.

[0036] Placing the amplifier 101e between the sampling and holding module 101a and the sub-analog-to-digital conversion module 101b helps to properly amplify the signal before quantization, thereby improving the sensitivity and dynamic range of the system. The feedback signal generated by the sub-analog-to-digital conversion module 101c is transmitted to the residual generator module 101d, forming a feedback control mechanism. This mechanism helps to introduce closed-loop control in the system and improve the stability and accuracy of the system. The residual generator module 101d subtracts the holding signal from the feedback signal to generate a residual signal. This setting helps to introduce an error correction mechanism in each pipeline stage 101, thereby improving the accuracy of the system. The residual signal is further transmitted to the sampling and holding module 101a of the next pipeline stage 101, forming a loop process, ensuring the coherence and global consistency of the system.

[0037] Preferably, the 12th pipeline stage includes a sampling and holding module 101a, a sub-analog-to-digital conversion module 101b, an amplifier 101e, a sub-digital-to-analog conversion module 101c and a residual generator module 101d which are connected in sequence.

[0038] The sampling and holding module 101a in this stage samples and holds the residual signal of the previous stage, obtains a holding signal, and transmits it to the sub-analog-to-digital conversion module 101b and the residual generator module 101d of this pipeline stage respectively;

[0039] The sub-analog-to-digital conversion module 101b quantizes the held signal and obtains a quantization result, which is transmitted to the amplifier 101e of the current pipeline stage;

[0040] The amplifier 101e amplifies the quantization result and transmits it to the sub-digital-to-analog conversion module 101c;

[0041] The sub-digital-to-analog conversion module 101c generates a feedback signal according to the quantization result and transmits it to the residual generator module 101d;

[0042] The residual generator module 101d subtracts the received hold signal from the feedback signal to obtain a residual signal, and transmits the residual signal to the sampling and holding module 101a of the next pipeline stage.

[0043] Among them, the sampling and holding module 101a samples and holds the residual signal to obtain a holding signal. Such a design consideration is to introduce an error correction mechanism at this stage. By sampling the residual signal for holding, it helps to reduce the impact of the error and improve the accuracy of the system. The amplifier 101e follows the sub-analog-to-digital conversion module 101b and amplifies the quantization result. This setting is to flexibly control the appropriate amplification of the signal after quantization to adapt to different input signal amplitudes, thereby optimizing the sensitivity and dynamic range of the system. The feedback signal generated by the sub-digital-to-analog conversion module 101c is transmitted to the residual generator module 101d to form a feedback mechanism. Through this mechanism, the system can adjust the residual signal, thereby introducing a feedback control in the pipeline stage to improve the stability and dynamic performance of the system. The residual generator module 101d subtracts the holding signal from the feedback signal to generate a residual signal, and then transmits the residual signal to the sampling and holding module 101a of the next pipeline stage. This connection method helps to maintain the fluency and consistency of the system and ensure that the signal transmission between each pipeline stage is orderly.

[0044] Preferably, the 13th pipeline stage includes: a sampling and holding module 101a, a sub-analog-to-digital conversion module 101b, a sub-digital-to-analog conversion module 101c, an amplifier 101e and a residual generator module 101d connected in sequence, wherein:

[0045] The sampling and holding module 101a samples and holds the residual signal to obtain a holding signal, and transmits it to the sub-analog-to-digital conversion module 101b and the residual generator module 101d of the current pipeline stage respectively;

[0046] The sub-analog-to-digital conversion module 101b quantizes the held signal and obtains a quantization result, and the quantization result is transmitted to the sub-digital-to-analog conversion module 101c of the current pipeline stage;

[0047] The sub-digital-to-analog conversion module 101c generates a feedback signal according to the quantization result and transmits it to the amplifier 101e;

[0048] The amplifier 101e amplifies the quantization result and transmits it to the residual generator module 101d;

[0049] The residual generator module 101d subtracts the received hold signal from the feedback signal to obtain a residual signal, and transmits the residual signal to the sampling and holding module 101a of the next pipeline stage.

[0050] Among them, in order to further optimize the error correction mechanism of the system at this stage, the residual signal is sampled and maintained, which helps to reduce the impact of the error on the system and improve the overall accuracy. The sub-digital-to-analog conversion module 101c generates a feedback signal according to the quantization result, and this feedback signal is transmitted to the amplifier 101e. This setting is to introduce a feedback control mechanism in the pipeline stage so as to more accurately adjust the working state of the system and improve the stability and dynamic performance of the system. The amplifier 101e amplifies the quantization result of the sub-digital-to-analog conversion module 101c in the pipeline stage. This design is to adjust the amplitude of the signal after the quantization result to adapt to different input signal amplitudes, thereby improving the sensitivity and dynamic range of the system. The residual generator module 101d subtracts the holding signal from the feedback signal to generate a residual signal, and then transmits the residual signal to the sampling and holding module 101a of the next pipeline stage. This connection method helps to maintain the fluency and consistency of the system and ensure that the signal transmission between each pipeline stage is orderly.

[0051] Preferably, the 14th pipeline stage includes: a sampling and holding module 101a, a sub-analog-to-digital conversion module 101b, a sub-digital-to-analog conversion module 101c, a residual generator module 101d and an amplifier 101e connected in sequence, wherein:

[0052] The sampling and holding module 101a samples and holds the residual signal to obtain a holding signal, and transmits it to the sub-analog-to-digital conversion module 101b and the residual generator module 101d of the current pipeline stage respectively;

[0053] The sub-analog-to-digital conversion module 101b quantizes the held signal and obtains a quantization result, and the quantization result is transmitted to the sub-digital-to-analog conversion module 101c of the current pipeline stage;

[0054] The sub-digital-to-analog conversion module 101c generates a feedback signal according to the quantization result and transmits it to the residual generator module 101d;

[0055] The residual generator module 101d subtracts the received hold signal from the feedback signal to obtain a residual signal, and transmits it to the amplifier 101e. After the signal is amplified, it is transmitted to the sampling and holding module 101a of the next pipeline stage.

[0056] Among them, the amplifier 101e is placed after the residual generator module 101d to amplify the residual signal. This setting is to adjust the amplitude of the residual signal to ensure that the residual signal has an appropriate amplitude when it is transmitted to the next stage, thereby preventing signal distortion and loss. The feedback signal generated by the sub-digital-to-analog conversion module 101c is transmitted to the residual generator module 101d to form a feedback control mechanism. Through this mechanism, the system can adjust the residual signal more accurately, thereby affecting the working state of the entire system. This feedback mechanism helps to improve the stability and dynamic performance of the system. The residual generator module 101d subtracts the holding signal from the feedback signal to generate a residual signal, and then transmits the residual signal to the amplifier 101e. This connection method ensures the orderly transmission of signals between pipeline stages and maintains the fluency and consistency of the system. The amplifier 101e amplifies the residual signal, enhancing the system's flexible processing capability for the residual signal. By performing signal amplification at this stage, it can better adapt to residual signals of different amplitudes and improve the dynamic range matching and adaptability of the system.

[0057] Similar to the above structure, the M1 pipeline stage includes: a sampling and holding module 101a, an amplifier 101e, a sub-analog-to-digital conversion module 101b, a sub-digital-to-analog conversion module 101c and a residual generator module 101d connected in sequence.

[0058] The M2 pipeline stage includes: a sampling and holding module 101, a sub-analog-to-digital conversion module 101b, an amplifier 101e, a sub-digital-to-analog conversion module 101c and a residual generator module 101d connected in sequence,

[0059] The M3 pipeline stage includes: a sampling and holding module 101, a sub-analog-to-digital conversion module 101b, a sub-digital-to-analog conversion module 101c, an amplifier 101e and a residual generator module 101d connected in sequence,

[0060] The M4th pipeline stage includes: a sampling and holding module 101, a sub-analog-to-digital conversion module 101b, a sub-digital-to-analog conversion module 101c, a residual generator module 101d and an amplifier 101e connected in sequence.

[0061] Thus, by designing the pipeline stage 101 as a large loop 200 composed of M small loops 100, each small loop 100 is composed of multiple pipeline stages 101, and the amplifier 101e in each pipeline stage 101 is positioned differently, the dynamic range of different stages can be flexibly matched to prevent signal distortion.

[0062] Example 2

[0063] The second embodiment of the present invention is based on the previous embodiment. This embodiment provides an analog-to-digital conversion method, which includes:

[0064] S1: The input analog signal is sampled and held by the sampling and holding module 101a to obtain a holding signal, and the holding signal is transmitted to the sub-analog-to-digital conversion module 101b and the residual generator module 101d of the current pipeline stage respectively.

[0065] S2: The sub-analog-to-digital conversion module 101b quantizes the held signal and obtains a quantization result, which is transmitted to the sub-digital-to-analog conversion module 101c of the current pipeline stage.

[0066] S3: The sub-DAC module 101c generates a feedback signal according to the quantization result and transmits it to the residual generator module 101d.

[0067] S4: The residual generator module 101d subtracts the received analog input signal from the feedback signal to obtain a residual signal, and transmits it to the sampling and holding module 101a of the next pipeline stage.

[0068] The amplifier 101e amplifies any one of the hold signal, the quantization result, the feedback signal, and the residual signal.

[0069] Among them, by introducing the amplifier 101e in each pipeline stage, the amplitude of the signal can be flexibly adjusted according to the dynamic range difference of the signal at different stages, so as to ensure that the entire system can make full use of the dynamic range when processing the input signal and prevent signal distortion. Signals at different stages have different amplitudes and characteristics. By introducing the amplifier 101e at each stage, it is helpful to optimize the signal in a personalized manner. The design of the amplifier 101e amplifying any signal increases the flexibility of the system. Designers can choose at which stage to amplify the signal according to the specific application scenario and signal characteristics to meet different needs, thereby improving the adaptability of the system. The introduction of the amplifier 101e helps to improve the signal-to-noise ratio. By amplifying the signal at the appropriate stage, the amplitude of the signal can be effectively increased, and the influence of the noise associated with the signal can be relatively reduced, thereby improving the noise performance of the system. The existence of the amplifier 101e also plays a key role in the feedback control link. By amplifying the feedback signal or the residual signal, the working state of the system can be adjusted more accurately, and the stability and control performance of the system can be improved.

[0070] Example 3

[0071] The third embodiment of the present invention is different from the previous embodiment in that:

[0072] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program code.

[0073] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as based on a computer, including a processor or other device that can fetch instructions from the instruction execution system, device or apparatus and execute instructions), or in conjunction with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with these instruction execution systems, devices or apparatuses.

[0074] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0075] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0076] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. An analog-to-digital converter, characterized in that: include, A small loop (100) comprising at least one pipeline stage (101); A large loop (200) comprising at least one small loop (100); The pipeline stages (101) are connected in series with each other, and the small loops (100) are connected in series with each other; The pipeline stage (101) comprises a sampling and holding module (101a), a sub-analog-to-digital conversion module (101b), a sub-digital-to-analog conversion module (101c) and a residual generator module (101d) connected in sequence, and also comprises an amplifier (101e) that can be arranged after any of the above modules.

2. The analog-to-digital converter according to claim 1, wherein: The structure of each of the small cycles (100) is the same.

3. The analog-to-digital converter according to claim 1 or 2, characterized in that: One of the small loops (100) comprises four pipeline stages (101) connected in sequence, the positions of the amplifiers (101e) in the four pipeline stages (101) are different from each other, and the four pipeline stages (101) are respectively a first pipeline stage (101-1), a second pipeline stage (101-2), a third pipeline stage (101-3) and a fourth pipeline stage (101-4).

4. The analog-to-digital converter according to claim 3, wherein: The first pipeline stage (101-1) comprises the sample-and-hold module (101a), the amplifier (101e), the sub-analog-to-digital conversion module (101b), the sub-digital-to-analog conversion module (101c) and the residual generator module (101d) which are connected in sequence.

5. The analog-to-digital converter according to claim 4, characterized in that: The second pipeline stage (101-2) comprises the sampling and holding module (101a), the sub-analog-to-digital conversion module (101b), the amplifier (101e), the sub-digital-to-analog conversion module (101c) and the residual generator module (101d) which are connected in sequence.

6. The analog-to-digital converter and the analog-to-digital conversion method according to claim 5, wherein: The third pipeline stage (101-3) comprises the sampling and holding module (101a), the sub-analog-to-digital conversion module (101b), the sub-digital-to-analog conversion module (101c), the amplifier (101e) and the residual generator module (101d) which are connected in sequence.

7. The analog-to-digital converter according to claim 6, wherein: The fourth pipeline stage (101-4) comprises the sample-and-hold module (101a), the sub-analog-to-digital conversion module (101b), the sub-digital-to-analog conversion module (101c), the residual generator module (101d) and the amplifier (101e) which are connected in sequence.

8. An analog-to-digital conversion method, characterized in that: Applicable to the analog-to-digital converter according to any one of claims 1 to 8, the method comprising: The input analog signal is sampled and held by a sample-and-hold module (101a) to obtain a held signal; quantizing the retained signal through a sub-analog-to-digital conversion module (101b) and obtaining a quantization result; Converting the quantization result into a feedback signal through a sub-digital-to-analog conversion module (101c); Converting the input analog signal and the feedback signal into a residual signal through a residual generator module (101d); Any one of the hold signal, the quantization result, the feedback signal and the residual signal is amplified by an amplifier (101e).

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method described in claim 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method described in claim 8 are implemented.

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