Clock synchronization method and device, computer equipment and storage medium

Abstract

The invention relates to a clock synchronization method, which comprises the following steps of: acquiring position information and power information of each clock source, and determining a coverage range of each clock source according to the position information and the power information of each clock source; according to the coverage area and the position information of the local terminal, determining the situation of receiving a clock source signal; receiving a main timestamp signal sent by the main clock source and an auxiliary timestamp signal sent by the auxiliary clock source to determine a standard clock source; and receiving the timestamp broadcasted by the standard clock source, and performing time synchronization on the clock of the local terminal according to the timestamp. By selecting the appropriate clock source as the standard clock, the accuracy of time synchronization by applying the IEEE1588 protocol is improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a clock synchronization method, device, computer equipment and storage medium. Background Art

[0002] Clock synchronization is to align clocks distributed in various places. You can choose one clock as the standard clock of the system (also called the master clock), and then compare other clocks in the system (also called local slave clocks) with the standard clock to achieve synchronization between other clocks in the system and the system standard clock. In the prior art, when synchronizing the local clock, it is necessary to input an external reliable clock source, and use the reliable clock source as the input reference clock signal of the local clock to achieve clock synchronization between the local clock and the master clock. At present, the IEEE 1588 protocol is mainly used in the process of clock synchronization. IEEE1588 uses both software and hardware and software, and has a more accurate timing synchronization effect.

[0003] However, when using the IEEE1588 protocol for clock synchronization, in order to fully cover the terminals that need clock synchronization, multiple clock sources are often required to provide timestamp signals. However, when the distance between the terminal's receiver and different clock sources is different, the time corresponding to the received timestamp signal will be different. As a result, the terminal cannot accurately determine which clock source to use as the reference for clock synchronization, which in turn reduces the accuracy of clock synchronization. Summary of the invention

[0004] The object of the present invention is to provide a clock synchronization method to solve the problems in the background technology.

[0005] A first aspect of the present invention provides a clock synchronization method, comprising:

[0006] Acquire location information and power information of each clock source, and determine the coverage range of each clock source according to the location information and power information of each clock source;

[0007] Determining, according to the coverage range and the location information of the local terminal, a situation in which a clock source signal is received;

[0008] If the number of received clock source signals is greater than one, the clock source with the strongest signal is used as the primary clock source, and the clock source with the second strongest signal is used as the secondary clock source;

[0009] Receive a main timestamp signal sent by the main clock source and a secondary timestamp signal sent by the secondary clock source, and determine whether a difference between the main timestamp signal and the secondary timestamp signal is within a preset error; if so, use the main timestamp signal as a standard clock source for clock synchronization; otherwise, determine the standard clock source according to the order in which the test messages are received;

[0010] A timestamp broadcasted by the standard clock source is received, and a clock of a local terminal is synchronized according to the timestamp.

[0011] In a possible implementation manner, determining the coverage range of each of the clock sources according to the location information and power information of each of the clock sources includes:

[0012] According to the location information and power information of each of the clock sources, establishing a Thiessen polygon for each of the clock sources;

[0013] The coverage range of each of the clock sources is determined according to the Thiessen polygons and the minimum power that can be received by the time board of the terminal to be clock synchronized.

[0014] In a possible implementation manner, after determining, according to the coverage range, that a clock source signal is received, the method further includes:

[0015] If the number of received clock source signals is one, the clock source is a standard clock source.

[0016] In a possible implementation manner, the receiving the timestamp broadcasted by the standard clock source and synchronizing the clock of the local terminal according to the timestamp includes:

[0017] Initializing the standard clock source and the receiver of the local terminal;

[0018] Performing parameter configuration on the standard clock source and the receiver of the local terminal;

[0019] Receiving the timestamp broadcasted by the standard clock source and measuring the transmission delay duration;

[0020] After the transmission delay is corrected, the time synchronization of the clock of the local terminal is completed.

[0021] In a possible implementation manner, after receiving the timestamp broadcasted by the standard clock source and synchronizing the clock of the local terminal according to the timestamp, the method further includes:

[0022] The time interval of arrival of the timestamp is monitored, and the number of times the time interval is greater than a preset time interval is obtained. If the number is greater than a preset number threshold, the secondary clock source is switched to a standard clock source.

[0023] In a possible implementation manner, the step of completing time synchronization of a clock of a local terminal after correcting the transmission delay includes:

[0024] Start the operating system, read the IEEE1588 network card driver and the compensation value file corresponding to the operating system, the compensation value file records the clock synchronization compensation values ​​corresponding to different system loads;

[0025] The actual system load is obtained, and an actual clock synchronization compensation value corresponding to the actual system load is determined according to the compensation value file, and clock synchronization is performed using the actual clock synchronization compensation value.

[0026] A second aspect of the present invention provides a clock synchronization device, comprising:

[0027] An acquisition module, used to acquire location information and power information of each clock source, and determine the coverage range of each clock source according to the location information and power information of each clock source;

[0028] An analysis module, configured to determine a situation in which a clock source signal is received according to the coverage range and location information of the local terminal;

[0029] A processing module, used for receiving a main timestamp signal sent by the main clock source and a secondary timestamp signal sent by the secondary clock source, and determining whether a difference between the main timestamp signal and the secondary timestamp signal is within a preset error; if so, using the main timestamp signal as a standard clock source for clock synchronization; otherwise, determining the standard clock source according to the order in which the test messages are received;

[0030] A timestamp broadcasted by the standard clock source is received, and a clock of a local terminal is synchronized according to the timestamp.

[0031] A third aspect of the present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the clock synchronization method as described in the first aspect of the present invention when executing the computer program.

[0032] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the clock synchronization method as described in the first aspect of the present invention is implemented.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1. By selecting a suitable clock source as the standard clock, the accuracy of time synchronization using the IEEE1588 protocol is improved;

[0035] 2. When there are multiple clock sources, when one clock source fails or the transmission is delayed, the backup clock source can be used for time synchronization without affecting the normal operation of the local terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of a clock synchronization method according to the present invention;

[0037] Figure 2 A schematic diagram of the architecture of a clock synchronization device of the present invention;

[0038] Figure 3 FIG. 4 is a schematic diagram of a computer device in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] It should be noted that the serial numbers assigned to the components in the embodiments of the present invention, such as "first" and "second", are only used to distinguish the objects being described and do not have any order or technical meaning.

[0041] Combine the following Figure 1 A clock synchronization method of the present invention is described.

[0042] A clock synchronization method, comprising:

[0043] S1. Obtaining location information and power information of each clock source, and determining the coverage range of each clock source according to the location information and power information of each clock source;

[0044] In the present invention, the clock source is preferably a 1588v2 clock. The 1588v2 clock is a high-precision clock that uses the IEEE1588V2 protocol. It uses a time distribution mechanism and a time scheduling concept. The client can use an ordinary oscillator and keep synchronization with the main clock of the main control machine through software scheduling. The process is simple and reliable, saving a lot of clock cables.

[0045] Since the application scenario of the present invention is mainly for time synchronization of terminals in various areas of a large city, the clock source signal will cause signal attenuation due to the transmission distance, and signal delay will also occur. In order to enable multiple terminals to be time synchronized to receive the signal sent by the clock source, multiple clock sources need to be configured. A high-power clock source has a large coverage range, while a low-power clock source has a small coverage range.

[0046] S2. Determine, according to the coverage range and the location information of the local terminal, a situation in which a clock source signal is received;

[0047] Specifically, a strength threshold of the received clock source signal can be set in the local terminal. When the received clock source signal strength is greater than the threshold, the clock source is judged as an alternative clock source. The clock source can use a single board or multiple boards, and the board preferably uses a PTM board for signal transmission.

[0048] Furthermore, after selecting the candidate clock source, the stability of the candidate clock source can be tested by a heartbeat test. Specifically, the local terminal sends a time synchronization acquisition instruction to the clock source every n milliseconds, receives the time data sent by each clock source, and if the time data sent by the clock source is not received after exceeding the preset interval threshold, the clock source is removed from the candidate clock source.

[0049] S3. If the number of received clock source signals is greater than one, the clock source with the strongest signal is used as the primary clock source, and the clock source with the second strongest signal is used as the secondary clock source;

[0050] The present invention is mainly aimed at the situation of multiple candidate clock sources, and if the number of received clock source signals is one, then the clock source is the standard clock source.

[0051] S4, receiving the main timestamp signal sent by the main clock source and the secondary timestamp signal sent by the secondary clock source, and determining whether the difference between the main timestamp signal and the secondary timestamp signal is within a preset error; if so, using the main timestamp signal as the standard clock source for clock synchronization; otherwise, determining the standard clock source according to the order in which the test messages are received;

[0052] S5. Receive the timestamp broadcast by the standard clock source, and synchronize the clock of the local terminal according to the timestamp.

[0053] The following steps can be used to synchronize time:

[0054] Initializing the standard clock source and the receiver of the local terminal;

[0055] Performing parameter configuration on the standard clock source and the receiver of the local terminal;

[0056] Receiving the timestamp broadcasted by the standard clock source and measuring the transmission delay duration;

[0057] After the transmission delay is corrected, the time synchronization of the clock of the local terminal is completed.

[0058] When correcting the transmission delay, you can use a correction algorithm, such as the statistical average method, the MAC layer timestamp method, the shortest path synchronization method, etc. You can also use the following methods to correct it:

[0059] Start the operating system, read the IEEE1588 network card driver and the compensation value file corresponding to the operating system, the compensation value file records the clock synchronization compensation values ​​corresponding to different system loads;

[0060] The actual system load is obtained, and an actual clock synchronization compensation value corresponding to the actual system load is determined according to the compensation value file, and clock synchronization is performed using the actual clock synchronization compensation value.

[0061] The compensation value file stores a plurality of compensation value mapping tables corresponding to system loads, and the compensation value corresponding to the load condition of the local terminal during actual operation can be extracted from the mapping table.

[0062] In one embodiment, determining the coverage range of each of the clock sources according to the location information and power information of each of the clock sources includes:

[0063] According to the location information and power information of each of the clock sources, establishing a Thiessen polygon for each of the clock sources;

[0064] The coverage range of each of the clock sources is determined according to the Thiessen polygons and the minimum power that can be received by the time board of the terminal to be clock synchronized.

[0065] Thiessen polygons are a type of partitioning of a spatial plane, and are characterized in that any position within a polygon is closest to the sample point of the polygon, and is far away from the sample point in an adjacent polygon, and each polygon contains and only contains one sample point. In the present invention, the position of the clock source is used as the sample point position of the Thiessen polygon. The Thiessen polygon can be used to effectively define the coverage range of each clock source.

[0066] In one embodiment, after receiving the timestamp broadcast by the standard clock source and synchronizing the clock of the local terminal according to the timestamp, the method further includes:

[0067] The time interval of arrival of the timestamp is monitored, and the number of times the time interval is greater than a preset time interval is obtained. If the number is greater than a preset number threshold, the secondary clock source is switched to a standard clock source.

[0068] When the timestamp reaches too long, it will affect the accuracy of clock synchronization, and the application of local time compensation cannot correct the time delay well. When switching the standard clock source, the aforementioned secondary clock source is preferred as the standard clock source for time synchronization, and monitoring is still performed. Monitoring can also be performed in time when the standard clock source fails, without affecting the time synchronization of the local terminal.

[0069] like Figure 2 As shown, the present invention also provides a clock synchronization device, comprising:

[0070] The acquisition module 10 is used to acquire the location information and power information of each clock source, and determine the coverage range of each clock source according to the location information and power information of each clock source;

[0071] An analysis module 20, configured to determine a situation in which a clock source signal is received according to the coverage range and location information of the local terminal;

[0072] The processing module 30 is used to receive the main timestamp signal sent by the main clock source and the secondary timestamp signal sent by the secondary clock source, and determine whether the difference between the main timestamp signal and the secondary timestamp signal is within a preset error. If it is within the preset error, the main timestamp signal is used as the standard clock source for clock synchronization; otherwise, the standard clock source is determined according to the order in which the test messages are received;

[0073] A timestamp broadcasted by the standard clock source is received, and a clock of a local terminal is synchronized according to the timestamp.

[0074] In one embodiment, Figure 3 As shown, a computer device 40 is provided, including a memory 42, a processor 41, and a computer program 43 stored in the memory 42 and executable on the processor 41. When the processor 41 executes the computer program 43, the steps in the data processing method in the above embodiment are implemented. To avoid repetition, they are not described here. Alternatively, when the processor 41 executes the computer program 43, the functions of each module in the above clock synchronization device embodiment are implemented. To avoid repetition, they are not described here.

[0075] In one embodiment, a readable storage medium is provided, wherein the readable storage medium stores a computer program 43. When the computer program 43 is executed by the processor 41, the steps in the data processing method in the above embodiment are implemented. To avoid repetition, it is not described here. Alternatively, when the processor 41 executes the computer program 43, the functions of each module in the above data processing device embodiment are implemented. To avoid repetition, it is not described here.

[0076] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0077] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules, sub-modules and units as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock synchronization method, characterized in that: include: Acquire location information and power information of each clock source, and determine the coverage range of each clock source according to the location information and power information of each clock source; Determining, according to the coverage range and the location information of the local terminal, a situation in which a clock source signal is received; If the number of received clock source signals is greater than one, the clock source with the strongest signal is used as the primary clock source, and the clock source with the second strongest signal is used as the secondary clock source; Receive a main timestamp signal sent by the main clock source and a secondary timestamp signal sent by the secondary clock source, and determine whether a difference between the main timestamp signal and the secondary timestamp signal is within a preset error; if so, use the main timestamp signal as a standard clock source for clock synchronization; otherwise, determine the standard clock source according to the order in which the test messages are received; A timestamp broadcasted by the standard clock source is received, and a clock of a local terminal is synchronized according to the timestamp.

2. The clock synchronization method according to claim 1, characterized in that: The determining, according to the location information and power information of each of the clock sources, the coverage range of each of the clock sources comprises: According to the location information and power information of each of the clock sources, establishing a Thiessen polygon for each of the clock sources; The coverage range of each of the clock sources is determined according to the Thiessen polygons and the minimum power that can be received by the time board of the terminal to be clock synchronized.

3. The clock synchronization method according to claim 1, characterized in that: After determining, according to the coverage range, that a clock source signal is received, the method further includes: If the number of received clock source signals is one, the clock source is a standard clock source.

4. The clock synchronization method according to claim 1, characterized in that: The receiving the timestamp broadcast by the standard clock source and synchronizing the clock of the local terminal according to the timestamp includes: Initializing the standard clock source and the receiver of the local terminal; Performing parameter configuration on the standard clock source and the receiver of the local terminal; Receiving the timestamp broadcasted by the standard clock source and measuring the transmission delay duration; After the transmission delay is corrected, the time synchronization of the clock of the local terminal is completed.

5. The clock synchronization method according to claim 1, characterized in that: After receiving the timestamp broadcasted by the standard clock source and synchronizing the clock of the local terminal according to the timestamp, the method further includes: The time interval of arrival of the timestamp is monitored, and the number of times the time interval is greater than a preset time interval is obtained. If the number is greater than a preset number threshold, the secondary clock source is switched to a standard clock source.

6. The clock synchronization method according to claim 1, characterized in that: The step of completing time synchronization of a clock of a local terminal after correcting the transmission delay comprises: Start the operating system, read the IEEE1588 network card driver and the compensation value file corresponding to the operating system, the compensation value file records the clock synchronization compensation values ​​corresponding to different system loads; The actual system load is obtained, and an actual clock synchronization compensation value corresponding to the actual system load is determined according to the compensation value file, and clock synchronization is performed using the actual clock synchronization compensation value.

7. A clock synchronization device, comprising: An acquisition module, used to acquire location information and power information of each clock source, and determine the coverage range of each clock source according to the location information and power information of each clock source; An analysis module, configured to determine a situation in which a clock source signal is received according to the coverage range and location information of the local terminal; A processing module, used for receiving a main timestamp signal sent by the main clock source and a secondary timestamp signal sent by the secondary clock source, and determining whether a difference between the main timestamp signal and the secondary timestamp signal is within a preset error; if so, using the main timestamp signal as a standard clock source for clock synchronization; otherwise, determining the standard clock source according to the order in which the test messages are received; A timestamp broadcasted by the standard clock source is received, and a clock of a local terminal is synchronized according to the timestamp.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the clock synchronization method according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the clock synchronization method according to any one of claims 1 to 6 is implemented.

Images