Switch based on FPGA, data transmission method and medium
By adopting FPGA design in the switch, flexible configuration and data processing are achieved, solving the problems of fixed functions, long development cycle and high cost of existing switches, providing flexibility, rapid development and low cost.
Patent Information
- Application Number
- CN202411284944.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2025-02-14
AI Technical Summary
The existing switch chip functions are fixed, the development cycle is long, and the cost is high, making it difficult to meet the rapidly changing market demand and the needs of flexible adjustment or upgrade.
Using FPGA-based switch design, flexible configuration and data processing are achieved through the MAC layer, reception management module, transmission management module and storage module of FPGA, reducing production costs and shortening development cycles.
It provides flexible configuration capabilities, short development cycles and low production costs, which can meet the diversified needs of switch performance in different application scenarios, and solves the problems of fixed functions, long development cycles and high costs.
Smart Images
Figure CN119449740A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of Ethernet technology, and in particular to a FPGA-based switch, a data transmission method and a medium. Background Art
[0002] With the rapid development of science and technology, Ethernet has been widely used in various industries and has become an indispensable part of network communication. As the core device in the network, the performance of the switch is directly related to the speed and reliability of network transmission, so it occupies a vital position in the network architecture.
[0003] In the related technology, switches are usually implemented using Application Specific Integrated Circuit (ASIC) chips. Although ASIC chips have powerful performance, the design, verification and production processes of ASIC chips are complicated, which not only easily leads to a long time period from demand analysis to switch listing, making it difficult to meet the rapidly changing market needs, but also easily leads to large initial R&D investment and relatively high production costs, increasing the overall cost of the switch. In addition, once the ASIC chip is designed, its function is relatively fixed, making it difficult for the switch to be flexibly adjusted or upgraded according to the actual application scenario. Summary of the invention
[0004] Based on the above problems, the present application provides an FPGA-based switch, data transmission method and medium, which can provide flexible configuration capabilities, shorter development cycle and lower production cost.
[0005] The embodiments of the present application disclose the following technical solutions:
[0006] In a first aspect, an embodiment of the present application discloses a switch based on a field programmable gate array FPGA, wherein the FPGA-based switch includes an FPGA and an Ethernet physical layer interface PHY, wherein the FPGA and the Ethernet PHY are connected through a target interface, and the FPGA includes a media access control MAC layer, a receiving management module, a sending management module, and a storage module;
[0007] The MAC layer is used to obtain the data frame of the Ethernet PHY through the target interface; and send the data frame to the receiving management module;
[0008] The receiving management module is used to obtain target information by parsing the data frame, wherein the target information includes at least one of a MAC address, a port number, and an Internet Protocol IP address; according to the target information, search the storage module for a message corresponding to the target information; and send the message to the sending management module;
[0009] The sending management module is used to send the message to the MAC layer, so that the MAC layer sends the message to the Ethernet PHY through the target interface.
[0010] Optionally, the receiving management module is specifically used to:
[0011] According to the target information, searching the storage module for a forwarding rule and / or a data identifier corresponding to the target information;
[0012] According to the forwarding rule and / or the data identifier, a message corresponding to the target information is obtained.
[0013] Optionally, the receiving management module is specifically used to:
[0014] If the data identifier is the first identifier, searching the storage module for a message corresponding to the MAC address, the port number, and the IP address;
[0015] If the data identifier is the second identifier, a message corresponding to any one of the MAC address, the port number and the IP address is searched in the storage module.
[0016] Optionally, the sending management module includes a plurality of port sub-queues; the sending management module is specifically used for:
[0017] Polling the cache status of each of the port sub-queues;
[0018] If the buffer state indicates that there is no unsent message in the port sub-queue and the buffer of the port sub-queue is not full, the message is sent to the MAC layer through the port sub-queue.
[0019] Optionally, the MAC layer is specifically used for:
[0020] Performing a security check on the data frame, the security check comprising at least one of address filtering, access control list matching, and deep packet inspection;
[0021] The data frame that passes the security check is sent to the receiving management module.
[0022] Optionally, the target interface comprises a Gigabit Media Independent GMII interface and / or a Reduced Gigabit Media Independent RGMII interface.
[0023] In a second aspect, an embodiment of the present application provides a data transmission method, which is applied to a switch based on a field programmable gate array FPGA, wherein the FPGA-based switch includes an FPGA and an Ethernet physical layer interface PHY, wherein the FPGA and the Ethernet PHY are connected through a target interface, and the FPGA includes a media access control MAC layer, a receiving management module, a sending management module, and a storage module; the method includes:
[0024] Obtain the data frame of the Ethernet physical layer interface PHY through the target interface;
[0025] Acquire target information by parsing the data frame, wherein the target information includes at least one of a MAC address, a port number, and an Internet Protocol IP address;
[0026] According to the target information, searching for a message corresponding to the target information;
[0027] The message is sent to the Ethernet PHY through the target interface.
[0028] Optionally, searching for a message corresponding to the target information according to the target information includes:
[0029] According to the target information, searching for a forwarding rule and / or a data identifier corresponding to the target information;
[0030] According to the forwarding rule and / or the data identifier, a message corresponding to the target information is obtained.
[0031] Optionally, acquiring a message corresponding to the target information according to the forwarding rule and / or the data identifier includes:
[0032] If the data identifier is the first identifier, searching for a message corresponding to the MAC address, the port number, and the IP address;
[0033] If the data identifier is the second identifier, a message corresponding to any one of the MAC address, the port number and the IP address is searched.
[0034] In a third aspect, the present application discloses a computer-readable storage medium, wherein the computer-readable storage medium is used to store program code, and the program code is used to execute the steps of the data transmission method described in the second aspect.
[0035] Compared with the prior art, this application has the following beneficial effects:
[0036] The embodiment of the present application discloses a switch based on FPGA, a data transmission method and a medium, wherein the MAC layer of the switch based on FPGA is used to obtain data frames of Ethernet PHY through a target interface; send data frames to a receiving management module; the receiving management module is used to obtain target information by parsing data frames; according to the target information, a message corresponding to the target information is searched in a storage module; a message is sent to a sending management module; the sending management module is used to send a message to the MAC layer, so that the MAC layer sends a message to Ethernet PHY through the target interface. Therefore, the FPGA-based switch disclosed in the embodiment of the present application uses FPGA as the implementation platform of the switch, provides flexible configuration capabilities, a shorter development cycle and a lower production cost, can meet the diverse requirements of switch performance in different application scenarios, and solves the problems of fixed switch chip functions, long development cycle and high cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0038] Figure 1 A schematic diagram of an FPGA-based switch provided in an embodiment of the present application;
[0039] Figure 2 A schematic diagram of another FPGA-based switch provided in an embodiment of the present application;
[0040] Figure 3 An interface definition diagram provided for an embodiment of the present application;
[0041] Figure 4 A schematic diagram of a sending queue provided in an embodiment of the present application;
[0042] Figure 5 A flowchart of a data transmission method provided in an embodiment of the present application. DETAILED DESCRIPTION
[0043] First, the technical terms involved in this application are explained:
[0044] A switch is a network device that works at the data link layer (mainly the second layer, i.e., the MAC layer) of the Open Systems Interconnection (OSI) reference model and is used to forward data packets within a local area network (LAN). The main function of a switch is to achieve fast switching of data packets, forwarding data packets from one port to another through the internal high-speed backplane and switching matrix, thereby achieving communication between different devices.
[0045] Field-Programmable Gate Array (FPGA) is a programmable logic device. As a semi-custom circuit in the field of ASIC, FPGA not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices. Its main features include reprogrammability, low power consumption, low latency and strong computing power.
[0046] The Ethernet physical layer transceiver (PHY) is responsible for implementing the functions of the Ethernet physical layer. It defines the electrical and optical signals, line status, clock reference, data encoding and circuits required for data transmission and reception, and provides a standard interface for data link layer devices.
[0047] As described above, current switches are usually implemented using ASIC chips. Although ASIC chips have powerful performance, the design, verification and production processes of ASIC chips are complicated, which not only easily leads to a long time period from demand analysis to switch listing, making it difficult to meet the rapidly changing market needs, but also easily leads to large initial R&D investment and relatively high production costs, increasing the overall cost of the switch. In addition, once the ASIC chip is designed, its function is relatively fixed, making it difficult for the switch to be flexibly adjusted or upgraded according to the actual application scenario.
[0048] After research, the inventor proposed a switch based on FPGA, a data transmission method and a medium, wherein the MAC layer of the switch based on FPGA is used to obtain data frames of Ethernet PHY through the target interface; send data frames to the receiving management module; the receiving management module is used to obtain target information by parsing the data frames; according to the target information, the message corresponding to the target information is searched in the storage module; the message is sent to the sending management module; the sending management module is used to send messages to the MAC layer, so that the MAC layer sends messages to Ethernet PHY through the target interface. Therefore, the FPGA-based switch disclosed in the embodiment of the present application uses FPGA as the implementation platform of the switch, provides flexible configuration capabilities, a shorter development cycle and a lower production cost, can meet the diverse requirements of switch performance in different application scenarios, and solves the problems of fixed switch chip functions, long development cycle and high cost.
[0049] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0050] See also Figure 1 , which is a schematic diagram of a FPGA-based switch provided in an embodiment of the present application. The FPGA-based switch 10 (hereinafter referred to as the switch) includes an FPGA 11 and an Ethernet PHY 12 .
[0051] In the embodiment disclosed in the present application, FPGA 11 serves as the core processing unit of the switch, integrating a media access control (MAC) layer 111, a receiving management module 112, a sending management module 113, and a storage module 114. Ethernet PHY 12 is connected to FPGA 11 through a target port, serving as a physical interface for data to enter and exit the switch.
[0052] The MAC layer 111 is part of the data link layer and is responsible for processing data transmission between the physical layer and the upper network layer. The MAC layer 111 communicates with the Ethernet PHY 12 through a specific target interface, receives data frames from the Ethernet PHY 12, and passes these data frames to the receiving management module 112 for further processing.
[0053] After receiving the data frame from the MAC layer 111, the receiving management module 112 obtains the target information by parsing the data frame. The target information includes the MAC address, port number, and IP address. Then, the receiving management module 112 searches for a message matching the target information in the storage module 114. Once a matching message is found, the receiving management module 112 sends the message to the sending management module 113 for subsequent sending. If no matching message is found, the receiving management module 112 may perform other operations, such as discarding the data frame, recording a log, etc.
[0054] It is understandable that the storage module 114 is a memory area for storing messages and other necessary data, and may include various types of storage media, such as Ternary Content Addressable Memory (TCAM), etc., to support different operation requirements of the switch. These messages may be pre-defined for quickly responding to specific network requests, or they may be cached or processed results of previously received data frames. This application does not limit the specific storage module 114.
[0055] The sending management module 113 is responsible for passing the message received from the receiving management module 112 back to the MAC layer 111, so as to send the message back to the Ethernet PHY 12 through the target interface, and finally transmit it to the target device through the physical medium.
[0056] In summary, the embodiment of the present application discloses a switch based on FPGA, wherein the MAC layer of the switch based on FPGA is used to obtain data frames of Ethernet PHY through a target interface; send data frames to a receiving management module; the receiving management module is used to obtain target information by parsing data frames; according to the target information, search for messages corresponding to the target information in the storage module; send messages to the sending management module; the sending management module is used to send messages to the MAC layer, so that the MAC layer sends messages to Ethernet PHY through the target interface. As a result, the FPGA-based switch realizes efficient data processing and network forwarding functions in a highly integrated manner based on the FPGA-based switch design, which helps to quickly respond to network changes, improve data processing capabilities, and allow users to customize logic as needed, which can meet the diverse needs of switch performance in different application scenarios, and solve the problems of fixed switch chip functions, long development cycles, and high costs.
[0057] See also Figure 2 , which is a schematic diagram of another FPGA-based switch provided in an embodiment of the present application. The FPGA-based switch includes an FPGA 21 and an Ethernet PHY 22.
[0058] Among them, FPGA and Ethernet PHY are connected through the target interface. It should be noted that Figure 2 The target interface is the Reduced Gigabit Media Independent Interface (RGMII) interface as an example. The RGMII interface is a simplified Gigabit Media Independent Interface that supports Gigabit Ethernet speeds and uses differential signal pairs to transmit data, making the RGMII interface more efficient in terms of cost and PCB layout. Figure 3 , which is an interface definition diagram provided in an embodiment of the present application. The diagram shows the interaction process of data and control signals between a transmitter and a receiver in a communication system. Figure 3 The main signals and components included are the transmitting clock signal (TX_CLK), the receiving clock signal (RX_CLK), the transmitting data line (TXD), the receiving data line (RXD) and related control signals (such as TX_CTRL, RX_CTRL), etc. In practical applications, the target interface can also be a Gigabit Media Independent Interface (GMII) interface. The GMII interface is also a Gigabit Media Independent Interface. The GMII interface provides an 8-bit data transmission path and independent clock signals for sending and receiving. It should be noted that this application does not limit the specific target interface. No matter which interface standard is selected, it is necessary to ensure that the MAC layer and Ethernet PHY22 in FPGA21 support the interface standard and correctly implement the interface protocol.
[0059] Specifically, first, the MAC layer 211 obtains the data frame of the Ethernet PHY 22 through the target interface (such as the RGMII interface or the GMII interface). It can be understood that the MAC layer 211 can ensure that each data frame complies with the communication rules specified in the IEEE802.3 specification. This communication rule defines the interface specification between the physical layer and the data link layer (especially the MAC layer 211), including the format of the data frame, the error detection mechanism, etc.
[0060] Secondly, after receiving the data frame, the MAC layer 211 will perform a series of security checks, including at least one of address filtering, access control list matching and deep packet inspection, to ensure the legitimacy and security of the received data frame. Among them, address filtering means that the MAC layer 211 will check the MAC address in the data frame to determine whether it is within the allowed range, which helps prevent the communication of unauthorized devices. Access control list matching means that the MAC layer 211 will check certain fields of the data frame (such as IP address, port number, etc.) according to the preset access control list to determine whether the data frame is allowed to pass. This enhances the security of the network and allows administrators to control network communications in a fine-grained manner according to needs. Deep packet inspection refers to checking whether the content of the data frame contains malicious code (such as viruses, Trojans) or sensitive information (such as personal identity information, commercial secrets), etc. Specifically, the MAC layer 211 will parse each field of the data frame and perform the above-mentioned security check on each field separately. If all fields of the data frame pass the security check, the MAC layer 211 will regard it as a valid data frame and prepare to pass it to the receiving management module 212 for further processing.
[0061] Subsequently, after receiving the data frame that has passed the security check of the MAC layer 211, the receiving management module 212 will search for the corresponding forwarding rules and / or data identifiers in the storage module 213 according to the target information in the data frame (such as MAC address, port number and IP address), and further obtain the message that matches the target information based on the forwarding rules and / or data identifiers found.
[0062] It is understandable that the storage module 213 can be a TCAM, because TCAM has a very high search speed and parallel processing capability, and is very suitable for fast forwarding decisions of network devices. Specifically, TCAM can complete parallel search of the entire table entry in a single clock cycle, thereby achieving fast matching of a large number of forwarding rules.
[0063] Specifically, the forwarding rule defines how to process data frames based on specific conditions (such as target information), which may include corresponding forwarding actions (such as forwarding to which port, discarding, modifying data frames, etc.). Data identifiers are used to distinguish different data processing logics.
[0064] In some specific implementations, when the data identifier of the data frame received by the receiving management module 212 is the first identifier, the receiving management module 212 will adopt a more stringent matching strategy, and accurately search for a message that completely corresponds to it in the storage module 213 according to the three pieces of information, namely, the MAC address, the port number, and the IP address in the data frame. This matching method is suitable for scenarios that require highly accurate control of data forwarding, such as financial transactions, medical record transmission, etc.
[0065] In another specific implementation, when the data identifier of the data frame received by the receiving management module 212 is the second identifier, the matching strategy of the receiving management module 212 will be relatively loose, and it is only necessary to search for the corresponding message in the storage module 213 according to any one of the information of the MAC address, port number and IP address. This matching method is suitable for those scenarios that do not require particularly high forwarding accuracy but require fast matching and forwarding, such as video streaming, online games, etc.
[0066] Therefore, by introducing data identification and different forwarding rules, and using efficient storage technologies such as TCAM, the receiving management module 212 can flexibly process data frames according to the network environment and application requirements. This mechanism not only improves the flexibility and adaptability of the switch, but also can meet the network transmission requirements in various scenarios while ensuring security and accuracy.
[0067] Then, after the receiving management module 212 finds the message corresponding to the target information and sends the found message to the sending management module 214, the sending management module 214 will periodically poll the cache status of each port sub-queue. The sending management module 113 contains multiple port sub-queues for managing the sending tasks of different ports. Periodically polling the cache status of each port sub-queue is to ensure that before sending a message, the port sub-queue is in a state where it can receive a new message, thereby avoiding data loss or network congestion.
[0068] In some specific implementations, the cache status usually includes two key information: whether there are unsent messages and whether the cache is not full. Among them, checking whether there are unsent messages is to ensure that there are no messages currently being processed in the port subqueue, or there are no other messages waiting to be sent in the port subqueue. If the queue is empty or the sending of the previous message has been completed, the port subqueue is considered to be idle or ready to send a new message. Checking whether the cache is not full is to prevent the port subqueue from overflowing due to exceeding its capacity limit after sending a new message. If the cache is not full, it means that there is enough space to store the new message.
[0069] See also Figure 4 , which is a schematic diagram of a sending queue provided in an embodiment of the present application. For message 1, if the cache state of the port subqueue of message 1 indicates that there is no unsent message in the port subqueue (that is, the sending of the previous message has been completed) and the cache of the port subqueue is not full, the sending management module 214 sends message 1 to the MAC layer through the port subqueue.
[0070] It should be noted that although the basic polling scheduling method checks the queues in a fixed order, the sending management module 214 can implement priority processing by sorting the queues before polling. This means that high-priority messages can be sent before low-priority messages. This sorting can be based on various attributes of the message, such as QoS (quality of service) marking, DSCP (differentiated service code point) field in the IP header, etc. The specific priority order is not limited in this application.
[0071] Finally, the sending management module 214 can send the message to the MAC layer 211, so that the MAC layer 211 sends the message to the Ethernet PHY 12 through the target interface after receiving the message from the sending management module 113. The Ethernet PHY 12 converts the message into a physical signal and transmits it to the target device through a physical medium.
[0072] Therefore, the FPGA-based switch disclosed in the embodiment of the present application has the following beneficial effects: First, the performance of the FPGA-based switch is improved. The present application adopts FPGA as the core processing unit. FPGA has parallel processing capabilities and high customizability, which can significantly improve the speed and efficiency of data processing. In the switch, this means that the processes of receiving, parsing, forwarding, etc. of data frames can be completed faster, reducing network delay and improving overall network performance. In addition, due to the direct hardware implementation of the internal logic of the FPGA, the instruction cycle and context switching overhead in the traditional CPU processing are reduced, so that the forwarding delay of the data frame is greatly reduced, which is particularly suitable for application scenarios with high real-time requirements. Secondly, the flexibility of the FPGA-based switch is enhanced. The programmable characteristics of the FPGA enable the switch to be flexibly configured and optimized according to different network requirements. When the network protocol or application requirements change, the FPGA can be reprogrammed to adapt to these changes without replacing the hardware equipment, which greatly reduces the upgrade and maintenance costs. In addition, the FPGA-based switch design integrates functional modules such as the MAC layer, receiving management module, sending management module and storage module into the FPGA. This modular design not only improves the maintainability of the switch, but also allows each module to be independently upgraded or replaced, further enhancing the flexibility and scalability of the switch. Finally, the FPGA-based switch optimizes resources. By integrating key functions such as the MAC layer, receiving management module, and sending management module into the FPGA, the dependence on external processors is reduced, thereby making more efficient use of hardware resources. In summary, the FPGA-based switch design realizes efficient data processing and network forwarding functions in a highly integrated manner, which helps to quickly respond to network changes, improve data processing capabilities, and allow users to customize logic as needed, which can meet the diverse needs of switch performance in different application scenarios and solve the problems of fixed switch chip functions, long development cycle and high cost.
[0073] See also Figure 5 , which is a flow chart of a data transmission method provided in an embodiment of the present application. The data transmission method is applied to an FPGA-based switch, the FPGA-based switch includes an FPGA and an Ethernet PHY, the FPGA and the Ethernet PHY are connected through a target interface, and the FPGA includes a MAC layer, a receiving management module, a sending management module, and a storage module.
[0074] The method includes:
[0075] S501: Acquire a data frame of an Ethernet physical layer interface PHY through a target interface.
[0076] In some specific implementations, the target interface includes a GMII interface and / or an RGMII interface.
[0077] S502: Acquire target information by parsing the data frame, where the target information includes at least one of a MAC address, a port number, and an Internet Protocol IP address.
[0078] S503: According to the target information, search for a message corresponding to the target information.
[0079] In some specific implementations, searching for a message corresponding to the target information according to the target information includes:
[0080] According to the target information, searching for a forwarding rule and / or a data identifier corresponding to the target information;
[0081] According to the forwarding rule and / or data identifier, a message corresponding to the target information is obtained.
[0082] In some specific implementations, obtaining a message corresponding to the target information according to the forwarding rule and / or the data identifier includes:
[0083] If the data identifier is the first identifier, then according to the target information, find a message corresponding to the MAC address, port number and IP address;
[0084] If the data identifier is the second identifier, a message corresponding to any one of the MAC address, port number and IP address is searched according to the target information.
[0085] S504: Send a message to the Ethernet PHY through the target interface.
[0086] In summary, the embodiment of the present application discloses a data transmission method, which realizes efficient data processing and network forwarding functions in a highly integrated manner based on FPGA switch design, which helps to quickly respond to network changes, improve data processing capabilities, and allow users to customize logic as needed, which can meet the diverse requirements of switch performance in different application scenarios and solve the problems of fixed switch chip functions, long development cycle and high cost.
[0087] The embodiment of the present application also provides a corresponding computer storage medium for implementing the solution provided by the embodiment of the present application.
[0088] The computer storage medium stores codes, and when the codes are executed, the device executing the codes implements the method described in any embodiment of the present application.
[0089] The "first" and "second" in the names such as "first" and "second" (if any) mentioned in the embodiments of the present application are only used as name identifiers and do not represent the first or second in order.
[0090] Through the description of the above implementation methods, it can be known that those skilled in the art can clearly understand that all or part of the steps in the above-mentioned embodiment method can be implemented by means of software plus a general hardware platform. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a storage medium, such as a read-only memory (ROM) / RAM, a magnetic disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment of the present application or some parts of the embodiments.
[0091] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments. The device and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components indicated as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.
[0092] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
[0093] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.
Claims
1. A switch based on a field programmable gate array FPGA, characterized in that: The FPGA-based switch includes an FPGA and an Ethernet physical layer interface PHY, the FPGA and the Ethernet PHY are connected through a target interface, and the FPGA includes a media access control MAC layer, a receiving management module, a sending management module and a storage module; The MAC layer is used to obtain the data frame of the Ethernet PHY through the target interface; Sending the data frame to the receiving management module; The receiving management module is used to obtain target information by parsing the data frame, wherein the target information includes at least one of a MAC address, a port number, and an Internet Protocol IP address; and according to the target information, search the storage module for a message corresponding to the target information; Sending the message to the sending management module; The sending management module is used to send the message to the MAC layer, so that the MAC layer sends the message to the Ethernet PHY through the target interface.
2. The FPGA-based switch according to claim 1, characterized in that: The receiving management module is specifically used for: According to the target information, searching the storage module for a forwarding rule and / or a data identifier corresponding to the target information; According to the forwarding rule and / or the data identifier, a message corresponding to the target information is obtained.
3. The FPGA-based switch according to claim 2, characterized in that: The receiving management module is specifically used for: If the data identifier is the first identifier, searching the storage module for a message corresponding to the MAC address, the port number, and the IP address; If the data identifier is the second identifier, a message corresponding to any one of the MAC address, the port number and the IP address is searched in the storage module.
4. The FPGA-based switch according to claim 1, characterized in that: The sending management module includes a plurality of port sub-queues; the sending management module is specifically used for: Polling the cache status of each of the port sub-queues; If the buffer state indicates that there is no unsent message in the port sub-queue and the buffer of the port sub-queue is not full, the message is sent to the MAC layer through the port sub-queue.
5. The FPGA-based switch according to claim 1, characterized in that: The MAC layer is specifically used for: Performing a security check on the data frame, the security check comprising at least one of address filtering, access control list matching, and deep packet inspection; The data frame that passes the security check is sent to the receiving management module.
6. The FPGA-based switch according to claim 1, characterized in that: The target interface includes a Gigabit Media Independent GMII interface and / or a Reduced Gigabit Media Independent RGMII interface.
7. A data transmission method, characterized in that: The invention is applied to a switch based on a field programmable gate array (FPGA), wherein the switch based on the FPGA includes an FPGA and an Ethernet physical layer interface (PHY), wherein the FPGA and the Ethernet PHY are connected via a target interface, and the FPGA includes a media access control (MAC) layer, a receiving management module, a sending management module and a storage module; the method includes: Obtain the data frame of the Ethernet physical layer interface PHY through the target interface; Acquire target information by parsing the data frame, wherein the target information includes at least one of a MAC address, a port number, and an Internet Protocol IP address; According to the target information, searching for a message corresponding to the target information; The message is sent to the Ethernet PHY through the target interface.
8. The method according to claim 7, characterized in that The searching, according to the target information, for a message corresponding to the target information includes: According to the target information, searching for a forwarding rule and / or a data identifier corresponding to the target information; According to the forwarding rule and / or the data identifier, a message corresponding to the target information is obtained.
9. The method according to claim 8, characterized in that The acquiring, according to the forwarding rule and / or the data identifier, a message corresponding to the target information includes: If the data identifier is the first identifier, searching for a message corresponding to the MAC address, the port number, and the IP address; If the data identifier is the second identifier, a message corresponding to any one of the MAC address, the port number and the IP address is searched.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store program codes, and the program codes are used to execute the steps of the data transmission method according to any one of claims 7 to 9.