Driving circuit of luminous fiber array and luminous fabric equipment

Abstract

The invention discloses a driving circuit of a light-emitting fiber array and light-emitting fabric equipment, and relates to the technical field of light-emitting fabric equipment, the driving circuit comprises a power supply module, a control module, a boost circuit, an H-bridge circuit and a switch array, and the switch array is connected with the light-emitting fiber array; the power supply module is connected with the boost circuit and the control module. The boost circuit is connected with the H-bridge circuit. The boost circuit is connected with the H-bridge circuit and is used for boosting input voltage to target voltage and inputting the target voltage into the H-bridge circuit; the control module is connected with the H-bridge circuit and is used for driving the H-bridge circuit to generate positive and negative alternating voltage according to the voltage inversion frequency corresponding to the target overall brightness; and the H-bridge circuit is connected with the luminous fiber array and is used for outputting positive and negative alternating voltage to the luminous fiber array, so that the luminous fiber array emits light according to the target overall brightness. The technical problem that an existing driving circuit for the light-emitting fiber array is low in reliability is solved.

Description

Technical Field

[0001] The present application relates to the field of electroluminescence technology, and in particular to a driving circuit of a luminous fiber array, a luminous fabric device and a control method thereof. Background Art

[0002] Electroluminescence (EL) technology has shown extensive application potential and research value with its unique energy conversion mechanism, which is the direct conversion of electrical energy into light energy. In particular, flexible electroluminescent devices (i.e., luminous fibers) have been applied to smart wearables, flexible displays, personalized fashion clothing and other fields due to their simplified preparation process, significant cost-effectiveness and excellent environmental adaptability.

[0003] Traditionally, the brightness of the luminous fiber array is mainly adjusted by directly controlling the voltage or current applied to the two ends of the luminous fiber array. Although this method is direct and effective, it has significant defects: when the current or driving voltage in the loop increases significantly, especially under high brightness requirements, it may cause excessive voltage at the load end, thereby causing the luminous fiber to break down. In other words, the existing driving circuit for the luminous fiber array has low reliability.

[0004] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of the present application is to provide a driving circuit for a luminous fiber array and a luminous fabric device, aiming to solve the technical problem of low reliability of the existing driving circuit for the luminous fiber array.

[0006] To achieve the above-mentioned purpose, the present application proposes a driving circuit for a light-emitting fiber array, the driving circuit comprising a power module, a control module, a boost circuit, an H-bridge circuit and a switch array, the switch array being connected to the light-emitting fiber array;

[0007] The power module is connected to the boost circuit and the control module, and the boost circuit is connected to the H-bridge circuit;

[0008] The boost circuit is connected to the H-bridge circuit and is used for boosting the input voltage to a target voltage and then inputting it into the H-bridge circuit;

[0009] The control module is connected to the H-bridge circuit and is used to drive the H-bridge circuit to generate positive and negative alternating voltages by a voltage inversion frequency corresponding to the target overall brightness;

[0010] The H-bridge circuit is connected to the light-emitting fiber array and is used to output positive and negative alternating voltages to the light-emitting fiber array so that the light-emitting fiber array emits light according to the target overall brightness.

[0011] In one embodiment, the switch array includes a plurality of switch units, and one switch unit is connected to one or more light-emitting fiber monomers in the light-emitting fiber array;

[0012] The control module is connected to the switch array and is used to control the opening and closing of the switch units in the switch array through the signal duty cycle corresponding to the target monomer brightness, so as to control the circuit conduction time of the luminous fiber monomer connected to the switch unit during the display refresh cycle, so that the luminous fiber monomer emits light according to the target monomer brightness.

[0013] In one embodiment, the control module includes a micro control unit and an IO expansion unit electrically connected;

[0014] The microcontroller unit is connected to the H-bridge circuit and is used to drive the H-bridge circuit to generate positive and negative alternating voltages by a voltage inversion frequency corresponding to the target overall brightness;

[0015] The micro control unit is connected to the switch array through the IO expansion unit, and is used to control the on and off of the circuit of the luminous fiber array connected to the switch array.

[0016] In one embodiment, the micro control unit includes an information acquisition subunit, a PWM frequency adjustment subunit and a GPIO adjustment subunit;

[0017] An information acquisition subunit, used to acquire target brightness information for the light-emitting fiber array, wherein the target brightness information includes the target overall brightness of the light-emitting fiber array and the target monomer brightness of a specified light-emitting fiber monomer;

[0018] The PWM frequency adjustment subunit is used to adjust the frequency of the PWM signal according to the voltage inversion frequency corresponding to the target overall brightness, and output the PWM signal after the frequency adjustment as a pulse drive signal to the H-bridge circuit;

[0019] The GPIO adjustment subunit is used to adjust the output state of the GPIO on the microcontroller unit according to the target duty cycle corresponding to the target single-unit brightness, so as to adjust the circuit conduction time of the switch unit in the switch array connected to the GPIO during the display refresh cycle.

[0020] In one embodiment, the control module further includes a timing control circuit, and the micro control unit is connected to the H-bridge circuit through the timing control circuit; the timing control circuit includes a first delay subcircuit, a second delay subcircuit, a first AND logic subcircuit, a second AND logic subcircuit and an inverting subcircuit;

[0021] After the first delay subcircuit and the first AND logic subcircuit are connected in series in sequence, the first delay subcircuit is connected to the micro control unit, and the first AND logic subcircuit is connected to the H-bridge circuit;

[0022] After the inverting sub-circuit, the second delay sub-circuit and the second AND logic sub-circuit are connected in series in sequence, the inverting sub-circuit is connected to the micro control unit, and the second AND logic sub-circuit is connected to the H-bridge circuit.

[0023] In one embodiment, the driving circuit of the light-emitting fiber array further includes: a current limiting circuit, through which the H-bridge circuit is connected to the light-emitting fiber array;

[0024] The current limiting circuit is used to limit the current flowing into the light-emitting fiber monomers in the light-emitting fiber array.

[0025] In one embodiment, the boost circuit includes a boost control chip, a boost input terminal and a boost output terminal, the boost input terminal is connected to the power module, and the boost output terminal is connected to the H-bridge circuit;

[0026] The first pin of the boost control chip is connected to the boost input terminal, and is connected to the boost output terminal through a power inductor and a voltage-resistant diode; one end of the boost input capacitor is connected to the boost input terminal, and the other end of the boost input capacitor is grounded;

[0027] The second pin of the boost control chip is connected to the gate of the first MOS tube, the drain of the first MOS tube is connected to the power inductor and the withstand voltage diode respectively, and the source of the first MOS tube is grounded via a power resistor;

[0028] The third pin of the boost control chip is respectively connected to the first feedback voltage divider resistor and the second feedback voltage divider resistor, and the second feedback voltage divider resistor is grounded; one end of the boost output capacitor is connected to the boost output end after being connected in parallel with the first feedback voltage divider resistor and the second feedback voltage divider resistor, and the other end of the boost output capacitor is grounded.

[0029] In one embodiment, the fourth pin of the boost control chip is connected to the first starting voltage-dividing resistor and the second starting voltage-dividing resistor respectively, and the second starting voltage-dividing resistor is grounded; one end of the boost input capacitor is connected to the first starting voltage-dividing resistor and the second starting voltage-dividing resistor in parallel and then connected to the boost input end;

[0030] The fifth pin of the boost control chip is grounded via a power resistor;

[0031] The sixth pin of the boost control chip is connected to ground via a series gain resistor and a gain capacitor.

[0032] In one embodiment, the withstand voltage diode includes a first diode, a second diode, a third diode, a fourth diode and a fifth diode, and the boost output capacitor includes a first output capacitor, a second output capacitor, a third output capacitor, a fourth output capacitor and a fifth output capacitor;

[0033] One end of the first diode is respectively connected to the power inductor, one end of the fourth output capacitor and the drain of the MOS tube, the other end of the first diode is respectively connected to one end of the second diode, the first end of the first output capacitor and one end of the second output capacitor, and the other end of the first output capacitor is grounded;

[0034] The other end of the second diode is respectively connected to the other end of the fourth output capacitor, one end of the fifth output capacitor and one end of the third diode;

[0035] The other end of the third diode is respectively connected to one end of the fourth diode, one end of the third output capacitor, and the other end of the second output capacitor;

[0036] The other end of the fourth diode is connected to one end of the fifth diode and the other end of the fifth output capacitor respectively;

[0037] The other end of the fifth diode is connected to the other end of the third output capacitor and the boost output end respectively.

[0038] In one embodiment, the H-bridge circuit is composed of two half-bridge circuits, the half-bridge circuit includes a signal input terminal, a voltage output terminal and an H-bridge driving chip, the signal input terminal is connected to the control module, and the signal input terminal includes a first signal input terminal and a second signal input terminal;

[0039] The first pin of the H-bridge driver chip is respectively connected to one end of the sixth diode and the power supply voltage;

[0040] The second pin of the H-bridge driver chip is respectively connected to the first signal input terminal and the first voltage-stabilizing resistor, and the first voltage-stabilizing resistor is grounded;

[0041] The third pin of the H-bridge driver chip is respectively connected to the second signal input terminal and the second voltage-stabilizing resistor, and the second voltage-stabilizing resistor is grounded;

[0042] The fourth pin of the H-bridge driver chip is respectively connected to the other end of the sixth diode and one end of the bootstrap capacitor;

[0043] The fifth pin of the H-bridge driver chip is respectively connected to the gate of the second MOS tube and one end of the third voltage-stabilizing resistor, the drain of the second MOS tube is connected to the boost output end of the boost circuit, and the source of the second MOS tube is connected in parallel with the other end of the third voltage-stabilizing resistor and then connected to the drain of the third MOS tube;

[0044] The sixth pin of the H-bridge driver chip is connected to the other end of the bootstrap capacitor and the voltage output end respectively;

[0045] The seventh pin of the H-bridge driver chip is respectively connected to the gate of the third MOS tube and one end of the fourth stabilizing resistor, and the source of the third MOS tube is connected in parallel with the other end of the fourth stabilizing resistor and then grounded.

[0046] In one embodiment, the power module includes a voltage conversion unit and a power interface unit;

[0047] The power interface unit is connected to the voltage conversion unit and the boost circuit respectively, and is used to connect to an external power source, and transmit the input voltage of the external power source to the voltage conversion unit and the boost circuit respectively;

[0048] The voltage conversion unit is connected to the control module and is used for converting the input voltage of the external power supply into the working voltage required by the control module.

[0049] In addition, to achieve the above objectives, the present application also proposes a light-emitting fabric device, which includes the above-mentioned driving circuit and light-emitting fiber array.

[0050] One or more technical solutions proposed in this application have at least the following technical effects:

[0051] The present application proposes a driving circuit for a light-emitting fiber array, the driving circuit includes a power module, a control module, a boost circuit, an H-bridge circuit and a switch array, the switch array is connected to the light-emitting fiber array; the power module is connected to the boost circuit and the control module, the boost circuit is connected to the H-bridge circuit; the boost circuit is connected to the H-bridge circuit, and is used to increase the input voltage to the target voltage and then input it into the H-bridge circuit, so that the present application realizes constant voltage power supply for the light-emitting fiber array according to its required target voltage. The control module is connected to the H-bridge circuit, and is used to drive the H-bridge circuit to generate positive and negative alternating voltages according to the voltage inversion frequency corresponding to the target overall brightness; the H-bridge circuit is connected to the light-emitting fiber array, and is used to output positive and negative alternating voltages to the light-emitting fiber array, so that the light-emitting fiber array emits light according to the target overall brightness. Therefore, the present application adjusts the frequency of the pulse driving signal according to the voltage inversion frequency corresponding to the target overall brightness through the control module, so as to drive the H-bridge circuit to generate positive and negative alternating voltages corresponding to the voltage inversion frequency, so that the H-bridge circuit outputs positive and negative alternating voltages to the light-emitting fiber array, so that the light-emitting fiber array can emit light according to the target overall brightness. Compared with the traditional method of adjusting voltage or current, the present application adjusts the overall brightness of the light-emitting fiber array by means of voltage inversion frequency, thereby avoiding the occurrence of light-emitting fiber breakdown caused by large fluctuations in voltage or current, effectively improving the reliability of the driving circuit of the light-emitting fiber array, and thus also improving the overall reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0053] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0054] Figure 1 A circuit diagram of a first embodiment of a driving circuit of a light-emitting fiber array of the present application;

[0055] Figure 2 A schematic diagram of the light-emitting principle of the light-emitting fiber involved in the embodiment of the present application;

[0056] Figure 3 A circuit diagram of a second embodiment of a driving circuit for a light-emitting fiber array of the present application;

[0057] Figure 4 A circuit diagram of a timing control circuit involved in an embodiment of the present application;

[0058] Figure 5 Another circuit diagram of the timing control circuit involved in the embodiment of the present application;

[0059] Figure 6 A complete circuit diagram of a timing control circuit according to an embodiment of the present application;

[0060] Figure 7 A circuit diagram of a third embodiment of a driving circuit for a light-emitting fiber array of the present application;

[0061] Figure 8 A circuit diagram of a boost circuit according to an embodiment of the present application;

[0062] Fig. 9 Another circuit diagram of the boost circuit involved in the embodiment of the present application;

[0063] Fig.10 A schematic diagram of a scenario of the control logic of the H-bridge circuit involved in an embodiment of the present application;

[0064] Fig.11 Another schematic diagram of the control logic of the H-bridge circuit involved in the embodiment of the present application;

[0065] Fig.12 A circuit diagram of an H-bridge circuit involved in an embodiment of the present application;

[0066] Fig.13 This is a circuit diagram of a fourth embodiment of a driving circuit for a light emitting fiber array of the present application.

[0067] Description of Figure Numbers:

[0068] 10. Power module; 11. Power interface unit; 12. Voltage conversion unit;

[0069] 20. Control module; 21. Micro control unit; 211. Information acquisition subunit; 212. PWM frequency adjustment subunit; 213. GPIO adjustment subunit; 22. IO expansion unit; 23. Timing control circuit; 231. First delay subcircuit; 232. Second delay subcircuit; 233. First AND logic subcircuit; 234. Second AND logic subcircuit; 235. Inverting subcircuit;

[0070] 30. Boost circuit; IC3, boost control chip; V SUPPLY , boost input terminal; V LOAD , boost output terminal; R UVLOT , the first starting voltage-dividing resistor; R UVLOB , the second starting voltage-dividing resistor; Cin, the boost input capacitor; Q1, the first MOS tube; L M , power inductor; D N , withstand voltage diode; R S , power resistance; R FBT , the first feedback voltage divider resistor; R FBB , the second feedback voltage divider resistor; Cout, boost output capacitor; R COMP , gain resistor; C COMP , gain capacitor; D1, first diode; D2, second diode; D3, third diode; D4, fourth diode; D5, fifth diode; Cout1, first output capacitor; Cout2, second output capacitor; Cout3, third output capacitor; Cout4, fourth output capacitor; Cout5, fifth output capacitor;

[0071] 40, H-bridge circuit; 41, half-bridge circuit; Min, signal input terminal; Vout, voltage output terminal; IC4, H-bridge driver chip; M1, first signal input terminal; M2, second signal input terminal; D6, sixth diode; R10, first voltage-stabilizing resistor; R20, second voltage-stabilizing resistor; R30, third voltage-stabilizing resistor; R40, fourth voltage-stabilizing resistor; Ct, bootstrap capacitor; Q2, second MOS tube; Q3, third MOS tube;

[0072] 50. switch array; 51. switch unit;

[0073] 60. Light-emitting fiber array; 61. Light-emitting fiber;

[0074] 70. Current limiting circuit.

[0075] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0076] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0077] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0078] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0079] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0080] The main solution of the embodiment of the present application is: the driving circuit includes a power module, a control module, a boost circuit, an H-bridge circuit and a switch array, and the switch array is connected to the light-emitting fiber array; the power module is connected to the boost circuit and the control module, and the boost circuit is connected to the H-bridge circuit; the boost circuit is connected to the H-bridge circuit, and is used to increase the input voltage to the target voltage and then input it into the H-bridge circuit; the control module is connected to the H-bridge circuit, and is used to drive the H-bridge circuit to generate a positive and negative alternating voltage corresponding to the voltage reversal frequency through a pulse driving signal; the H-bridge circuit is connected to the light-emitting fiber array, and is used to output a positive and negative alternating voltage to the light-emitting fiber array, so that the light-emitting fiber array emits light according to the target overall brightness; the control module is connected to the switch array, and is used to control the circuit conduction time of the light-emitting fiber monomers in the light-emitting fiber array connected to the switch array within the display refresh cycle, so that the light-emitting fiber monomers emit light according to the target monomer brightness.

[0081] Traditionally, the brightness of the luminous fiber array composed of luminous fibers is mainly adjusted by directly controlling the voltage or current applied to the two ends of the luminous fiber array. Although this method is direct and effective, it has significant defects: when the current or driving voltage in the loop increases significantly, especially under high brightness requirements, it may cause excessive voltage at the load end, thereby causing the luminous fiber to break down. In other words, the existing driving circuit for the luminous fiber array has low reliability.

[0082] The present application provides a solution. In the driving circuit of the present application, the control module adjusts the frequency of the pulse driving signal according to the voltage reversal frequency corresponding to the target overall brightness to drive the H-bridge circuit to generate a positive and negative alternating voltage corresponding to the voltage reversal frequency, so that the H-bridge circuit outputs the positive and negative alternating voltage to the light-emitting fiber array, so that the light-emitting fiber array can emit light according to the target overall brightness. Compared with the traditional way of adjusting voltage or current, the present application changes the reversal frequency of the positive and negative alternating voltage according to the voltage reversal frequency to adjust the overall brightness of the light-emitting fiber array, avoids the breakdown of the light-emitting fiber caused by large fluctuations in voltage or current, effectively improves the reliability of the driving circuit of the light-emitting fiber array, and thus also improves the overall reliability of the product.

[0083] Based on this, the present application proposes a driving circuit for a light-emitting fiber array.

[0084] See also Figure 1 In one embodiment of the driving circuit of the luminous fiber array of the present application, the driving circuit of the luminous fiber array includes a power module 10, a control module 20, a boost circuit 30, an H-bridge circuit 40 and a switch array 50, and the switch array 50 is connected to the luminous fiber array 60;

[0085] The power module 10 is connected to the boost circuit 30 and the control module 20, and the boost circuit 30 is connected to the H-bridge circuit 40;

[0086] The boost circuit 30 is connected to the H-bridge circuit 40 and is used to boost the input voltage to the target voltage of the light-emitting fiber array 60 and input it into the H-bridge circuit 40;

[0087] The control module 20 is connected to the H-bridge circuit 40 and is used to drive the H-bridge circuit 40 to generate positive and negative alternating voltages according to the voltage inversion frequency corresponding to the target overall brightness;

[0088] The H-bridge circuit 40 is connected to the light-emitting fiber array 60 and is used to output positive and negative alternating voltages to the light-emitting fiber array 60 so that the light-emitting fiber array 60 emits light according to the target overall brightness.

[0089] It should be noted that the power module 10 can be used as a module connected to an external power source, or it can be a module with an independent energy storage device (such as a disposable battery or a rechargeable battery). The luminous fiber array 60 is composed of a predetermined number of luminous fiber monomers 61. The luminous fiber monomers 61 in the luminous fiber array 60 can be simply arranged, or can be formed into a desired pattern through embroidery, weaving and other processes.

[0090] It should also be noted that the switch array 50 includes a plurality of switch units 51, each of which is connected to one or more light-emitting fiber monomers 61 in the light-emitting fiber array 60. The switch array 50 may be composed of an optocoupler relay or an integrated analog switch chip.

[0091] In this embodiment, the driving circuit includes a power module 10, a control module 20, a boost circuit 30, an H-bridge circuit 40 and a switch array 50, wherein the switch array 50 is connected to the light-emitting fiber array 60, wherein the switch unit 51 in the switch array 50 is electrically connected to one or more light-emitting fiber monomers 61 in the light-emitting fiber array 60, thereby the circuit on and off of the light-emitting fiber monomers 61 in the light-emitting fiber array 60 can be realized by controlling the closing and opening of the switch unit 51 in the switch array 50. The power module 10 is connected to the boost circuit 30 and the control module 20, and the boost circuit 30 is connected to the H-bridge circuit 40. The boost circuit 30 is connected to the H-bridge circuit 40, and is used to increase the input voltage to the target voltage and input it into the H-bridge circuit 40, wherein the target voltage is the voltage expected to be loaded on both ends of the light-emitting fiber array 60, thereby realizing constant voltage power supply to the light-emitting fiber array according to the target voltage required.

[0092] The control module 20 is connected to the H-bridge circuit 40, and is used to drive the H-bridge circuit 40 to generate a positive and negative alternating voltage by a voltage inversion frequency corresponding to the target overall brightness, wherein there is a corresponding relationship between the target overall brightness and the voltage inversion frequency, and there is a positive correlation between the voltage inversion frequency and the target overall brightness. The H-bridge circuit 40 is connected to the light-emitting fiber array 60, and is used to output a positive and negative alternating voltage to the light-emitting fiber array 60, so that the light-emitting fiber array 60 emits light according to the target overall brightness. Therefore, this embodiment can adjust the frequency of the pulse drive signal transmitted to the H-bridge circuit by the voltage inversion frequency corresponding to the target overall brightness (that is, the frequency at which the polarity of the voltage is reversed), thereby changing the frequency of the positive and negative alternating voltage polarity reversal output to the light-emitting fiber array 60, so that the light-emitting fiber array 60 emits light according to the target overall brightness. Figure 2 As shown, under the action of applying an electric field to the two electrodes of the light-emitting fiber monomer 61, the electrons in the insulating medium are accelerated to obtain sufficient physical kinetic energy to directly collide with the luminescent center (i.e., electroluminescent material, such as zinc sulfide). When the electrons in the luminescent center are excited, they will transition from the excited state high energy level to the ground state low energy level to emit visible light, which is the electroluminescence phenomenon. If the direction of the electric field does not change, the electrons will only move in one direction and accumulate to cause a reverse electric field inside the luminescent fiber. Finally, the internal and external balance will no longer have electrons collide with the luminescent center, and the luminescence will terminate. Therefore, it is necessary to apply a reverse electric field, that is, to use a negative voltage to accelerate the electrons so that they can produce continuous excitation and luminescence. Therefore, it is necessary to input a positive and negative alternating voltage to drive the luminescent fiber array 60 to emit light continuously and stably. Since the number of times of luminescence is fixed in each luminescence cycle, as the voltage reversal frequency increases (gradually from low frequency to high frequency), the faster the frequency of the polarity reversal of the positive and negative alternating voltage output to the luminescent fiber array 60, the shorter the luminescence cycle of the luminescent fiber array 60 per unit time, and the more times of luminescence, thereby effectively improving the overall brightness of the luminescent fiber array 60. Therefore, this embodiment can adjust the frequency of the pulse drive signal transmitted to the H-bridge circuit according to the voltage reversal frequency (i.e., the frequency at which the polarity of the voltage is reversed) corresponding to the target overall brightness, thereby changing the frequency of the positive and negative alternating voltage polarity reversal output to the light-emitting fiber array 60, thereby actually changing the number of light-emitting phenomena occurring per unit time (i.e., the frequency of electrons hitting the light-emitting center), so as to change the overall light-emitting brightness of the light-emitting fiber array 60. Since this brightness adjustment method does not involve changing the voltage and current of the driving circuit, it is less likely to cause the light-emitting fiber breakdown phenomenon than the traditional method of adjusting the voltage or current.

[0093] In some embodiments, the switch array 50 includes a plurality of switch units 51 , and one switch unit 51 is connected to one or more light-emitting fiber monomers 61 in the light-emitting fiber array 60 ;

[0094] The control module 20 is connected to the switch array 50, and is used to control the opening and closing of the switch unit 51 in the switch array 50 through the signal duty cycle corresponding to the target monomer brightness, so as to control the circuit conduction time of the luminous fiber monomer 61 connected to the switch unit 51 within the display refresh cycle, so that the luminous fiber monomer 61 emits light according to the target monomer brightness.

[0095] It should be noted that after the control module 20 is connected to the switch array 50 , the control module 20 can send a control signal through the switch array 50 to control the opening and closing of the switch unit 51 in the switch array 50 .

[0096] In addition, it should be noted that the target monomer brightness is the brightness of the light emitted by the specified light-emitting fiber monomer 61 in the light-emitting fiber array 60 under the target overall brightness. The signal duty cycle is the effective time ratio of the control signal sent by the control module 20 to the switch array 50. There is a corresponding relationship between the target monomer brightness and the signal duty cycle, and the target monomer brightness and the signal duty cycle are positively correlated.

[0097] In this embodiment, the control module 20 is connected to the switch array 50, and is used to control the opening and closing of the switch unit 51 in the switch array 50 by the signal duty ratio corresponding to the target monomer brightness, so as to control the circuit conduction time of the luminous fiber monomer 61 connected to the switch unit 51 in the display refresh cycle, and adjust the brightness of the luminous fiber monomer 61 in the luminous fiber array 60. Exemplarily, in this embodiment, the output state (high level, low level) output to the GPIO (General-Purpose Input / Output) connected to the switch array 50 in the control module 20 can be changed according to the signal duty ratio, so as to output a control signal corresponding to the duty ratio to the switch unit 51, and the control signal is used to control the opening and closing of the switch unit 51, that is, the effective time ratio in the control signal closes the switch unit 51 to load the positive and negative alternating voltage at both ends of the luminous fiber monomer 61, and the switch unit 51 is disconnected at other time ratios except the effective time ratio, so as to cancel the loading of the positive and negative alternating voltage at both ends of the luminous fiber monomer 61, thereby adjusting the proportion of the luminous duration of the luminous fiber monomer 61 in the refresh cycle to achieve the adjustment of the target monomer brightness of the luminous fiber monomer. Therefore, this embodiment changes the duty cycle of the control signal according to the target monomer brightness to adjust the circuit conduction time within the display refresh cycle, thereby achieving brightness control of the light-emitting fiber monomer 61 and improving the precision of brightness control of the light-emitting fiber array 60.

[0098] In some embodiments, the control module 20 includes a micro control unit 21 and an IO expansion unit 22 that are electrically connected;

[0099] The micro control unit 21 is connected to the H-bridge circuit 40 and is used to drive the H-bridge circuit 40 to generate positive and negative alternating voltages by a voltage inversion frequency corresponding to the target overall brightness;

[0100] The micro control unit 21 is connected to the switch array 50 through the IO expansion unit 22 , and is used to control the on / off of the circuit of the light emitting fiber array 60 connected to the switch array 50 .

[0101] The control module 20 may be a field programmable gate array (FPGA) or a micro-controller unit (MCU). Figure 3 As shown, the control module 20 may also adopt a combination of an electrically connected microcontroller unit 21 and an IO (Input / Output) expansion unit 22. The microcontroller unit 21 is connected to the H-bridge circuit 40, and is used to drive the H-bridge circuit 40 to generate positive and negative alternating voltages according to the voltage inversion frequency corresponding to the target overall brightness; the microcontroller unit 21 is connected to the switch array 50 through the IO expansion unit 22, and is used to control the circuit on and off of the luminous fiber array 60 connected to the switch array 50. In this embodiment, the combination of the microcontroller unit 210 and the IO expansion unit 220 is generally lower in power consumption than an FPGA with higher performance and integration, and is more economical and easy to use. And compared with a simple MCU, the circuit on and off control of the luminous fiber array composed of more luminous fibers can be realized.

[0102] In some embodiments, the micro control unit 21 includes an information acquisition subunit 211, a PWM frequency adjustment subunit 212, and a GPIO adjustment subunit 213;

[0103] The information acquisition subunit 211 is used to acquire target brightness information for the light-emitting fiber array 60, wherein the target brightness information includes the target overall brightness of the light-emitting fiber array 60 and the target single brightness of a specified light-emitting fiber single body;

[0104] The PWM frequency adjustment subunit 212 is used to adjust the frequency of the PWM signal according to the voltage inversion frequency corresponding to the target overall brightness, and output the frequency-adjusted PWM signal as a pulse drive signal to the H-bridge circuit 40;

[0105] The GPIO adjustment subunit 213 is used to adjust the output state of the GPIO on the micro control unit 21 according to the target duty cycle corresponding to the target single brightness, so as to adjust the circuit conduction time of the switch unit 51 in the switch array 50 connected to the GPIO within the display refresh cycle.

[0106] It should be noted that there is a positive correlation between the voltage reversal frequency and the overall brightness, and there is also a positive correlation between the target duty cycle and the target single brightness. The display refresh cycle is a cycle for repeatedly drawing the entire display content to update the display image, such as 20 frames, 30 frames, 60 frames, etc.

[0107] In this embodiment, the microcontroller unit 21 includes an information acquisition subunit 211, a PWM (Pulse-Width Modulation) frequency adjustment subunit 212 and a GPIO adjustment subunit 213. The information acquisition subunit 211 acquires target brightness information for the light-emitting fiber array 60, wherein the target brightness information includes the target overall brightness of the light-emitting fiber array 60 and the target single brightness of the specified light-emitting fiber single. Then the PWM frequency adjustment subunit 212 can adjust the frequency of the PWM signal according to the voltage reversal frequency corresponding to the target overall brightness, and output the PWM signal after the frequency adjustment as a pulse drive signal to the H-bridge circuit 40, so that the H-bridge circuit 40 can control the frequency of voltage polarity reversal according to the voltage reversal frequency after receiving the PWM signal after the frequency adjustment, thereby changing the number of light-emitting phenomena occurring per unit time (i.e., the frequency of electrons hitting the light-emitting center) to change the overall light-emitting brightness of the light-emitting fiber array 60. For the monomer brightness, the GPIO adjustment subunit 213 can adjust the output state (high level state or low level state) of the GPIO on the microcontroller unit 21 according to the target duty cycle corresponding to the target monomer brightness, thereby controlling the effective time ratio of the positive and negative alternating voltages loaded onto the two ends of the light-emitting fiber monomer, so as to change the proportion of the luminous time of the light-emitting fiber monomer in the refresh cycle by adjusting the circuit conduction time of the switch unit 51 in the switch array 50 connected to the GPIO during the display refresh cycle, thereby achieving adjustment of the target monomer brightness of the light-emitting fiber monomer.

[0108] In one embodiment, the control module 20 further includes a timing control circuit 23, and the micro control unit 21 is connected to the H-bridge circuit 40 through the timing control circuit 23; the timing control circuit 23 includes a first delay subcircuit 231, a second delay subcircuit 232, a first AND logic subcircuit 233, a second AND logic subcircuit 234 and an inverting subcircuit 235;

[0109] After the first delay sub-circuit 231 and the first AND logic sub-circuit 233 are connected in series, the first delay sub-circuit 231 is connected to the micro control unit 21, and the first AND logic sub-circuit 233 is connected to the H-bridge circuit 40;

[0110] After the inverting sub-circuit 235 , the second delay sub-circuit 232 and the second AND logic sub-circuit 234 are sequentially connected in series, the inverting sub-circuit 235 is connected to the micro control unit 21 , and the second AND logic sub-circuit 234 is connected to the H-bridge circuit 40 .

[0111] like Figure 4 For a microcontroller unit 21 that cannot directly output a set of inverted PWM signals, this embodiment can be implemented by adding an inverting circuit. In order to prevent the H-bridge circuit from being "deadlocked" (i.e., the transistors or MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor) in the H-bridge circuit are turned on at the same time due to improper control, resulting in a direct connection between the positive and negative electrodes of the power supply, forming a short circuit). Figure 5 As shown, in this embodiment, the control module 20 also includes a timing control circuit 23, and the micro control unit 21 is connected to the H-bridge circuit 40 through the timing control circuit 23; the timing control circuit 23 includes a first delay sub-circuit 231, a second delay sub-circuit 232, a first AND logic sub-circuit 233, a second AND logic sub-circuit 234 and an inverting sub-circuit 235; after the first delay sub-circuit 231 and the first AND logic sub-circuit 233 are connected in series in sequence, the first delay sub-circuit 231 is connected to the micro control unit 21, and the first AND logic sub-circuit 233 is connected to the H-bridge circuit 40; after the inverting sub-circuit 235, the second delay sub-circuit 232 and the second AND logic sub-circuit 234 are connected in series in sequence, the inverting sub-circuit 235 is connected to the micro control unit 21, and the second AND logic sub-circuit 234 is connected to the H-bridge circuit 40. Wherein, V LOGIC It is the logic voltage for supplying power to the timing control circuit 23.

[0112] Therefore, this embodiment introduces a fixed time delay when the switch state of the MOS tube in the H-bridge circuit is switched by adding a delay sub-circuit in the circuit to avoid simultaneous conduction, and improves the integrity of the delayed PWM signal with the help of the "AND logic" circuit, thereby avoiding the "deadlock" of the H-bridge circuit.

[0113] For example, Figure 6 As shown, the inverting sub-circuit 235 includes an inverting MOS tube Q f , the first inverting resistor R f1 and the second inverting resistor R f2 .

[0114] The first delay sub-circuit 231 includes a first delay diode D y1 , the first delay resistor R y1 and the first delay capacitor C y1 The second delay sub-circuit 232 includes a second delay diode D y2 , the second delay resistor R y2 and the second delay capacitor C y2Thus, the "AND logic" circuit constructed by the first delay sub-circuit 231, the second delay sub-circuit 232, and the first AND gate chip IC1 and the second AND gate chip IC2 forms a complete timing control circuit 23. The first delay diode D y1 With the first delay resistor R y1 After the parallel connection, one end is connected to the micro control unit 21 to receive the PWM signal, and the other end is connected to the first delay capacitor C y1 and the second input pin of the first AND gate chip IC1 (i.e. Figure 6 The first AND gate chip IC1 is connected to the B pin, and the first delay capacitor C y1 Ground.

[0115] The first input pin of the first AND gate chip IC1 (i.e. Figure 6 The A pin of the first AND gate chip IC1 in the circuit is connected to the logic voltage V LOGIC and the first voltage stabilizing capacitor C w1 Connect the input voltage pin of the first AND gate chip IC1 (i.e. Figure 6 The VCC pin of the first AND gate chip IC1 is connected to the logic voltage and the first input voltage stabilizing capacitor C VCC1 Connect. The output pin of the first AND gate chip IC1 (i.e. Figure 6 The Y pin of the first AND gate chip IC1 in the circuit is used to output the PWM signal after the compensation delay processing.

[0116] Inverting MOS tube Q f The gate and the first inverting resistor R f1 One end of the inverting MOS tube Q is connected in parallel with the micro control unit 21 to receive the PWM signal. f The source and the first inverting resistor R f1 The other end is connected in parallel and then grounded, and the inverting MOS tube Q f The drain of the f2 Connected to the logic voltage and connected to the second delay sub-circuit 232.

[0117] The second delay diode D y2 With the second delay resistor R y2 One end of the parallel connection is connected to the inverting sub-circuit 235 to receive the inverted PWM signal, and the other end is connected to the second delay capacitor C y2 and the second input pin of the second AND gate chip IC2 (i.e. Figure 6 The second delay capacitor C y2 Ground. The first input pin of the second AND gate chip IC2 (i.e. Figure 6 The A pin of the second AND gate chip IC2 is connected to the logic voltage and the second voltage stabilizing capacitor C w2Connect the input voltage pin of the second AND gate chip IC2 (i.e. Figure 6 The VCC pin of the second AND gate chip IC2 is connected to the logic voltage and the second input stabilizing capacitor C VCC2 The output pin of the second AND gate chip IC2 (i.e. Figure 6 The Y pin of the second AND gate chip IC2 in the circuit is used to output the PWM signal after the compensation delay processing.

[0118] In some embodiments, the driving circuit of the light-emitting fiber array further includes: a current limiting circuit 70, through which the H-bridge circuit 40 is connected to the light-emitting fiber array 60;

[0119] The current limiting circuit 70 is used to limit the current flowing into the light emitting fiber monomers 61 in the light emitting fiber array 60 .

[0120] Since the present embodiment uses the voltage reversal frequency adjustment to adjust the overall brightness of the light-emitting fiber array 60, the proportion of the on-off time of the switch unit 51 in the display refresh cycle is adjusted to adjust the brightness of the light-emitting fiber monomer 61. Figure 7 As shown, the driving circuit in this embodiment further includes: a current limiting circuit 70, through which the H-bridge circuit 40 is connected to the light-emitting fiber array 60, and the current limiting circuit 70 is used to limit the current flowing into the light-emitting fiber monomer 61 in the light-emitting fiber array 60. Exemplarily, the current limiting circuit 70 can be a transistor current limiting circuit (i.e., a transistor is used as a switch, and when the current exceeds the set value, the transistor is turned on to shunt or close the circuit), an adjustable resistor current limiting circuit (adjusting the current limit value within a certain range using an adjustable resistor), a current sensing resistor current limiting circuit (i.e., a current sensing resistor is used in conjunction with an amplifier to accurately measure and limit the current), and other circuits for limiting the current peak. Therefore, this embodiment can avoid the situation where a large current breaks down the light-emitting fiber when it is turned on or in the process of adjusting the brightness without affecting the brightness of the light-emitting fiber array 60, thereby further improving the reliability of the driving circuit.

[0121] In some embodiments, the boost circuit 30 includes a boost control chip IC3, a boost input terminal V SUPPLY and boost output V LOAD , boost input terminal V SUPPLY Connected to the power module 10, the boost output terminal V LOAD connected to the H-bridge circuit 40;

[0122] The first pin of the boost control chip IC3 is connected to the boost input terminal V SUPPLY Connect and connect through the power inductor L M , withstand voltage diode D N With the boost output V LOADConnect one end of the boost input capacitor Cin to the boost input terminal V SUPPLY Connect, and the other end of the boost input capacitor Cin is grounded;

[0123] The second pin of the boost control chip IC3 is connected to the gate of the first MOS tube Q1, and the drain of the first MOS tube Q1 is connected to the power inductor L M And the withstand voltage diode D N The source of the first MOS tube Q1 is connected through the power resistor R S Grounding;

[0124] The third pin of the boost control chip IC3 is connected to the first feedback voltage divider resistor R FBT and the second feedback voltage divider resistor R FBB Connect the second feedback voltage divider resistor R FBB Ground; one end of the boost output capacitor Cout is connected to the first feedback voltage divider resistor R FBT and the second feedback voltage divider resistor R FBB After being connected in parallel with the boost output terminal V LOAD The other end of the boost output capacitor Cout is connected to ground.

[0125] This embodiment uses the boost control module IC3 to achieve the boost processing of the input voltage of the power module 10. Figure 8 As shown, the boost circuit 30 includes a boost control chip IC3, a boost input terminal V SUPPLY and the boost output V LOAD , boost input terminal V SUPPLY Connected to the power module 10, the boost output terminal V LOAD connected to the H-bridge circuit 40; the first pin BIAS (bias pin) of the boost control chip IC3 is connected to the boost input terminal V SUPPLY Connect and connect through the power inductor L M , withstand voltage diode D N With the boost output V LOAD Connection. Withstand voltage diode D N The second pin GATE (gate pin) of the boost control chip IC3 is connected to the gate of the first MOS tube Q1, and the drain of the first MOS tube Q1 is connected to the power inductor L M And the withstand voltage diode D N The source of the first MOS tube Q1 is connected through the power resistor R S The third pin FB (Feedback, feedback pin) of the boost control chip IC3 is connected to the first feedback voltage divider resistor R FBT and the second feedback voltage divider resistor R FBB Connect the second feedback voltage divider resistor R FBBGround; one end of the boost output capacitor Cout is connected to the first feedback voltage divider resistor R FBT and the second feedback voltage divider resistor R FBB After parallel connection with the boost output VLOAD The other end of the boost output capacitor Cout is connected to the ground. The first feedback voltage divider resistor R FBT and the second feedback voltage divider resistor R FBB It is a resistor voltage divider combination used to form a 1V target feedback voltage. Taking the output voltage of 150V as an example, the first feedback voltage divider resistor R FBT and the second feedback voltage divider resistor R FBB A resistor combination of 149kR:1kR or equal ratios can be used.

[0126] In another embodiment, the fourth pin of the boost control chip IC3 is respectively connected to the first starting voltage dividing resistor R UVLOT and the second starting voltage dividing resistor R UVLOB Connect the second starting voltage divider resistor R UVLOB Ground; one end of the boost input capacitor Cin and the first starting voltage dividing resistor R UVLOT and the second starting voltage dividing resistor R UVLOB After being connected in parallel with the boost input terminal V SUPPLY Connect, and the other end of the boost input capacitor Cin is grounded;

[0127] The fifth pin of the boost control chip IC3 is connected to the power resistor R S Grounding;

[0128] The sixth pin of the boost control chip IC3 is connected to the boost control chip IC3 through a series gain resistor R COMP and gain capacitor C COMP Ground.

[0129] See also Figure 8 The fourth pin UVLO (Under-Voltage Lock-Out) of the boost control chip IC3 is connected to the first starting voltage-dividing resistor RUVLOT and the second starting voltage divider resistor RUVLOB Connect the second starting voltage divider resistor R UVLOB Ground; one end of the boost input capacitor Cin and the first starting voltage dividing resistor R UVLOT and the second starting voltage dividing resistor R UVLOB After being connected in parallel with the boost input terminal V SUPPLY The other end of the boost input capacitor Cin is connected to the ground. The first starting voltage divider resistor R UVLOT and the second starting voltage dividing resistor R UVLOB It is a resistor voltage divider combination. SUPPLYA voltage division value is formed at the starting voltage (the typical value of the starting voltage is 1.5V) at the fourth pin UVLO of the boost control chip IC3, but in practice the voltage is usually increased to obtain better stability. Take the voltage division value of 1.6V as an example. If the boost input terminal V SUPPLY The input voltage is 5V, then the first starting voltage divider resistor R UVLOT and the second starting voltage dividing resistor R UVLOB A voltage divider combination of 200kR:94kR can be used. The input voltage is 20V, and the first starting voltage divider resistor R UVLOT and the second starting voltage dividing resistor R UVLOB The voltage divider combination of 800kR:70kR can be used. The fifth pin CS (ChipSelect, chip select pin) of the boost control chip IC3 is connected to the power resistor R S The sixth pin COMP (Comparator) of the boost control chip IC3 is connected to the ground through a series gain resistor R COMP and gain capacitor C COMP Ground. Gain resistor R COMP and gain capacitor C COMP is a gain combination used to set the gain of the error amplifier. Figure 8 As shown, the seventh pin VCC (Voltage Common Collector, positive voltage pin) of the boost control chip IC3 is connected to the positive voltage pin through the voltage capacitor C VCC The eighth pin RT (Timing Resistor) of the boost control chip IC3 is connected to ground through a resistor R T Ground, the ninth pin SS (Soft Start) of the boost control chip IC3 is connected to the ground through the starting capacitor C SS Ground, start capacitor C SS It is used to set the soft start time of the boost control chip IC3. The tenth pin AGND (Analog Ground) and the eleventh pin PGND (Power Ground) of the boost control chip IC3 are grounded.

[0130] In some embodiments, the withstand voltage diode D N It includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4 and a fifth diode D5, and the boost output capacitor Cout includes a first output capacitor Cout1, a second output capacitor Cout2, a third output capacitor Cout3, a fourth output capacitor Cout4 and a fifth output capacitor Cout5;

[0131] One end of the first diode D1 is connected to the power inductor LM , one end of the fourth output capacitor Cout4 is connected to the drain of the MOS tube, the other end of the first diode D1 is respectively connected to one end of the second diode D2, the first end of the first output capacitor Cout1 and one end of the second output capacitor Cout2, and the other end of the first output capacitor Cout1 is grounded;

[0132] The other end of the second diode D2 is respectively connected to the other end of the fourth output capacitor Cout4, one end of the fifth output capacitor Cout5 and one end of the third diode D3;

[0133] The other end of the third diode D3 is respectively connected to one end of the fourth diode D4, one end of the third output capacitor Cout3 and the other end of the second output capacitor Cout2;

[0134] The other end of the fourth diode D4 is connected to one end of the fifth diode D5 and the other end of the fifth output capacitor Cout5 respectively;

[0135] The other end of the fifth diode D5 is connected to the other end of the third output capacitor Cout3 and the boost output terminal V LOAD connect.

[0136] like Fig. 9 As shown, in this embodiment, the withstand voltage diode D N The boost output capacitor Cout includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4 and a fifth diode D5. The boost output capacitor Cout includes a first output capacitor Cout1, a second output capacitor Cout2, a third output capacitor Cout3, a fourth output capacitor Cout4 and a fifth output capacitor Cout5. One end of the first diode D1 is connected to the power inductor L M , one end of the fourth output capacitor Cout4 is connected to the drain of the MOS tube, the other end of the first diode D1 is respectively connected to one end of the second diode D2, the first end of the first output capacitor Cout1 and one end of the second output capacitor Cout2, and the other end of the first output capacitor Cout1 is grounded; the other end of the second diode D2 is respectively connected to the other end of the fourth output capacitor Cout4, one end of the fifth output capacitor Cout5 and one end of the third diode D3; the other end of the third diode D3 is respectively connected to one end of the fourth diode D4, one end of the third output capacitor Cout3 and the other end of the second output capacitor Cout2; the other end of the fourth diode D4 is respectively connected to one end of the fifth diode D5 and the other end of the fifth output capacitor Cout5; the other end of the fifth diode D5 is respectively connected to the other end of the third output capacitor Cout3 and the boost output terminal V LOADIn this embodiment, the first output capacitor Cout1, the second output capacitor Cout2, the third output capacitor Cout3, the fourth output capacitor Cout4 and the fifth output capacitor Cout5 are used as the boost output capacitor Cout, so as to effectively reduce the withstand voltage requirement of the output capacitor.

[0137] In some embodiments, the H-bridge circuit 40 is composed of two half-bridge circuits 41, the half-bridge circuit 41 includes a signal input terminal Min, a voltage output terminal Vout and an H-bridge driver chip IC4, the signal input terminal Min is connected to the control module 20, and the signal input terminal Min includes a first signal input terminal M1 and a second signal input terminal M2;

[0138] The first pin of the H-bridge driver chip IC4 is respectively connected to one end of the sixth diode D6 and the power supply voltage;

[0139] The second pin of the H-bridge driving chip IC4 is respectively connected to the first signal input terminal M1 and the first voltage-stabilizing resistor R10, and the first voltage-stabilizing resistor R10 is grounded;

[0140] The third pin of the H-bridge driver chip IC4 is respectively connected to the second signal input terminal M2 and the second voltage-stabilizing resistor R20, and the second voltage-stabilizing resistor R20 is grounded;

[0141] The fourth pin of the H-bridge driver chip IC4 is connected to the other end of the sixth diode D6 and one end of the bootstrap capacitor Ct respectively;

[0142] The fifth pin of the H-bridge driver chip IC4 is connected to the gate of the second MOS transistor Q2 and one end of the third voltage-stabilizing resistor R30 respectively. The drain of the second MOS transistor Q2 is connected to the boost output terminal V LOAD The source of the second MOS tube Q2 is connected in parallel with the other end of the third voltage-stabilizing resistor R30 and then connected to the drain of the third MOS tube Q3;

[0143] The sixth pin of the H-bridge driver chip IC4 is connected to the other end of the bootstrap capacitor Ct and the voltage output terminal Vout respectively;

[0144] The seventh pin of the H-bridge driver chip IC4 is connected to the gate of the third MOS transistor Q3 and one end of the fourth stabilizing resistor R40 respectively. The source of the third MOS transistor Q3 is connected in parallel with the other end of the fourth stabilizing resistor R40 and then grounded.

[0145] See also Fig.10 and Fig.11 , Fig.10 and Fig.11 Schematic diagram of the control logic of the H-bridge circuit. Fig.10 and Fig.11In the embodiment, a basic H-bridge circuit 40 is formed by a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4. The first switch S1 and the fourth switch S4 are controlled by a PWM signal of the same phase, and the second switch S2 and the third switch S3 are also controlled by a PWM signal of another phase. Fig.10 As shown, when the first switch S1 and the fourth switch S4 are turned on after receiving the PWM signal, and the second switch S2 and the third switch S3 are turned off, the current is input from the boost circuit 30 to V LOAD After that, it flows through the first switch S1 in sequence and is loaded onto each light-emitting fiber unit 61 of the light-emitting fiber array 60, and then flows out from the light-emitting fiber array 60 to the switch array 50 and then returns to the ground network (GND) of the power supply through the fourth switch S4. Fig.11 As shown, when the second switch S2 and the third switch S3 are turned on after receiving the PWM signal, and the first switch S1 and the fourth switch S4 are turned off, the current is input from the boost circuit 30 to V LOAD After that, it flows through the third switch S3 in sequence, passes through the switch array 50, and is loaded onto each light-emitting fiber unit 61 of the light-emitting fiber array 60, and flows out of the light-emitting fiber array 60 and returns to the ground network (GND) of the power supply through the second switch S2. Therefore, this embodiment achieves the reversal of the polarity of the voltage loaded on the light-emitting fiber array 60 by controlling the switch in the H-bridge circuit 40 to close.

[0146] like Fig.12As shown, in this embodiment, the H-bridge circuit 40 is composed of two half-bridge circuits 41, and the half-bridge circuit 41 includes a signal input terminal Min, a voltage output terminal Vout and an H-bridge driving chip IC4. The signal input terminal Min is connected to the control module 20, and the signal input terminal Min includes a first signal input terminal M1 and a second signal input terminal M2. The first pin VCC (Voltage Common Collector, positive voltage pin) of the H-bridge driver chip IC4 is respectively connected to one end of the sixth diode D6 and the power supply voltage Vcc; the second pin HIN (High Input, high level input pin) of the H-bridge driver chip IC4 is respectively connected to the first signal input terminal M1 and the first voltage-stabilizing resistor R10, and the first voltage-stabilizing resistor R10 is grounded; the third pin LIN (Low Input, high level input pin) of the H-bridge driver chip IC4 is respectively connected to the second signal input terminal M2 and the second voltage-stabilizing resistor R20, and the second voltage-stabilizing resistor R20 is grounded; the fourth pin VB (Vcc for Bridge, power supply pin) of the H-bridge driver chip IC4 is respectively connected to the other end of the sixth diode D6 and one end of the bootstrap capacitor Ct; the fifth pin HO (High Side Output, high side output pin) of the H-bridge driver chip IC4 is respectively connected to the gate of the second MOS tube Q2 and one end of the third voltage-stabilizing resistor R30, and the drain of the second MOS tube Q2 is connected to the boost output terminal V of the boost circuit 30. LOAD The source of the second MOS tube Q2 is connected in parallel with the other end of the third voltage-stabilizing resistor R30 and then connected to the drain of the third MOS tube Q3; the sixth pin VS (Voltage Sense, voltage sensing pin) of the H-bridge driver chip IC4 is respectively connected to the other end of the bootstrap capacitor Ct and the voltage output terminal Vout; the seventh pin LO (Low Side Output, low-end output pin) of the H-bridge driver chip IC4 is respectively connected to the gate of the third MOS tube Q3 and one end of the fourth voltage-stabilizing resistor R40, and the source of the third MOS tube Q3 is connected in parallel with the other end of the fourth voltage-stabilizing resistor R40 and then grounded. In this embodiment, the H-bridge driver chip IC4 in each half-bridge circuit 41 is used to drive the closing and opening of two switch elements (i.e., the second MOS tube Q2 and the third MOS tube Q3) in the half-bridge circuit 41.

[0147] In one embodiment, the power module 10 includes a voltage conversion unit 11 and a power interface unit 12;

[0148] The power interface unit 12 is connected to the voltage conversion unit 11 and the boost circuit 30 respectively, and is used to connect to an external power source and transmit the input voltage of the external power source to the voltage conversion unit 11 and the boost circuit 30 respectively;

[0149] The voltage conversion unit 11 is connected to the control module 20 and is used to convert the input voltage of the external power supply into the working voltage required by the control module 20 .

[0150] It should be noted that the voltage conversion unit 11 may be a DC-DC (Direct Current-Direct Current) converter.

[0151] like Fig.13 As shown, the power module 10 includes an electrically connected voltage conversion unit 11 and a power interface unit 12. The power interface unit 12 is connected to the voltage conversion unit 11 and the boost circuit 30 respectively, and is used to connect an external power source and transmit the input voltage of the external power source to the voltage conversion unit 11 and the boost circuit 30 respectively; the voltage conversion unit 11 is connected to the control module 20, and is used to convert the input voltage of the external power source into the working voltage required by the control module 20.

[0152] In addition, the embodiment of the present application also provides a light-emitting fabric device, which includes the above-mentioned driving circuit and light-emitting fiber array. Exemplarily, the light-emitting fabric device can be a smart bracelet, a smart watch, a smart clothing, etc. The fabric part of the light-emitting fabric device can be composed only of the light-emitting fiber array, or it can be composed of the light-emitting fiber array and textile materials (such as natural material silk, polymer silk, leather, etc.).

[0153] The above are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A driving circuit for a light-emitting fiber array, characterized in that: The driving circuit includes a power module, a control module, a boost circuit, an H-bridge circuit and a switch array, and the switch array is connected to the light-emitting fiber array; The power module is connected to the boost circuit and the control module, and the boost circuit is connected to the H-bridge circuit; The boost circuit is connected to the H-bridge circuit and is used to boost the input voltage to a target voltage and then input it into the H-bridge circuit; The control module is connected to the H-bridge circuit and is used to drive the H-bridge circuit to generate positive and negative alternating voltages according to a voltage inversion frequency corresponding to the target overall brightness; The H-bridge circuit is connected to the light-emitting fiber array and is used to output the positive and negative alternating voltages to the light-emitting fiber array, so that the light-emitting fiber array emits light according to the target overall brightness.

2. The driving circuit according to claim 1, characterized in that: The switch array comprises a plurality of switch units, and one switch unit is connected to one or more light-emitting fiber monomers in the light-emitting fiber array; The control module is connected to the switch array, and is used to control the opening and closing of the switch units in the switch array through the signal duty cycle corresponding to the target unit brightness, so as to control the circuit conduction time of the luminous fiber unit connected to the switch unit within the display refresh cycle, so that the luminous fiber unit emits light according to the target unit brightness.

3. The driving circuit according to claim 2, characterized in that: The control module includes a micro control unit and an IO expansion unit that are electrically connected; The micro control unit is connected to the H-bridge circuit and is used to drive the H-bridge circuit to generate positive and negative alternating voltages according to a voltage inversion frequency corresponding to the target overall brightness; The micro control unit is connected to the switch array via an IO expansion unit, and is used to control the on / off of the circuit of the light-emitting fiber array connected to the switch array.

4. The driving circuit according to claim 3, characterized in that: The micro control unit includes an information acquisition subunit, a PWM frequency adjustment subunit and a GPIO adjustment subunit; The information acquisition subunit is used to acquire target brightness information for the light-emitting fiber array, wherein the target brightness information includes the target overall brightness of the light-emitting fiber array and the target single brightness of a specified light-emitting fiber single unit; The PWM frequency adjustment subunit is used to adjust the frequency of the PWM signal according to the voltage inversion frequency corresponding to the target overall brightness, and output the PWM signal after the frequency adjustment as a pulse driving signal to the H-bridge circuit; The GPIO adjustment subunit is used to adjust the output state of the GPIO on the microcontroller unit according to the target duty cycle corresponding to the target single-unit brightness, so as to adjust the circuit conduction time of the switch unit in the switch array connected to the GPIO within the display refresh cycle.

5. The driving circuit according to claim 3, characterized in that: The control module also includes a timing control circuit, and the micro control unit is connected to the H-bridge circuit through the timing control circuit; the timing control circuit includes a first delay subcircuit, a second delay subcircuit, a first AND logic subcircuit, a second AND logic subcircuit and an inverting subcircuit; After the first delay sub-circuit and the first AND logic sub-circuit are sequentially connected in series, the first delay sub-circuit is connected to the micro control unit, and the first AND logic sub-circuit is connected to the H-bridge circuit; After the inverting sub-circuit, the second delay sub-circuit and the second AND logic sub-circuit are sequentially connected in series, the inverting sub-circuit is connected to the micro control unit, and the second AND logic sub-circuit is connected to the H-bridge circuit.

6. The driving circuit according to claim 1, characterized in that: The driving circuit of the light-emitting fiber array further includes: a current limiting circuit, through which the H-bridge circuit is connected to the light-emitting fiber array; The current limiting circuit is used to limit the current flowing into the light-emitting fiber monomers in the light-emitting fiber array.

7. The driving circuit according to claim 1, characterized in that: The boost circuit comprises a boost control chip, a boost input terminal and a boost output terminal, wherein the boost input terminal is connected to the power module, and the boost output terminal is connected to the H-bridge circuit; The first pin of the boost control chip is connected to the boost input terminal, and is connected to the boost output terminal through a power inductor and a withstand voltage diode; one end of the boost input capacitor is connected to the boost input terminal, and the other end of the boost input capacitor is grounded; The second pin of the boost control chip is connected to the gate of the first MOS tube, the drain of the first MOS tube is connected to the power inductor and the withstand voltage diode respectively, and the source of the first MOS tube is grounded via a power resistor; The third pin of the boost control chip is respectively connected to the first feedback voltage divider resistor and the second feedback voltage divider resistor, and the second feedback voltage divider resistor is grounded; one end of the boost output capacitor is connected to the boost output end after being connected in parallel with the first feedback voltage divider resistor and the second feedback voltage divider resistor, and the other end of the boost output capacitor is grounded.

8. The driving circuit according to claim 7, characterized in that: The fourth pin of the boost control chip is connected to the first starting voltage-dividing resistor and the second starting voltage-dividing resistor respectively, and the second starting voltage-dividing resistor is grounded; one end of the boost input capacitor is connected to the first starting voltage-dividing resistor and the second starting voltage-dividing resistor in parallel and then connected to the boost input end; The fifth pin of the boost control chip is grounded via the power resistor; The sixth pin of the boost control chip is connected to the ground via a series gain resistor and a gain capacitor.

9. The driving circuit according to claim 7, characterized in that: The withstand voltage diodes include a first diode, a second diode, a third diode, a fourth diode and a fifth diode, and the boost output capacitors include a first output capacitor, a second output capacitor, a third output capacitor, a fourth output capacitor and a fifth output capacitor; One end of the first diode is respectively connected to the power inductor, one end of the fourth output capacitor and the drain of the MOS tube, the other end of the first diode is respectively connected to one end of the second diode, the first end of the first output capacitor and one end of the second output capacitor, and the other end of the first output capacitor is grounded; The other end of the second diode is respectively connected to the other end of the fourth output capacitor, one end of the fifth output capacitor and one end of the third diode; The other end of the third diode is respectively connected to one end of the fourth diode, one end of the third output capacitor and the other end of the second output capacitor; The other end of the fourth diode is connected to one end of the fifth diode and the other end of the fifth output capacitor respectively; The other end of the fifth diode is connected to the other end of the third output capacitor and the boost output end respectively.

10. The driving circuit according to claim 1, wherein: The H-bridge circuit is composed of two half-bridge circuits, the half-bridge circuit includes a signal input terminal, a voltage output terminal and an H-bridge driving chip, the signal input terminal is connected to the control module, and the signal input terminal includes a first signal input terminal and a second signal input terminal; The first pin of the H-bridge driver chip is respectively connected to one end of the sixth diode and the power supply voltage; The second pin of the H-bridge driver chip is respectively connected to the first signal input terminal and the first voltage-stabilizing resistor, and the first voltage-stabilizing resistor is grounded; The third pin of the H-bridge driver chip is respectively connected to the second signal input terminal and the second voltage-stabilizing resistor, and the second voltage-stabilizing resistor is grounded; The fourth pin of the H-bridge driver chip is respectively connected to the other end of the sixth diode and one end of the bootstrap capacitor; The fifth pin of the H-bridge driver chip is respectively connected to the gate of the second MOS tube and one end of the third voltage-stabilizing resistor, the drain of the second MOS tube is connected to the boost output end of the boost circuit, and the source of the second MOS tube is connected in parallel with the other end of the third voltage-stabilizing resistor and then connected to the drain of the third MOS tube; The sixth pin of the H-bridge driver chip is respectively connected to the other end of the bootstrap capacitor and the voltage output end; The seventh pin of the H-bridge driver chip is respectively connected to the gate of the third MOS tube and one end of the fourth stabilizing resistor, and the source of the third MOS tube is connected in parallel with the other end of the fourth stabilizing resistor and then grounded.

11. The driving circuit according to claim 1, characterized in that: The power module includes a voltage conversion unit and a power interface unit; The power interface unit is connected to the voltage conversion unit and the boost circuit respectively, and is used to connect to an external power source and transmit the input voltage of the external power source to the voltage conversion unit and the boost circuit respectively; The voltage conversion unit is connected to the control module and is used for converting the input voltage of the external power supply into the working voltage required by the control module.

12. A light-emitting fabric device, characterized in that: The light-emitting textile device comprises a driving circuit and a light-emitting fiber array as claimed in any one of claims 1 to 11.

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