Thin film transistor and its manufacturing method, array substrate

Abstract

The present application is applicable to the field of display technology, and provides a thin film transistor and a preparation method thereof, and an array substrate. The thin film transistor includes a copper gate, an active layer, and an insulating layer group located between the active layer and the copper gate. The insulating layer group includes at least three low-speed deposited gate insulating layers, and the at least three low-speed deposited gate insulating layers are sequentially covered on the copper gate layer by layer; a medium-speed deposited gate insulating layer and / or a high-speed deposited gate insulating layer are arranged between the two low-speed deposited gate insulating layers. A medium-speed deposited gate insulating layer and / or a high-speed deposited gate insulating layer are arranged between the two low-speed insulating layers to improve processing efficiency. On the one hand, the denser characteristics of the lower low-speed deposited gate insulating layer are utilized to effectively block the diffusion of metallic copper. On the other hand, the denser characteristics of the upper low-speed deposited gate insulating layer are utilized to fully contact with the active layer, thereby ensuring the cleanliness of the interface between the insulating layer and the active layer, reducing the concave-convex phenomenon of the interface, and improving the electron mobility.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and more specifically, relates to a thin film transistor and a preparation method thereof, and an array substrate. Background Art

[0002] Thin Film Transistor (TFT), as a component that controls the switching of display pixels, plays the role of the heart in the display and directly affects the quality of the display. The thin film transistor liquid crystal display includes a thin film transistor array substrate, a color filter substrate arranged opposite to the thin film transistor array substrate, and a liquid crystal layer sandwiched between the thin film transistor array substrate and the color filter substrate. In general, metal aluminum as the electrode of thin film transistors can well meet the needs of thin film transistors of various displays. However, with the development of science and technology and the progress of society, displays are developing towards higher refresh rates, higher brightness, higher resolution, and larger sizes. Copper metal film is considered to be the best substitute for aluminum thin film metal due to its advantages such as low resistance, high film uniformity, and high repair success rate.

[0003] However, the traditional gate insulating layer is mainly composed of three layers: GH (High deposit rate Gate insulator) / GM (Middle deposit rate Gate insulator) / GL (Low deposit rate Gate insulator). The loose insulating layer GH (reducing the production cycle) will be quickly deposited on the gate metal, and the loose insulating layer cannot effectively prevent the diffusion of the metal. In addition, compared with aluminum (a layer of molybdenum is generally plated on aluminum to prevent metal diffusion, while copper will not be plated with molybdenum on its surface to reduce etching time), copper metal is more likely to diffuse into the insulating layer or even the active layer, especially in a high temperature environment. This affects the characteristics of the device and reduces the quality of the display. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a thin film transistor and a method for manufacturing the same, and an array substrate, in order to solve the technical problem in the prior art that the insulating layer of a thin film transistor using a copper gate is prone to metal diffusion.

[0005] To achieve the above-mentioned purpose, according to one aspect of the present application, a thin film transistor is provided, which includes a copper gate, an active layer and an insulating layer group located between the active layer and the copper gate, and the insulating layer group includes: at least three low-speed deposited gate insulation layers, at least three low-speed deposited gate insulation layers are sequentially covered on the copper gate layer by layer; a medium-speed deposited gate insulation layer and / or a high-speed deposited gate insulation layer is arranged between two low-speed deposited gate insulation layers.

[0006] Optionally, the insulating layer group further includes: a medium-speed deposited gate insulating layer, wherein the medium-speed deposited gate insulating layer is arranged between two adjacent low-speed deposited gate insulating layers.

[0007] Optionally, the insulating layer group further includes: a high-speed deposited gate insulating layer, wherein the high-speed deposited gate insulating layer is arranged between two adjacent low-speed deposited gate insulating layers.

[0008] Optionally, three adjacent low-speed deposited gate insulation layers are arranged in sequence along the direction from the copper gate to the active layer, namely a first low-speed deposited gate insulation layer, a second low-speed deposited gate insulation layer and a third low-speed deposited gate insulation layer, and the insulation layer group also includes: a medium-speed deposited gate insulation layer, which is located between the second low-speed deposited gate insulation layer and the third low-speed deposited gate insulation layer; and a high-speed deposited gate insulation layer, which is located between the first low-speed deposited gate insulation layer and the second low-speed deposited gate insulation layer.

[0009] Optionally, the thickness of the gate insulation layer deposited at a low speed is

[0010] Optionally, the thickness of the gate insulation layer deposited at a medium speed is

[0011] Optionally, the thickness of the gate insulation layer deposited at high speed is

[0012] Optionally, the thin film transistor also includes: an N-type doped amorphous silicon layer, a source and drain metal layer, an insulating protective layer, and an electrode layer, wherein the N-type doped amorphous silicon layer is formed on the active layer; the source and drain metal layer is formed on the N-type doped amorphous silicon layer; the insulating protective layer is formed on the source and drain metal layer; and the electrode layer is formed on the insulating protective layer.

[0013] According to another aspect of the present application, a method for preparing a thin film transistor is provided. The method is used to prepare the above-mentioned thin film transistor, and the method comprises:

[0014] forming a copper gate on a substrate;

[0015] forming a first low-rate deposited gate insulating layer on the copper gate and the substrate at a first rate;

[0016] forming a high-speed deposited gate insulating layer on the first low-speed deposited gate insulating layer at a third rate;

[0017] forming a second low-speed deposited gate insulating layer on the high-speed deposited gate insulating layer at a first rate;

[0018] forming a medium-speed deposited gate insulating layer on the second low-speed deposited gate insulating layer at a second rate;

[0019] forming a third low-speed deposited gate insulating layer on the medium-speed deposited gate insulating layer at a first rate;

[0020] forming an active layer on the insulating layer group;

[0021] forming an N-type doped amorphous silicon layer on the active layer;

[0022] forming a source-drain metal layer on the N-type doped amorphous silicon layer;

[0023] The source and drain metal layer, the N-type doped amorphous silicon layer and the active layer are etched to obtain the source and drain; wherein the first rate is less than the second rate, and the second rate is less than the third rate.

[0024] Optionally, an insulating protection layer is formed on the source and drain electrodes; and an electrode layer is formed on the insulating protection layer.

[0025] According to another aspect of the present application, an array substrate is provided, which includes a glass substrate, a thin film transistor and a pixel electrode disposed on the glass substrate, wherein the thin film transistor is the above-mentioned thin film transistor.

[0026] The thin film transistor provided by the present application has the following beneficial effects: compared with the prior art, the present application takes into account the problem that the copper gate is prone to diffusion during operation, and further sets three low-speed deposited gate insulating layers, and takes into account the overall thickness of the insulating layer group to prevent the occurrence of breakdown, and sets a medium-speed deposited gate insulating layer and / or a high-speed deposited gate insulating layer between the two low-speed deposited gate insulating layers to increase the thickness of the insulating layer group and improve processing efficiency. On the one hand, the present application utilizes the relatively dense characteristics of the low-speed deposited gate insulating layer at the bottom to effectively block the diffusion of metallic copper, and on the other hand, utilizes the relatively dense characteristics of the low-speed deposited gate insulating layer at the top to fully contact with the active layer, thereby ensuring the cleanliness of the interface between the insulating layer (G-SiNx) and the active layer (Ia-si), reducing the concave-convex phenomenon of the interface, and improving the electron mobility. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0028] Figure 1 A schematic diagram of the structure of a thin film transistor provided in Example 1 of the present application;

[0029] Figure 2A schematic diagram of the structure of a thin film transistor with a medium-speed deposited gate insulating layer and without a high-speed deposited gate insulating layer according to the present application;

[0030] Figure 3 A schematic diagram of the structure of a thin film transistor with a high-speed deposited gate insulating layer but without a medium-speed deposited gate insulating layer according to the present application;

[0031] Figure 4 A flow chart of a method for preparing a thin film transistor provided in Example 2 of the present application;

[0032] Figure 5 This is a schematic diagram of the structure of the array substrate provided in Example 3 of the present application.

[0033] The reference numerals in the above drawings are as follows:

[0034] 1. Thin film transistor; 2. Pixel electrode; 3. Glass substrate; 10. Insulating layer group; 11. Low-speed deposition of gate insulating layer; 12. Medium-speed deposition of gate insulating layer; 13. High-speed deposition of gate insulating layer; 20. Copper gate; 30. Substrate; 40. Active layer; 50. N-type doped amorphous silicon layer; 60. Drain; 70. Source; 80. Insulating protection layer; 90. Electrode layer. DETAILED DESCRIPTION

[0035] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0036] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or indirectly connected to the other element. In the absence of conflict, the embodiments in this application and the features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0037] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0039] In order to solve the problem that the insulating layer of the copper gate thin film transistor is prone to metal diffusion, see Figure 1 As shown, an embodiment of the present application provides a thin film transistor, which includes a copper gate 20, an active layer 40, and an insulating layer group 10 located between the active layer 40 and the copper gate 20, and the insulating layer group 10 includes: at least three low-speed deposited gate insulating layers 11, at least three low-speed deposited gate insulating layers 11 are sequentially covered on the copper gate 20 layer by layer; a medium-speed deposited gate insulating layer 12 and / or a high-speed deposited gate insulating layer 13 are arranged between two low-speed deposited gate insulating layers 11. In view of the problem that the copper gate 20 is prone to diffusion during operation, the present application further arranges three low-speed deposited gate insulating layers 11, and in view of ensuring the overall thickness of the insulating layer group 10 and preventing the occurrence of breakdown, a medium-speed deposited gate insulating layer 12 and / or a high-speed deposited gate insulating layer 13 are arranged between two low-speed deposited gate insulating layers 11 to increase the thickness of the insulating layer group 10 and improve processing efficiency. On the one hand, the present application utilizes the denser characteristics of the lower slow-deposited gate insulating layer 11 to effectively block the diffusion of metallic copper. On the other hand, it utilizes the denser characteristics of the upper slow-deposited gate insulating layer 11 to fully contact the active layer 40, thereby ensuring the cleanliness of the interface between the insulating layer group 10 (G-SiNx) and the active layer 40 (Ia-si), reducing the unevenness of the interface, and improving the electron mobility. The slow-deposited gate insulating layer 11 is the GL layer.

[0040] See also Figure 2 As shown, in one embodiment of the present application, the insulating layer group 10 in this embodiment further includes: a medium-speed deposited gate insulating layer 12, which is disposed between two adjacent low-speed deposited gate insulating layers 11. On the one hand, the thickness of the overall insulating layer group 10 is increased by depositing the gate insulating layer 12 at a medium speed, and on the other hand, the denser characteristics of the low-speed deposited gate insulating layer 11 are utilized to effectively block the diffusion of the metal copper of the lower copper gate 20, and to fully contact with the upper active layer 40, thereby ensuring the cleanliness of the interface between the insulating layer (G-SiNx) and the active layer 40 (Ia-si), reducing the concave-convex phenomenon of the interface, and improving the electron mobility, wherein the medium-speed deposited gate insulating layer 12 is the GM layer.

[0041] In other embodiments of the present application, the medium-speed deposited gate insulating layer 12 can be two, three, four, etc., separated from each other by insulating layers. For example, the insulating layer group 10 has a total of five layers, which are GL layer, GM layer, GL layer, GM layer, and GL layer from bottom to top. The present application uses the bottom layer of dense low-speed deposited gate insulating layer 11 as a sacrificial layer to block the diffusion of metal copper. At the same time, adding a dense low-speed deposited gate insulating layer 11 to the insulating layer group 10 can prevent positively charged ions from accumulating at the bottom of the insulating layer under the action of negative gate bias (the gate voltage of the TFT device works in a negative bias state most of the time), resulting in a decrease in Vth (Threshold voltage), thereby causing Ioff (off-state current) to increase and device characteristics to deteriorate.

[0042] See also Figure 3 As shown, in another embodiment of the present application, the insulating layer group 10 in this embodiment further includes: a high-speed deposited gate insulating layer 13, and the high-speed deposited gate insulating layer 13 is arranged between two adjacent low-speed deposited gate insulating layers 11. On the one hand, the thickness of the entire insulating layer group 10 is increased by depositing the gate insulating layer 13 at a high speed, and the overall preparation efficiency is improved by forming the insulating layer at a high speed. On the other hand, the denser characteristics of the low-speed deposited gate insulating layer 11 are utilized to effectively block the diffusion of the metal copper of the lower copper gate 20, and to fully contact with the upper active layer 40, thereby ensuring the cleanliness of the interface between the insulating layer (G-SiNx) and the active layer 40 (Ia-si), reducing the concave-convex phenomenon of the interface, and improving the electron mobility, wherein the high-speed deposited gate insulating layer 13 is the GH layer.

[0043] In other embodiments of the present application, the high-speed deposited gate insulating layer 13 can be two, three, four, etc., separated from each other by insulating layers. For example, the insulating layer group 10 has a total of five layers, which are GL layer, GH layer, GL layer, GH layer, and GL layer from bottom to top. The middle GL layer can block the positively charged ions from accumulating at the bottom of the insulating layer under the action of the negative gate bias (the gate voltage of the TFT device works in a negative bias state most of the time), causing Vth (Threshold voltage) to become smaller, thereby causing Ioff (off-state current) to increase and device characteristics to deteriorate.

[0044] In order to meet the production capacity and improve the performance, in a preferred embodiment of the present application, the insulating layer group 10 in this embodiment includes three low-speed deposited gate insulating layers 11, wherein the three adjacent low-speed deposited gate insulating layers 11 are arranged in sequence along the direction from the copper gate 20 to the active layer 40, namely the first low-speed deposited gate insulating layer, the second low-speed deposited gate insulating layer and the third low-speed deposited gate insulating layer, and the insulating layer group 10 also includes: a medium-speed deposited gate insulating layer 12, the medium-speed deposited gate insulating layer 12 is located between the second low-speed deposited gate insulating layer and the third low-speed deposited gate insulating layer; a high-speed deposited gate insulating layer 13, the high-speed deposited gate insulating layer 13 is located between the first low-speed deposited gate insulating layer and the second low-speed deposited gate insulating layer. The second low-speed deposited gate insulating layer can block the accumulation of positively charged ions at the bottom of the insulating layer under the action of the negative gate bias (the gate voltage of the TFT device works in a negative bias state most of the time), resulting in a decrease in Vth (Threshold voltage), thereby causing Ioff (off-state current) to increase and device characteristics to deteriorate.

[0045] The thickness of the gate insulating layer 11 deposited at a low speed in this embodiment is Preferably This can prevent the gate insulating layer 11 deposited at a low speed from being too thin and failing to play a good barrier role, and can also prevent the gate insulating layer 11 deposited at a low speed from being too thick and affecting production efficiency.

[0046] The thickness of the gate insulating layer 12 deposited at a medium speed in this embodiment is Preferably This can prevent the gate insulating layer 12 deposited at a medium speed from being too thin and failing to play the role of preventing breakdown by increasing the overall thickness, and can also prevent the gate insulating layer 12 deposited at a medium speed from being too thick and affecting production efficiency.

[0047] The thickness of the high-speed deposited gate insulating layer 13 in this embodiment is Preferably This can prevent the gate insulation layer 13 deposited at a high speed from being too thin and failing to play the role of preventing breakdown by increasing the overall thickness, and can also prevent the gate insulation layer 13 deposited at a high speed from being too thick and affecting production efficiency.

[0048] The thin film transistor of this embodiment also includes: an N-type doped amorphous silicon layer 50, a source and drain metal layer, an insulating protection layer, and an electrode layer, wherein the N-type doped amorphous silicon layer is formed on the active layer; the source and drain metal layer is formed on the N-type doped amorphous silicon layer; the insulating protection layer 80 is formed on the source and drain metal layer; and the electrode layer 90 is formed on the insulating protection layer 80.

[0049] Embodiment 2

[0050] See also Figure 4As shown, according to another aspect of the present application, this embodiment provides a method for preparing a thin film transistor, the method is used to prepare the above-mentioned thin film transistor, the method comprising:

[0051] S101, forming a copper gate 20 on a substrate 30; S102, forming a first low-speed deposited gate insulating layer on the copper gate 20 and the substrate 30 at a first rate, wherein the low-speed deposited gate insulating layer 11 has a thickness of Preferably This can prevent the low-speed deposited gate insulating layer 11 from being too thin and unable to play a good blocking role, and can also prevent the low-speed deposited gate insulating layer 11 from being too thick and affecting production efficiency; S103, forming a high-speed deposited gate insulating layer 13 on the first low-speed deposited gate insulating layer at a third rate, wherein the high-speed deposited gate insulating layer 13 has a thickness of Preferably This can prevent the high-speed deposited gate insulating layer 13 from being too thin and unable to play the role of preventing breakdown by increasing the overall thickness, and can also prevent the high-speed deposited gate insulating layer 13 from being too thick and affecting production efficiency; S104, forming a second low-speed deposited gate insulating layer on the high-speed deposited gate insulating layer 13 at the first rate, wherein the thickness of the low-speed deposited gate insulating layer 11 is Preferably This can prevent the low-speed deposited gate insulating layer 11 from being too thin and unable to play a good blocking role, and can also prevent the low-speed deposited gate insulating layer 11 from being too thick and affecting production efficiency; S105, forming a medium-speed deposited gate insulating layer 12 on the second low-speed deposited gate insulating layer at a second rate, wherein the medium-speed deposited gate insulating layer 12 has a thickness of Preferably This can prevent the medium-speed deposited gate insulating layer 12 from being too thin and unable to play the role of preventing breakdown by increasing the overall thickness, and can also prevent the medium-speed deposited gate insulating layer 12 from being too thick and affecting production efficiency; S106, forming a third low-speed deposited gate insulating layer on the medium-speed deposited gate insulating layer 12 at the first rate, wherein the thickness of the low-speed deposited gate insulating layer 11 is Preferably This can prevent the gate insulation layer 11 from being too thin and unable to play a good blocking role when deposited at a low speed, and can also prevent the gate insulation layer 11 from being too thick and affecting production efficiency when deposited at a low speed; wherein the first rate is less than the second rate, and the second rate is less than the third rate.

[0052] The method in this embodiment also includes: S107, forming an active layer 40 on the insulating layer group 10; S108, forming an N-type doped amorphous silicon layer 50 on the active layer 40; S109, forming a source and drain metal layer on the N-type doped amorphous silicon layer 50; S110, etching the source and drain metal layer, the N-type doped amorphous silicon layer 50 and the active layer, i.e., the active amorphous silicon layer, to obtain a source 70 and a drain 60; forming an insulating protective layer 80 on the source and drain 60; and forming an electrode layer 90 on the insulating protective layer 80.

[0053] Preferably, the first rate in this embodiment is The CVD (Chemical Vapor Deposition) power is 10-15kw, and the gas flow ratio is N2:NH3:SiH4=20-25:6-8:1.

[0054] The second rate is The CVD power is 15-20kw, and the gas flow ratio is N2:NH3:SiH4=13-17:4-6:1.

[0055] The third rate is The CVD power is 20-25 kw, N2:NH3:SiH4=8-12:3-5:1.

[0056] Embodiment 3

[0057] See also Figure 5 As shown, according to another aspect of the present application, this embodiment provides an array substrate, which includes a glass substrate, a thin film transistor and a pixel electrode arranged on the glass substrate, wherein the thin film transistor is the above-mentioned thin film transistor.

[0058] In summary, the thin film transistor provided by this embodiment has at least the following beneficial technical effects:

[0059] The thin film transistor provided by the present application has the following beneficial effects: compared with the prior art, the present application takes into account the problem that the copper gate is prone to diffusion during operation, and further sets three low-speed deposited gate insulating layers, and takes into account the overall thickness of the insulating layer group to prevent the occurrence of breakdown, and sets a medium-speed deposited gate insulating layer and / or a high-speed deposited gate insulating layer between the two low-speed deposited gate insulating layers to increase the thickness of the insulating layer group and improve processing efficiency. On the one hand, the present application utilizes the relatively dense characteristics of the low-speed deposited gate insulating layer at the bottom to effectively block the diffusion of metallic copper, and on the other hand, utilizes the relatively dense characteristics of the low-speed deposited gate insulating layer at the top to fully contact with the active layer, thereby ensuring the cleanliness of the interface between the insulating layer (G-SiNx) and the active layer (Ia-si), reducing the concave-convex phenomenon of the interface, and improving the electron mobility.

[0060] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A thin film transistor, comprising a copper gate, an active layer, and an insulating layer group located between the active layer and the copper gate, characterized in that: The insulating layer group comprises: At least three low-speed deposited gate insulating layers, wherein the at least three low-speed deposited gate insulating layers are layered on the copper gate; A medium-speed deposited gate insulating layer and / or a high-speed deposited gate insulating layer is disposed between the at least two low-speed deposited gate insulating layers; The three adjacent low-speed deposited gate insulation layers are arranged in sequence along the direction from the copper gate to the active layer, and are respectively a first low-speed deposited gate insulation layer, a second low-speed deposited gate insulation layer and a third low-speed deposited gate insulation layer, and the insulation layer group further includes: A medium-speed deposited gate insulating layer, wherein the medium-speed deposited gate insulating layer is located between the second low-speed deposited gate insulating layer and the third low-speed deposited gate insulating layer; A high-speed deposited gate insulating layer is disposed between the first low-speed deposited gate insulating layer and the second low-speed deposited gate insulating layer.

2. The thin film transistor according to claim 1, characterized in that: The thickness of the low-speed deposited gate insulating layer is 200-300Å.

3. The thin film transistor according to claim 1, characterized in that: The thickness of the medium-speed deposited gate insulating layer is 1000-2500Å.

4. The thin film transistor according to claim 1, characterized in that: The thickness of the high-speed deposited gate insulating layer is 500-1000Å.

5. The thin film transistor according to claim 1, characterized in that: The thin film transistor also includes: an N-type doped amorphous silicon layer, a source and drain metal layer, an insulating protective layer, and an electrode layer, wherein the N-type doped amorphous silicon layer is formed on the active layer; the source and drain metal layer is formed on the N-type doped amorphous silicon layer; the insulating protective layer is formed on the source and drain metal layer; and the electrode layer is formed on the insulating protective layer.

6. A method for preparing a thin film transistor, characterized in that: The preparation method is used to prepare the thin film transistor according to claim 1, and the method comprises: forming a copper gate on a substrate; forming the first low-rate deposited gate insulating layer on the copper gate and the substrate at a first rate; forming the high-speed deposited gate insulating layer on the first low-speed deposited gate insulating layer at a third rate; forming the second low-speed deposited gate insulating layer on the high-speed deposited gate insulating layer at the first speed; forming the medium-speed deposited gate insulating layer on the second low-speed deposited gate insulating layer at a second rate; forming the third low-speed deposited gate insulating layer on the medium-speed deposited gate insulating layer at the first speed; forming an active layer on the insulating layer group; forming an N-type doped amorphous silicon layer on the active layer; forming a source-drain metal layer on the N-type doped amorphous silicon layer; Etching the source and drain metal layer, the N-type doped amorphous silicon layer and the active layer to obtain a source and a drain; wherein the first rate is less than the second rate, and the second rate is less than the third rate; The method further comprises: forming an insulating protection layer on the source and drain metal layer; An electrode layer is formed on the insulating protection layer.

7. An array substrate, characterized in that: The array substrate comprises a glass substrate, a thin film transistor and a pixel electrode disposed on the glass substrate, wherein the thin film transistor is the thin film transistor according to any one of claims 1 to 5.

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