Printed circuit board

Abstract

The present disclosure relates to a printed circuit board including: an interconnection bridge including an insulating material, a plurality of conductive pattern layers respectively disposed on or in the insulating material, and a conductive pillar disposed on the insulating material; a first insulating layer having the interconnection bridge embedded therein and having a recess exposing the conductive pillar; and a first wiring layer disposed on the first insulating layer and including a first pad pattern connected to an exposed portion of the conductive pillar exposed by the recess.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0102186 filed on August 4, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] With the rapid increase in the number of CPU cores and GPU cores in server products, die split technology, which can effectively increase the number of cores, has become increasingly common. In addition, with the increasing demand for packages including high-bandwidth memory (HBM), technology for connecting die-to-die with microcircuit line widths is needed. To meet these technical requirements, technology using silicon interposers has been developed, but commercialization has been limited due to cost issues and complex assembly processes. In addition, technology has been developed for embedding silicon bridges in substrates, but due to bridge position deviations, via processing deviations, pad exposure deviations, etc., there are limitations in achieving high matching when embedding the bridge. Summary of the Invention

[0004] An aspect of the present disclosure is to provide a printed circuit board that can improve matching when an interconnection bridge is built in.

[0005] Another aspect of the present disclosure is to provide a printed circuit board that can be manufactured by a process that has little effect on thickness variation of interconnection bridges.

[0006] As one of the various solutions proposed in the present disclosure, a conductive pillar is raised on an interconnection bridge and covered with an insulating layer, and the insulating layer is scraped to expose a portion of the conductive pillar to form a recess, and then a conductive pad connected to the conductive pillar is formed in the recess.

[0007] For example, according to one aspect of the present disclosure, a printed circuit board may include: an interconnection bridge, including an insulating material, a plurality of conductive pattern layers respectively arranged on or in the insulating material, and a conductive pillar arranged on the insulating material; a first insulating layer, in which the interconnection bridge is embedded and has a recess that exposes the conductive pillar; and a first wiring layer, which is arranged on the first insulating layer and includes a first pad pattern, and the first pad pattern is connected to the exposed portion of the conductive pillar exposed by the recess.

[0008] For example, according to one aspect of the present disclosure, a printed circuit board may include: a first substrate unit including a plurality of first insulating layers, a plurality of first wiring layers disposed on or in the plurality of first insulating layers, and a plurality of first via layers respectively penetrating the plurality of first insulating layers; and a second substrate unit including a plurality of second insulating layers, a plurality of second wiring layers disposed on or in the plurality of second insulating layers, a plurality of second via layers respectively penetrating the plurality of second insulating layers, and a plurality of conductive pillars disposed on an uppermost second insulating layer among the plurality of second insulating layers. The second substrate unit may be disposed in the first substrate unit, an average pitch of wiring of at least one of the plurality of second wiring layers may be smaller than an average pitch of wiring of at least one of the plurality of first wiring layers, and at least one of the plurality of first insulating layers may have a step region exposing a portion of each of the plurality of conductive pillars.

[0009] For example, according to one aspect of the present disclosure, a printed circuit board may include: an interconnection bridge, including an insulating material, a plurality of conductive pattern layers respectively arranged on or in the insulating material, and a conductive column arranged on the upper surface of the insulating material; a first insulating layer, so that the interconnection bridge is embedded and in contact with at least a portion of the upper surface of the insulating material; a first wiring layer, arranged on the first insulating layer and including a first pad pattern in contact with the conductive column; a second wiring layer, arranged in the first insulating layer; and a first via layer, penetrating the first insulating layer and connecting the first wiring layer and the second wiring layer.

[0010] One effect of the present disclosure is to provide a printed circuit board that can improve matching when an interconnection bridge is built in.

[0011] Another effect of the present disclosure is to provide a printed circuit board that can be manufactured by a process that has little influence on thickness variation of interconnection bridges. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram schematically illustrating an example of an electronic device system; Figure 2 is a perspective view schematically showing an example of an electronic device; Figure 3 is a cross-sectional view schematically showing a state in which a BGA package is mounted on a mainboard of an electronic device; Figure 4 is a cross-sectional view schematically showing a state where a silicon interposer package is mounted on a mainboard; Figure 5 is a cross-sectional view schematically showing a state in which an organic interposer package is mounted on a main board; Figure 6 is a cross-sectional view schematically showing an example of a printed circuit board; Figure 7 is a schematic cross-sectional view showing an example of an interconnection bridge; Figure 8A It is schematically shown Figure 6 An enlarged cross-sectional view of an example of region A; Figure 8B It is schematically shown Figure 6 An enlarged cross-sectional view of another example of region A; 9A to 9H is a process diagram schematically showing an example of manufacturing a printed circuit board; Figure 10 is a cross-sectional view schematically showing a modified example of a printed circuit board; Figure 11 is a cross-sectional view schematically showing another example of a printed circuit board; Figure 12 is a schematic cross-sectional view of another example of an interconnect bridge; Figure 13 is a cross-sectional view schematically showing another example of a printed circuit board; Figure 14 is a schematic cross-sectional view of another example of an interconnect bridge; Figure 15 is a cross-sectional view schematically showing another example of a printed circuit board; Figure 16 is a schematic cross-sectional view of another example of an interconnect bridge; Figure 17 is a cross-sectional view schematically showing another example of a printed circuit board; Figure 18 is a schematic cross-sectional view of another example of an interconnect bridge; Figure 19 is a schematic cross-sectional view of another example of a printed circuit board; Figure 20 is a schematic cross-sectional view of another example of an interconnect bridge; Figure 21 is a cross-sectional view schematically showing another example of a printed circuit board; and Figure 22 is a schematic cross-sectional view of another example of an interconnect bridge. DETAILED DESCRIPTION

[0013] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes and sizes of elements may be exaggerated or reduced for clearer description.

[0014] electronic devices Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0015] Reference Figure 1 The electronic device 1000 includes a motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the motherboard 1010. These components are also connected to other electronic components described below via various signal lines 1090.

[0016] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs) and application-specific integrated circuits (ASICs). However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be connected to each other. Chip-related components 1020 may be in the form of a package that includes the aforementioned chips and / or electronic components.

[0017] The network-related components 1030 may include components that are compatible with or communicate according to protocols such as: Wireless Fidelity (Wi-Fi) (such as the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High-Speed ​​Packet Access Plus (HSPA+), High-Speed ​​Downlink Packet Access Plus (HSDPA+), High-Speed ​​Uplink Packet Access Plus (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), third generation mobile communication technology (3G) protocols, fourth generation mobile communication technology (4G) protocols, and fifth generation mobile communication technology (5G) protocols, as well as any other wireless standards or protocols and wired standards or protocols designated hereafter. However, the network-related component 1030 is not limited thereto and may also include components compatible with or communicating according to various other wireless standards or protocols or wired standards or protocols. Furthermore, the network-related component 1030 may be connected to the chip-related component 1020.

[0018] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), and the like. However, other components are not limited thereto and may also include passive components in the form of chip components for various other purposes. Furthermore, other components 1040 may be connected to each other along with chip-related components 1020 and / or network-related components 1030.

[0019] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto and may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard drive), a compact disc (CD) drive, a digital versatile disc (DVD) drive, and the like. Furthermore, depending on the type of electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0020] The electronic device 1000 may be a smartphone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, or an automotive component. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0021] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0022] Reference Figure 2 The electronic device may be, for example, a smartphone 1100. A mainboard 1110 may be housed in smartphone 1100, and electronic components 1120 may be physically and / or electrically connected to mainboard 1110. Furthermore, other electronic components (such as a camera module 1130 and / or a speaker 1140) that may or may not be physically and / or electrically connected to mainboard 1110 may be housed in smartphone 1100. Some of electronic components 1120 may be the aforementioned chip-related components, such as component package 1121, but the present disclosure is not limited thereto. Component package 1121 may be in the form of a printed circuit board on which electronic components (including active and / or passive components) are surface-mounted. Alternatively, component package 1121 may be in the form of a printed circuit board in which the electronic components (including active and / or passive components) are embedded. On the other hand, the electronic device is not necessarily limited to smartphone 1100 and may be other electronic devices as described above.

[0023] Semiconductor package including interposer Typically, semiconductor chips contain numerous fine circuits. However, the semiconductor chips themselves may not be used as finished semiconductor products and may be damaged by external physical or chemical impact. Therefore, the semiconductor chips themselves may not be usable, but may be packaged and used in electronic devices, etc.

[0024] Semiconductor packaging is necessary because of the difference in circuit width between the semiconductor chip and the mainboard of an electronic device, which is crucial for electrical connection. Specifically, the size of the semiconductor chip's connection pads and the spacing between them are very precise, but the size of the component mounting pads on the mainboard used in electronic devices and the spacing between them are significantly larger than the size of the semiconductor chip's connection pads and the spacing between them. Therefore, it can be difficult to directly mount the semiconductor chip on the mainboard, necessitating packaging technology to mitigate the difference in circuit width between the semiconductor chip and the mainboard.

[0025] Hereinafter, a semiconductor package including an interposer manufactured using the packaging technology will be described in more detail with reference to the accompanying drawings.

[0026] Figure 3 is a cross-sectional view schematically showing a state in which a BGA package is mounted on a main board of an electronic device.

[0027] Semiconductor chips, such as those provided with graphics processing units (GPUs) and / or application-specific integrated circuits, are very expensive and therefore may need to be packaged with a high yield. To this end, a ball grid array (BGA) substrate 2210 capable of redistributing thousands to millions of connection pads may be prepared before mounting the semiconductor chips. Expensive semiconductor chips such as GPUs 2220 may be mounted and packaged on BGA substrate 2210 using surface mount technology (SMT), and then mounted on mainboard 2110. Alternatively, BGA substrate 2210 may include a flip-chip BGA (FCBGA) substrate.

[0028] Furthermore, in the case of the GPU 2220, it may be necessary to significantly reduce the signal path to a memory such as a high-bandwidth memory (HBM), and for this purpose, typically, a semiconductor chip such as the HBM 2240 is mounted on the interposer 2230 and packaged, and the semiconductor chips are stacked in a package-on-package format and used on the package mounted with the GPU 2220. However, in this case, the thickness of the device may increase significantly, and there may be limitations in reducing the signal path.

[0029] Figure 4 is a cross-sectional view schematically showing a state in which a silicon interposer package is mounted on a mainboard.

[0030] To address the aforementioned issues, a semiconductor package 2310 including a silicon interposer can be manufactured using interposer technology, which involves mounting a first semiconductor chip, such as a GPU 2220, and a second semiconductor chip, such as an HBM 2240, side by side on a surface of a silicon interposer 2250 and encapsulating the first and second semiconductor chips. In this case, the GPU 2220 and the HBM 2240, each having thousands to millions of connection pads, can be redistributed via the silicon interposer 2250, and the GPU 2220 and the HBM 2240 can be electrically connected to each other via a significantly reduced path. Furthermore, by redistributing the semiconductor package 2310 including a silicon interposer by remounting it on a BGA substrate 2210 or the like, the semiconductor package can be mounted on the mainboard 2110.

[0031] However, in the case of the silicon interposer 2250 , it may be difficult to form through silicon vias (TSVs), and the manufacturing cost of the silicon interposer is also high, and thus, it may be difficult to implement a semiconductor package having a large area at low cost.

[0032] Figure 5 is a cross-sectional view schematically showing a state in which an organic interposer package is mounted on a main board.

[0033] To address the aforementioned issues, an organic interposer 2260 can be used in place of the silicon interposer 2250. For example, a semiconductor package 2320 including an organic interposer can be manufactured using interposer technology that mounts a first semiconductor chip, such as a GPU 2220, and a second semiconductor chip, such as an HBM 2240, side by side on the surface of the organic interposer 2260 and packages the first and second semiconductor chips. In this case, the GPU 2220 and the HBM 2240, each having thousands to millions of connection pads, can be redistributed via the organic interposer 2260. Furthermore, the GPU 2220 and the HBM 2240 can be electrically connected to each other via a significantly reduced path. Furthermore, by re-mounting the semiconductor package 2320 including the organic interposer on a BGA substrate 2210 or the like and redistributing the semiconductor package, the semiconductor package can be mounted on the mainboard 2110. Consequently, a semiconductor package with a large area can be realized at low cost.

[0034] However, when the organic interposer 2260 is used, semiconductor chips (such as the GPU 2220 and the HBM 2240) must also be mounted on the organic interposer 2260 and then mounted on the BGA substrate 2210, so the process may be somewhat complicated and the packaging yield may be reduced.

[0035] Printed circuit board with built-in bridge Figure 6 is a cross-sectional view schematically showing an example of a printed circuit board.

[0036] Figure 7 is a schematic cross-sectional view illustrating an example of an interconnection bridge.

[0037] Referring to the drawings, a printed circuit board 100A according to an example embodiment may include an interconnection bridge 150A, a first insulating layer 111, and a first wiring layer 121. The interconnection bridge 150A includes an insulating material 151, a plurality of conductive pattern layers 152 disposed in or on the insulating material 151, and a conductive pillar 154 disposed on the insulating material 151. The first insulating layer 111 embeds the interconnection bridge 150A and has a recess R exposing a portion of the conductive pillar 154. The first wiring layer 121 is disposed on the first insulating layer 111 and includes a first pad pattern P1. The first connection pad P1 is connected to the exposed portion of the conductive pillar 154 exposed by the recess R. Here, the exposure of the conductive pillar 154 may be determined based on the first insulating layer 111. For example, exposure may refer to exposure from the first insulating layer 111. If desired, the first wiring layer 121 may further include a second pad pattern P2 disposed in an area of ​​the first insulating layer 111 other than the recess R and spaced apart from the conductive pillar 154.

[0038] As described above, in the printed circuit board 100A according to the example embodiment, the interconnect bridge 150A may include a conductive pillar 154 that is relatively narrower and taller than typical pads. Because the first pad pattern P1 connected thereto is relatively wide, sufficient exposure tolerance and / or alignment tolerance can be ensured. Furthermore, after the interconnect bridge 150A is embedded, the conductive pillar 154 can be directly connected to the first pad pattern P1 without forming a via, which can further improve matching. Furthermore, because a portion of the conductive pillar 154 can be exposed through the recess R, the above-described structure and its effects can be more easily achieved and have little effect on thickness variations in the first insulating layer 111 and / or the interconnect bridge 150A. Consequently, the process window can be wider and more conducive to mass production. Furthermore, the difficulty of the manufacturing process can be reduced.

[0039] If necessary, the printed circuit board 100A according to an example embodiment may further include: a second wiring layer 122, which is disposed in the first insulating layer 111; a first via layer 131, which penetrates the first insulating layer 111 and connects the first wiring layer 121 and the second wiring layer 122; the second insulating layer 112, which is disposed below the first insulating layer 111; a third wiring layer 123, which is disposed in the second insulating layer 112; a second via layer 132, which penetrates the second insulating layer 112 and connects the second wiring layer 122 and the third wiring layer 123; the third insulating layer 113, which is disposed on the first insulating layer 111 and covers the first wiring layer 121; a fourth wiring layer 124, which is disposed on the third insulating layer 113; and a third via layer 133, which penetrates the third insulating layer 113 and connects the first wiring layer 121 and the fourth wiring layer 124.

[0040] In this manner, printed circuit board 100A may have an embedded trace substrate (ETS) structure. However, the present disclosure is not limited thereto, and printed circuit board 100A may be a core-type board including a core insulating layer. For example, the portion shown in the drawings may represent the stacked upper portion of a core-type substrate. Printed circuit board 100A may be a BGA board or an FCBGA board, but the present disclosure is not limited thereto.

[0041] In addition, the recess R may be tapered so that the width of its upper portion is greater than the width of its lower portion in cross section. The upper surface of the first insulating layer 111 may have a stepped portion due to the recess R. For example, the first insulating layer 111 may have a stepped region due to the recess R. The first pad pattern P1 may be disposed in the stepped region, and the second pad pattern P2 may be disposed outside the stepped region. Therefore, the upper surface of the first pad pattern P1 and the upper surface of the second pad pattern P2 may not be on the same plane, and the lower surface of the first pad pattern P1 and the lower surface of the second pad pattern P2 may not be on the same plane. In addition, the stepped portion of the first insulating layer 111 caused by the recess R can be restored by the third insulating layer 113. For example, the upper surface of the third insulating layer 113 may be substantially flat.

[0042] Hereinafter, components of a printed circuit board 100A according to an example will be described in more detail with reference to the accompanying drawings.

[0043] Each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include an insulating material. Examples of insulating materials include thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, materials in which these resins are mixed with inorganic fillers such as silica, or resins impregnated with inorganic fillers into a core material such as glass fiber (e.g., glass fabric, exemplified by glass cloth), or organic insulating materials such as Ajinomoto built-up film (ABF) and prepreg, but the present disclosure is not limited thereto. As a non-limiting example, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include substantially the same material, but the present disclosure is not limited thereto. Here, the substantially the same material may be an insulating material with the same brand name. Solder resist (SR) may be used as the material for the third insulating layer 113. For example, the third insulating layer 113 may be a solder resist layer.

[0044] Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a metal material. Examples of metal materials include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include an electroless plating layer (e.g., a chemical copper plating layer) and / or an electrolytic plating layer (e.g., an electrolytic copper plating layer). If desired, the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a sputtered layer. If desired, the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include copper foil. The first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may perform various functions depending on the design of each corresponding layer. For example, the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a ground pattern, a power pattern, and a signal pattern. Here, the signal pattern may include various signal (e.g., data signal) patterns in addition to the ground pattern, the power pattern, etc. These patterns may each include a line pattern, a plane pattern, and / or a pad pattern. For example, the first wiring layer 121 may include a first pad pattern P1 and a second pad pattern P2.

[0045] Each of the first via layer 131, the second via layer 132, and the third via layer 133 may include a metal material. Examples of the metal material include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the first via layer 131, the second via layer 132, and the third via layer 133 may include an electroless plating layer (e.g., an electroless copper plating layer) and / or an electrolytic plating layer (e.g., an electrolytic copper plating layer). If desired, the first via layer 131, the second via layer 132, and the third via layer 133 may include a sputtered layer. Each of the first via layer 131, the second via layer 132, and the third via layer 133 may include a filled-type via in which the via hole is filled with a metal material, but is not limited thereto and may be a conformal via in which the metal material is disposed along the wall of the via hole. Each of the first via layer 131, the second via layer 132, and the third via layer 133 may have a tapered shape in which its upper end is wider than its lower end in cross section. Each of the first via layer 131, the second via layer 132, and the third via layer 133 may perform various functions according to the design of each corresponding layer. For example, the first via layer 131, the second via layer 132, and the third via layer 133 may include ground vias, power vias, and signal vias. Here, the signal vias may include vias for transmitting various signals (e.g., data signals, etc.) in addition to ground vias, power vias, etc. Depending on the upper and lower connection types, the first via layer 131, the second via layer 132, and the third via layer 133 may include stacked vias and / or staggered vias.

[0046] Interconnect bridge 150A can be a silicon bridge manufactured by using silicon dioxide as an insulator and forming wiring through a deposition process, or it can be an organic bridge manufactured by using an organic insulating material as an insulator and forming wiring through a plating process. Interconnect bridge 150A is preferably an organic bridge, and in this case, reliability issues caused by coefficient of thermal expansion (CTE) mismatch may be less likely to occur. In addition, the process difficulty and cost of manufacturing interconnect bridge 150A can be reduced. In addition, interconnect bridge 150A can have an ETS structure, such as a coreless substrate structure. In this way, when interconnect bridge 150A is formed in the form of a coreless substrate, a wiring design with a finer pitch can be achieved. In addition, interconnect bridge 150A can be manufactured at a lower cost than a silicon bridge, and its manufacturing process can be simpler. The organic bridge can be a high-density circuit board.

[0047] Insulating material 151 may include an organic insulating material, such as a photosensitive insulating material (e.g., photosensitive dielectric (PID)). Using a photosensitive insulating material (e.g., PID) as insulating material 151 minimizes the thickness of insulating material 151 and allows for the formation of optical path holes, thereby enabling the design of multiple conductive pattern layers 152 at a high density. However, the material is not limited thereto, and other organic insulating materials such as ABF may be used. If desired, an inorganic insulating material such as silicon may be included. Insulating material 151 may include multiple insulating layers, with no particular limitation on the number of layers. The boundaries between the multiple insulating layers may be distinguishable or easily distinguishable.

[0048] The multiple conductive pattern layers 152 can provide chip-to-chip wiring paths. The multiple conductive pattern layers 152 can include multiple layers, and the number of layers is not particularly limited. The multiple conductive pattern layers 152 can perform various functions depending on the design of the corresponding layer and may include at least a signal pattern. Each of the multiple conductive pattern layers 152 can include a line pattern, a plane pattern, and / or a pad pattern. Each of the multiple conductive pattern layers 152 can include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the multiple conductive pattern layers 152 can include an electroless plating layer (e.g., a chemical copper plating layer) and / or an electrolytic plating layer (e.g., an electrolytic copper plating layer). If desired, the multiple conductive pattern layers 152 can include a sputtered layer.

[0049] The plurality of conductive pattern layers 152 may have a higher circuit density than the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124. In other words, the plurality of conductive pattern layers 152 may include higher-density circuits. For example, the average pitch of the wiring included in at least one of the plurality of conductive pattern layers 152 may be smaller than the average pitch of the wiring included in at least one of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124. Furthermore, the average interlayer insulation distance between the plurality of conductive pattern layers 152 may be smaller than the average interlayer insulation distance between the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124.

[0050] The plurality of conductive pattern layers 152 may include two high-density wiring layers and one ground layer, and a line pattern for signal transmission may be omitted in the ground layer, but the present disclosure is not limited thereto. The high-density wiring layer may have only one design rule, for example, a line / space (L / S) of 2 μm / 2 μm or 1 μm / 1 μm, but the present disclosure is not limited thereto.

[0051] The multiple conductive pattern layers 152 can be electrically connected to each other via multiple conductive via layers 153. Each of the multiple conductive via layers 153 may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the multiple conductive via layers 153 may include an electroless plating layer (e.g., a chemical copper plating layer) and / or an electrolytic plating layer (e.g., an electrolytic copper plating layer). If desired, the multiple conductive via layers 153 may include a sputtered layer. Each of the multiple conductive via layers 153 may have a filled-type via in which a via hole is filled with a metal material, but is not limited thereto. It may also be a conformal via in which the metal material is disposed along the wall of the via hole. Each of the multiple conductive via layers 153 may have a tapered cross-section with its upper end wider than its lower end. Each of the multiple conductive via layers 153 may perform various functions depending on the design of each corresponding layer. For example, the plurality of conductive via layers 153 may include ground vias, power vias, and signal vias. Here, the signal vias may include vias for transmitting various signals (e.g., data signals, etc.) in addition to ground vias and power vias. Depending on the type of up-and-down connection, the plurality of conductive via layers 153 may include stacked vias and / or staggered vias.

[0052] The conductive pillars 154 may have a high aspect ratio. For example, the aspect ratio may be greater than 1. The conductive pillars 154 may perform various functions, such as signal pillars, ground pillars, power pillars, etc. The conductive pillars 154 may include at least a signal pillar. The conductive pillars 154 may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The conductive pillars 154 may be formed using a plating process and may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. If desired, the conductive pillars 154 may include a sputtered layer. The conductive pillars 154 may be connected to the uppermost conductive pattern layer 152 of the plurality of conductive pattern layers 152 via the uppermost conductive via layer 153 of the plurality of conductive via layers 153. A plurality of conductive pillars 154 may be provided.

[0053] The interconnection bridge 150A may be attached to the upper surface of the second insulating layer 112 by an adhesive 155. The adhesive 155 may include a known adhesive material such as an epoxy-based adhesive material, but the material is not particularly limited thereto.

[0054] Figure 8A It is schematically shown Figure 6 An enlarged cross-sectional view of an example of region A.

[0055] Reference Figure 8AConductive pillar 154 may be formed so that a portion thereof is embedded in first insulating layer 111, while another portion thereof protrudes above first insulating layer 111. For example, the upper surface of conductive pillar 154 may have a stepped portion relative to the upper surface of first insulating layer 111. In this case, the contact area with first pad pattern P1 can be increased, thereby allowing for better adhesion. First pad pattern P1 may be disposed on the upper surface of first insulating layer 111 within recess R and may cover the other portion (i.e., the protruding portion) of conductive pillar 154. First pad pattern P1 may include a first metal layer M1 and a second metal layer M2. The first metal layer M1 covers the upper surface of first insulating layer 111 and the upper and side surfaces of the protruding portion of conductive pillar 154 with a substantially constant thickness. The second metal layer M2 is disposed on the first metal layer M1 and has an average thickness thicker than that of the first metal layer M1. The first metal layer M1 may be a seed layer formed by electroless plating and / or sputtering. The second metal layer M2 may be a plated layer formed by electrolytic plating.

[0056] Figure 8B It is schematically shown Figure 6 An enlarged cross-sectional view of another example of region A.

[0057] Reference Figure 8B , the conductive pillar 154 may be embedded in the first insulating layer 111, and its upper surface may be exposed from the upper surface of the first insulating layer 111. For example, the upper surface of the conductive pillar 154 may be substantially coplanar with the upper surface of the first insulating layer 111. In this case, the conductive pillar 154 can provide a flatter surface. The first pad pattern P1 may be disposed on the upper surface of the first insulating layer 111 and located in the recess R, and may cover the exposed upper surface of the conductive pillar 154. The first pad pattern P1 may include a first metal layer M1 and a second metal layer M2, the first metal layer M1 covering the upper surface of the first insulating layer 111 and the exposed upper surface of the conductive pillar 154 with a substantially constant thickness, and the second metal layer M2 being disposed on the first metal layer M1, and having an average thickness thicker than the average thickness of the first metal layer M1. The first metal layer M1 may be a seed layer formed by electroless plating and / or sputtering. The second metal layer M2 may be a plated layer formed by electrolytic plating.

[0058] 9A to 9H is a process diagram schematically showing an example of manufacturing a printed circuit board.

[0059] Reference Figure 9AThe second insulating layer 112, the second and third wiring layers 122 and 123, and the second via layer 132 are formed using a carrier substrate through a buildup process. Via holes for forming the second via layer 132 can be formed using laser processing, mechanical drilling, or the like. The second and third wiring layers 122 and 123, as well as the second via layer 132, can be formed using circuit formation processes such as additive process (AP), semi-AP (SAP), modified SAP (MSAP), and via sealing (TT). The second insulating layer 112 can be formed using a lamination process such as ABF.

[0060] Reference Figure 9B , interconnect bridge 150A is attached using adhesive 155. Interconnect bridge 150A can be manufactured using a substrate process. For example, interconnect bridge 150A can be manufactured by forming multiple conductive pattern layers 152 and multiple conductive via layers 153 on insulating material 151 using a carrier substrate using a buildup process, and then forming multiple conductive pillars 154 on insulating material 151 using a plating process using a resist. Among multiple conductive via layers 153, the uppermost conductive via layer 153 can be formed together with multiple conductive pillars 154.

[0061] Reference Figure 9C The first insulating layer 111 is stacked on the second insulating layer 112 so that the interconnection bridge 150A is embedded. For example, the first insulating layer 111 may be formed by performing a process such as stacking ABF on the second insulating layer 112 .

[0062] Reference Figure 9D A recess R is formed in the first insulating layer 111 to expose a portion of the conductive pillar 154. The recess R can be formed by a local scraping process or a local thinning process. Plasma etching, wet etching, dry etching, laser processing, sandblasting, etc. can be used in the scraping process or the thinning process. The recess R can form a step region on the upper side of the first insulating layer 111.

[0063] Reference Figure 9E , a via hole v is formed in the first insulating layer 111. The via hole v can be formed by laser processing, mechanical drilling, or the like.

[0064] Reference Figure 9F , a first wiring layer 121 including a first pad pattern P1 and a second pad pattern P2 is formed on the first insulating layer 111. In addition, a first via layer 131 is formed in the via hole v. The first wiring layer 121 and the first via layer 131 can be formed using a circuit formation process such as AP, SAP, MSAP, TT process, etc. The first pad pattern P1 can cover and be connected to the exposed conductive pillar 154.

[0065] Reference Figure 9G, a third insulating layer 113 may be stacked on the first insulating layer 111. The stepped portion may be restored by the third insulating layer 113. For example, the third insulating layer 113 may be formed by performing an ABF or SR lamination process on the first insulating layer 111. Alternatively, the third insulating layer 113 may be formed by applying an SR material and curing it.

[0066] Reference Figure 9H , a fourth wiring layer 124 and a third via layer 133 are formed on the third insulating layer 113. Via holes for forming the third via layer 133 can be formed using laser processing, mechanical drilling, or the like. The fourth wiring layer 124 and the third via layer 133 can be formed using a circuit forming process such as AP, SAP, MSAP, or TT process. The printed circuit board 100A according to the aforementioned exemplary embodiment can be manufactured through a series of processes.

[0067] Figure 10 is a cross-sectional view schematically showing a modified example of the printed circuit board.

[0068] Reference Figure 10 A printed circuit board 500A according to a modified example may include a first substrate unit 200, a second substrate unit 150A disposed within the first substrate unit 200, and first and second semiconductor chips 310 and 320, respectively disposed on the first substrate unit 200 and connected to each other via the second substrate unit 150A. The first substrate unit 200 may be a multi-layer core substrate and may include a plurality of first insulating layers 211, 212, 213, 214, and 215, a plurality of first wiring layers 221, 222, and 223, and a plurality of first via layers 231, 232, 233, and 234. The second substrate unit 150A may be the aforementioned interconnect bridge 150A and may include a plurality of second insulating layers 151, a plurality of second wiring layers 152, a plurality of second via layers 153, and a plurality of conductive pillars 154. The second substrate unit 150A may be attached to the first substrate unit 200 via an adhesive 155. The printed circuit board 100A according to the aforementioned exemplary embodiment may be partially applied to the printed circuit board 500A according to the modified example. For example, a printed circuit board 500A according to a modified example may include the printed circuit board 100A according to the aforementioned example embodiment as a portion of a package substrate, for example, as a portion of an upper buildup region in a core substrate, and may be in the form of a semiconductor package on which a first semiconductor chip 310 and a second semiconductor chip 320 are mounted. The first semiconductor chip 310 and the second semiconductor chip 320 may be connected to each other through at least one second wiring layer 152 and at least one conductive pillar 154.

[0069] Each of the plurality of first insulating layers 211, 212, 213, 214, and 215 may include an insulating material. The insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, a material in which these resins are mixed with an inorganic filler such as silica, or a resin impregnated with an inorganic filler into a core material such as glass fiber (e.g., glass fabric, exemplified by glass cloth). For example, organic insulating materials such as copper-clad laminate (CCL), Ajinomoto build-up film (ABF), and prepreg may be used, but the present disclosure is not limited thereto. As a non-limiting example, the first-first insulating layer 211 may include a CCL as the core layer, and the plurality of first-second insulating layers 212 and the plurality of first-third insulating layers 213 may include ABF or prepreg as the build-up layers, but the present disclosure is not limited thereto. The first-fourth insulating layers 214 and the first-fifth insulating layers 215 may include ABF or solder resist as the outermost layers, but the present disclosure is not limited thereto. If necessary, the first-first insulating layer 211 may include an insulating material other than the organic insulating material, such as a glass plate.

[0070] Each of the plurality of first wiring layers 221, 222, and 223 may comprise a metal material. Examples of the metal material include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the plurality of first wiring layers 221, 222, and 223 may comprise an electroless plating layer (e.g., an electroless copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. A sputtered layer may be formed as the electroless plating layer instead of the electroless copper plating layer, or the plurality of first wiring layers 221, 222, and 223 may comprise both a sputtered layer and an electroless copper plating layer. If desired, the plurality of first wiring layers 221, 222, and 223 may further comprise copper foil. The plurality of first wiring layers 221, 222, and 223 may perform various functions depending on the design of each corresponding layer. For example, the plurality of first wiring layers 221, 222, and 223 may comprise a ground pattern, a power pattern, and a signal pattern. These patterns may include line patterns, plane patterns and / or pad patterns, respectively.

[0071] Each of the plurality of first via layers 231, 232, 233, and 234 may comprise a metal material. Examples of the metal material include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the plurality of first via layers 231, 232, 233, and 234 may perform various functions depending on the design. For example, the plurality of first via layers 231, 232, 233, and 234 may include ground vias, power vias, and signal vias. Each of the plurality of first via layers 231, 232, 233, and 234 may comprise an electroless plating layer (e.g., an electroless copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. A sputtered layer may be formed as the electroless plating layer instead of the electroless copper plating layer, or the plurality of first via layers 231, 232, 233, and 234 may comprise both a sputtered layer and an electroless copper plating layer. The first-first via layer 231 may include a through-via. The through-via may include a metal layer formed on the wall surface of the via hole and / or a plug filled in the space between the metal layers. The through-via may have a cylindrical shape, but is not limited thereto, and may also have an hourglass shape. Each of the plurality of first-second via layers 232, the plurality of first-third via layers 233, and the first-fourth via layer 234 may include a microvia. The microvia may be a filled via that fills the via hole or a conformal via arranged along the wall surface of the via hole. The microvias may be arranged in a stacked and / or staggered manner. The microvia may have a tapered shape. The microvias of the plurality of first-second via layers 232 and the microvias of the plurality of first-third via layers 233 may have shapes that taper in opposite directions.

[0072] Each of the first semiconductor chip 310 and the second semiconductor chip 320 may include an integrated circuit (IC) die in which hundreds to millions of components are integrated into a single chip. In this case, the IC die may be a processor chip, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or an application processor (AP); a logic chip, such as a field programmable gate array (FPGA), an analog-to-digital converter, or an application-specific integrated circuit (ASIC), but the present disclosure is not limited thereto. The IC die may also be a memory chip, such as a volatile memory (e.g., DRAM, high-bandwidth memory (HBM)), a non-volatile memory (e.g., ROM, flash memory), or a different type of chip, such as a power management integrated circuit (PMIC). For example, the first semiconductor chip 310 may include a processor chip, such as a GPU, and the second semiconductor chip 320 may include a memory chip, such as an HBM. Alternatively, the first semiconductor chip 310 and the second semiconductor chip 320 may be separate logic chips, each having different cores, separated by die partitioning. However, the present disclosure is not limited thereto.

[0073] Each of the first semiconductor chip 310 and the second semiconductor chip 320 can be formed based on an active wafer. In this case, silicon (Si), germanium (Ge), or gallium arsenide (GaAs) can be used as the base material for forming each body. Various circuits can be formed in the body. Connection pads can be formed on each body, and the connection pads can include a conductive material such as aluminum (Al) or copper (Cu). The first semiconductor chip 310 and the second semiconductor chip 320 can be bare dies, in which case metal bumps can be provided on the connection pads. The first semiconductor chip 310 and the second semiconductor chip 320 can be packaged dies, in which case a redistribution layer can be additionally formed on the connection pads, and metal bumps can be provided on the redistribution layer. However, the present disclosure is not limited to this.

[0074] The first semiconductor chip 310 and the second semiconductor chip 320 can be connected to the first to third wiring layers 223 via a plurality of bumps 330. Each of the plurality of bumps 330 can be formed using a low-melting-point metal, for example, a solder such as tin (Sn)-aluminum (Al)-copper (Cu), but this is merely an example, and the material thereof is not particularly limited thereto. Each of the plurality of bumps 330 can be formed in multiple layers or a single layer. When the plurality of bumps 330 are formed in multiple layers, the plurality of bumps 330 may include copper pillars and solder, and when the plurality of bumps 330 are formed in a single layer, the plurality of bumps 330 may include tin-silver solder or copper, but the present disclosure is not limited thereto.

[0075] The other contents are basically the same as the above, so their redundant descriptions will be omitted.

[0076] Figure 11 is a cross-sectional view schematically showing another example of a printed circuit board.

[0077] Figure 12 is a schematic cross-sectional view of another example of an interconnect bridge.

[0078] Referring to the drawings, compared to the printed circuit board 100A according to the above-described example embodiment and the interconnection bridge 150A included therein, a printed circuit board 100B according to another example embodiment and the interconnection bridge 150B included therein may further include a protective material 156. For example, the interconnection bridge 150B may further include the protective material 156 disposed on the insulating material 151 and surrounding at least one of the plurality of conductive pillars 154. The protective material 156 may be disposed in a portion of the upper surface of the insulating material 151. The protective material 156 may surround the side surface of at least one of the plurality of conductive pillars 154 and expose a portion of the upper end of the conductive pillar 154. Before embedding the interconnection bridge 150B, the protective material 156 may be formed to completely cover the corresponding conductive pillar 154. After embedding the interconnection bridge 150B, a portion of the protective material 156 may be removed during the process of forming the recess R. The upper surface of the protective material 156 may be substantially coplanar with the upper surface of the first insulating layer 111 located in the recess R. For example, the protective material 156 may be planarized during the process of forming the recess R. The protective material 156 may include an insulating material. The insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material obtained by mixing these resins with an inorganic filler such as silica, for example, an organic insulating material such as ABF, but the present disclosure is not limited thereto. The protective material 156 may include an organic insulating material with high transparency. For example, the protective material 156 may have a relatively higher transparency than the insulating material 151 or the first and second insulating layers 111 and 112. As described above, the printed circuit board 100B according to another exemplary embodiment may surround the plurality of conductive pillars 154 with the protective material 156. This protects the conductive pillars 154 and increases the effective thickness of the interconnect bridge 150B. Furthermore, a flatter surface may be provided when the interconnect bridge 150B is installed. Furthermore, when the protective material 156 has high transparency, alignment and recognition during installation of the interconnect bridge 150B are facilitated, thereby improving the accuracy of the installation position. Therefore, when the interconnection bridge 150B is embedded, the matching degree can be improved.

[0079] The other contents are substantially the same as those described above. In addition, the structure of the printed circuit board 100B according to another exemplary embodiment can also be applied to the printed circuit board 500A according to the above-described modified example, and a detailed description thereof will be omitted.

[0080] Figure 13 is a cross-sectional view schematically showing another example of a printed circuit board.

[0081] Figure 14 is a schematic cross-sectional view of another example of an interconnect bridge.

[0082] Referring to the drawings, compared to the printed circuit board 100B and the interconnection bridge 150B included therein according to the aforementioned another exemplary embodiment, the printed circuit board 100C and the interconnection bridge 150C included therein according to another exemplary embodiment may further include an alignment mark 157. For example, the interconnection bridge 150C may further include an alignment mark 157 disposed on the insulating material 151 and spaced apart from the protective material 156. The alignment mark 157 may be disposed at substantially the same height as the plurality of conductive pillars 154. When the plurality of conductive pillars 154 are formed, the alignment mark 157 may be formed using the same material. For example, the alignment mark 157 may include the aforementioned metal material. The alignment mark 157 may be embedded in the first insulating layer 111, and if desired, a portion of the alignment mark 157 may be exposed through the recess R. As described above, in the printed circuit board 100C according to the another exemplary embodiment, the interconnection bridge 150C may include the alignment mark 157. Therefore, when installing the interconnection bridge 150C, alignment recognition may be facilitated, and the accuracy of the mounting position may be improved. Therefore, when the interconnection bridge 150C is embedded, the matching degree can be improved.

[0083] The other contents are substantially the same as those described above. In addition, the structure of the printed circuit board 100C according to another exemplary embodiment can also be applied to the printed circuit board 500A according to the above-described modified example, and a detailed description thereof will be omitted.

[0084] Figure 15 is a cross-sectional view schematically showing another example of a printed circuit board.

[0085] Figure 16 is a schematic cross-sectional view of another example of an interconnect bridge.

[0086] Referring to the drawings, compared to the printed circuit board 100A and the interconnection bridge 150A included therein according to the above-described exemplary embodiment, in a printed circuit board 100D and the interconnection bridge 150D included therein according to another exemplary embodiment, the uppermost conductive pattern layer 152 of the plurality of conductive pattern layers 152 may be disposed on the upper surface of the insulating material 151, and the uppermost conductive pattern layer 152 may include a conductive pad P3 connected to a conductive pillar 154 and a first ground pattern G1 spaced apart from the conductive pillar 154. As described above, if desired, the conductive pad P3 for the conductive pillar 154 may be further formed on the insulating material 151, and the first ground pattern G1 may be further formed in the remaining space. Therefore, the conductive pillar 154 can be formed more easily and at a higher height, and a more diverse design can be achieved.

[0087] The other contents are substantially the same as those described above. In addition, the structure of the printed circuit board 100D according to another exemplary embodiment can also be applied to the printed circuit board 500A according to the above-described modified example, and a detailed description thereof will be omitted.

[0088] Figure 17 is a cross-sectional view schematically showing another example of a printed circuit board.

[0089] Figure 18 is a schematic cross-sectional view of another example of an interconnect bridge.

[0090] Referring to the drawings, compared to the printed circuit board 100D according to the above-described another example and the interconnection bridge 150D included in the printed circuit board 100D according to another exemplary embodiment, the printed circuit board 100E according to another exemplary embodiment and the interconnection bridge 150E included in the printed circuit board 100E according to another exemplary embodiment may further include a protective material 156. For example, the interconnection bridge 150E may further include the protective material 156 disposed on the insulating material 151, surrounding at least one of the plurality of conductive pillars 154 and covering the conductive pad P3 connected thereto. In this manner, the printed circuit board 100E according to another exemplary embodiment may further include the protective material 156. Therefore, as described above, when the interconnection bridge 150E is embedded, various effects, such as improved matching, may be achieved.

[0091] The other contents are substantially the same as those described above. In addition, the structure of the printed circuit board 100E according to another exemplary embodiment can also be applied to the printed circuit board 500A according to the above-described modified example, and a detailed description thereof will be omitted.

[0092] Figure 19 is a schematic cross-sectional view of another example of a printed circuit board.

[0093] Figure 20 is a schematic cross-sectional view of another example of an interconnect bridge.

[0094] Referring to the drawings, compared to the printed circuit board 100E according to the aforementioned another example and the interconnection bridge 150E included therein according to the another example embodiment, the printed circuit board 100F according to the another example embodiment and the interconnection bridge 150F included therein according to the another example embodiment may selectively include a protective material 156. For example, the protective material 156 may surround some of the conductive pillars 154 and cover some of the conductive pads P3 connected thereto. In this manner, the printed circuit board 100F according to the another example embodiment may selectively include the protective material 156, further increasing design freedom.

[0095] The other contents are substantially the same as those described above. In addition, the structure of the printed circuit board 100F according to another exemplary embodiment can also be applied to the printed circuit board 500A according to the above-described modified example, and a detailed description thereof will be omitted.

[0096] Figure 21 is a cross-sectional view schematically showing another example of a printed circuit board.

[0097] Figure 22 is a schematic cross-sectional view of another example of an interconnect bridge.

[0098] Referring to the drawings, compared to the printed circuit board 100A and the interconnection bridge 150A included therein according to the aforementioned exemplary embodiment, in a printed circuit board 100G and an interconnection bridge 150G included therein according to another exemplary embodiment, the lowest conductive pattern layer 152 of the plurality of conductive pattern layers 152 of interconnection bridge 150G may be in contact with adhesive 155, and furthermore, the lowest conductive pattern layer 152 may include a second ground pattern G2. For example, from the lowest layer upward, the first and third layers may be ground layers, the second and fourth layers may be signal layers, and signal connection lines may not be provided in the ground layers. In this manner, the printed circuit board 100G according to another exemplary embodiment can achieve a more diverse design.

[0099] The other contents are substantially the same as those described above. In addition, the structure of the printed circuit board 100G according to another exemplary embodiment can also be applied to the printed circuit board 500A according to the above-described modified example, and a detailed description thereof will be omitted.

[0100] In the present disclosure, the thickness, width, length, depth, etc. can be measured based on a cross section obtained by polishing or cutting a printed circuit board using a scanning microscope or an optical microscope. The cut section can be a vertical cross section or a horizontal cross section, and each value can be measured based on the desired cut section. When the value is not constant, the value can be determined as the average value of the values ​​measured at any five random points. The width of the upper end and / or lower end of the through hole or recess can be measured on a cross section of the substrate cut in the thickness direction. The depth of the through hole or recess can be measured as the distance from the upper end to the lower end of each object on a cross section of the central axis of each object cut in the thickness direction of the substrate.

[0101] In the present disclosure, the pitch can be measured by capturing a cut cross section of the printed circuit board with a scanning microscope or an optical microscope, and the average pitch can be the average value of the pitches between wirings measured at any five points. The interlayer insulation distance can also be measured by capturing a cut cross section of the printed circuit board with a scanning microscope or an optical microscope, and the average interlayer insulation distance can be the average value of the insulation distances between adjacent wirings or redistribution portions measured at any five points.

[0102] In the present disclosure, transparency can be measured by grinding or cutting a printed circuit board in the length or width direction to the depth at which the interconnect bridges are exposed, obtaining a cross section, and then observing the cross section using a scanning microscope or an optical microscope such as an Olympus optical microscope (1000x magnification). Alternatively, transparency can be determined by transmittance and haze values, which can be measured using a PerkinElmer Lambda 1050 UV-Vis spectrometer. Transmittance can also be determined by component analysis, identifying components and then recombining them to obtain transmittance. Transparency can also be determined by reflectance.

[0103] In the present disclosure, the expression "cover" may include the case of covering at least a portion as well as the case of covering the entirety, and may also include the case of direct covering as well as the case of indirect covering. In addition, the expression "fill" may include not only the case of complete filling but also the case of substantial filling, for example, the case of the presence of some holes or gaps.

[0104] In the present disclosure, "substantially" can be defined to encompass process errors or positional deviations generated during the manufacturing process, as well as errors during measurement. For example, "substantially coplanar" includes not only the situation where components are completely on the same plane, but also the situation where components are substantially on the same plane. Furthermore, "substantially identical materials" includes not only the situation where the composition and degree of curing of the materials are exactly the same, but also the situation where they are substantially identical.

[0105] In the present disclosure, the meaning of "cross section" may refer to the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when the object is viewed from the side. In addition, the meaning of "plane" may refer to the plane shape when an object is cut horizontally, or the plane shape when the object is viewed from a top or bottom perspective.

[0106] In the present disclosure, "lower" in "lower side", "lower portion", and "lower surface" refers to a downward direction relative to a cross section of the drawings, and "upper" in "upper side", "upper portion", and "upper surface" refers to the opposite direction. However, this is a direction defined for the convenience of explanation, and the scope of the claims is not particularly limited by the description of such a direction, and the concepts of "upper" and "lower" may be changed at any time.

[0107] In the present disclosure, the concept of "connection" includes not only direct connection but also indirect connection through an adhesive layer, etc. In addition, "electrical connection" is a concept that includes both physical connection and non-physical connection. In addition, expressions such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

[0108] The term "exemplary embodiment" used in this disclosure does not necessarily mean the same embodiment, and is provided to illustrate different unique features. However, the exemplary embodiments presented above do not exclude implementation in combination with features of other exemplary embodiments. For example, even if matters described in a particular exemplary embodiment are not described in other exemplary embodiments, they can be understood as descriptions related to other exemplary embodiments unless there is a statement that is contrary or contradictory to the matters in other exemplary embodiments.

[0109] The terms used in the present disclosure are only used to describe example embodiments and are not intended to limit the present disclosure. In this case, unless they are clearly indicated as different in context, a singular expression includes a plural expression.

[0110] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: An interconnection bridge, comprising an insulating material, a plurality of conductive pattern layers respectively disposed on or in the insulating material, and a conductive column disposed on the insulating material; a first insulating layer, embedding the interconnection bridge and having a recess exposing the conductive pillar; as well as A first wiring layer is disposed on the first insulating layer and includes a first pad pattern connected to an exposed portion of the conductive pillar exposed through the recess.

2. The printed circuit board according to claim 1, wherein: The first wiring layer further includes a second pad pattern disposed in a region of the first insulating layer excluding the recess and spaced apart from the conductive pillar, and An upper surface of the first land pattern and an upper surface of the second land pattern are not on the same plane.

3. The printed circuit board according to claim 1, wherein: A portion of the conductive pillar is embedded in the first insulating layer, and another portion of the conductive pillar protrudes from an upper surface of the first insulating layer.

4. The printed circuit board according to claim 3, wherein: The first pad pattern is disposed on the upper surface of the first insulating layer and in the recess to cover the other portion of the conductive pillar.

5. The printed circuit board according to claim 4, wherein: The first pad pattern comprises: a first metal layer covering the upper surface of the first insulating layer and the upper surface and side surfaces of the other portion of the conductive pillar with a constant thickness; and The second metal layer is disposed on the first metal layer and has an average thickness thicker than that of the first metal layer.

6. The printed circuit board according to claim 1, wherein The conductive pillar is embedded in the first insulating layer and exposed from an upper surface of the first insulating layer such that an upper surface of the conductive pillar is coplanar with the upper surface of the first insulating layer.

7. The printed circuit board according to claim 6, wherein: The first pad pattern is disposed on the upper surface of the first insulating layer and in the recess to cover an exposed upper surface of the conductive pillar.

8. The printed circuit board according to claim 7, wherein: The first pad pattern comprises: a first metal layer covering the upper surface of the first insulating layer and the exposed upper surface of the conductive pillar with a constant thickness; and The second metal layer is disposed on the first metal layer and has an average thickness thicker than that of the first metal layer.

9. The printed circuit board according to claim 1, wherein: The interconnection bridge includes a plurality of the conductive pillars, The interconnection bridge further includes a protection material disposed on the insulating material and surrounding at least one conductive pillar of the plurality of conductive pillars, and The protective material is disposed in a partial region on the upper surface of the insulating material.

10. The printed circuit board according to claim 9, wherein: The interconnection bridge further includes an alignment mark disposed on the insulating material and spaced apart from the protection material.

11. The printed circuit board according to claim 1, wherein: A conductive pattern layer disposed on the uppermost side among the plurality of conductive pattern layers is disposed on the upper surface of the insulating material, and The conductive pattern layer disposed at the uppermost side includes a conductive pad connected to the conductive pillar and a first ground pattern spaced apart from the conductive pillar.

12. The printed circuit board according to claim 1, wherein: A conductive pattern layer disposed at a lowermost side among the plurality of conductive pattern layers is in contact with an adhesive attached to a lower side of the interconnection bridge, and The conductive pattern layer disposed at the lowermost side includes a second ground pattern.

13. The printed circuit board according to claim 1, further comprising: a second wiring layer, disposed in the first insulating layer; a first via layer, penetrating the first insulating layer and connecting the first wiring layer and the second wiring layer; a second insulating layer, disposed below the first insulating layer; A third wiring layer is provided in the second insulating layer; a second via layer, penetrating the second insulating layer and connecting the second wiring layer and the third wiring layer; a third insulating layer, disposed on the first insulating layer and covering the first wiring layer; a fourth wiring layer, disposed on the third insulating layer; as well as a third via layer, penetrating the third insulating layer and connecting the first wiring layer and the fourth wiring layer, Wherein, the upper surface of the third insulating layer is flat.

14. The printed circuit board according to claim 1, wherein: The recess is tapered such that a width of an upper end of the recess is greater than a width of a lower end of the recess.

15. The printed circuit board according to claim 1, wherein The conductive pillar has a height-to-width ratio greater than 1.

16. A printed circuit board, comprising: A first substrate unit includes a plurality of first insulating layers, a plurality of first wiring layers disposed on or in the plurality of first insulating layers, and a plurality of first via layers respectively penetrating the plurality of first insulating layers; as well as The second substrate unit includes a plurality of second insulating layers, a plurality of second wiring layers disposed on or in the plurality of second insulating layers, a plurality of second via layers penetrating the plurality of second insulating layers respectively, and a plurality of conductive pillars disposed on the second insulating layer disposed on the uppermost side among the plurality of second insulating layers. Wherein, the second substrate unit is arranged in the first substrate unit, An average pitch of wirings of at least one of the plurality of second wiring layers is smaller than an average pitch of wirings of at least one of the plurality of first wiring layers, and At least one of the plurality of first insulating layers has a step region exposing a portion of each of the plurality of conductive pillars.

17. The printed circuit board according to claim 16, wherein: Each of the plurality of first insulating layers and the plurality of second insulating layers includes an organic insulating material.

18. The printed circuit board according to claim 16, further comprising: A first semiconductor chip and a second semiconductor chip are disposed on the first substrate unit and connected to each other through at least one second wiring layer of the plurality of second wiring layers of the second substrate unit and at least one conductive pillar of the plurality of conductive pillars.

19. A printed circuit board, comprising: An interconnection bridge, comprising an insulating material, a plurality of conductive pattern layers respectively disposed on or in the insulating material, and a conductive column disposed on an upper surface of the insulating material; a first insulating layer having the interconnect bridge embedded in and in contact with at least a portion of the upper surface of the insulating material; a first wiring layer disposed on the first insulating layer and including a first pad pattern contacting the conductive pillar; a second wiring layer, disposed in the first insulating layer; as well as The first via layer penetrates the first insulating layer and connects the first wiring layer and the second wiring layer.

20. The printed circuit board according to claim 19, wherein A portion of the conductive pillar is embedded in the first insulating layer, and another portion of the conductive pillar protrudes from an upper surface of the first insulating layer.

21. The printed circuit board according to claim 19, wherein The conductive pillar is embedded in the first insulating layer and exposed from an upper surface of the first insulating layer such that an upper surface of the conductive pillar is coplanar with the upper surface of the first insulating layer.

22. The printed circuit board according to claim 19, wherein The interconnection bridge includes a plurality of the conductive pillars, The interconnection bridge further includes a protection material disposed on the insulating material and surrounding at least one conductive pillar of the plurality of conductive pillars, and The protective material is disposed in a partial region of the upper surface of the insulating material.

23. The printed circuit board according to claim 22, wherein: The interconnection bridge further includes an alignment mark disposed on the insulating material and spaced apart from the protection material.

24. The printed circuit board according to claim 19, wherein A conductive pattern layer disposed on the uppermost side among the plurality of conductive pattern layers is disposed on the upper surface of the insulating material, and The conductive pattern layer disposed on the uppermost side includes a conductive pad connected to the conductive pillar.

25. The printed circuit board according to claim 24, wherein The conductive pattern layer further includes a first ground pattern spaced apart from the conductive pillar.

26. The printed circuit board according to claim 19, wherein A conductive pattern layer disposed at a lowermost side among the plurality of conductive pattern layers is in contact with an adhesive attached to a lower side of the interconnection bridge, and The conductive pattern layer disposed at the lowermost side includes a second ground pattern.

27. The printed circuit board according to claim 19, further comprising: a second insulating layer, disposed below the first insulating layer; A third wiring layer is provided in the second insulating layer; a second via layer, penetrating the second insulating layer and connecting the second wiring layer and the third wiring layer; a third insulating layer, disposed on the first insulating layer and covering the first wiring layer; a fourth wiring layer, disposed on the third insulating layer; as well as The third via layer penetrates the third insulating layer and connects the first wiring layer and the fourth wiring layer.

Images