Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a substrate; forming a storage gate structure on the substrate; forming a dielectric layer on the surface of the substrate and the surface of the storage gate structure; forming a first opening in the dielectric layer, wherein the first opening exposes part of the surface of the top of the storage gate structure; forming a first isolation layer on the surface of the side wall of the first opening; forming a contact bolt structure filling the first opening on the side wall surface of the first isolation layer and the bottom surface of the first opening; and removing the first isolation layer, and forming a gap between the side wall of the contact bolt structure and the side wall of the first opening. According to the method, the distance between the adjacent contact bolt structures is increased, the risk of device burnout caused by the fact that the distance between the adjacent contact bolt structures is too close during high-voltage work is reduced, the first isolation layer is removed subsequently, a gap is formed between the side wall of the contact bolt structure and the side wall of the first opening, and the resistance value of the contact bolt structure is not affected.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] NOR Flash (Not OR Flash) is a non-volatile flash memory technology with high transmission efficiency. The traditional NOR Flash contact window is generally composed of two parts, one is the adhesive layer, and the other is the metal filler plug contact hole. With the update and size reduction of NOR Flash, the distance between the plug contact holes and the distance between the plug contact holes and the control gate are gradually shrinking under the high voltage state.

[0003] However, the existing NOR Flash contact window structure needs to be further improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the NOR Flash contact window structure.

[0005] In order to solve the above technical problems, the present invention provides a semiconductor structure and a method for forming the same, wherein the forming method comprises: providing a substrate; forming a storage gate structure on the substrate; forming a dielectric layer on the surface of the substrate and the surface of the storage gate structure; forming a first opening in the dielectric layer, wherein the first opening exposes a top portion of the surface of the storage gate structure; forming a first insulating layer on the side wall surface of the first opening; forming a contact plug structure filling the first opening on the side wall surface of the first insulating layer and the bottom surface of the first opening; removing the first insulating layer to form a gap between the side wall of the contact plug structure and the side wall of the first opening.

[0006] Optionally, the storage gate structure includes: a floating gate structure and a control gate structure located on the surface of the floating gate structure; the floating gate structure includes a floating gate dielectric layer and a floating gate located on the surface of the floating gate dielectric layer; the control gate structure includes a control gate dielectric layer, a control gate located on the surface of the control gate dielectric layer, and a metal silicide layer located on the surface of the control gate.

[0007] Optionally, the storage gate structure further includes: sidewalls located on sidewall surfaces of the floating gate structure and sidewall surfaces of the control gate structure.

[0008] Optionally, the method for forming the first opening includes: forming a first mask layer on the surface of the dielectric layer, the first mask layer exposing a portion of the surface of the dielectric layer; using the first mask layer as a mask, etching the dielectric layer and the metal silicide layer to form the first opening, the first opening exposing a top portion of the surface of the storage gate structure; the size of the first opening in a direction parallel to the substrate surface is less than or equal to the size of the control gate in a direction parallel to the substrate surface.

[0009] Optionally, the method for forming the first isolation layer includes: forming an initial first isolation layer in the first opening; flattening the surface of the initial first isolation layer until the surface of the dielectric layer is exposed; forming a second mask layer on the surface of the initial first isolation layer and the surface of the dielectric layer, the second mask layer exposing a portion of the surface of the initial first isolation layer; etching the initial first isolation layer using the second mask layer as a mask to form a second opening and the first isolation layer, the second opening exposing a top portion of the surface of the storage gate structure; the size of the second opening in a direction parallel to the substrate surface is smaller than the size of the first opening in a direction parallel to the substrate surface.

[0010] Optionally, the material of the initial first insulating layer includes: a mixture of one or more of high molecular polymers, oxides, nitrides, oxynitrides, and metals.

[0011] Optionally, the method for forming the initial first insulating layer includes: one or more of thermal oxidation, rapid thermal annealing, chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition.

[0012] Optionally, the contact plug structure includes: an adhesive layer located on the side wall surface of the first insulating layer and the bottom surface of the first opening, and a conductive layer filling the first opening.

[0013] Optionally, the method for forming the contact plug structure includes: forming an adhesive layer on the side wall surface of the first insulating layer and the bottom surface of the first opening; forming an initial conductive layer on the bottom surface of the adhesive layer and the side wall surface of the adhesive layer, the initial conductive layer filling the first opening; and planarizing the initial conductive layer to form a conductive layer.

[0014] Optionally, the method for forming the adhesive layer includes: pre-treating the side wall surface of the first insulating layer and the bottom surface of the first opening; and depositing the adhesive layer on the side wall surface of the first insulating layer and the bottom surface of the first opening.

[0015] Optionally, the pretreatment method includes: wet pickling or plasma bombardment; the material of the bonding layer includes one or more of metals or metal nitrides, and the metal includes one or more of titanium, aluminum, and tantalum.

[0016] Optionally, the method for removing the first insulating layer includes: etching to remove the first insulating layer; the etching process for removing the first insulating layer includes one or more of dry plasma etching, wet chemical etching, high temperature evaporation, high temperature ablation, and ultraviolet degradation.

[0017] Optionally, it also includes: before forming the dielectric layer, forming a source region and a drain region in the substrate on both sides of the storage gate structure respectively; the first opening also exposes the surface of one or both of the source region and the drain region; the first opening, the gap and the contact plug structure are also located on the surface of one or both of the source region and the drain region.

[0018] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, comprising: a substrate; a storage gate structure located on the substrate; a dielectric layer located on the surface of the substrate and the surface of the storage gate structure, the surface of the dielectric layer is higher than the top surface of the storage gate structure; a first opening located in the dielectric layer, the first opening exposing the top portion of the surface of the storage gate structure; a contact plug structure located in the first opening, a gap between the side wall of the contact plug structure and the side wall of the first opening.

[0019] Optionally, the storage gate structure includes: a floating gate structure and a control gate structure located on the surface of the floating gate structure; the floating gate structure includes a floating gate dielectric layer and a floating gate located on the surface of the floating gate dielectric layer; the control gate structure includes a control gate dielectric layer, a control gate located on the surface of the control gate dielectric layer, and a metal silicide layer located on the surface of the control gate; the size of the first opening in a direction parallel to the substrate surface is less than or equal to the size of the control gate in a direction parallel to the substrate surface.

[0020] Optionally, the contact plug structure includes: an adhesive layer located on the sidewall surface of the gap and the bottom surface of the first opening, and a conductive layer filling the first opening.

[0021] Optionally, the material of the bonding layer includes one or more of metals or metal nitrides, and the metal includes one or more of titanium, aluminum, and tantalum; the material of the conductive layer includes one or more of tungsten, titanium, aluminum, gold, and copper.

[0022] Optionally, it also includes: a source region and a drain region located in the substrate on both sides of the storage gate structure; the first opening, the gap and the contact plug structure are also located on the surface of one or both of the source region and the drain region.

[0023] Optionally, the width of the gap ranges from 1 nm to 150 nm.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In the semiconductor structure of the technical solution of the present invention, the contact plug structure is located on the side wall surface of the gap and the bottom surface of the first opening, and fills the first opening. On the one hand, the existence of the gap increases the distance between adjacent contact plug structures, reduces the risk of device burnout due to the close distance between adjacent contact plug structures during high-voltage operation, and improves the reliability of the device; on the other hand, the medium of the gap is air, which does not affect the resistance of the contact plug structure.

[0026] In the method for forming a semiconductor structure of the technical solution of the present invention, a first insulating layer is formed on the side wall surface of the first opening, and then a contact plug structure filling the first opening is formed on the side wall surface of the first insulating layer and the bottom surface of the first opening. On the one hand, the presence of the first insulating layer increases the distance between adjacent contact plug structures, reduces the risk of device burnout due to the close distance between adjacent contact plug structures during high-voltage operation, and improves the reliability of the device; on the other hand, the subsequent removal of the first insulating layer forms a gap between the side wall of the contact plug structure and the side wall of the first opening, which does not affect the resistance of the contact plug structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of a cross-sectional structure of a semiconductor structure;

[0028] Figures 2 to 10 It is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] As described in the background art, the existing NOR Flash contact window structure needs to be further improved.

[0030] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure.

[0031] Please refer to Figure 1 The semiconductor structure includes: a substrate 100; a storage gate structure 101 located on the substrate 100; a dielectric layer 102 located on the surface of the substrate 100 and the surface of the storage gate structure 101, wherein the surface of the dielectric layer 102 is higher than the top surface of the storage gate structure 101; a first opening (not shown) located in the dielectric layer 102, wherein the first opening (not shown) exposes a top portion of the surface of the storage gate structure 101; and a contact plug structure 103 located in the first opening (not shown).

[0032] The contact plug structure 103 includes an adhesive layer and a conductive layer located on the surface of the adhesive layer.

[0033] With the iteration and size reduction of semiconductor devices, the distance between adjacent contact plug structures 103 and the distance between the contact plug 103 and the storage gate structure 101 are continuously reduced, and the risk of device burnout is greatly increased when high voltage is applied.

[0034] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein a first insulating layer is formed on the side wall surface of the first opening, and then a contact plug structure filling the first opening is formed on the side wall surface of the first insulating layer and the bottom surface of the first opening. On the one hand, the presence of the first insulating layer increases the distance between adjacent contact plug structures, reduces the risk of device burnout due to the close distance between adjacent contact plug structures during high-voltage operation, and improves the reliability of the device; on the other hand, the subsequent removal of the first insulating layer forms a gap between the side wall of the contact plug structure and the side wall of the first opening, which does not affect the resistance of the contact plug.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 2 to 10 It is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0037] Please refer to Figure 2 , providing a substrate 200; forming a storage gate structure 201 on the substrate 200; and forming a dielectric layer 202 on the surface of the substrate 200 and the surface of the storage gate structure 201.

[0038] The substrate 200 may be made of silicon, silicon carbide, silicon germanium, silicon on insulator (SOI), or germanium on insulator (GOI).

[0039] The storage gate structure 201 includes: a floating gate structure 203 and a control gate structure 204 located on the surface of the floating gate structure 203; the floating gate structure 203 includes a floating gate dielectric layer 205 and a floating gate 206 located on the surface of the floating gate dielectric layer 205; the control gate structure 204 includes a control gate dielectric layer 207, a control gate 208 located on the surface of the control gate dielectric layer 207, and a metal silicide layer 209 located on the surface of the control gate 208.

[0040] Specifically, in this embodiment, the size of the control gate 208 in a direction parallel to the surface of the substrate 200 ranges from 50 nm to 200 nm.

[0041] Specifically, in this embodiment, the storage gate structure 201 further includes: a spacer 210 located on the sidewall surface of the floating gate structure 203 and the sidewall surface of the control gate structure 204 .

[0042] The method for forming the storage gate structure 201 includes: forming an initial floating gate dielectric layer (not shown) on the surface of the substrate 200; forming a floating gate material layer (not shown) on the surface of the initial floating gate dielectric layer (not shown); forming an initial control gate structure (not shown) on the floating gate material layer (not shown), the initial control gate structure (not shown) including an initial control gate dielectric layer (not shown), a control gate material layer (not shown) located on the surface of the initial control gate dielectric layer (not shown), and an initial metal silicide layer located on the surface of the control gate material layer (not shown); forming a third mask layer on the surface of the initial control gate structure (not shown); using the third mask layer as a mask, etching the initial control gate structure (not shown), the floating gate material layer (not shown), and the initial floating gate dielectric layer until the surface of the substrate 200 is exposed, thereby forming the floating gate structure 203 and the control gate structure 204 located on the surface of the floating gate structure 203.

[0043] The formation methods of the initial floating gate dielectric layer (not shown), the floating gate material layer (not shown), and the initial control gate structure (not shown) include: chemical vapor deposition, thermal oxidation, rapid thermal annealing, physical deposition, atomic layer deposition, and jet vapor deposition; the chemical vapor deposition includes low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, and high-pressure chemical vapor deposition.

[0044] The floating gate structure 203 includes a floating gate dielectric layer 205 and a floating gate 206 located on the surface of the floating gate dielectric layer 205 .

[0045] The material of the floating gate dielectric layer 205 includes silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0046] The material of the floating gate 206 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0047] The control gate structure 204 includes a control gate dielectric layer 207 , a control gate 208 located on a surface of the control gate dielectric layer 207 , and a metal silicide layer 209 located on a surface of the control gate 208 .

[0048] The material of the control gate dielectric layer 207 includes one or more of silicon nitride and silicon oxide.

[0049] The material of the control gate 208 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0050] The material of the metal silicide layer 209 includes: copper silicide, nickel silicide, and aluminum silicide doped with one or more of the conductive metals platinum, silver, and gold.

[0051] The etching method includes: dry etching such as plasma etching or wet etching such as chemical wet etching.

[0052] The method for forming the sidewall 210 includes: depositing the sidewall 210 on the sidewall surface of the floating gate structure 203 and the sidewall surface of the control gate structure 204; the deposition method of the sidewall 210 includes: one or more of chemical vapor deposition, thermal oxidation, rapid thermal annealing, physical deposition, atomic layer deposition, and jet vapor deposition.

[0053] The material of the sidewall spacer 210 includes a mixture of one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0054] Specifically, in this embodiment, after forming the storage gate structure 201 and before forming the dielectric layer 202 , the method further includes: forming a source region 211 and a drain region 212 in the substrate 200 at both sides of the storage gate structure 201 .

[0055] Specifically, in this embodiment, the first opening 213 formed subsequently exposes the surface of one or both of the source region 211 and the drain region 212 , and the first opening 213 , the gap 221 and the contact plug structure 217 formed subsequently are also located on the surface of one or both of the source region 211 and the drain region 212 .

[0056] After the source region 211 and the drain region 212 are formed, a dielectric layer 202 is formed on the surface of the substrate 200 and the surface of the storage gate structure 201 .

[0057] The dielectric layer 202 may be formed by chemical vapor deposition, thermal oxidation, rapid thermal annealing, physical deposition, atomic layer deposition, or jet vapor deposition.

[0058] The depth from the surface of the dielectric layer 202 to the surface of the control gate structure 204 ranges from 20 nm to 1000 nm. The depth of the dielectric layer 202 determines the depth of the contact plug structure 217 formed subsequently.

[0059] The material of the dielectric layer 202 includes: a mixture of one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0060] Please refer to Figure 3 A first opening 213 is formed in the dielectric layer 202 , wherein the first opening 213 exposes a top portion of the surface of the storage gate structure 201 .

[0061] The method for forming the first opening 213 includes: forming a first mask layer (not shown) on the surface of the dielectric layer 202, wherein the first mask layer (not shown) exposes a portion of the surface of the dielectric layer 202; using the first mask layer (not shown) as a mask, etching the dielectric layer 202 and the metal silicide layer 209 to form the first opening 213, wherein the first opening 213 exposes a portion of the top surface of the storage gate structure 201; a dimension a of the first opening 213 in a direction parallel to the surface of the substrate 200 is less than or equal to a dimension b of the control gate 208 in a direction parallel to the surface of the substrate 200.

[0062] The size a of the first opening 213 ranges from 20 nm to 200 nm.

[0063] The first opening 213 exposes the surface of one or both of the source region 211 and the drain region 212 , and the first opening 213 , the subsequently formed gap 221 , and the subsequently formed contact plug structure 217 are also located on the surface of one or both of the source region 211 and the drain region 212 .

[0064] The etching method of the first opening 213 includes: dry etching or wet etching.

[0065] Please refer to Figure 4 , an initial first insulating layer 214 is formed in the first opening 213 .

[0066] In this embodiment, the material of the initial first insulating layer 214 includes: a mixture of one or more of high molecular polymer, oxide, nitride, oxynitride, and metal.

[0067] In this embodiment, the method for forming the initial first insulating layer 214 includes: one or more of thermal oxidation, rapid thermal annealing, chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition.

[0068] The initial first insulating layer 214 provides a structural basis for the subsequent formation of the first insulating layer 216 .

[0069] On the one hand, the initial first insulating layer 214 subsequently forms a gap 221, which increases the distance between adjacent contact plug structures 217, reduces the risk of device burnout due to the close distance between adjacent contact plug structures 217 during high-voltage operation, and improves the reliability of the device; on the other hand, the initial first insulating layer 214 is subsequently post-processed to form a gap 221, and the insulating medium of the gap 221 is air, which does not affect the resistance value of the contact plug structure 217.

[0070] Please refer to Figure 5 , the initial first isolation layer 214 is planarized until the surface of the dielectric layer 202 is exposed.

[0071] The planarization method includes: chemical mechanical polishing; specifically, in this embodiment, the polishing material of the chemical mechanical polishing includes a single substance or a mixture of multiple substances.

[0072] Please refer to Figure 6 In the initial first insulating layer 214 (such as Figure 5 A second mask layer (not shown) is formed on the surface of the dielectric layer 202, and the second mask layer (not shown) exposes the initial first isolation layer 214 (as shown in FIG. Figure 5 Using the second mask layer (not shown) as a mask, etching the initial first isolation layer 214 (as shown Figure 5 ), forming a second opening 215 and a first insulating layer 216, wherein the second opening 215 exposes a top portion of the surface of the storage gate structure 201; the dimension c of the second opening 215 in a direction parallel to the surface of the substrate 200 is smaller than that of the first opening 213 (as shown in FIG. Figure 3 ) in a direction parallel to the surface of the substrate 200.

[0073] The size c of the second opening 215 in a direction parallel to the surface of the substrate 200 ranges from 20 nm to 200 nm.

[0074] The method of etching to form the second opening 215 includes dry etching or wet etching.

[0075] The second opening 215 provides a structural basis for subsequently forming a contact plug structure 217 .

[0076] The material of the first insulating layer 216 includes: a mixture of one or more of high molecular polymer, oxide, nitride, oxynitride and metal.

[0077] The thickness of the first insulating layer 216 ranges from 0 to 180 nm.

[0078] After the first insulating layer 216 is formed, the sidewall surface of the first insulating layer 216 and the first opening 213 (such as Figure 3 The bottom surface of the first opening 213 (as shown) is formed to fill the first opening 213 Figure 3 For details, please refer to Figures 7 to 9 .

[0079] The contact plug structure 217 includes: a contact plug structure 217 located on the sidewall surface of the first insulating layer 216 and the first opening 213 (such as Figure 3 ) and fill the first opening 213 (as shown in FIG. Figure 3 ) a conductive layer 220.

[0080] Please refer to Figure 7 , on the sidewall surface of the first insulating layer 216 and the first opening 213 (such as Figure 3 An adhesive layer 218 is formed on the bottom surface of the substrate.

[0081] The function of the adhesive layer 218 is to enhance the adhesion between the contact plug structure and the metal silicide, thereby facilitating the conductive connection of the contact plug structure.

[0082] The thickness of the adhesive layer 218 is in the range of 1 nm to 20 nm.

[0083] The method for forming the adhesive layer 218 includes: forming the first insulating layer 216 sidewall surface and the first opening 213 (such as Figure 3 The bottom surface of the first insulating layer 216 is pre-processed; the side wall surface of the first insulating layer 216 and the first opening 213 (as shown in Figure 3 An adhesive layer 218 is deposited on the bottom surface of the substrate (as shown).

[0084] Specifically, in this embodiment, the pretreatment method includes: wet pickling or plasma bombardment.

[0085] The material of the adhesion layer 218 includes one or more of metals or metal nitrides, and the metal includes one or more of titanium, aluminum, and tantalum.

[0086] Please refer to Figure 8 An initial conductive layer 219 is formed on the bottom surface of the adhesive layer 218 and the sidewall surface of the adhesive layer 218, and the initial conductive layer 219 fills the first opening 213 (such as Figure 3 shown).

[0087] The material of the initial conductive layer 219 includes one or more of tungsten, titanium, aluminum, gold, and copper.

[0088] The initial conductive layer 219 may be formed by one or more methods selected from the group consisting of electrochemical deposition, chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition.

[0089] Please refer to Fig. 9 , the initial conductive layer 219 is planarized to form a conductive layer 220.

[0090] The planarization method includes: chemical mechanical polishing; specifically, in this embodiment, the polishing material of the chemical mechanical polishing includes a single substance or a mixture of multiple substances.

[0091] The material of the conductive layer 220 includes one or more of tungsten, titanium, aluminum, gold, and copper.

[0092] The aspect ratio of the conductive layer 220 ranges from 1:10 to 50:1.

[0093] Please refer to Fig.10 , the first isolation layer 216 is post-processed, and the sidewalls of the contact plug structure 217 and the first opening 213 (such as Figure 3 A second insulating layer is formed between the side walls.

[0094] In this embodiment, the second insulating layer is a gap 221 .

[0095] In this embodiment, the method for post-processing the first isolation layer 216 includes: etching to remove the first isolation layer 216; the etching process for removing the first isolation layer 216 includes one or more of dry plasma etching, wet chemical etching, high temperature evaporation, high temperature ablation, and ultraviolet degradation.

[0096] Specifically, in this embodiment, the width of the gap 221 ranges from 1 nm to 150 nm.

[0097] Specifically, in this embodiment, the first opening 213 (such as Figure 3 As shown in FIG. 1 ), the gap 221 and the contact plug structure 217 are also located on the surface of one or both of the source region 211 and the drain region 212 .

[0098] On the one hand, the existence of the gap 221 increases the distance between adjacent contact plug structures 217, reduces the risk of device burnout due to the close distance between adjacent contact plug structures 217 during high-voltage operation, and improves the reliability of the device; on the other hand, the medium of the gap 221 is air, which does not affect the resistance of the contact plug structure 217.

[0099] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig.10 , comprising: a substrate 200; a storage gate structure 201 located on the substrate 200; a dielectric layer 202 located on the surface of the substrate 200 and the surface of the storage gate structure 201, wherein the surface of the dielectric layer 202 is higher than the top surface of the storage gate structure 201; a first opening 213 (such as Figure 3 The first opening 213 exposes a top portion of the surface of the storage gate structure 201; a contact plug structure 217 located in the first opening 213, the sidewall of the contact plug structure 217 and the first opening 213 (as shown in FIG. Figure 3 There is a gap 221 between the side walls.

[0100] The semiconductor structure includes a substrate 200 .

[0101] The substrate 200 may be made of silicon, silicon carbide, silicon germanium, silicon on insulator (SOI), or germanium on insulator (GOI).

[0102] The semiconductor structure includes a storage gate structure 201 located on the substrate 200 .

[0103] The storage gate structure 201 includes: a floating gate structure 203 and a control gate structure 204 located on the surface of the floating gate structure 203; the floating gate structure 203 includes a floating gate dielectric layer 205 and a floating gate 206 located on the surface of the floating gate dielectric layer 205; the control gate structure 204 includes a control gate dielectric layer 207, a control gate 208 located on the surface of the control gate dielectric layer 207, and a metal silicide layer 209 located on the surface of the control gate 208.

[0104] Specifically, in this embodiment, it also includes: a source region 211 and a drain region 212 located in the substrate 200 on both sides of the storage gate structure 201; a first opening 213, a gap and a contact plug structure 217 are also located on the surface of one or both of the source region 211 and the drain region 212.

[0105] Specifically, in this embodiment, the size of the control gate 208 in a direction parallel to the surface of the substrate 200 ranges from 50 nm to 200 nm.

[0106] Specifically, in this embodiment, the storage gate structure 201 further includes: a spacer 210 located on the sidewall surface of the floating gate structure 203 and the sidewall surface of the control gate structure 204 .

[0107] The material of the floating gate dielectric layer 205 includes silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0108] The material of the floating gate 206 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0109] The material of the control gate dielectric layer 207 includes one or more of silicon nitride and silicon oxide.

[0110] The material of the control gate 208 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0111] The material of the metal silicide layer 209 includes: copper silicide, nickel silicide, and aluminum silicide doped with one or more of the conductive metals platinum, silver, and gold.

[0112] The material of the sidewall spacer 210 includes a mixture of one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0113] The semiconductor structure includes: a dielectric layer 202 located on the surface of the substrate 200 and the surface of the storage gate structure 201 , and the surface of the dielectric layer 202 is higher than the top surface of the storage gate structure 201 .

[0114] The depth range from the surface of the dielectric layer 202 to the surface of the control gate structure 204 is 20 nm to 1000 nm.

[0115] The material of the dielectric layer 202 includes: a mixture of one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0116] The semiconductor structure includes: a first opening 213 (eg, Figure 3 As shown in FIG. 2 , the first opening 213 exposes a top portion of the surface of the storage gate structure 201 .

[0117] The size of the first opening 213 in the direction parallel to the surface of the substrate 200 ranges from 20 nm to 200 nm. The size of the first opening 213 in the direction parallel to the surface of the substrate 200 is smaller than the size of the control gate 208 in the direction parallel to the surface of the substrate 200.

[0118] The semiconductor structure includes a contact plug structure 217 located in the first opening 213, and a sidewall of the contact plug structure 217 is adjacent to the first opening 213 (such as Figure 3 There is a gap 221 between the side walls.

[0119] The contact plug structure 217 includes: a contact plug structure 217 located on the sidewall surface of the gap 221 and the first opening 213 (such as Figure 3 ) and fill the first opening 213 (as shown in FIG. Figure 3 ) a conductive layer 220.

[0120] The thickness of the adhesive layer 218 is in the range of 1 nm to 20 nm.

[0121] The material of the adhesion layer 218 includes one or more of metals or metal nitrides, and the metal includes one or more of titanium, aluminum, and tantalum.

[0122] The material of the conductive layer 220 includes one or more of tungsten, titanium, aluminum, gold, and copper.

[0123] The aspect ratio of the conductive layer 220 ranges from 1:10 to 50:1.

[0124] The insulating medium of the gap 221 is air.

[0125] Specifically, in this embodiment, the width of the gap 221 ranges from 1 nm to 150 nm.

[0126] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; a storage gate structure located on the substrate; A dielectric layer located on the surface of the substrate and the surface of the storage gate structure, wherein the surface of the dielectric layer is higher than the top surface of the storage gate structure; a first opening in the dielectric layer, the first opening exposing a top portion of a surface of the storage gate structure; A contact plug structure is located in the first opening, and a gap is formed between a side wall of the contact plug structure and a side wall of the first opening.

2. The semiconductor structure according to claim 1, wherein: The storage gate structure includes: a floating gate structure and a control gate structure located on the surface of the floating gate structure; the floating gate structure includes a floating gate dielectric layer and a floating gate located on the surface of the floating gate dielectric layer; the control gate structure includes a control gate dielectric layer, a control gate located on the surface of the control gate dielectric layer, and a metal silicide layer located on the surface of the control gate; the size of the first opening in a direction parallel to the substrate surface is less than or equal to the size of the control gate in a direction parallel to the substrate surface.

3. The semiconductor structure according to claim 1, wherein: The contact plug structure includes: an adhesive layer located on the sidewall surface of the gap and the bottom surface of the first opening, and a conductive layer filling the first opening.

4. The semiconductor structure according to claim 3, characterized in that The material of the bonding layer includes one or more of metals or metal nitrides, and the metal includes one or more of titanium, aluminum, and tantalum; the material of the conductive layer includes one or more of tungsten, titanium, aluminum, gold, and copper.

5. The semiconductor structure according to claim 1, wherein: Also includes: A source region and a drain region are located in the substrate on both sides of the storage gate structure; the first opening, the gap and the contact plug structure are also located on the surface of one or both of the source region and the drain region.

6. The semiconductor structure according to claim 2, wherein: The width of the gap ranges from 1 nm to 150 nm.

7. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a storage gate structure on the substrate; forming a dielectric layer on the surface of the substrate and the surface of the storage gate structure; forming a first opening in the dielectric layer, wherein the first opening exposes a top portion of a surface of the storage gate structure; forming a first insulating layer on the sidewall surface of the first opening; forming a contact plug structure filling the first opening on the side wall surface of the first insulating layer and the bottom surface of the first opening; The first insulating layer is removed to form a gap between the sidewall of the contact plug structure and the sidewall of the first opening.

8. The method for forming a semiconductor structure according to claim 7, wherein: The storage gate structure includes: a floating gate structure and a control gate structure located on the surface of the floating gate structure; the floating gate structure includes a floating gate dielectric layer and a floating gate located on the surface of the floating gate dielectric layer; the control gate structure includes a control gate dielectric layer, a control gate located on the surface of the control gate dielectric layer, and a metal silicide layer located on the surface of the control gate.

9. The method for forming a semiconductor structure according to claim 8, wherein: The storage gate structure further includes: sidewalls located on the sidewall surfaces of the floating gate structure and the sidewall surfaces of the control gate structure.

10. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the first opening includes: forming a first mask layer on the surface of the dielectric layer, the first mask layer exposing a portion of the surface of the dielectric layer; using the first mask layer as a mask, etching the dielectric layer and the metal silicide layer to form the first opening, the first opening exposing a top portion of the surface of the storage gate structure; the size of the first opening in a direction parallel to the substrate surface is less than or equal to the size of the control gate in a direction parallel to the substrate surface.

11. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the first isolation layer includes: forming an initial first isolation layer in the first opening; flattening the surface of the initial first isolation layer until the surface of the dielectric layer is exposed; forming a second mask layer on the surface of the initial first isolation layer and the surface of the dielectric layer, the second mask layer exposing a portion of the surface of the initial first isolation layer; etching the initial first isolation layer using the second mask layer as a mask to form a second opening and the first isolation layer, the second opening exposing a portion of the top surface of the storage gate structure; the size of the second opening in a direction parallel to the substrate surface is smaller than the size of the first opening in a direction parallel to the substrate surface.

12. The method for forming a semiconductor structure according to claim 11, wherein: The material of the initial first insulating layer includes: a mixture of one or more of high molecular polymer, oxide, nitride, oxynitride and metal.

13. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the initial first insulating layer includes: one or more of thermal oxidation, rapid thermal annealing, chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition.

14. The method for forming a semiconductor structure according to claim 7, wherein: The contact plug structure includes: an adhesive layer located on the side wall surface of the first insulating layer and the bottom surface of the first opening, and a conductive layer filling the first opening.

15. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the contact plug structure includes: forming an adhesive layer on the side wall surface of the first insulating layer and the bottom surface of the first opening; forming an initial conductive layer on the bottom surface of the adhesive layer and the side wall surface of the adhesive layer, wherein the initial conductive layer fills the first opening; and flattening the initial conductive layer to form a conductive layer.

16. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the adhesive layer comprises: pre-treating the side wall surface of the first insulating layer and the bottom surface of the first opening; and depositing the adhesive layer on the side wall surface of the first insulating layer and the bottom surface of the first opening.

17. The method for forming a semiconductor structure according to claim 16, wherein: The pretreatment method includes: wet pickling or plasma bombardment; the material of the bonding layer includes one or more of metals or metal nitrides, and the metal includes one or more of titanium, aluminum, and tantalum.

18. The method for forming a semiconductor structure according to claim 7, wherein: The method for removing the first insulating layer includes: etching to remove the first insulating layer; the etching process for removing the first insulating layer includes one or more of dry plasma etching, wet chemical etching, high temperature evaporation, high temperature ablation, and ultraviolet degradation.

19. The method for forming a semiconductor structure according to claim 7, wherein: Also includes: Before forming the dielectric layer, a source region and a drain region are respectively formed in the substrate on both sides of the storage gate structure; the first opening also exposes the surface of one or both of the source region and the drain region; the first opening, the gap and the contact plug structure are also located on the surface of one or both of the source region and the drain region.

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