Germanium-silicon heterojunction bipolar transistor
By setting a dielectric buried layer at the bottom of the collector region of the silicon germanium heterojunction bipolar transistor to separate the semiconductor substrate, the problem of low cutoff frequency of existing devices is solved, and higher cutoff frequency and improved performance is achieved.
Patent Information
- Application Number
- CN202411464852.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-02-14
AI Technical Summary
The cutoff frequency of existing silicon germanium heterojunction bipolar transistors is low, resulting in poor device performance.
A dielectric buried layer is arranged at the bottom of the collector region to separate the semiconductor substrate into the top layer of the semiconductor and the main layer, reducing the capacitance between the collector region and the base region, thereby reducing the crossing time and increasing the cutoff frequency.
By reducing the capacitance between the collector region and the base region and reducing the transition time, the cutoff frequency of the silicon germanium heterojunction bipolar transistor is significantly improved, thereby improving the performance of the device.
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Figure CN119451142A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor integrated circuit, and in particular to a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT). Background Art
[0002] In the 0.1-1THz band, SiGe HBT has become the core device of silicon-based high-frequency integrated circuits due to its huge potential and technical advantages in SiGe BiCMOS circuit and system applications;
[0003] Cut-off frequency f T It is one of the main performance parameters of HBT, which is related to the doping concentration, parasitic resistance and parasitic capacitance of HBT. It is generally defined as the frequency corresponding to the current gain decreasing to 1. For conventional SiGe HBT, the cut-off frequency f T The expression of is shown in formula (1); τ ec，SiGe As shown in formula (2). If f>f T , the transistor loses its current amplification capability; the characteristic frequency of the transistor mainly depends on the total transit time τ of electrons from the emitter (E) to the collector (C) ec , is the frequency limit of the current amplification capability of the common emitter connected transistor.
[0004]
[0005] Above, f T represents the characteristic frequency, τ ec，SiGe represents the transit time between E and C of SiGe HBT, i.e. τ ec .
[0006] T is the thermodynamic temperature, q is the charge of the electron, k is the Boltzmann constant, and kT / q represents the thermovoltage. At room temperature, the thermovoltage is about 26mV.
[0007] Ic represents the collector current.
[0008] Ceb represents the capacitance between the emitter and the base;
[0009] Ccb represents the capacitance between the collector and the base;
[0010] τ b，SiGe Represents the transit time of the base region of the SiGe HBT.
[0011] like Figure 1 As shown, it is a schematic diagram of the structure of the existing germanium-silicon heterojunction bipolar transistor; taking NPN as an example, the existing germanium-silicon heterojunction bipolar transistor includes:
[0012] An N-type doped collector region 102 is formed in a semiconductor substrate 101; a shallow trench isolation 105 is formed in the semiconductor substrate 101, the area surrounded by the shallow trench isolation 105 is an active area, the top area of the collector region 102 is located in the active area, and the depth of the collector region 102 is greater than the depth of the shallow trench isolation 105.
[0013] The P-type doped base region 107 is composed of a silicon germanium epitaxial layer formed on the top of the collector region 102 .
[0014] The emitter region 108 is composed of N-type doped polysilicon formed on the top of the base region 107 .
[0015] The lead-out structure of the collector region 102 includes:
[0016] The N-type heavily doped buried layer 103, namely the N-type buried layer (NBL), is formed between the collector region 102 and the dielectric buried layer 301, and the bottom surface of the collector region 102 is in contact with the top surface of the doped buried layer 103; the doped buried layer 103 extends laterally into the semiconductor substrate 101 outside the shallow trench isolation 105.
[0017] An N-type heavily doped sinker region 104 is formed in the semiconductor substrate 101 outside the shallow trench isolation 105 . The sinker region 104 extends downward from the top surface of the semiconductor substrate 101 and contacts the top surface of the doped buried layer 103 .
[0018] The structure also includes a deep trench isolation 106 formed outside the sinker region 104 .
[0019] The deep trench isolation 106 is composed of a dielectric layer such as an oxide layer filled in the deep trench.
[0020] The base window is formed by surrounding the base window dielectric layer 109; the base window is located directly above the active area and the area of the base window is larger than the area of the active area.
[0021] The silicon germanium epitaxial layer is formed in the base window and also extends to the surface of the base window dielectric layer 109 outside the base window. Since epitaxial growth can only form single crystals on the surface of single crystal structures, and only polycrystalline structures can be formed on the surface of dielectric or polycrystalline structures, it can be known that the silicon germanium epitaxial layer in contact with the active area is a single crystal structure, and the silicon germanium epitaxial layer extending outside the active area is a polycrystalline structure. The silicon germanium epitaxial layer extending outside the active area will be located on the shallow trench isolation surface between the base window and the active area and the surface of the base window dielectric layer 109 outside the base window.
[0022] The emission region window is formed by surrounding the emission region window dielectric layer 110; the emission region window is located directly above the active region and the region range of the emission region window is smaller than the region range of the active region.
[0023] The polysilicon is formed in the emitter window and also extends onto the surface of the emitter window dielectric layer 110 outside the emitter window.
[0024] The silicon germanium epitaxial layer directly below the emitter window forms an intrinsic base region, and the silicon germanium epitaxial layer outside the intrinsic base region forms an extrinsic base region.
[0025] The collector region 102 also includes an N-type doped central ion implantation region 102b, the formation area of which is defined by the emitter window. The central ion implantation region 102b is also called a high speed (HS) ion implantation region, which is used to increase the speed of the device. Figure 1 In the embodiment, the collector region 102 further includes a doping region 102 a located outside the central ion implantation region 102 b , and the doping region 102 a is directly doped with the semiconductor substrate 101 . Summary of the invention
[0026] The technical problem to be solved by the present invention is to provide a germanium-silicon heterojunction bipolar transistor, which can increase the cut-off frequency of the device and thus improve the performance of the device.
[0027] In order to solve the above technical problems, the present invention provides a germanium-silicon heterojunction bipolar transistor comprising:
[0028] A collector region doped with a first conductive type is formed in the top layer of the semiconductor; a shallow trench isolation is formed in the top layer of the semiconductor, the area surrounded by the shallow trench isolation is an active area, the top area of the collector region is located in the active area, and the depth of the collector region is greater than the depth of the shallow trench isolation.
[0029] A dielectric buried layer is formed between the semiconductor top layer and the semiconductor main layer, and the dielectric buried layer isolates the collector region and the semiconductor main layer from top to bottom.
[0030] The second conductive type doped base region is composed of a germanium silicon epitaxial layer formed on the top of the collector region.
[0031] The emitter region is composed of polysilicon doped with the first conductivity type formed on the top of the base region.
[0032] A further improvement is that the material of the semiconductor top layer includes silicon; and the material of the semiconductor main layer includes silicon.
[0033] A further improvement is that the material of the dielectric buried layer includes an oxide layer.
[0034] A further improvement is that the lead-out structure of the collector region includes:
[0035] A doped buried layer heavily doped with the first conductivity type is formed between the collector region and the dielectric buried layer, and the bottom surface of the collector region contacts the top surface of the doped buried layer; the doped buried layer extends laterally into the semiconductor top layer outside the shallow trench isolation.
[0036] A first conductive type heavily doped sinker region is formed in the semiconductor top layer outside the shallow trench isolation, and the sinker region extends downward from the top surface of the semiconductor top layer and contacts the top surface of the doped buried layer.
[0037] A further improvement is that it also includes: deep trench isolation formed outside the sinker area.
[0038] The deep trench isolation extends downward from the top surface of the semiconductor top layer and through the dielectric buried layer into the semiconductor body layer.
[0039] Further improvements include:
[0040] A base window is formed by surrounding a base window dielectric layer; the base window is located directly above the active area and the area range of the base window is larger than the area range of the active area.
[0041] The silicon germanium epitaxial layer is formed in the base window and also extends onto the surface of the base window dielectric layer outside the base window.
[0042] Further improvements include:
[0043] The emission area window is formed by surrounding the emission area window dielectric layer; the emission area window is located directly above the active area and the area range of the emission area window is smaller than the area range of the active area.
[0044] The polysilicon is formed in the emitter window and also extends onto the surface of the emitter window dielectric layer outside the emitter window.
[0045] The silicon germanium epitaxial layer directly below the emitter window forms an intrinsic base region, and the silicon germanium epitaxial layer outside the intrinsic base region forms an extrinsic base region.
[0046] A further improvement is that the collector region further includes a central ion implantation region doped with the first conductivity type, and a formation area of the central ion implantation region is defined by the emitter region window.
[0047] A further improvement is that the thickness of the dielectric buried layer is
[0048] A further improvement is that the germanium-silicon heterojunction bipolar transistor is NPN, the first conductivity type is N type, and the second conductivity type is P type; or, the germanium-silicon heterojunction bipolar transistor is PNP, the first conductivity type is P type, and the second conductivity type is N type.
[0049] The present invention sets a dielectric buried layer at the bottom of the collector region. The dielectric buried layer can divide the semiconductor substrate into a semiconductor top layer and a semiconductor main layer, and can completely isolate the collector region formed in the semiconductor top layer from the semiconductor main layer, so that the influence of the semiconductor main layer on the collector region can be minimized, especially the capacitance between the collector region and the base region can be reduced, so that the transit time τ between the collector region and the base region bc will become smaller, and the transit time τ between the entire emitter region and the collector region ec will also become smaller, the cutoff frequency and τ ec Inverting, it can finally increase the cutoff frequency of the device, thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0050] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0051] Figure 1 It is a schematic diagram of the structure of an existing germanium-silicon heterojunction bipolar transistor;
[0052] Figure 2 It is a schematic diagram of the structure of a germanium-silicon heterojunction bipolar transistor according to an embodiment of the present invention. DETAILED DESCRIPTION
[0053] like Figure 2 , which is a schematic diagram of the structure of a germanium-silicon heterojunction bipolar transistor according to an embodiment of the present invention; the germanium-silicon heterojunction bipolar transistor according to an embodiment of the present invention comprises:
[0054] A collector region 202 doped with a first conductive type is formed in a semiconductor top layer 201b; a shallow trench isolation 205 is formed in the semiconductor top layer 201b, the area surrounded by the shallow trench isolation 205 is an active area, the top area of the collector region 202 is located in the active area, and the depth of the collector region 202 is greater than the depth of the shallow trench isolation 205.
[0055] A dielectric buried layer 301 is formed between the semiconductor top layer 201b and the semiconductor main layer 201a, and the dielectric buried layer 301 isolates the collector region 202 and the semiconductor main layer 201a from top to bottom. Figure 2As shown, the semiconductor top layer 201b and the semiconductor main layer 201a together form a semiconductor substrate 201. In the region where the dielectric buried layer 301 is not formed, the semiconductor top layer 201b and the semiconductor main layer 201a are an integral structure.
[0056] In the embodiment of the present invention, the dielectric buried layer 301 can reduce the parasitic effect of the collector region 202, especially the parasitic effect caused by the influence of the semiconductor main layer 201a on the collector region 202, and finally reduce the effective capacitance Cbc between the collector region 202 and the subsequent base region 207. In some embodiments, the thickness of the dielectric buried layer 301 is
[0057] The second conductivity type doped base region 207 is composed of a germanium silicon epitaxial layer formed on the top of the collector region 202 .
[0058] The emitter region 208 is composed of polysilicon doped with the first conductivity type formed on the top of the base region 207 .
[0059] In the embodiment of the present invention, the material of the semiconductor top layer 201b includes silicon; the material of the semiconductor main layer 201a includes silicon.
[0060] The material of the dielectric buried layer 301 includes an oxide layer.
[0061] The lead-out structure of the collector region 202 includes:
[0062] A heavily doped buried layer 203 of the first conductive type is formed between the collector region 202 and the dielectric buried layer 301, and the bottom surface of the collector region 202 is in contact with the top surface of the doped buried layer 203; the doped buried layer 203 extends laterally into the semiconductor top layer 201b outside the shallow trench isolation 205.
[0063] A first conductive type heavily doped sinker region 204 is formed in the semiconductor top layer 201b outside the shallow trench isolation 205 . The sinker region 204 extends downward from the top surface of the semiconductor top layer 201b and contacts the top surface of the doped buried layer 203 .
[0064] The embodiment of the present invention further includes: a deep trench isolation 206 formed outside the sinker region 204 .
[0065] The deep trench isolation 206 extends downward from the top surface of the semiconductor top layer 201b and passes through the dielectric buried layer 301 into the semiconductor main layer 201a. The deep trench isolation 206 is composed of a dielectric layer such as an oxide layer filled in the deep trench.
[0066] The base window is formed by surrounding the base window dielectric layer 209; the base window is located directly above the active area and the area of the base window is larger than the area of the active area.
[0067] The silicon germanium epitaxial layer is formed in the base window and also extends to the surface of the base window dielectric layer 209 outside the base window. Since epitaxial growth can only form single crystals on the surface of single crystal structures, and only polycrystalline structures can be formed on the surface of dielectric or polycrystalline structures, it can be known that the silicon germanium epitaxial layer in contact with the active area is a single crystal structure, and the silicon germanium epitaxial layer extending outside the active area is a polycrystalline structure. The silicon germanium epitaxial layer extending outside the active area will be located on the shallow trench isolation surface between the base window and the active area and the surface of the base window dielectric layer 209 outside the base window.
[0068] The emission region window is formed by surrounding the emission region window dielectric layer 210; the emission region window is located directly above the active region and the region range of the emission region window is smaller than the region range of the active region.
[0069] The polysilicon is formed in the emitter window and is also extended to the surface of the emitter window dielectric layer 210 outside the emitter window.
[0070] The silicon germanium epitaxial layer directly below the emitter window forms an intrinsic base region, and the silicon germanium epitaxial layer outside the intrinsic base region forms an extrinsic base region.
[0071] The collector region 202 also includes a first conductive type doped central ion implantation region 202b, the formation area of which is defined by the emitter window. The central ion implantation region 202b is also called a high speed (HS) ion implantation region, which is used to increase the speed of the device. Figure 2 In the embodiment, the collector region 202 further includes a doping region 202a located outside the central ion implantation region 202b, and the doping region 202a directly adopts the doping of the semiconductor top layer 201b.
[0072] In the embodiment of the present invention, the germanium-silicon heterojunction bipolar transistor is NPN, the first conductivity type is N type, and the second conductivity type is P type. In some embodiments, the germanium-silicon heterojunction bipolar transistor can also be PNP, the first conductivity type is P type, and the second conductivity type is N type.
[0073] In the embodiment of the present invention, a dielectric buried layer 301 is provided at the bottom of the collector region 202. The dielectric buried layer 301 can divide the semiconductor substrate into a semiconductor top layer 201b and a semiconductor main layer 201a, and can completely isolate the collector region 202 formed in the semiconductor top layer 201b from the semiconductor main layer 201a. In this way, the influence of the semiconductor main layer 201a on the collector region 202 can be minimized, and in particular, the capacitance between the collector region 202 and the base region 207 can be reduced. In this way, the transit time τ between the collector region 202 and the base region 207 is bc will become smaller, and the transit time τ between the entire emitter region 208 and the collector region 202 ec will also become smaller, the cutoff frequency and τ ec Inverting, it can finally increase the cutoff frequency of the device, thereby improving the performance of the device.
[0074] In the embodiment of the present invention, the effective capacitance between the collector region 202 and the base region 207 is Figure 1 The capacitance introduced by the dielectric buried layer 301 is connected in series on the basis of the existing capacitance shown, which will eventually lead to a transit time τ between the collector region 202 and the base region 207. bc The last term in formula (2) is the transit time τ bc Formula, after the capacitance introduced by the dielectric buried layer 301 is connected in series, the transit time τ bc The formula changes to the following formula (3):
[0075]
[0076] Substituting the last term in formula (2) with formula (3) yields the following formula (4):
[0077]
[0078] Among them, τ bc,BOXSiGe It represents the transit time between the collector region 202 and the base region 207 after the dielectric buried layer 301 is provided;
[0079] C cb represents the capacitance between the collector and the base when the capacitance introduced by the dielectric buried layer 301 is not included;
[0080] C BOX represents the capacitance introduced by the dielectric buried layer 301; τ ec,BOXSiGe It represents the transition time between E and C of SiGeHBT after the dielectric buried layer 301 is introduced.
[0081] Comparing formula (2) and formula (4), we can see that the parameter C is added in formula (4). BOX， By adjusting C BOX Can adjust τ ec,BOXSiGe , and finally adjust fT In the embodiment of the present invention, by increasing the thickness of the dielectric buried layer 301, C BOX, C BOX Reducing energy can reduce τ ec,BoXSiGe , τ ec,BOXSiGe Reducing can increase f T。 Therefore, the embodiment of the present invention can increase the thickness of the dielectric buried layer 301 to improve f T .
[0082] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A germanium-silicon heterojunction bipolar transistor, characterized in that: include: A collector region doped with a first conductivity type is formed in the semiconductor top layer; A shallow trench isolation is formed in the top layer of the semiconductor, the area surrounded by the shallow trench isolation is an active area, the top area of the collector area is located in the active area, and the depth of the collector area is greater than the depth of the shallow trench isolation; A dielectric buried layer is formed between the semiconductor top layer and the semiconductor main layer, and the dielectric buried layer isolates the collector region and the semiconductor main layer from top to bottom; A second conductivity type doped base region, composed of a germanium silicon epitaxial layer formed on top of the collector region; The emitter region is composed of polysilicon doped with the first conductivity type formed on the top of the base region.
2. The silicon-germanium heterojunction bipolar transistor according to claim 1, characterized in that: The material of the semiconductor top layer includes silicon; the material of the semiconductor main layer includes silicon.
3. The germanium-silicon heterojunction bipolar transistor according to claim 1, characterized in that: The material of the dielectric buried layer includes an oxide layer.
4. The germanium-silicon heterojunction bipolar transistor according to claim 1, characterized in that: The lead-out structure of the collector region comprises: A doped buried layer heavily doped with a first conductivity type is formed between the collector region and the dielectric buried layer, the bottom surface of the collector region is in contact with the top surface of the doped buried layer; the doped buried layer extends laterally into the semiconductor top layer outside the shallow trench isolation; A first conductive type heavily doped sinker region is formed in the semiconductor top layer outside the shallow trench isolation, and the sinker region extends downward from the top surface of the semiconductor top layer and contacts the top surface of the doped buried layer.
5. The silicon-germanium heterojunction bipolar transistor according to claim 4, characterized in that: Also includes: Deep trench isolation, formed outside the sinker region; The deep trench isolation extends downward from the top surface of the semiconductor top layer and through the dielectric buried layer into the semiconductor body layer.
6. The germanium-silicon heterojunction bipolar transistor according to claim 5, characterized in that: Also includes: A base window is formed by surrounding a base window dielectric layer; the base window is located directly above the active area and the area of the base window is larger than the area of the active area; The silicon germanium epitaxial layer is formed in the base window and also extends onto the surface of the base window dielectric layer outside the base window.
7. The germanium-silicon heterojunction bipolar transistor according to claim 6, characterized in that: Also includes: An emission region window is formed by surrounding the emission region window dielectric layer; the emission region window is located directly above the active region and the region range of the emission region window is smaller than the region range of the active region; The polysilicon is formed in the emitter window and also extends on the surface of the emitter window dielectric layer outside the emitter window; The silicon germanium epitaxial layer directly below the emitter window forms an intrinsic base region, and the silicon germanium epitaxial layer outside the intrinsic base region forms an extrinsic base region.
8. The silicon-germanium heterojunction bipolar transistor according to claim 7, characterized in that: The collector region also includes a central ion implantation region doped with the first conductive type, and a formation area of the central ion implantation region is defined by the emitter region window.
9. The germanium-silicon heterojunction bipolar transistor according to claim 1, characterized in that: The thickness of the dielectric buried layer is 10. The germanium-silicon heterojunction bipolar transistor according to any one of claims 1 to 9, characterized in that: The germanium-silicon heterojunction bipolar transistor is NPN, the first conductivity type is N type, and the second conductivity type is P type; or, the germanium-silicon heterojunction bipolar transistor is PNP, the first conductivity type is P type, and the second conductivity type is N type.