Semiconductor power device and preparation method thereof

Abstract

The invention provides a semiconductor power device and a preparation method thereof. The semiconductor power device comprises a semiconductor substrate layer; a drift layer on the semiconductor substrate layer; the gate structure is located in the drift layer and extends in the first direction; the well regions are located in the drift layer on the two sides of the gate structure in the second direction, and the second direction is perpendicular to the first direction; the first doped region and the second doped region are located in the drift layer on one side, facing the semiconductor substrate layer, of the well region and are arranged at intervals in the second direction, the conduction type of the first doped region is the same as that of the drift layer and opposite to that of the second doped region, and the doping concentration of the first doped region is larger than that of the drift layer; the first doped region surrounds the side wall and part of the bottom wall of one side of the gate structure along the second direction, the second doped region surrounds the side wall and part of the bottom wall of the other side of the gate structure along the second direction, and the first doped region and the second doped region are spaced from the well region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor power device and a preparation method thereof. Background Art

[0002] Silicon Carbide (SiC), a wide bandgap semiconductor material, has become an ideal choice for high-voltage, high-temperature, high-frequency, and high-power power electronic devices due to its advantages such as high critical breakdown electric field, high thermal conductivity, and high electron saturation velocity. SiC Metal-Oxide-Semiconductor FieldEffecTransistor (MOSFET) is a unipolar device with ideal gate insulation characteristics. There is no tail current during the shutdown process, which can greatly reduce switching losses and reduce the size of the heat sink. In addition, the high switching frequency of SiC MOSFET is conducive to reducing the size and weight of source filter components in power electronic devices, and improving the efficiency and power density of the device.

[0003] Compared with planar gate structure SiC MOSFET, trench gate MOSFET can effectively reduce the cell size and increase the channel density. However, for trench SiC MOSFET, the phenomenon of excessively high gate oxide electric field at the bottom of the trench in the blocking state has always been a problem that needs to be solved urgently. Summary of the invention

[0004] The technical problem to be solved by the present invention is to overcome the problem in the prior art that the electric field strength at the gate dielectric layer at the bottom of the gate structure is too high in the reverse blocking state of the semiconductor power device.

[0005] In order to solve the above technical problems, the present invention provides a semiconductor power device, comprising: a semiconductor substrate layer; a drift layer located on the semiconductor substrate layer; a gate structure located in the drift layer and extending along a first direction; a well region, respectively located in the drift layer on both sides of the gate structure along a second direction, the second direction being perpendicular to the first direction; a first doping region and a second doping region arranged at intervals along the second direction in the drift layer on a side of the well region facing the semiconductor substrate layer, the conductivity type of the first doping region being the same as the conductivity type of the drift layer and opposite to the conductivity type of the second doping region, and the doping concentration of the first doping region being greater than the doping concentration of the drift layer; the first doping region surrounding the side wall and a portion of the bottom wall of the gate structure on one side along the second direction, the second doping region surrounding the side wall and a portion of the bottom wall of the gate structure on the other side along the second direction, and the first doping region and the second doping region being spaced from the well region.

[0006] Optionally, the doping concentration of the first doping region is 2 to 8 times the doping concentration of the drift layer.

[0007] Optionally, the doping concentration of the second doping region is less than the doping concentration of the well region.

[0008] Optionally, the doping concentration of the well region is 2 to 5 times the doping concentration of the second doping region.

[0009] Optionally, the spacing distance between the first doped region and the well region along the direction perpendicular to the surface of the semiconductor substrate layer is 0.2 microns to 0.6 microns; the spacing distance between the second doped region and the well region along the direction perpendicular to the surface of the semiconductor substrate layer is 0.2 microns to 0.6 microns.

[0010] Optionally, a size of a bottom surface of the gate structure between the first doping region and the second doping region adjacent to each other along the second direction is 0.2 micrometer to 0.8 micrometer along the second direction.

[0011] Optionally, the second doping region includes a plurality of second sub-doping regions arranged at intervals along a direction perpendicular to the surface of the semiconductor substrate layer.

[0012] Optionally, the second doping region includes a first sub-doping region and a second sub-doping region arranged in a direction perpendicular to the surface of the semiconductor substrate layer, and a size of the first sub-doping region along the second direction is smaller than a size of the second sub-doping region along the second direction; wherein the side wall and a portion of the bottom wall of the gate structure on the other side along the second direction are surrounded by the first sub-doping region, or the side wall and a portion of the bottom wall of the gate structure on the other side along the second direction are surrounded by the second sub-doping region.

[0013] Optionally, a difference between a size of the second sub-doping region along the second direction and a size of the first sub-doping region along the second direction is 0.1 micrometer to 0.3 micrometer.

[0014] Optionally, the first sub-doping regions and the second sub-doping regions are alternately arranged along a direction perpendicular to the surface of the semiconductor substrate layer.

[0015] Optionally, the first doping region and the second doping region both extend along the first direction.

[0016] Optionally, the first doping regions and the second doping regions are also alternately arranged along the first direction; the side wall of the gate structure on one side along the second direction is surrounded by a partial number of the first doping regions and a partial number of the second doping regions, and the side wall of the gate structure on the other side along the second direction is surrounded by a partial number of the first doping regions and a partial number of the second doping regions.

[0017] Optionally, a size of a bottom surface of the gate structure between the first doping region and the second doping region adjacent to each other along the first direction is 0.2 micrometers to 0.8 micrometers along the first direction.

[0018] The present application also provides a method for preparing a semiconductor power device, comprising: forming a drift layer on a semiconductor substrate layer; forming a first doped region and a second doped region arranged at intervals along a second direction in the drift layer, wherein the conductivity type of the first doped region is the same as the conductivity type of the drift layer and is opposite to the conductivity type of the second doped region; forming a gate structure extending along a first direction in the drift layer; forming a well region in the drift layer, wherein the well regions are respectively located on both sides of the gate structure along the second direction, and the second direction is perpendicular to the first direction; the first doped region and the second doped region are located on a side of the well region facing the semiconductor substrate layer and are both spaced from the well region, the first doped region surrounds the side wall and a portion of the bottom wall of the gate structure on one side along the second direction, and the second doped region surrounds the side wall and a portion of the bottom wall of the gate structure on the other side along the second direction.

[0019] Optionally, the step of forming the drift layer includes: forming a first sub-drift layer and a second sub-drift layer stacked in a direction perpendicular to the surface of the semiconductor substrate layer on one side of the semiconductor substrate layer, the doping type of the second sub-drift layer is the same as the doping type of the first sub-drift layer, and the doping concentration of the second sub-drift layer is greater than the doping concentration of the first sub-drift layer; wherein the step of forming the second doping region includes: forming the second doping region in the second sub-drift layer and the first sub-drift layer, the second doping region includes a first sub-doping region and a second sub-doping region arranged in a direction perpendicular to the surface of the semiconductor substrate layer, the first sub-doping region is located in the second sub-drift layer, the second sub-doping region is located in the first sub-drift layer, and the size of the first sub-doping region along the second direction is smaller than the size of the second sub-doping region along the second direction.

[0020] Optionally, the step of forming the second doping region includes: forming a plurality of second sub-doping regions arranged at intervals along a direction perpendicular to the surface of the semiconductor substrate layer.

[0021] The technical solution of the present invention has the following technical effects:

[0022] The semiconductor power device provided by the technical solution of the present invention has the same conductivity type as the drift layer, the doping concentration of the first doping region is greater than the doping concentration of the drift layer, the first doping region surrounds the side wall and part of the bottom wall of the gate structure along the second direction, and the first doping region is used to provide a forward conduction path to reduce the forward conduction resistance. The conductivity type of the second doping region is opposite to that of the first doping region, and the second doping region surrounds the side wall and part of the bottom wall of the gate structure along the other side of the second direction. When the semiconductor power device is in reverse withstand voltage, the second doping region and the drift layer at the bottom of the second doping region will form a PN junction, and part of the electric field peak will be transferred to the junction of the PN junction. The PN junction protects the gate dielectric layer at the bottom of the gate structure, so that the shielding effect of the second doping region on the electric field is enhanced, the electric field strength at the position of the gate dielectric layer is reduced, and the protective effect of the second doping region on the gate dielectric layer is enhanced. The first doping region is spaced from the well region to avoid contact between the first doping region and the well region, thereby avoiding the first doping region and the well region from generating a high electric field in the contact area. The second doping region is spaced from the well region to reduce the channel length and the channel resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A three-dimensional schematic diagram of a semiconductor power device provided by an embodiment of the present invention;

[0025] Figure 2 for Figure 1 A top view of the first doped region and the second doped region;

[0026] Figure 3 For along Figure 1 Sectional view of the middle cutting line A1-A2;

[0027] Figure 4 A three-dimensional schematic diagram of a semiconductor power device provided by another embodiment of the present invention;

[0028] Figure 5 for Figure 4 A top view of the first doped region and the second doped region;

[0029] Figure 6 A schematic diagram of a semiconductor power device provided by another embodiment of the present invention;

[0030] Figure 7 A schematic diagram of a semiconductor power device provided by another embodiment of the present invention;

[0031] Figure 8 A schematic diagram of a semiconductor power device provided by another embodiment of the present invention;

[0032] Fig. 9 A schematic diagram of a semiconductor power device provided by another embodiment of the present invention;

[0033] Figures 10 to 12 A structural diagram of a semiconductor power device manufacturing process provided by an embodiment of the present invention;

[0034] Figures 13 to 15 A structural diagram of a semiconductor power device manufacturing process provided by an embodiment of the present invention;

[0035] Figures 16 to 21 A structural diagram of a semiconductor power device manufacturing process provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0036] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0038] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0039] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0040] Example 1

[0041] This embodiment provides a semiconductor power device, referring to Figure 1 and Figure 4 ,include:

[0042] Semiconductor substrate layer 100;

[0043] A drift layer 110 located on the semiconductor substrate layer 100;

[0044] A gate structure 160 located in the drift layer 110 and extending along a first direction Y;

[0045] The well regions 120 are respectively located in the drift layer 110 on both sides of the gate structure 160 along a second direction X, where the second direction X is perpendicular to the first direction Y;

[0046] A first doping region 171 and a second doping region 172 are arranged at intervals along the second direction X in the drift layer 110 located on the side of the well region 120 facing the semiconductor substrate layer 100, wherein the conductivity type of the first doping region 171 is the same as the conductivity type of the drift layer 110 and is opposite to the conductivity type of the second doping region 172, and the doping concentration of the first doping region 171 is greater than the doping concentration of the drift layer 110; the first doping region 171 surrounds the side wall and part of the bottom wall of the gate structure 160 on one side along the second direction X, and the second doping region 172 surrounds the side wall and part of the bottom wall of the gate structure 160 on the other side along the second direction X, and the first doping region 171 and the second doping region 172 are both spaced from the well region 120.

[0047] In this embodiment, the conductivity type of the first doping region 171 is the same as that of the drift layer 110, the doping concentration of the first doping region 171 is greater than that of the drift layer 110, the first doping region 171 surrounds the side wall and part of the bottom wall of the gate structure 160 along the second direction X, and the first doping region 171 is used to provide a forward conduction path to reduce the forward conduction resistance. The conductivity type of the second doping region 172 is opposite to that of the first doping region 171, and the second doping region 172 surrounds the side wall and part of the bottom wall of the gate structure 160 along the other side of the second direction X. When the semiconductor power device is in reverse withstand voltage, the second doping region 172 and the drift layer 110 at the bottom of the second doping region 172 will form a PN junction, and part of the electric field peak will be transferred to the junction of the PN junction. The PN junction protects the gate dielectric layer at the bottom of the gate structure 160, so that the shielding effect of the second doping region 172 on the electric field is enhanced, the electric field strength at the position of the gate dielectric layer 161 is reduced, and the protection effect of the second doping region 172 on the gate dielectric layer 161 is enhanced. The first doping region 171 is spaced from the well region 120 to avoid contact between the first doping region 171 and the well region 120, thereby avoiding a high electric field generated in the contact region between the first doping region 171 and the well region 120. The second doping region 172 is spaced from the well region 120, thereby reducing the channel length and the channel resistance.

[0048] In this embodiment, the new generation of SiC-based semiconductor power devices represented by SiC have higher reverse withstand voltage, lower forward conduction loss, faster switching frequency and stronger environmental tolerance compared to Si-based semiconductor power devices, and are therefore considered to be a new hope in the field of power conversion. It should be noted that in this embodiment, the semiconductor substrate layer 100 is silicon carbide (SiC) doped with conductive ions. In one embodiment, the conductive ions in the semiconductor substrate layer 100 are N-type ions. In other embodiments, there is no restriction on the conductivity type of the semiconductor substrate layer 100.

[0049] In one embodiment, the conductivity type of the drift layer 110 is the same as the conductivity type of the semiconductor substrate layer 100, and the doping concentration of the drift layer 110 is less than the doping concentration of the semiconductor substrate layer 100. In one embodiment, the material of the drift layer 110 is silicon carbide doped with N-type conductive ions. The N-type conductive ions may be phosphorus ions or nitrogen ions.

[0050] The conductivity type of the well region 120 is opposite to the conductivity type of the drift layer 110. In this embodiment, when the conductivity type of the drift layer 110 is N-type, the conductivity type of the well region 120 is P-type.

[0051] In this embodiment, the semiconductor power device further includes: a first source region 140 located in the well region 120, the conductivity type of the first source region 140 being opposite to the conductivity type of the well region 120. In this embodiment, when the conductivity type of the well region 120 is P-type, the conductivity type of the first source region 140 is N-type; a second source region 150 located in the well region 120, the second source region 150 is in contact with the first source region 140, and the conductivity type of the second source region 150 is opposite to the conductivity type of the first source region 140. In one embodiment, the conductivity type of the second source region 150 is P-type, and the conductivity type of the first source region 140 is N-type.

[0052] In this embodiment, the gate structure 160 includes a gate electrode layer 162 and a gate dielectric layer 161, and the gate dielectric layer 161 is located on the sidewall surface and the bottom surface of the gate electrode layer 162. The material of the gate dielectric layer 161 includes silicon oxide. The material of the gate electrode layer 162 includes polysilicon or metal gate material.

[0053] The width direction of the gate structure 160 is parallel to the second direction X. The length direction of the gate structure 160 is parallel to the first direction Y.

[0054] The number of the gate structure 160 is one or more. When the number of the gate structure 160 is multiple, the multiple gate structures 160 are arranged along the second direction X at intervals.

[0055] The conductivity type of the first doping region 171 is the same as the conductivity type of the drift layer 110 and opposite to the conductivity type of the second doping region 172. When the conductivity type of the drift layer 110 is N-type, the conductivity type of the first doping region 171 is N-type, and the conductivity type of the second doping region 172 is P-type.

[0056] In one embodiment, the doping concentration of the first doping region 171 is 2 to 8 times, for example, 2 times, 4 times, 6 times, or 8 times, the doping concentration of the drift layer 110 .

[0057] In other embodiments, the doping concentration of the first doping region 171 is not limited.

[0058] In one embodiment, the doping concentration of the second doping region 172 is less than the doping concentration of the well region 120. The advantage is that the electric field strength at the initial depletion position of the PN junction between the second doping region 172 and the drift layer 110 at the bottom of the second doping region 172 is prevented from being too high at the junction when reverse biased, thereby preventing the PN junction from breaking down prematurely.

[0059] In one embodiment, the doping concentration of the well region 120 is 2 to 5 times, for example, 2 times, 2 times, 3 times, or 5 times, the doping concentration of the second doping region 172 .

[0060] In other embodiments, the doping concentration of the second doping region 172 is not limited.

[0061] If the spacing distance between the first doping region 171 and the well region 120 along the direction Z perpendicular to the surface of the semiconductor substrate layer 100 is too small, it is difficult to control the distance in the process, and there is a risk of contact between the first doping region 171 and the well region 120, and the PN junction junction near the first doping region 171 and the well region 120 is prone to premature breakdown due to the high electric field during reverse depletion; if the spacing distance between the first doping region 171 and the well region 120 along the direction Z perpendicular to the surface of the semiconductor substrate layer 100 is too large, the electron expansion ability of the first doping region 171 during forward conduction becomes weak, and the conduction gain effect becomes weak. In summary, in one embodiment, the spacing distance between the first doping region 171 and the well region 120 along the direction Z perpendicular to the surface of the semiconductor substrate layer 100 is 0.2 microns to 0.6 microns, 0.2 microns, 0.3 microns, 0.4 microns, 0.5 microns or 0.6 microns.

[0062] In other embodiments, there is no limitation on the spacing distance between the first doping region 171 and the well region 120 along the direction Z perpendicular to the surface of the semiconductor substrate layer 100 .

[0063] If the spacing distance between the second doping region 172 and the well region 120 along the direction Z perpendicular to the surface of the semiconductor substrate layer 100 is too small, it is difficult to control the distance in the process, and there is a risk of contact between the second doping region 172 and the well region 120, and the space between the second doping region 172 and the well region 120 is small, which is not conducive to reducing the resistance of the current path; if the spacing distance between the second doping region 172 and the well region 120 along the direction Z perpendicular to the surface of the semiconductor substrate layer 100 is too large, the area of ​​the sidewall of the gate structure 160 exposed by the second doping region 172 is large, and the degree of enhancing the protection of the gate dielectric layer is small. In summary, in one embodiment, the spacing distance between the second doping region 172 and the well region 120 along the direction Z perpendicular to the surface of the semiconductor substrate layer 100 is 0.2 micrometers to 0.6 micrometers, for example, 0.2 micrometers, 0.3 micrometers, 0.4 micrometers, 0.5 micrometers or 0.6 micrometers.

[0064] In other embodiments, there is no limitation on the spacing distance between the second doping region 172 and the well region 120 along the direction Z perpendicular to the surface of the semiconductor substrate layer 100 .

[0065] The first doping region 171 and the second doping region 172 are arranged at intervals to avoid the first doping region 171 and the second doping region 172 from contacting each other and thus to avoid the first doping region 171 and the second doping region 172 from generating a high electric field in the contacting region.

[0066] If the size of the bottom surface of the gate structure 160 between the first doping region 171 and the second doping region 172 adjacent to each other along the second direction X is too small, it is difficult to control the size in the process, and there is a risk of contact between the first doping region 171 and the second doping region 172, which may easily cause the electric field strength at the PN junction interface near the first doping region 171 and the second doping region 172 to be too high, and the PN junction has the risk of premature breakdown; if the size of the bottom surface of the gate structure 160 between the first doping region 171 and the second doping region 172 adjacent to each other along the second direction X is too large, the area of ​​the bottom surface of the gate structure 160 exposed by the first doping region 171 and the second doping region 172 is large, and the degree of improvement in the protection of the gate dielectric layer is weak. In one embodiment, a size of a bottom surface of the gate structure 160 between the first doping region 171 and the second doping region 172 adjacent to each other along the second direction X along the second direction X is 0.2 micrometers to 0.8 micrometers, for example, 0.2 micrometers, 0.3 micrometers, 0.4 micrometers, 0.5 micrometers, 0.6 micrometers, 0.7 micrometers or 0.8 micrometers.

[0067] In other embodiments, the size of the bottom surface of the gate structure 160 between the first doping region 171 and the second doping region 172 adjacent to each other along the second direction X is not limited.

[0068] In one embodiment, in combination with reference 1 to Figure 5 , each of the second doping regions 172 is an integral structure.

[0069] In one embodiment, in combination with reference 4 and Figure 5 , the first doping region 171 and the second doping region 172 both extend along the first direction Y. The first doping region 171 and the second doping region 172 are both strip-shaped structures.

[0070] In one embodiment, in combination with reference 1 to Figure 3 The first doping regions 171 and the second doping regions 172 are also alternately arranged along the first direction Y. The first doping regions 171 and the second doping regions 172 are alternately arranged along the second direction X and alternately arranged along the first direction Y. The first doping regions 171 and the second doping regions 172 are arranged in an array.

[0071] Further, combined with reference Figure 1 and Figure 2 The first doping regions 171 and the second doping regions 172 are arranged alternately along the second direction X, and the first doping regions 171 and the second doping regions 172 are also arranged alternately along the first direction Y.

[0072] In one embodiment, in conjunction with reference Figure 1 and Figure 2 , the sidewall of the gate structure 160 on one side along the second direction X is surrounded by a portion of the first doping region 171 and a portion of the second doping region 172, and the sidewall of the gate structure 160 on the other side along the second direction X is surrounded by a portion of the first doping region 171 and a portion of the second doping region 172. In this way, the gate structure 160 has a forward conductive channel on both sides of the second direction X, and the current distribution is more uniform.

[0073] If the size of the bottom surface of the gate structure 160 between the first doping region 171 and the second doping region 172 adjacent to each other along the first direction Y is too small, it is difficult to control the size in the process, and there is a risk of contact between the first doping region 171 and the second doping region 172, which may easily cause the electric field strength at the PN junction junction near the first doping region 171 and the second doping region 172 to be too high, and the PN junction has the risk of premature breakdown; if the size of the bottom surface of the gate structure 160 between the first doping region 171 and the second doping region 172 adjacent to each other along the first direction Y is too large, the area of ​​the bottom surface of the gate structure 160 exposed by the first doping region 171 and the second doping region 172 is large, and the degree of improvement in the protection of the gate dielectric layer is weak. In one embodiment, the size of the bottom surface of the gate structure 160 between the first doping region 171 and the second doping region 172 adjacent to each other along the first direction Y is 0.2 micrometers to 0.8 micrometers, such as 0.2 micrometers, 0.3 micrometers, 0.4 micrometers, 0.5 micrometers, 0.6 micrometers, 0.7 micrometers or 0.8 micrometers. In this embodiment, the semiconductor power device further includes: a drain 101, located on the side of the semiconductor substrate layer 100 away from the drift layer 110; a front electrode 190, located on the second source region 150 and a portion of the first source region 140; an isolation layer 180, covering the gate structure 160 and a portion of the first source region 140, and the isolation layer 180 isolates the front electrode 190 from the gate structure 160. The material of the isolation layer 180 includes silicon oxide.

[0074] Example 2

[0075] This embodiment provides a semiconductor power device. The difference between this embodiment and embodiment 1 is that: Figure 6 The second doping region 172 includes a plurality of second sub-doping regions 1721 arranged at intervals along a direction Z perpendicular to the surface of the semiconductor substrate layer 100. The advantages are: reducing the peak voltage of the reverse recovery process, improving the reverse recovery performance of the semiconductor power device, and increasing the softness factor.

[0076] In one embodiment, the first doping region 171 and the second doping region 172 both extend along the first direction Y. The second sub-doping region 1721 extends along the first direction Y.

[0077] In one embodiment, the first doping regions 171 and the second doping regions 172 are arranged at intervals along the first direction Y and at intervals along the second direction X. The sidewall of the gate structure 160 on one side along the second direction X is surrounded by a portion of the first doping regions 171 and a portion of the second doping regions 172, and the sidewall of the gate structure 160 on the other side along the second direction X is surrounded by a portion of the first doping regions 171 and a portion of the second doping regions 172. Specifically, the sidewall of the gate structure 160 on one side along the second direction X is surrounded by a portion of the second sub-doping regions 1721 and a portion of the first doping regions 171, and the sidewall of the gate structure 160 on the other side along the second direction X is surrounded by a portion of the second sub-doping regions 1721 and a portion of the first doping regions 171.

[0078] In one embodiment, the bottom surface of the gate structure 160 between the first doping region 171 and the second doping region 172 adjacent to each other along the first direction Y is spaced from 0.2 micrometers to 0.8 micrometers along the first direction Y. The bottom surface of the gate structure 160 between the first doping region 171 and the second doping region 172 adjacent to each other along the second direction X is spaced from 0.2 micrometers to 0.8 micrometers along the second direction X.

[0079] The same contents between this embodiment and the previous embodiment 1 will not be described in detail.

[0080] Example 3

[0081] This embodiment provides a semiconductor power device. The difference between this embodiment and embodiment 1 is that: Figures 7 to 9 The second doping region 172 includes a first sub-doping region 1722 and a second sub-doping region 1721 arranged along a direction Z perpendicular to the surface of the semiconductor substrate layer 100, and the size of the first sub-doping region 1722 along the second direction X is smaller than the size of the second sub-doping region 1721 along the second direction X; wherein, with reference to Figure 8 , the sidewall and part of the bottom wall of the gate structure 160 on the other side along the second direction X are surrounded by the first sub-doping region 1722, or, with reference to Figure 7 and Fig. 9 , the sidewall and part of the bottom wall of the gate structure 160 on the other side along the second direction X are surrounded by the second sub-doping region 1721. The size of the first sub-doping region 1722 along the second direction X is smaller than the size of the second sub-doping region 1721 along the second direction X, thereby increasing the conduction path of electrons and reducing the on-resistance.

[0082] In one embodiment, the difference between the size of the second sub-doping region 1721 along the second direction X and the size of the first sub-doping region 1722 along the second direction X is 0.1 micrometers to 0.3 micrometers, for example, 0.1 micrometers, 0.2 micrometers or 0.3 micrometers. If the difference between the size of the second sub-doping region 1721 along the second direction X and the size of the first sub-doping region 1722 along the second direction X is too small, the degree of reducing the on-resistance is weak; if the difference between the size of the second sub-doping region 1721 along the second direction X and the size of the first sub-doping region 1722 along the second direction X is too large, the protection capability of the gate dielectric layer in the bottom area of ​​the gate structure will be reduced.

[0083] In one embodiment, the first sub-doping regions 1722 and the second sub-doping regions 1721 are alternately arranged along a direction Z perpendicular to the surface of the semiconductor substrate layer 100 .

[0084] The same contents between this embodiment and the previous embodiment 1 will not be described in detail.

[0085] Example 4

[0086] The present embodiment provides a method for preparing a semiconductor power device, comprising: forming a drift layer on a semiconductor substrate layer; forming a first doping region and a second doping region arranged at intervals along a second direction in the drift layer, wherein the conductivity type of the first doping region is the same as the conductivity type of the drift layer and is opposite to the conductivity type of the second doping region; forming a gate structure extending along a first direction in the drift layer; forming a well region in the drift layer, wherein the well regions are respectively located on both sides of the gate structure along the second direction, and the second direction is perpendicular to the first direction; the first doping region and the second doping region are located on a side of the well region facing the semiconductor substrate layer and are both spaced from the well region, the first doping region surrounds the side wall and a portion of the bottom wall of the gate structure on one side along the second direction, and the second doping region surrounds the side wall and a portion of the bottom wall of the gate structure on the other side along the second direction.

[0087] The following reference Figures 10 to 12 The preparation process of semiconductor power devices is introduced in detail.

[0088] refer to Fig.10 , a drift layer 110 is formed on a semiconductor substrate layer 100; a first doping region 171 and a second doping region 172 are formed in the drift layer 110 and are arranged at intervals along a second direction X, wherein the conductivity type of the first doping region 171 is the same as that of the drift layer 110 and is opposite to that of the second doping region 172.

[0089] The process of forming the first doping region 171 includes an ion implantation process. The process of forming the second doping region 172 includes an ion implantation process.

[0090] In one embodiment, the first doping region 171 and the second doping region 172 both extend along the first direction Y. The first doping region 171 and the second doping region 172 are both strip-shaped structures.

[0091] In one embodiment, the first doping regions 171 and the second doping regions 172 are arranged at intervals along the second direction X and at intervals along the first direction Y. The first doping regions 171 and the second doping regions 172 are arranged in an array. Further, the first doping regions 171 and the second doping regions 172 are arranged alternately at intervals along the second direction X, and the first doping regions 171 and the second doping regions 172 are also arranged alternately at intervals along the first direction Y.

[0092] refer to Fig.11 , a gate structure 160 extending along a first direction Y is formed in the drift layer 110; a well region 120 is formed in the drift layer 110, and the well regions 120 are respectively located on both sides of the gate structure 160 along a second direction X, and the second direction X is perpendicular to the first direction Y.

[0093] The first doping region 171 and the second doping region 172 are located on a side of the well region 120 facing the semiconductor substrate layer 100 and are both spaced apart from the well region 120. The first doping region 171 surrounds the side wall and a portion of the bottom wall of the gate structure 160 along one side of the second direction X, and the second doping region 172 surrounds the side wall and a portion of the bottom wall of the gate structure 160 along the other side of the second direction X.

[0094] In this embodiment, the method further includes: forming a first source region 140 in the well region 120 , wherein the conductivity type of the first source region 140 is opposite to that of the well region 120 ; forming a second source region 150 in the well region 120 ;

[0095] refer to Fig.12 , forming an isolation layer 180 covering the gate structure 160 and a portion of the first source region 140; forming a front electrode 190, the front electrode 190 is located on the second source region 150 and a portion of the first source region 140; and forming a drain 101 on the side of the semiconductor substrate layer 100 away from the drift layer 110.

[0096] Example 5

[0097] The following reference Figures 13 to 15 The preparation process of semiconductor power devices is introduced in detail.

[0098] refer to Fig.13, a drift layer 110 is formed on a semiconductor substrate layer 100; a first doping region 171 and a second doping region 172 are formed in the drift layer 110 and are arranged at intervals along a second direction X, wherein the conductivity type of the first doping region 171 is the same as that of the drift layer 110 and is opposite to that of the second doping region 172.

[0099] The process of forming the first doping region 171 includes an ion implantation process. The process of forming the second doping region 172 includes an ion implantation process.

[0100] In one embodiment, the first doping region 171 and the second doping region 172 both extend along the first direction Y. The first doping region 171 and the second doping region 172 are both strip-shaped structures.

[0101] In one embodiment, the first doping regions 171 and the second doping regions 172 are arranged at intervals along the second direction X and at intervals along the first direction Y. The first doping regions 171 and the second doping regions 172 are arranged in an array. Further, the first doping regions 171 and the second doping regions 172 are arranged alternately at intervals along the second direction X, and the first doping regions 171 and the second doping regions 172 are also arranged alternately at intervals along the first direction Y.

[0102] The difference between this embodiment and Embodiment 4 is that the step of forming the second doping region 172 includes: forming a plurality of second sub-doping regions 1721 arranged at intervals along a direction Z perpendicular to the surface of the semiconductor substrate layer 100 .

[0103] refer to Fig.14 , a gate structure 160 extending along a first direction Y is formed in the drift layer 110; a well region 120 is formed in the drift layer 110, and the well regions 120 are respectively located on both sides of the gate structure 160 along a second direction X, and the second direction X is perpendicular to the first direction Y; a first source region 140 is formed in the well region 120, and the conductivity type of the first source region 140 is opposite to the conductivity type of the well region 120; and a second source region 150 is formed in the well region 120.

[0104] refer to Fig.15 , forming an isolation layer 180 covering the gate structure 160 and a portion of the first source region 140; forming a front electrode 190, the front electrode 190 is located on the second source region 150 and a portion of the first source region 140; and forming a drain 101 on the side of the semiconductor substrate layer 100 away from the drift layer 110.

[0105] Example 6

[0106] The following reference Figures 16 to 19 The preparation process of semiconductor power devices is introduced in detail.

[0107] refer to Figures 16 to 18, forming a drift layer 110 on a semiconductor substrate layer 100, and forming the drift layer 110 on the semiconductor substrate layer 100 includes: forming a first sub-drift layer 1101 and a second sub-drift layer 1102 stacked in a direction perpendicular to the surface of the semiconductor substrate layer 100 on one side of the semiconductor substrate layer 100, the doping type of the second sub-drift layer 1102 is the same as the doping type of the first sub-drift layer 1101, and the doping concentration of the second sub-drift layer 1102 is greater than the doping concentration of the first sub-drift layer 1101. The semiconductor substrate layer 100 is in contact with the first sub-drift layer 1101.

[0108] refer to Fig.16 , step S1: forming an initial layer 110a on one side of the semiconductor substrate layer 100; referring to Fig.17 , step S2: performing ion implantation on a partial region of the initial layer 110 a to form a second sub-drift layer 1102 in the initial layer 110 a , and a region of the initial layer 110 a except the second sub-drift layer 1102 constitutes a first sub-drift layer 1101 .

[0109] refer to Fig.18 , repeat step S1 and step S2.

[0110] refer to Fig.19 , first doping regions 171 and second doping regions 172 are formed in the drift layer 110 and are arranged in a second direction X at intervals, and the conductivity type of the first doping regions 171 is the same as that of the drift layer 110 and is opposite to that of the second doping regions 172 .

[0111] The step of forming the second doping region 172 includes: forming the second doping region 172 in the second sub-drift layer 1102 and the first sub-drift layer 1101, the second doping region 172 includes a first sub-doping region 1722 and a second sub-doping region 1721 arranged in a direction perpendicular to the surface of the semiconductor substrate layer 100, the first sub-doping region 1722 is located in the second sub-drift layer 1102, the second sub-doping region 1721 is located in the first sub-drift layer 1101, and the size of the first sub-doping region 1722 along the second direction X is smaller than the size of the second sub-doping region 1721 along the second direction X.

[0112] The process of forming the first doping region 171 includes an ion implantation process.

[0113] In one embodiment, the first doping region 171 and the second doping region 172 both extend along the first direction Y. The first doping region 171 and the second doping region 172 are both strip-shaped structures.

[0114] In one embodiment, the first doping regions 171 and the second doping regions 172 are arranged at intervals along the second direction X and at intervals along the first direction Y. The first doping regions 171 and the second doping regions 172 are arranged in an array. Further, the first doping regions 171 and the second doping regions 172 are arranged alternately at intervals along the second direction X, and the first doping regions 171 and the second doping regions 172 are also arranged alternately at intervals along the first direction Y.

[0115] refer to Fig. 20 , a gate structure 160 extending along a first direction Y is formed in the drift layer 110; a well region 120 is formed in the drift layer 110, and the well regions 120 are respectively located on both sides of the gate structure 160 along a second direction X, and the second direction X is perpendicular to the first direction Y; a first source region 140 is formed in the well region 120, and the conductivity type of the first source region 140 is opposite to the conductivity type of the well region 120; and a second source region 150 is formed in the well region 120.

[0116] refer to Fig.21 , forming an isolation layer 180 covering the gate structure 160 and a portion of the first source region 140; forming a front electrode 190, the front electrode 190 is located on the second source region 150 and a portion of the first source region 140; and forming a drain 101 on the side of the semiconductor substrate layer 100 away from the drift layer 110.

[0117] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A semiconductor power device, characterized in that: include: Semiconductor substrate layer; a drift layer located on the semiconductor substrate layer; A gate structure located in the drift layer and extending along a first direction; Well regions are respectively located in the drift layer on both sides of the gate structure along a second direction, where the second direction is perpendicular to the first direction; A first doping region and a second doping region are arranged at intervals along the second direction in the drift layer located on the side of the well region facing the semiconductor substrate layer, wherein the conductivity type of the first doping region is the same as the conductivity type of the drift layer and is opposite to the conductivity type of the second doping region, and the doping concentration of the first doping region is greater than the doping concentration of the drift layer; the first doping region surrounds the side wall and part of the bottom wall of the gate structure on one side along the second direction, and the second doping region surrounds the side wall and part of the bottom wall of the gate structure on the other side along the second direction, and the first doping region and the second doping region are both spaced from the well region.

2. The semiconductor power device according to claim 1, characterized in that: The doping concentration of the first doping region is 2 to 8 times the doping concentration of the drift layer.

3. The semiconductor power device according to claim 1, characterized in that: The doping concentration of the second doping region is less than the doping concentration of the well region; Preferably, the doping concentration of the well region is 2 to 5 times the doping concentration of the second doping region.

4. The semiconductor power device according to claim 1, characterized in that: The spacing distance between the first doped region and the well region along the direction perpendicular to the surface of the semiconductor substrate layer is 0.2 micrometer to 0.6 micrometer; the spacing distance between the second doped region and the well region along the direction perpendicular to the surface of the semiconductor substrate layer is 0.2 micrometer to 0.6 micrometer.

5. The semiconductor power device according to claim 1, characterized in that: A size of a bottom surface of the gate structure between the first doping region and the second doping region adjacent to each other along the second direction is 0.2 micrometers to 0.8 micrometers along the second direction.

6. The semiconductor power device according to claim 1, characterized in that: The second doping region includes a plurality of second sub-doping regions arranged at intervals along a direction perpendicular to the surface of the semiconductor substrate layer.

7. The semiconductor power device according to claim 1, characterized in that: The second doping region includes a first sub-doping region and a second sub-doping region arranged in a direction perpendicular to the surface of the semiconductor substrate layer, and a size of the first sub-doping region along the second direction is smaller than a size of the second sub-doping region along the second direction; The sidewall and part of the bottom wall of the gate structure on the other side along the second direction are surrounded by the first sub-doping region, or the sidewall and part of the bottom wall of the gate structure on the other side along the second direction are surrounded by the second sub-doping region; Preferably, a difference between a size of the second sub-doping region along the second direction and a size of the first sub-doping region along the second direction is 0.1 micrometer to 0.3 micrometer.

8. The semiconductor power device according to claim 7, characterized in that: The first sub-doping regions and the second sub-doping regions are alternately arranged along a direction perpendicular to the surface of the semiconductor substrate layer.

9. The semiconductor power device according to claim 1, characterized in that: The first doping region and the second doping region both extend along the first direction.

10. The semiconductor power device according to claim 1, characterized in that: The first doping regions and the second doping regions are also arranged alternately and spaced along the first direction; A sidewall of the gate structure on one side along the second direction is surrounded by a portion of the first doping regions and a portion of the second doping regions, and a sidewall of the gate structure on the other side along the second direction is surrounded by a portion of the first doping regions and a portion of the second doping regions; Preferably, a size of a bottom surface of the gate structure between the first doping region and the second doping region adjacent to each other along the first direction is 0.2 micrometers to 0.8 micrometers along the first direction.

11. A method for preparing a semiconductor power device, characterized in that: include: forming a drift layer on the semiconductor substrate layer; forming a first doping region and a second doping region arranged in a second direction in the drift layer, wherein the conductivity type of the first doping region is the same as the conductivity type of the drift layer and opposite to the conductivity type of the second doping region; forming a gate structure extending along a first direction in the drift layer; forming a well region in the drift layer, wherein the well regions are respectively located on both sides of the gate structure along a second direction, and the second direction is perpendicular to the first direction; The first doped region and the second doped region are located on a side of the well region facing the semiconductor substrate layer and are both spaced apart from the well region; the first doped region surrounds the side wall and a portion of the bottom wall of the gate structure along one side of the second direction, and the second doped region surrounds the side wall and a portion of the bottom wall of the gate structure along the other side of the second direction.

12. The method for preparing a semiconductor power device according to claim 11, characterized in that: The step of forming the drift layer comprises: forming a first sub-drift layer and a second sub-drift layer stacked in a direction perpendicular to a surface of the semiconductor substrate layer on one side of the semiconductor substrate layer, wherein the doping type of the second sub-drift layer is the same as the doping type of the first sub-drift layer, and the doping concentration of the second sub-drift layer is greater than the doping concentration of the first sub-drift layer; Among them, the step of forming the second doping region includes: forming the second doping region in the second sub-drift layer and the first sub-drift layer, the second doping region includes a first sub-doping region and a second sub-doping region arranged in a direction perpendicular to the surface of the semiconductor substrate layer, the first sub-doping region is located in the second sub-drift layer, the second sub-doping region is located in the first sub-drift layer, and the size of the first sub-doping region along the second direction is smaller than the size of the second sub-doping region along the second direction.

13. The method for preparing a semiconductor power device according to claim 11, characterized in that: The step of forming the second doping region includes: forming a plurality of second sub-doping regions arranged at intervals along a direction perpendicular to the surface of the semiconductor substrate layer.

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