Formation method of semiconductor structure

Abstract

The invention provides a method for forming a semiconductor structure, and relates to the technical field of semiconductors. The forming method comprises the following steps: providing a substrate; a gate structure protruding out of the substrate is formed on the surface of the substrate, and the gate structure comprises a gate oxide layer, a gate and a gate protection layer; forming a first source-drain electrode and a second source-drain electrode in the substrate, wherein the first source-drain electrode and the second source-drain electrode are respectively located at two sides of the gate structure; and the gate protection layer is thinned in the direction from the side wall of the gate to the interior of the gate to expose a first sub-surface and a second sub-surface of the substrate, the first sub-surface is located between the gate structure and the first source-drain electrode, and the second sub-surface is located between the gate structure and the second source-drain electrode. The gate protection layer in the semiconductor structure is thinned, so that a large space can be provided for subsequent formation of the metal silicide film layer, the resistance of the metal silicide film layer is reduced, and the performance of the device is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] In the semiconductor field, metal silicide can significantly reduce resistance and improve the conductivity of current in the device when it contacts the source, drain or gate in the device. Therefore, forming a uniform and low-resistance metal silicide film layer is one of the important means to improve the performance of semiconductor devices.

[0003] At present, the formation of metal silicide is usually achieved by depositing a metal layer on the surface of a silicon-based material and then performing a high-temperature annealing process to allow the metal to react with silicon to form a metal silicide. However, due to the reduction in the characteristic size of the device, in the process of mutual diffusion of silicon ions in the silicon-based material and metal ions in the metal layer through a heat treatment process, the diffusion is inhibited by the film layer boundary, making it difficult to form a metal silicide film layer with uniform structure and low resistance.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In view of this, a method for forming a semiconductor structure is provided. By thinning the thickness of the gate protection layer in the semiconductor structure, the space for subsequent metal silicide film formation can be increased, the resistance of the metal silicide film can be reduced, and the performance of the device can be improved.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising:

[0008] providing a substrate;

[0009] A gate structure protruding from the surface of the substrate is formed on the surface of the substrate, the gate structure comprising a gate oxide layer, a gate and a gate protection layer, the gate oxide layer is formed on the substrate, the gate is formed on the gate oxide layer, and the gate protection layer is formed on the sidewall of the gate;

[0010] forming a first source-drain electrode and a second source-drain electrode in the substrate, wherein the first source-drain electrode and the second source-drain electrode are respectively located at two sides of the gate structure;

[0011] The gate protection layer is thinned along the direction from the side wall of the gate to the inside of the gate to expose the first sub-surface and the second sub-surface of the substrate, wherein the first sub-surface is located between the gate structure and the first source and drain, and the second sub-surface is located between the gate structure and the second source and drain.

[0012] In an exemplary embodiment of the present disclosure, the first sub-surface is flush with the surface of the first source and drain electrode; and the second sub-surface is flush with the surface of the second source and drain electrode.

[0013] In an exemplary embodiment of the present disclosure, the gate protection layer includes at least one insulating layer and at least one passivation layer, the insulating layer and the passivation layer are alternately arranged, and the passivation layer is formed on a side of the insulating layer away from the gate, and the gate protection layer is thinned, including:

[0014] The passivation layer having the largest distance from the gate is etched by wet etching to reduce the thickness of the gate protection layer.

[0015] In an exemplary embodiment of the present disclosure, the passivation layer is thinned to a thickness ratio of 30% to 70%.

[0016] In an exemplary embodiment of the present disclosure, the wet etching solution includes at least one of hydrofluoric acid, nitric acid, and phosphoric acid.

[0017] In an exemplary embodiment of the present disclosure, after the gate protection layer is thinned, the method further includes:

[0018] A metal silicide layer is formed, and the metal silicide layer is formed on the first surface, the surface of the gate, and the second surface respectively; wherein the first surface is a surface jointly formed by the first source and drain and the first sub-surface, and the second surface is a surface jointly formed by the second source and drain and the second sub-surface.

[0019] In an exemplary embodiment of the present disclosure, the forming of the metal silicide layer includes:

[0020] forming a metal layer, the metal layer conformally covering a surface of the gate structure, a surface formed by the first surface and the second surface;

[0021] Performing a first heat treatment on the metal layer to form a first sub-metal silicide layer on the top of the gate structure, the first surface, and the second surface, respectively;

[0022] The remaining metal layer is removed to form an intermediate semiconductor structure.

[0023] In an exemplary embodiment of the present disclosure, after forming the metal layer, the method further includes:

[0024] A barrier layer is formed, wherein the barrier layer conformally covers the surface of the metal layer.

[0025] In an exemplary embodiment of the present disclosure, after forming the first sub-metal silicide layer, the method further includes:

[0026] forming a stress layer, wherein the stress layer conformally covers the surface of the intermediate semiconductor structure;

[0027] The intermediate semiconductor structure having the stress layer is subjected to a second heat treatment so that the first sub-metal silicide layer forms a second sub-metal silicide layer to obtain a target semiconductor structure, wherein the temperature of the second heat treatment is higher than the temperature of the first heat treatment.

[0028] In an exemplary embodiment of the present disclosure, after performing a second heat treatment on the intermediate semiconductor structure having the stress layer, the method further includes:

[0029] forming an oxide layer, wherein the oxide layer covers the target semiconductor structure;

[0030] The oxide layer is planarized.

[0031] In an exemplary embodiment of the present disclosure, the semiconductor structure further includes an isolation structure, wherein the isolation structure is formed in the substrate and is located on a side of the first source and drain or the second source and drain away from the gate structure.

[0032] In an exemplary embodiment of the present disclosure, the method further includes:

[0033] An isolation layer is formed, wherein the isolation layer exposes the first surface, the second surface and the gate structure, and the isolation layer is used to protect the isolation structure.

[0034] In an exemplary embodiment of the present disclosure, after the gate protection layer is thinned, the method further includes:

[0035] The gate structure is cleaned by dry cleaning.

[0036] In an exemplary embodiment of the present disclosure, the method further includes:

[0037] An end of the gate protection layer away from the substrate is etched to expose a portion of the side wall of the gate.

[0038] The present invention provides a method for forming a semiconductor structure, by forming a gate structure on a substrate, and forming a first source and a second source and a drain on both sides of the gate structure respectively, and thinning the gate protection layer along the side wall of the gate in a direction pointing to the inside of the gate, and exposing a first sub-surface between the gate structure and the first source and a drain, and exposing a second sub-surface between the gate structure and the second source and a drain, thereby increasing the space provided for the formation of a metal silicide film layer in a subsequent device, which is conducive to forming a metal silicide film layer with a relatively small resistance value, overcoming the problem that the metal silicide film layer cannot form a uniform low-resistance phase due to process limitations, reducing the contact resistance of the device, and thereby improving the performance of the device.

[0039] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0041] Figure 1 The present invention discloses a flow chart of a method for forming a semiconductor structure in an exemplary embodiment.

[0042] Figure 2 It is a schematic diagram of a semiconductor structure in which a first photolithography layer is formed in an exemplary embodiment of the present disclosure.

[0043] Figure 3 A schematic diagram of a semiconductor structure during an ion implantation process in an exemplary embodiment of the present disclosure.

[0044] Figure 4 It is a schematic diagram of a semiconductor structure for forming a first source and a second source and a drain in an exemplary embodiment of the present disclosure.

[0045] Figure 5 It is a schematic diagram of a semiconductor structure for forming a first film layer in an exemplary embodiment of the present disclosure.

[0046] Figure 6 It is a schematic diagram of a semiconductor structure for forming a second film layer in an exemplary embodiment of the present disclosure.

[0047] Figure 7 It is a schematic diagram of a semiconductor structure in which a second photolithography layer is formed in an exemplary embodiment of the present disclosure.

[0048] Figure 8It is a schematic diagram of a semiconductor structure in which an isolation layer is formed in an exemplary embodiment of the present disclosure.

[0049] Fig. 9 It is a schematic diagram of a semiconductor structure with a thinned passivation layer in an exemplary embodiment of the present disclosure.

[0050] Fig.10 FIG. 4 is a schematic diagram of a semiconductor structure after cleaning in an exemplary embodiment of the present disclosure.

[0051] Fig.11 FIG. 1 is a schematic diagram of a semiconductor structure for forming a metal layer in an exemplary embodiment of the present disclosure.

[0052] Fig.12 It is a schematic diagram of a semiconductor structure for forming a barrier layer in an exemplary embodiment of the present disclosure.

[0053] Fig.13 It is a schematic diagram of a semiconductor structure for forming a first sub-metal silicide layer in an exemplary embodiment of the present disclosure.

[0054] Fig.14 FIG. 4 is a schematic diagram of a semiconductor structure for forming a second sub-metal silicide layer in an exemplary embodiment of the present disclosure.

[0055] Fig.15 FIG. 1 is a schematic diagram of a semiconductor structure in which an oxide layer is formed in an exemplary embodiment of the present disclosure.

[0056] The reference numerals are described as follows:

[0057] 100, substrate; 110, first source and drain; 120, second source and drain; 101, first sub-surface; 102, second sub-surface; 10, first surface; 20, second surface; 200, gate structure; 210, gate oxide layer; 220, gate; 230, gate protection layer; 231, insulating layer; 232, passivation layer; 300, metal silicide layer; 310, first sub-metal silicide layer; 320, second sub-metal silicide layer; 400, metal layer; 500, barrier layer; 600, stress layer; 700, oxide layer; 800, isolation structure; 801, isolation layer; 811, first film layer; 821, second film layer; 901, first photolithography layer; 902, second photolithography layer. DETAILED DESCRIPTION

[0058] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0059] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0060] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0061] In the related art, due to the increasing requirements for the degree of integration of semiconductor devices, the size of semiconductor devices is also constantly shrinking, which poses a huge challenge to the semiconductor process, especially with the reduction of feature size, the change in the performance of the film layer inside the device directly or indirectly changes the overall performance of the device. In the semiconductor structure, metal silicide is usually one of the indispensable film layers in semiconductor devices due to its characteristics of reducing contact resistance, improving thermal stability, and improving device performance. When it contacts the source, drain or gate in the device, it can significantly reduce resistance and improve the conductivity of current, which is crucial to the improvement of the overall electrical performance of the device; in addition, the metal silicide film layer has good thermal stability and is not easy to decompose or degrade in high-temperature processes. It also plays an important role in the semiconductor process. Therefore, it is necessary to ensure the formation of a uniform and low-resistance metal silicide film layer.

[0062] At present, the formation of metal silicide is usually carried out by depositing a metal layer on the surface of a silicon-based material, and then performing a high-temperature annealing process to allow the metal to react with silicon to form a metal silicide. However, due to the reduction in the characteristic size of the device, in the process of diffusing silicon ions in the silicon-based material to the formed metal silicide layer through a heat treatment process, the silicon ions are inhibited from diffusing by the film layer boundary, and it is difficult for the silicon ions to diffuse evenly into the formed metal silicide layer, so that the surface layer of the metal silicide layer is still in a high-resistance molecular structure, resulting in the inability to form a metal silicide film layer with a uniform structure and a small resistance value.

[0063] Based on this, the present disclosure provides a method for forming a semiconductor structure, such as Figure 1 As shown, combined Figures 2 to 15 The forming method includes: step S10 to step S40.

[0064] Wherein, step S10: providing a substrate 100;

[0065] Step S20: A gate structure 200 protruding from the surface of the substrate 100 is formed on the surface of the substrate 100, the gate structure 200 includes a gate oxide layer 210, a gate 220 and a gate protection layer 230, the gate oxide layer 210 is formed on the substrate 100, the gate 220 is formed on the gate oxide layer 210, and the gate protection layer 230 is formed on the sidewall of the gate 220;

[0066] Step S30: forming a first source-drain electrode 110 and a second source-drain electrode 120 in the substrate 100 , wherein the first source-drain electrode 110 and the second source-drain electrode 120 are respectively located on two sides of the gate structure 200 ;

[0067] Step S40: The gate protection layer 230 is thinned along the side wall of the gate 220 in a direction pointing to the inside of the gate 220 to expose the first sub-surface 101 and the second sub-surface 102 of the substrate 100, wherein the first sub-surface 101 is located between the gate structure 200 and the first source and drain 110, and the second sub-surface 102 is located between the gate structure 200 and the second source and drain 120.

[0068] The present invention provides a method for forming a semiconductor structure, by forming a gate structure 200 on the surface of a substrate 100, and forming a first source-drain electrode 110 and a second source-drain electrode 120 on both sides of the gate structure 200, respectively, and thinning the gate protection layer 230 along the direction of the side wall of the gate 220 pointing to the inside of the gate 220, and exposing the first sub-surface 101 between the gate structure 200 and the first source-drain electrode 110, and exposing the second sub-surface 102 between the gate structure 200 and the second source-drain electrode 120, thereby increasing the space provided for the formation of a metal silicide film layer in a subsequent device, which is conducive to forming a metal silicide film layer with a smaller resistance value, overcoming the problem that the metal silicide film layer cannot form a uniform low-resistance phase due to process limitations, reducing the contact resistance of the device, and thereby improving the performance of the device.

[0069] The following will describe in detail the steps of the method for forming a semiconductor structure provided by the embodiment of the present disclosure in conjunction with the accompanying drawings:

[0070] In the embodiments provided in the present disclosure, Figure 2 As shown, in step S10 and step S20, a substrate 100 is provided, and a gate structure 200 protruding from the surface of the substrate 100 is formed on the surface of the substrate 100, and the gate structure 200 includes a gate oxide layer 210, a gate 220 and a gate protection layer 230, the gate oxide layer 210 is formed on the substrate 100, the gate 220 is formed on the gate oxide layer 210, and the gate protection layer 230 is formed on the side wall of the gate 220.

[0071] Wherein, the substrate 100 may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a germanium silicon (GeSi) substrate, SOI (Silicon On Insulator), SOS (Silicon-on-Sapphire) or GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, for example, silicon carbide (SiC), indium phosphide (InP) or gallium arsenide (GaAs). The embodiments provided in the present disclosure are described by taking the substrate 100 as a silicon (Si) substrate as an example. Of course, for other types of substrates 100, corresponding deformations or improvements can be made to the embodiments of the present disclosure, all of which are within the protection scope of the present disclosure.

[0072] A gate structure 200 is formed on the surface of the substrate 100. The gate structure 200 includes a gate oxide layer 210. The gate oxide layer 210 is formed on the substrate 100. The gate oxide layer 210 may be silicon dioxide (SiO 2 ) or other high-K dielectric material layers, such as hafnium oxide (HfO2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ) or yttrium oxide (Y 2 O 3 ) or more thereof. It may be formed by one or more of methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, molecular beam epitaxy (MBE) or plasma enhanced chemical vapor deposition (PECVD). The specific formation method may be adaptively selected and adjusted according to the material and other characteristics of the gate oxide layer 210.

[0073] The gate structure 200 also includes a gate 220, which is formed on the gate oxide layer 210. The gate 220 is formed on the surface of the gate oxide layer 210, and the gate 220 can be polysilicon (poly) or other metal materials, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), cobalt (Co), nickel (Ni), ruthenium (Ru) or iridium (Ir) One or more. It can be formed by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALE), sputtering, photolithography or etching, etc., and can be selected according to the material and other characteristics of the gate 220. In the embodiment provided in the present disclosure, the gate 220 is polysilicon as an example for explanation, but it should be noted that the gate 220 of the present disclosure can also be made of materials other than polysilicon.

[0074] The gate structure 200 also includes a gate protection layer 230, which is formed on the side wall of the gate 220. The gate protection layer 230 may include at least one insulating layer 231 and at least one passivation layer 232 formed in sequence along the side wall direction away from the gate 220. Of course, the gate protection layer 230 may also be formed by one insulating layer 231 or one passivation layer 232 according to the actual structural requirements of the device. If there are multiple insulating layers 231 and passivation layers 232, the multiple insulating layers 231 and the multiple passivation layers 232 are alternately distributed on the side wall of the gate 220 in sequence along the side wall direction away from the gate 220, and the film layer farthest from the side wall of the gate 220 is the passivation layer 232. In the embodiment of the present disclosure, the gate protection layer 230 is a multi-layer structure as an example for description.

[0075] The insulating layer 231 in the gate protection layer 230 may be silicon dioxide (SiO 2 ) or other high dielectric constant material layers, such as hafnium oxide (HfO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ) or yttrium oxide (Y 2 O 3 ) or more thereof. It may be formed by one or more of methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). The specific formation method may be adaptively selected and adjusted according to the material and other characteristics of the insulating layer 231.

[0076] The passivation layer 232 may be silicon nitride (Si 3 N 4 ) and other materials, which can be formed by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) and other methods. Of course, the material of the passivation layer 232 can also be formed by other materials and process methods according to the actual structural requirements of the device.

[0077] In the embodiments provided in the present disclosure, Figure 4 As shown, in step S30 , a first source-drain electrode 110 and a second source-drain electrode 120 are formed in the substrate 100 , and the first source-drain electrode 110 and the second source-drain electrode 120 are respectively located on two sides of the gate structure 200 .

[0078] Among them, the semiconductor structure composed of the gate 220, the first source and drain 110 and the second source and drain 120 can be an NMOS (N-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor field effect transistor) device structure, a PMOS (Positive-channel-Metal-Oxide-Semiconductor, P-type metal oxide semiconductor field effect transistor) device structure or a CMOS (Complementary Metal-Oxide-Semiconductor, complementary metal-oxide-semiconductor) device structure.

[0079] When the semiconductor structure is an NMOS device structure, the substrate 100 can be a P-type silicon substrate, and an N-type well or an N-type isolation region is formed on the substrate 100; two high-concentration N-type regions are formed in the N-type well by ion implantation or diffusion process to form a source or drain.

[0080] When the semiconductor structure is a PMOS device structure, the substrate 100 may be a P-type silicon substrate, an epitaxial layer is formed on the substrate 100, and the epitaxial layer may be N-type; an N-type well or an N-type isolation region is formed in the epitaxial layer by ion implantation or diffusion process; two high-concentration P-type regions are formed in the N-type well by ion implantation or diffusion process to form a source or a drain. If the initial device structure is PMOS, it can be understood that the substrate 100 proposed in this article includes the epitaxial layer required to form PMOS.

[0081] Of course, the semiconductor structure can also be a CMOS device structure, and its formation method can be analogous to the formation method of PMOS or NMOS, or the combination of the above two formation methods can be adaptively deformed to obtain the formation process of the CMOS device structure, which will not be described in detail here. The embodiments provided in the present disclosure are described using the PMOS device structure as an example, but it should be noted that when the semiconductor structure is a device structure of different types, it can be formed by the formation method provided in the present disclosure after adaptive deformation.

[0082] In the present disclosure, the first source drain 110 and the second source drain 120 are located on both sides of the gate structure 200, which means that the edges of the first source drain 110 and the edges of the second source drain 120 are respectively adjacent to the outer edges of the side walls of the gate structure 200, that is, there is no gap or the gap is very small and can be ignored between the first source drain 110, the second source drain 120 and the outer edge of the gate structure 200.

[0083] Among them, Figure 3 and Figure 4As shown, forming the first source and drain 110 and the second source and drain 120 may include: forming a first photolithography layer 901 on a substrate 100 having a gate structure 200, the first photolithography layer 901 exposing a first region and a second region, wherein the first region is used to form the first source and drain 110, and the second region is used to form the second source and drain 120; performing ion implantation on the first region and the second region to form the first source and drain 110 and the second source and drain 120 in the first region and the second region, respectively; and removing the first photolithography layer 901.

[0084] In the embodiment provided in the present disclosure, the semiconductor structure further includes an isolation structure 800, which is formed in the substrate 100. The isolation structure 800 is located on the side of the substrate 100 where the first source and drain 110 or the second source and drain 120 is away from the gate structure 200. At least one semiconductor structure can be formed on the substrate 100. If there are multiple semiconductor structures, the multiple semiconductor structures can be arranged at intervals and distributed in an array. Adjacent semiconductor structures and semiconductor structures and other devices or regions can be electrically isolated by the isolation structure 800. The isolation structure 800 can be a shallow trench isolation structure, such as Figure 2 As shown, the distribution form of the semiconductor structures and the distance between adjacent semiconductor structures can be selected according to the actual design requirements of the device.

[0085] The method for forming the isolation structure 800 on the substrate 100 may include: defining a region for forming the isolation structure 800 on the substrate 100 by photolithography, and etching a shallow trench in the defined region by dry or wet etching; filling the shallow trench with an insulating material, such as silicon oxide (SiO 2 ) to form an isolation film layer in the shallow trench; and then perform a planarization process to expose the surface of the substrate 100. The number of the isolation structure 800 is at least one, and when the number is multiple, the multiple isolation structures 800 can be distributed in an array on the substrate 100. By providing the isolation structure 800 on the substrate 100, current leakage between devices can be effectively prevented, and the performance and reliability of the device can be improved.

[0086] In order to prevent the subsequent processes from damaging or destroying the non-reactive regions such as the isolation structure 800, after forming the above structure, the formation method further includes: forming an isolation layer 801, the isolation layer 801 exposes the first surface 10, the second surface 20 and the gate structure 200, and the isolation layer 801 is used to protect the isolation structure 800. The first surface 10 includes the surface of the first source and drain 110, and the second surface 20 includes the surface of the second source and drain 120.

[0087] like Figure 5 , Figure 6 , Figure 7 and Figure 8As shown, the method for forming the isolation layer 801 may include: sequentially forming a first film layer 811 and a second film layer 821 on the surface of the substrate 100, as shown in FIG. Figure 6 As shown, the first film layer 811 conformally covers the surfaces of the gate structure 200, the first source and drain electrodes 110 and the second source and drain electrodes 120 and other regions of the substrate 100; a second photolithography layer 902 is formed on the isolation layer 801, as shown in FIG. Figure 7 As shown; using the second photolithography layer 902 as a mask, the isolation layer 801 located on the surface of the gate structure 200, the first source and drain 110 and the second source and drain 120 is removed to expose the surface of the gate structure 200, the first source and drain 110 and the second source and drain 120, as shown Figure 8 As shown, the second photolithography layer 902 is removed. Among them, the isolation layer 801 can be used to protect the device structure such as the shallow trench isolation structure 800, so as to prevent the subsequent process from affecting the isolation structure 800, causing the adjacent device structures to be electrically connected, thereby damaging the overall performance of the device.

[0088] The first film layer 811 may be silicon dioxide (SiO 2 ) film layer, the second film layer 821 can be silicon nitride (Si 3 N 4 ). The first film layer 811 and the second film layer 821 can be formed by one or more methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). Dry etching or wet etching process can be used to remove part of the first film layer 811 and the second film layer 821, and the specific process can be selected according to the actual process design requirements.

[0089] In the embodiment provided in the present disclosure, after forming the gate structure 200, the formation method may further include: etching the end of the gate protection layer 230 away from the substrate 100 to expose a portion of the sidewall of the gate 220. Since it is necessary to form a metal silicide layer 300 on the top of the gate 220 in the subsequent process, that is, it is necessary to diffuse the ions required to form the metal silicide layer 300 to the top of the gate 220 through processes such as ion diffusion, in order to further increase the line width of the gate 220, that is, the effective width of the gate 220 to form the metal silicide layer 300, the gate protection layer 230 located on the top of the gate 220 can be removed to expose a portion of the sidewall of the gate 220, and the line width of the gate 220 can be increased by this method.

[0090] Specifically, a portion of the gate protection layer 230 on the top of the gate 220 can be etched away in a direction close to the substrate 100 by an etching process. For example, a portion of the gate protection layer 230 can be removed by dry etching or wet etching. Since the insulating layer 231 and the passivation layer 232 are made of different materials, the etching selectivity of the two layers under the same process conditions is different. It is difficult to ensure that the sizes of the insulating layer 231 and the passivation layer 232 removed are the same or substantially the same by the same process. Therefore, two or more steps of processing can be used to remove the insulating layer 231 and the passivation layer 232 respectively, so as to achieve the purpose of exposing the side wall of the gate 220. The specific etching process can be selected according to the actual process requirements. Of course, in order to further increase the formation area of ​​the metal silicide on the gate structure 200, the gate protection layer 230 can continue to be etched to further remove the gate protection layer 230 and increase the exposed area of ​​the side wall of the gate 220. For example, multiple etchings can be used to remove part of the gate protection layer 230, wherein the exposed height of the side wall of the gate 220 can be 10% to 30% of the overall height of the gate 220.

[0091] The inventors found that in order to reduce the influence of the line width effect on the formation of the metal silicide film layer, it is necessary to increase the line width of the source, drain and gate 220. However, due to the current requirements for device miniaturization, the line width of each structure of the device is actually getting smaller and smaller as the degree of device integration increases, and the purpose of increasing the line width cannot be achieved. In particular, the formation space provided for the metal silicide film layer on the source and drain is also gradually decreasing. Due to the influence of the line width effect, that is, the inhibition of diffusion by the boundary, silicon ions are difficult to diffuse into the gate structure 200, the first source and drain 110 and the second source and drain 120, resulting in the metal silicide layer 300 formed on the surface close to the gate structure 200, the first source and drain 110 and the second source and drain 120 still existing in the form of a high resistance phase, and it is impossible to form a metal silicide film layer with good performance and low resistance. The use of increasing the temperature to promote the diffusion of silicon ions in the related art will cause the metal silicide to agglomerate, forming agglomeration defects, and the metal silicide film layer will be broken and cannot be used.

[0092] Therefore, in order to improve the quality of the film layer formed in the subsequent process, such as Fig. 9 and Fig.10 As shown, in step S40, the gate protection layer 230 is thinned along the side wall of the gate 220 in a direction pointing to the inside of the gate 220 to expose the first sub-surface 101 and the second sub-surface 102 of the substrate 100, wherein the first sub-surface 101 is located between the gate structure 200 and the first source and drain 110, and the second sub-surface 102 is located between the gate structure 200 and the second source and drain 120.

[0093] The thinning process of the gate protection layer 230 may include etching the passivation layer 232 which is the largest distance from the gate 220 by wet etching to reduce the thickness of the gate protection layer 230. In order to ensure the protection effect of the gate protection layer 230 on the gate 220 and reduce the thickness of the gate protection layer 230, the passivation layer 232 located on the outermost side may be etched after the gate protection layer 230 is formed to reduce the thickness of the gate protection layer 230.

[0094] Among them, the first sub-surface 101 is flush with the surface of the first source and drain 110, and the second sub-surface 102 is flush with the surface of the second source and drain 120. The line width of the first source and drain 110 is increased by the first sub-surface 101, and the line width of the second source and drain 120 is increased by the second sub-surface 102, providing a good device foundation for the formation of subsequent film layers.

[0095] It should be noted that due to process limitations, when thinning the gate protection layer 230, the etching solution or etching gas may damage the exposed surface of the substrate 100, so that the first sub-surface 101 is lower than the surface of the first source and drain 110, and the second sub-surface 102 is lower than the surface of the second source and drain 120, forming a first recess between the first source and drain 110 and the gate structure, and a second recess between the second source and drain 120 and the gate structure, wherein lower than means closer to the substrate 100, but it should be understood that the first recess and the second recess are both within the scope of protection of the present disclosure within the range allowed by the process error.

[0096] Among them, the first sub-surface 101 is exposed and the second sub-surface is exposed. When the first sub-surface 101 is flush with the surface of the first source and drain 110, and the second sub-surface 102 is flush with the surface of the second source and drain 120, it can refer to the first sub-surface 101 and the second sub-surface 102 in the direction parallel to the substrate after the gate protection layer 230 is thinned. When the first sub-surface 101 is lower than the surface of the first source and drain 110, and the second sub-surface 102 is lower than the surface of the second source and drain 120, it can refer to the surface of the first recess and the second recess exposed after the gate protection layer 230 is thinned.

[0097] The thinning thickness ratio of the passivation layer 232 is 30% to 70%, that is, the thickness of the outermost passivation layer 232 after thinning is 70% to 30% of the thickness of the outermost passivation layer 232 before thinning. For example, the thinning thickness ratio of the passivation layer 232 can be 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, etc.

[0098] In some embodiments, if the thickness of the passivation layer 232 before thinning can be 10nm to 100nm, the thickness of the passivation layer 232 after thinning can be 3nm to 70nm. In some specific embodiments, the thickness of the passivation layer 232 before thinning is 20nm, and the thickness of the passivation layer 232 after thinning is 6nm to 14nm; the thickness of the passivation layer 232 before thinning is 50nm, and the thickness of the passivation layer 232 after thinning is 15nm to 35nm; the thickness of the passivation layer 232 before thinning is 80nm, and the thickness of the passivation layer 232 after thinning is 24nm to 56nm, and so on. The thickness of the passivation layer 232 after thinning can be determined according to the thickness of the passivation layer 232 before thinning. Of course, the thickness range of the passivation layer 232 cited in the above embodiments will become thinner as the process progresses. At this time, it can also be formed according to the formation method provided by the present disclosure.

[0099] Since the insulating layer 231 and the passivation layer 232 in the gate protection layer 230 are made of different materials, in the same process, the selective etching ratios of the two are different, and the etching rates of the same etching solution are different. Therefore, in order to ensure effective removal of the passivation layer 232 and protect the insulating layer 231, the passivation layer 232 can be etched by wet etching, wherein the wet etching solution can include hydrofluoric acid (HF), nitric acid (HNO 3 ), phosphoric acid (H 3 PO 4 ) at least one of the following. 3 PO 4 ) is used to etch the passivation layer 232, the passivation layer 232 is made of silicon nitride, and the reaction process between the two may include SiN x +yH 3 PO 4 →SiPO 4 +NH 3 +H 2 O, wherein x is greater than 0, y is greater than 0, x and y can be adaptively adjusted according to the ratio between the elements in the specific process of the reaction, and the reaction process of other solutions and silicon nitride is not listed here. The above solution can be used to remove the passivation layer 232 while retaining the insulating layer 231, avoiding damage to the protective effect of the gate protection layer 230 on the gate 220.

[0100] The formation method provided by the present disclosure can etch the passivation layer 232 of the outermost layer of the gate protection layer 230. On the one hand, in the subsequent process, the line width of the source and drain is increased, which is beneficial to the subsequent formation of a low-resistance metal silicide film layer and avoids the agglomeration defects of the film layer due to high temperature. On the other hand, the above-mentioned formation method can ensure the protection of the gate protection layer 230 on the gate 220 while thinning the gate protection layer 230, without affecting the overall performance of the device.

[0101] In the embodiments provided by the present disclosure, in order to further remove organic pollutants, inorganic particles, metal ions and other pollutants on the device surface and ensure the cleanliness of the device surface, after the gate protection layer 230 is thinned, the formation method may further include: using dry cleaning to clean the gate structure 200. The dry cleaning process may include plasma cleaning, gas phase cleaning, ion milling and other methods. The dry cleaning process can avoid damage to structures such as the gate structure 200 by chemical substances, and can also avoid pollution from chemical waste liquid.

[0102] After the gate protection layer 230 is thinned, the formation method may further include: forming a metal silicide layer 300, the metal silicide layer 300 being respectively formed on the first surface 10, the surface of the gate 220 and the second surface 20; wherein the first surface 10 is a surface jointly formed by the first source and drain 110 and the first sub-surface 101, and the second surface 20 is a surface jointly formed by the second source and drain 120 and the second sub-surface 102.

[0103] Specifically, Fig.11 As shown, forming the metal silicide layer 300 includes: forming a metal layer 400, the metal layer 400 conformally covering the surface of the gate structure 200, the surface formed by the first surface 10 and the second surface 20; performing a first heat treatment on the metal layer 400 to form a first sub-metal silicide layer 310 on the top of the gate structure 200, the first surface 10 and the second surface 20 respectively; and removing the remaining metal layer 400 to form an intermediate semiconductor structure.

[0104] In order to prevent the influence of external impurities on the metal layer 400, especially to prevent the oxidation of the metal layer 400 by oxygen, after the metal layer 400 is formed, Fig.12 As shown, the formation method may further include: forming a barrier layer 500, wherein the barrier layer 500 is conformally covered on the surface of the metal layer 400. The barrier layer 500 may be one or more of materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), etc., and may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD), etc. The specific material and formation process of the barrier layer 500 may be adaptively selected and adjusted according to the device process design. Taking the barrier layer 500 as titanium nitride (TiN) as an example, the thickness of the barrier layer 500 may be 5nm to 15nm, for example, the barrier layer 500 may be 5nm, 8nm, 10nm, 13nm, 15nm, etc.

[0105] In the above example, the metal layer 400 can be a cobalt (Co) film layer, and the metal layer 400 can also be made of metal nickel (Ni) or metal tungsten (W). The present disclosure uses the metal layer 400 as a cobalt (Co) film layer for description, and for other metal materials, the embodiments provided in the present disclosure need to be adaptively deformed or adjusted to obtain subsequent process steps. The thickness of the metal layer 400 (cobalt) can be 5nm to 20nm, for example, it can be 5nm, 10nm, 15nm, 20nm, etc. The metal layer 400 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or other methods.

[0106] like Fig.13 As shown, the metal layer 400 is subjected to a first heat treatment so that the metal ions in the metal layer 400 diffuse into the gate 220, the first surface 10 and the second surface 20, so as to form a first sub-metal silicide layer 310 on the gate 220, the first surface 10 and the second surface 20. The first sub-metal silicide layer 310 may include dicobalt silicon (Co 2 The thickness of the first sub-metal silicide layer 310 may be 5 nm to 30 nm, for example, 5 nm, 8 nm, 15 nm, 20 nm, 22 nm, 25 nm, 29 nm or 30 nm. 2 The ratio of Si to CoSi is different, and the thickness of the first sub-metal silicide layer 310 is different. In this embodiment, the thickness of the first sub-metal silicide layer 310 refers to the size of the film layer in the direction perpendicular to the substrate 100.

[0107] The first heat treatment may include a first sub-heat treatment and a second sub-heat treatment, wherein the first sub-heat treatment includes: at a temperature of 250° C. to 410° C., using cobalt ions in the metal layer 400 as a diffusion source, so that the cobalt ions are doped into the gate 220, the first surface 10 and the second surface 20, and dicobalt silicon (Co2) is formed in the gate 220, the first surface 10 and the second surface 20. 2 In particular, the concentration of cobalt ions is high at the gate 220, the first surface 10 and the second surface 20 near the exposed position, forming more dicobalt silicon (Co 2 Si).

[0108] The second sub-heat treatment includes: at a temperature of 410°C to 700°C, cobalt ions continue to diffuse into the gate 220, the first surface 10 and the second surface 20 as diffusion sources, and form cobalt silicon (CoSi) in the gate 220, the first surface 10 and the second surface 20. After the heat treatment, dicobalt silicon (CoSi) 2Si) and cobaltized silicon (CoSi) may exist in the first sub-metal silicide layer 310 at the same time, and dicobaltized silicon (Co 2 The resistivity of Si and CoSi is relatively high, and the resistance value of the formed first sub-metal silicide layer 310 is also relatively large. The temperature ranges of the first sub-heat treatment and the second sub-heat treatment in the above-mentioned first heat treatment are only shown as exemplary embodiments. In the actual heat treatment process, the above-mentioned temperature ranges do not have strict limits and can be adaptively adjusted according to actual process requirements.

[0109] In order to further form a metal silicide film layer with a lower resistance, after forming the first sub-metal silicide layer 310, as shown in Fig.14 As shown, the method also includes: forming a stress layer 600, which conformally covers the surface of the intermediate semiconductor structure; performing a second heat treatment on the intermediate semiconductor structure having the stress layer 600, so that the first sub-metal silicide layer 310 forms a second sub-metal silicide layer 320, so as to obtain a target semiconductor structure, wherein the temperature of the second heat treatment is higher than the temperature of the first heat treatment.

[0110] As the heat treatment temperature is further increased, such as when the temperature is increased to more than 700° C., the silicon ions in the device diffuse into the first sub-metal silicide layer 310 as diffusion sources, and the formed dicobalt silicon (Co 2 Si) and cobalt silicon (CoSi) continue to combine with silicon ions to form cobalt disilicide (CoSi 2 ), Cobalt disilicide (CoSi 2 ) has a higher resistivity than dicobalt silicon (Co 2 Si) and cobalt silicon (CoSi) are both small, and cobalt disilicide (CoSi 2 ) has a small resistance value, which can effectively reduce the contact resistance and improve the overall electrical performance of the device.

[0111] Therefore, a stress layer 600 is formed on the surface of the intermediate semiconductor structure, wherein the stress layer 600 includes silicon elements, for example, the stress layer 600 may be formed of silicon nitride or the like. After the stress layer 600 is formed, the silicon atoms in the stress layer 600 are diffused into the first sub-metal silicide layer 310 in a free state by a second heat treatment, so that the first sub-metal silicide layer 310 with a higher resistance value forms a second sub-metal silicide layer 320 with a lower resistance value, wherein the second sub-metal silicide layer 320 has a uniform cobalt disilicide (CoSi 2) molecular structure. In the present disclosure, since the first surface 10 is composed of the first source and drain 110 and the first sub-surface 101, and the second surface 20 is composed of the second source and drain 120 and the second sub-surface 102, the line width of the second sub-metal silicide layer 320 is increased, and when silicon ions diffuse into the first sub-metal silicide layer 310, the boundary inhibition effect can be reduced, so that the first sub-metal silicide layer 310 can uniformly form the second sub-metal silicide layer 320, effectively reducing the resistance of the metal silicide layer 300 and improving the overall electrical performance of the device.

[0112] The second sub-metal silicide layer 320 may include cobalt disilicide (CoSi 2 ), the thickness of the second sub-metal silicide layer 320 can be 15nm~55nm, for example, can be 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, etc.

[0113] The temperature of the second heat treatment is greater than the temperature of the first heat treatment. Specifically, the temperature of the second heat treatment may be greater than 700°C, such as 750°C, 800°C, 850°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C or even higher. The time of the second heat treatment may also be different according to the temperature within the temperature conditions. The second heat treatment time may be in the nanosecond to millisecond range. For example, under high temperature conditions, the treatment time may be appropriately shortened; under low temperature conditions, the treatment time may be appropriately increased.

[0114] In the embodiment provided by the present disclosure, in order to achieve capacitive coupling and short circuit between adjacent devices, after forming the second sub-metal silicide layer 320, as shown in FIG. Fig.15 As shown, the forming method may further include: forming an oxide layer 700 , wherein the oxide layer 700 covers the target semiconductor device; and performing a planarization process on the oxide layer 700 .

[0115] The oxide layer 700 may be silicon dioxide (SiO 2 ) or other high dielectric constant material layers, such as hafnium oxide (HfO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ) or yttrium oxide (Y 2 O 3) and other materials, which can be formed by one or more of methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). The specific formation method can be adaptively selected and adjusted according to the material characteristics of the oxide layer 700.

[0116] The oxide layer 700 may be planarized by chemical mechanical polishing (CMP) to provide a good structural foundation for subsequent process steps and ensure the isolation reliability of the device.

[0117] The method for forming a semiconductor structure provided by the present disclosure forms a gate structure 200 on a substrate 100, and forms a first source-drain electrode 110 and a second source-drain electrode 120 on both sides of the gate structure 200, respectively, and thins the gate protection layer 230 in a direction pointing from the sidewall of the gate 220 to the inside of the gate 220, and exposes a first sub-surface 101 between the gate structure 200 and the first source-drain electrode 110, and exposes a second sub-surface 102 between the gate structure 200 and the second source-drain electrode 120, thereby increasing the space provided for the formation of a metal silicide film layer in a subsequent device, which is conducive to the formation of a metal silicide film layer with a smaller resistance value, and overcomes the problem that the metal silicide film layer cannot form a uniform low-resistance phase due to process limitations; in addition, the semiconductor structure provided by the present disclosure has a larger gate 220 line width, which is also conducive to the formation of a low-resistance phase metal silicide film layer, reduces the contact resistance of the device, and thereby improves the performance of the device.

[0118] It should be noted that, although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0119] The present disclosure also provides a semiconductor structure, such as Fig.15 As shown, the semiconductor structure can be manufactured by the above-mentioned semiconductor structure forming method. The semiconductor structure has a metal silicide film layer with uniform structure and low resistivity, and has a small contact resistance, so that the device as a whole has good electrical performance.

[0120] The semiconductor structure provided by the present disclosure can be applied to dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, etc. Of course, it can also be applied to other storage devices not listed here, which will not be listed one by one.

[0121] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A gate structure protruding from the surface of the substrate is formed on the surface of the substrate, the gate structure comprising a gate oxide layer, a gate and a gate protection layer, the gate oxide layer is formed on the substrate, the gate is formed on the gate oxide layer, and the gate protection layer is formed on the sidewall of the gate; a first source-drain electrode and a second source-drain electrode are formed in the substrate, the first source-drain electrode and the second source-drain electrode are respectively located on two sides of the gate structure; The gate protection layer is thinned along the direction from the side wall of the gate to the inside of the gate to expose the first sub-surface and the second sub-surface of the substrate, wherein the first sub-surface is located between the gate structure and the first source and drain, and the second sub-surface is located between the gate structure and the second source and drain.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first sub-surface is flush with the surface of the first source and drain electrode; the second sub-surface is flush with the surface of the second source and drain electrode.

3. The method for forming a semiconductor structure according to claim 1, wherein: The gate protection layer includes at least one insulating layer and at least one passivation layer, the insulating layer and the passivation layer are alternately arranged, and the passivation layer is formed on a side of the insulating layer away from the gate, and the gate protection layer is thinned, including: The passivation layer having the largest distance from the gate is etched by wet etching to reduce the thickness of the gate protection layer.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: The passivation layer has a reduced thickness ratio of 30% to 70%.

5. The method for forming a semiconductor structure according to claim 3, wherein: The wet etching solution includes at least one of hydrofluoric acid, nitric acid and phosphoric acid.

6. The method for forming a semiconductor structure according to claim 1, wherein: After the gate protection layer is thinned, the method further includes: A metal silicide layer is formed, and the metal silicide layer is formed on the first surface, the surface of the gate, and the second surface respectively; wherein the first surface is a surface jointly formed by the first source and drain and the first sub-surface, and the second surface is a surface jointly formed by the second source and drain and the second sub-surface.

7. The method for forming a semiconductor structure according to claim 6, wherein: The forming of the metal silicide layer comprises: forming a metal layer, the metal layer conformally covering a surface of the gate structure, a surface formed by the first surface and the second surface; Performing a first heat treatment on the metal layer to form a first sub-metal silicide layer on the top of the gate structure, the first surface, and the second surface, respectively; The remaining metal layer is removed to form an intermediate semiconductor structure.

8. The method for forming a semiconductor structure according to claim 7, characterized in that: After forming the metal layer, the method further comprises: A barrier layer is formed, wherein the barrier layer conformally covers the surface of the metal layer.

9. The method for forming a semiconductor structure according to claim 7, wherein: After forming the first sub-metal silicide layer, the method further comprises: forming a stress layer, wherein the stress layer conformally covers the surface of the intermediate semiconductor structure; The intermediate semiconductor structure having the stress layer is subjected to a second heat treatment so that the first sub-metal silicide layer forms a second sub-metal silicide layer to obtain a target semiconductor structure, wherein the temperature of the second heat treatment is higher than the temperature of the first heat treatment.

10. The method for forming a semiconductor structure according to claim 9, characterized in that: After performing a second thermal treatment on the intermediate semiconductor structure having the stress layer, the method further includes: forming an oxide layer, wherein the oxide layer covers the target semiconductor structure; The oxide layer is planarized.

11. The method for forming a semiconductor structure according to claim 6, wherein: The semiconductor structure further includes an isolation structure, which is formed in the substrate and is located on a side of the first source and drain or the second source and drain away from the gate structure.

12. The method for forming a semiconductor structure according to claim 11, characterized in that: The method further comprises: An isolation layer is formed, wherein the isolation layer exposes the first surface, the second surface and the gate structure, and the isolation layer is used to protect the isolation structure.

13. The method for forming a semiconductor structure according to any one of claims 1 to 12, characterized in that: After the gate protection layer is thinned, the method further includes: The gate structure is cleaned by dry cleaning.

14. The method for forming a semiconductor structure according to any one of claims 1 to 12, characterized in that: The method further comprises: An end of the gate protection layer away from the substrate is etched to expose a portion of the side wall of the gate.

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