Preparation method of waterproof layer in radio frequency chip and radio frequency chip structure

Abstract

The embodiment of the invention provides a preparation method of a waterproof layer in a radio frequency chip and a radio frequency chip structure with a waterproof layer structure, and the method comprises the steps: carrying out the air gap etching and the first-stage waterproof layer etching at the same time through ingenious utilization of an inherent air gap preparation technology in a radio frequency chip preparation process; a first-stage waterproof layer gap is formed; after preparation of all subsequent interconnection layers is completed, second-stage waterproof layer etching is carried out until gaps of the first-stage waterproof layer are communicated, and finally a waterproof layer cavity is formed; therefore, a deep groove etching process in the prior art is avoided by utilizing a graded etching mode, the etching difficulty is reduced, the etching time is shortened, and the production efficiency is improved. And the preparation process of the air gap is an inherent process step in the preparation process of the radio frequency chip, so that no extra process is added, and the cost is effectively controlled.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a method for preparing a waterproof layer in a radio frequency chip and a radio frequency chip structure. Background Art

[0002] Radio Frequency Silicon-On-Insulator (RF SOI) technology is an advanced semiconductor technology that uses insulating materials between silicon transistors to reduce parasitic capacitance and improve integration and speed. RFSOI technology has gradually replaced compound process technology in wireless communication fields such as smartphones and WiFi.

[0003] With the development of wireless communication technology, the performance requirements for FR switches are getting higher and higher, especially in terms of switching speed, because fast switching capability is crucial to improving communication efficiency, reducing power consumption and improving user experience.

[0004] Parasitic capacitance is a major reason for the degradation of switching performance, which is also the main reason why low dielectric constant (LK) or even ultra-low dielectric constant (ULK) dielectric layers are introduced in the back end.

[0005] However, LK and even ULK dielectric layers are prone to water absorption. Under high-frequency operation, water molecules will produce a coupling effect, affecting communication quality.

[0006] In order to reduce the impact of water molecules, the corresponding solution is to make a waterproof layer in the RF-SOI chip.

[0007] The existing waterproof layer is prepared after the back-end LK or even ULK dielectric layer related processes are completed. Therefore, in the process of making the waterproof layer, deep trench etching is required to form the deep trench, and then a waterproof layer film is deposited in the deep trench to form the waterproof layer.

[0008] However, deep trench etching and depositing a waterproof layer film in the deep trench are both difficult to implement in terms of technology.

[0009] Therefore, it is necessary to improve the existing process for preparing the waterproof layer. Summary of the invention

[0010] The embodiments of the present invention provide a method for preparing a waterproof layer in a radio frequency chip and a radio frequency chip structure to solve the problem that in the prior art, deep groove etching and deposition of a waterproof layer film in the deep groove are required during the preparation of the waterproof layer, which makes the process difficult to implement.

[0011] According to a first aspect of the present invention, there is provided a method for preparing a waterproof layer in a radio frequency chip, comprising:

[0012] Providing an SOI substrate, on which the RF chip front-end process has been completed, and an interlayer dielectric layer and a first interconnect layer have been formed; wherein the SOI substrate includes a device area and an edge area, and an RF device is formed in the device area; the first interconnect layer includes a contact hole formed in the first interlayer dielectric layer, a first metal layer located above the contact hole, and a first interconnect dielectric layer filled between each first metal in the first metal layer;

[0013] Forming an air gap cavity of a preset depth and a first-level waterproof layer cavity at a first preset position of the device area and a second preset position of the edge area of ​​the first interlayer dielectric layer;

[0014] Depositing a second interconnect dielectric layer on the first interconnect layer, wherein the second interconnect dielectric layer fills the air gap cavity and the first-level waterproof layer cavity to form an air gap and a first-level waterproof layer gap respectively;

[0015] forming a first through hole and a second metal layer in the second interconnect dielectric layer, and completing the preparation of all subsequent interconnect layers;

[0016] forming a second-level waterproof layer cavity aligned with the first-level waterproof layer cavity in an interconnection layer above the first interconnection layer, and the second-level waterproof cavity is connected to the first-level waterproof layer gap to form a waterproof layer cavity;

[0017] A waterproof medium is deposited in the cavity of the waterproof layer to form a waterproof layer, and at least one waterproof gap exists in the waterproof medium; the waterproof layer is arranged around the radio frequency chip body.

[0018] Optionally, the waterproof medium includes a waterproof film and a waterproof medium layer, and the formation of the waterproof medium mainly includes:

[0019] Depositing the waterproof film, the waterproof film covers the top layer of the interconnection layer and the inner sidewall of the cavity of the waterproof layer;

[0020] A waterproof medium layer is deposited, wherein the waterproof medium layer covers the waterproof film and fills the cavity of the waterproof layer to form the waterproof gap in the cavity of the waterproof layer.

[0021] Optionally, the waterproof film is made of silicon dioxide or silicon nitride.

[0022] Optionally, forming an air gap cavity and a first-level waterproof layer cavity of a preset depth at a first preset position of the device area and a second preset position of the edge area of ​​the first interlayer dielectric layer specifically includes:

[0023] forming a first patterned mask layer on the first interconnect layer, wherein the first patterned mask layer comprises an air gap pattern and a waterproof layer pattern, the air gap pattern is located in the device area, the waterproof layer pattern is located in the edge area, and the waterproof layer pattern is arranged around the RF chip body;

[0024] The air gap etching and the first waterproof layer etching are performed using the first patterned mask layer as a mask until the first interlayer dielectric layer is etched to the preset depth and then stopped to form an air gap cavity and a first waterproof layer cavity.

[0025] Optionally, before forming the first patterned mask layer on the first interconnect layer, the method further includes forming a hard mask layer on the first interconnect layer, wherein the first patterned mask layer is formed on the hard mask layer.

[0026] Optionally, the method further includes:

[0027] performing surface planarization processing on the deposited second interconnect dielectric layer;

[0028] A passivation layer is deposited on the second interconnect dielectric layer after surface planarization; the passivation layer includes a first passivation layer film and a second passivation layer film located on the first passivation layer film; wherein the material of the first passivation layer film includes doped silicon carbide or silicon nitride; the material of the second passivation layer film includes SION.

[0029] Optionally, forming a second-level waterproof layer cavity aligned with the first-level waterproof layer cavity in the interconnection layer above the first interconnection layer, and the second-level waterproof cavity is connected to the first-level waterproof layer gap to form a waterproof layer cavity, specifically includes:

[0030] forming a second patterned mask layer on the top layer of the interconnect layer, wherein the second patterned mask layer includes a waterproof layer pattern;

[0031] Using the second patterned mask layer as a mask, a second waterproof layer cavity aligned with the first waterproof layer cavity is formed in the interconnect layer above the first interconnect layer, and the second waterproof layer cavity is connected to the first waterproof layer gap to form a waterproof layer cavity.

[0032] Optionally, the interconnection dielectric layers in all the interconnection layers are low dielectric constant dielectric layers or ultra-low dielectric constant dielectric layers.

[0033] Optionally, after depositing the waterproofing medium, the following steps are further included:

[0034] The waterproof medium is subjected to a surface flattening treatment.

[0035] According to a second aspect of the present invention, there is provided a radio frequency chip structure with a waterproof layer structure, comprising:

[0036] An SOI substrate, the SOI substrate comprising a device region and an edge region, an RF device structure is formed in the device region, and the RF device structure comprises an RF device and an interconnection layer;

[0037] A waterproof layer structure is formed in the edge area, comprising a waterproof layer cavity, a waterproof film and a waterproof dielectric layer; wherein the waterproof film covers the top of the RF device structure and the inner wall of the waterproof layer cavity; the waterproof dielectric layer covers the waterproof film and fills the waterproof layer cavity to form a waterproof gap in the waterproof layer cavity;

[0038] Wherein, the waterproof layer structure is prepared by using the method for preparing the waterproof layer in the radio frequency chip described in any one of the first aspects above.

[0039] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0040] The method for preparing the waterproof layer in the radio frequency chip provided by the technical solution of the present invention cleverly utilizes the inherent air gap preparation process in the radio frequency chip preparation process, performs the first-level waterproof layer etching while performing the air gap etching, and forms the first-level waterproof layer gap; and performs the second-level waterproof layer etching after completing the preparation of all subsequent interconnection layers, until the first-level waterproof layer gap is connected, and finally forms the waterproof layer cavity; thereby utilizing the graded etching method, avoiding the deep groove etching process in the prior art, reducing the etching difficulty, reducing the etching time, and improving the production efficiency. And because the air gap preparation process is an inherent process step in the radio frequency chip preparation process, no additional process is added, and the cost is effectively controlled. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1A-Figure 1D It is a schematic diagram of the device structure corresponding to each step of the preparation method of the waterproof layer in the existing radio frequency chip;

[0042] Figure 2 It is a flow chart of a method for preparing a waterproof layer in a radio frequency chip provided in one embodiment of the present invention;

[0043] Figure 3-Figure 11 A schematic diagram of device structures corresponding to each step of a method for preparing a waterproof layer in a radio frequency chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0045] As described in the background technology, the technical solution of the present invention aims to solve the problem that the preparation of the existing waterproof layer requires deep groove etching and deposition of a waterproof layer film in the deep groove, both of which are difficult to implement in terms of process.

[0046] Figure 1A-Figure 1D The present invention is a schematic diagram of the device structure corresponding to each step of the preparation method of the waterproof layer in the existing radio frequency chip.

[0047] Please combine Figure 1A-Figure 1D The existing method for preparing the waterproof layer in the radio frequency chip includes the following steps:

[0048] S1: Provide an SOI substrate 100, on which the front-end process and the back-end process of the radio frequency chip have been completed, that is, the device area 110 and the interconnection layer 120 have been formed, such as Figure 1A As shown;

[0049] S2: Forming a first patterned photoresist layer 130 on top of the interconnect layer 120, such as Figure 1B As shown;

[0050] S3: using the first patterned photoresist layer 130 as a mask, etching the interconnection layer 120 until a portion of the substrate 100 is etched away, so as to form a deep trench 140; Figure 1C As shown;

[0051] S4: depositing an oxide layer 150, wherein the oxide layer 150 is deposited on the interconnect layer 120 and fills the deep trench 140, wherein the oxide layer 150 forms an air gap 160 during the process of filling the deep trench; Figure 1D The formation of the air gap 160 is a natural phenomenon generated during the deposition of the deep trench oxide layer.

[0052] It can be seen that the preparation of the above-mentioned existing waterproof layer is done after the relevant processes of the back-end LK or even ULK dielectric layer are completed, and then the waterproof layer is made; therefore, in the process of making the waterproof layer, deep groove etching is required to form a deep groove, and then a waterproof layer film is deposited in the deep groove to form a waterproof layer. However, deep groove etching and deposition of waterproof layer film in deep grooves are both difficult to implement in terms of technology. And because the thickness of the deep groove is usually more than 30um, the etching process takes up a lot of machine space, and in the process of deep groove etching, it is necessary to pass through different material layers, and the etching morphology is difficult to control.

[0053] In view of this, an embodiment of the present invention provides a method for preparing a waterproof layer in a radio frequency chip, comprising:

[0054] Providing an SOI substrate, on which the RF chip front-end process has been completed, and an interlayer dielectric layer and a first interconnect layer have been formed; wherein the SOI substrate includes a device area and an edge area, and an RF device is formed in the device area; the first interconnect layer includes a contact hole formed in the first interlayer dielectric layer, a first metal layer located above the contact hole, and a first interconnect dielectric layer filled between each first metal in the first metal layer;

[0055] An air gap cavity and a first-level waterproof layer cavity of a preset depth are formed at a first preset position of the device area and a second preset position of the edge area of ​​the first interlayer dielectric layer; a second interconnect dielectric layer is deposited on the first interconnect layer, and the second interconnect dielectric layer fills the air gap cavity and the first-level waterproof layer cavity to form an air gap and a first-level waterproof layer gap respectively;

[0056] forming a first through hole and a second metal layer in the second interconnect dielectric layer, and completing the preparation of all subsequent interconnect layers;

[0057] forming a second-level waterproof layer cavity aligned with the first-level waterproof layer cavity in an interconnection layer above the first interconnection layer, and the second-level waterproof cavity is connected to the first-level waterproof layer gap to form a waterproof layer cavity;

[0058] A waterproof medium is deposited in the cavity of the waterproof layer to form a waterproof layer, and at least one waterproof gap exists in the waterproof medium; the waterproof layer is arranged around the radio frequency chip body.

[0059] The method for preparing the waterproof layer in the radio frequency chip provided by the technical solution of the present invention cleverly utilizes the inherent air gap preparation process in the radio frequency chip preparation process, performs the first-level waterproof layer etching while performing the air gap etching, and forms the first-level waterproof layer gap; and performs the second-level waterproof layer etching after completing the preparation of all subsequent interconnection layers, until the first-level waterproof layer gap is connected, and finally forms the waterproof layer cavity; thereby utilizing the graded etching method, avoiding the deep groove etching process in the prior art, reducing the etching difficulty, reducing the etching time, and improving the production efficiency. And because the air gap preparation process is an inherent process step in the radio frequency chip preparation process, no additional process is added, and the cost is effectively controlled.

[0060] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, the technical scheme of the present invention is described in detail below with reference to the accompanying drawings.

[0061] Figure 2 It is a flow chart of a method for preparing a waterproof layer in a radio frequency chip provided in one embodiment of the present invention; Figure 3-Figure 11 A schematic diagram of device structures corresponding to each step of a method for preparing a waterproof layer in a radio frequency chip provided in an embodiment of the present invention.

[0062] Please refer to Figure 2 , and combined with reference Figure 3-Figure 11 , the method for preparing a waterproof layer in a radio frequency chip provided by an embodiment of the present invention comprises:

[0063] S1: Provide an SOI substrate 200, on which the RF chip front-end process has been completed, and an interlayer dielectric layer and a first interconnect layer 221 have been formed; wherein the SOI substrate 200 includes a device area 201 and an edge area 202, and a semiconductor device 210 including an RF device is formed in the device area 201; the first interconnect layer includes a contact hole formed in the first interlayer dielectric layer, a first metal layer located above the contact hole, and a first interconnect dielectric layer filled between each first metal in the first metal layer; Figure 3 shown.

[0064] It can be understood that the SOI substrate 200 includes a plurality of device regions 201, each of which is used to form a corresponding semiconductor device; the edge region 202 can be understood to be located at the periphery of the device region 201 and arranged around the device region 201. Specifically, for example, the outer side of the device region 201 is usually a sealing ring, the outer side of the sealing ring is a cutting belt, and the edge region 202 is located between the device region 201 and the sealing ring.

[0065] Among them, the SOI substrate is a silicon-on-insulator substrate, that is, an insulating layer is added between the top silicon and the bottom substrate. SOI substrates are widely used in CMOS devices, radio frequency devices and silicon photonic devices. Of course, the present invention is not limited to this, and the substrate in the embodiment of the present invention can also be other types of substrates, such as a germanium-on-insulator substrate.

[0066] Among them, the front-end process (FEOL, Front End of Line) can be understood as the process of manufacturing active parts such as transistors, that is, after the front-end process is completed, various semiconductor devices such as transistors are formed on the substrate. The back-end process (BEOL, Back End of Line) can be understood as the interconnection process of subsequent multi-layer wiring after the front-end process is completed, that is, forming an interconnection layer. The interconnection layer generally includes multiple layers, specifically including a first interconnection layer, an intermediate interconnection layer, and a top interconnection layer. Among them, the gate, source, and drain of the semiconductor device are isolated by an interlayer dielectric layer; the contact hole of the first interconnection layer is formed in the interlayer dielectric layer, and a first metal layer is formed above the contact hole, and the metals of the first metal layer are isolated by the first interconnection dielectric layer. And an interlayer dielectric layer will be formed between each subsequent interconnection layer to isolate adjacent interconnection layers.

[0067] As an implementation mode, the RF device includes an RF switch tube. This is because the performance of the RF switch is significantly affected by water molecules under high-frequency operation, so solving the waterproof problem of the RF switch tube is particularly important for the radio frequency chip. Of course, it should be appreciated that the present invention is not limited to this. Without departing from the concept of the present invention, the RF device may also include other specific devices.

[0068] S2: forming an air gap cavity 2521 of a preset depth and a first-level waterproof layer cavity 2522 at a first preset position of the device area and a second preset position of the edge area of ​​the first interconnect layer; Figure 5 shown.

[0069] The first preset position can be understood as a position directly above the gate (Poly) of the semiconductor device, and the second preset position can be understood as a middle position in the edge area. Of course, the present invention is not limited to this, and the first position and the second position are offset by a certain distance in the left and right directions, which is also within the protection scope of the present invention.

[0070] As an implementation manner, step S2 specifically includes, for example:

[0071] S21: forming a first patterned mask layer 251 on the first interconnect layer 221, wherein the first patterned mask layer 251 comprises an air gap pattern 2511 and a waterproof layer pattern 2512, wherein the air gap pattern 2511 is located in the device area, and the waterproof layer pattern 2512 is located in the edge area; the waterproof layer pattern is arranged around the main body of the RF chip; Figure 4 shown.

[0072] Wherein, the first interconnection layer 221, for example, includes a three-layer structure, which includes, from bottom to top, a first interlayer dielectric layer, an etch stop layer, and a first interconnection dielectric layer; wherein, the first interlayer dielectric layer and the first interconnection dielectric layer can be silicon oxide, silicon nitride, aluminum oxide, LK material, ULK material, HK (high dielectric constant) material, etc. Preferably, since the RF chip needs to increase and reduce capacitance to improve its performance, LK material or ULK material is often used as the interconnection dielectric layer; wherein, LK material includes organic silicon, silicon fluoride, polyimide, etc. The etch stop layer is generally silicon nitride or SiCN, and its function is to improve etching uniformity. Of course, it should be appreciated that the structure of the first interconnection layer 221 is not limited to this, and it can also be a structure with other numbers of layers, and the materials of each layer are not limited.

[0073] S22: Using the first patterned mask layer 251 as a mask, perform air gap etching and first-level waterproof layer etching until the first interlayer dielectric layer is etched to the preset depth, so as to form an air gap cavity 2521 and a first-level waterproof layer cavity 2522; after the etching is completed, remove the remaining first patterned mask layer 251; the schematic diagram of the device structure after removing the remaining first patterned mask layer 251 is as shown in FIG. Figure 5 shown.

[0074] The preset depth can be understood as follows: after etching to the preset depth, the thickness of the first interlayer dielectric layer remaining between the bottom of the air gap cavity 2521 and the upper surface of the gate of the semiconductor device is Of course, it should be appreciated that the present invention is not limited thereto, and the thickness of the remaining first interlayer dielectric layer can be adjusted as needed.

[0075] Among them, air gap etching is a necessary step in the preparation of conventional RF SOI devices. In the embodiment of the present invention, the first-level waterproof layer cavity is etched while the air gap etching is performed to complete a part of the waterproof layer etching. Since the etching of the first-level waterproof layer cavity is completed at the same time as the conventional air gap etching, it does not cause the increase of additional process steps; by completing the first-level waterproof layer cavity by etching the air gap at the same time, the waterproof layer etching is completed in stages, which reduces the process difficulty of deep trench etching of the waterproof layer after completing all back-end processes, and also avoids the process defects caused by deep trench etching to the interlayer dielectric layer, and reduces the possibility of device performance changes due to deep trench etching.

[0076] The material of the first patterned mask layer 251 may be, for example, photoresist, and the method of forming the first patterned mask layer 251 may specifically include:

[0077] S211: coating a photoresist layer on the first interconnect layer 221;

[0078] S212 : using a first photomask to expose and develop the photoresist layer to form a patterned photoresist layer as the first patterned mask layer 251 .

[0079] Of course, it should be appreciated that the first patterned mask layer 251 may also be made of other materials and may also be formed in other ways, and the present invention is not limited thereto.

[0080] As a preferred embodiment, before forming the first patterned mask layer 251 on the first interconnect layer 221, the method further includes:

[0081] A hard mask layer 260 is formed on the first interconnect layer 221, and the first patterned mask layer 251 is formed on the hard mask layer 260; specifically, the hard mask layer material is one of SiN / SiO2 or a combination of the two. Figure 4 The hard mask layer mainly plays a protective role, protecting the functional layers below the hard mask layer.

[0082] S3: depositing a second interconnect dielectric layer 270 on the first interconnect layer 221, and the second interconnect dielectric layer 270 fills the air gap cavity and the first waterproof layer cavity to form an air gap 2531 and a first waterproof layer gap 2531 respectively; Figure 6 shown.

[0083] Specifically, the second interconnect dielectric layer 270 can be silicon oxide, silicon nitride, aluminum oxide, LK material, ULK material, HK (high dielectric constant) material, etc. Preferably, since the RF chip needs to increase and reduce capacitance to improve its performance, LK material or ULK material is often used as the interconnect dielectric layer. Among them, LK material includes organic silicon, silicon fluoride, polyimide, etc.

[0084] Among them, the air gap 2531 and the first-level waterproof layer gap 2531 are naturally formed in the process of filling the second interconnect dielectric layer 270, and the position of the air gap 2531 is generally located directly above the gate (Poly) of the semiconductor device, penetrating the first interlayer dielectric layer, the first interconnect dielectric layer and the second interconnect dielectric layer, and the bottom of the air gap 2531 is higher than the upper surface of the gate (that is, there is a part of the first interlayer dielectric layer between the bottom of the air gap 2531 and the upper surface of the gate), the top of the air gap 2531 is lower than the top of the second interconnect dielectric layer 270, and the top of the air gap 2531 is lower than the bottom of the second interconnect metal layer, such as Figure 7 shown.

[0085] Wherein, as a preferred embodiment, after depositing the second interconnect dielectric layer 270 on the first interconnect layer, the method further comprises:

[0086] S31: performing a surface planarization process on the second interconnect dielectric layer 270 to make the surface of the second interconnect dielectric layer 270 flat.

[0087] Furthermore, as a further preferred embodiment, after step S31, the following steps are further included:

[0088] S32: depositing a passivation layer on the second interconnect dielectric layer 270 after the surface planarization process.

[0089] As an implementation manner, the passivation layer includes a first passivation layer film 281 and a second passivation layer film 282 located on the first passivation layer film 281. Figure 6 As shown. In one example, the first passivation layer film 281 may be, for example, TiN or doped silicon carbide, and the second passivation layer film 282 may be, for example, SiON; wherein the TiN layer (or doped silicon carbide layer) and the SiON layer are both used to improve the effect of subsequent exposure and serve as a stop layer for subsequent wet etching. As another example, the first passivation layer film 281 may be, for example, TEOS, and the second passivation layer film 282 may be, for example, DARC; wherein the DARC layer is used to improve the effect of subsequent exposure, and the TEOS layer is used to protect the second interconnect dielectric layer 270 to prevent the second interconnect dielectric layer 270 from being consumed too quickly during CMP (chemical mechanical polishing process).

[0090] Of course, it should be appreciated that the passivation layer may also be a single-layer structure, for example, including only one SiON layer or one doped silicon carbide layer or silicon nitride layer; the present invention is not limited thereto.

[0091] S4: forming a first through hole and a second metal layer in the second interconnect dielectric layer, and completing the preparation of all subsequent interconnect layers 220, such as Figure 7 shown.

[0092] It should be noted that when the first passivation layer film 281 is TiN or doped silicon carbide, and the second passivation layer film 282 is SiON, after the preparation of the second metal layer is completed, the first passivation layer film 281 and the second passivation layer film 282 are removed by CMP, and a hard mask layer 260 is deposited on the second interconnect dielectric layer. Figure 7 shown.

[0093] When the first passivation layer film 281 is TEOS and the second passivation layer film 282 is DARC, the second passivation layer film 282 is etched away during the etching of the metal trench, while the TEOS layer will remain, and a subsequent hard mask layer will be deposited on the TEOS layer.

[0094] As a preferred embodiment, after completing the preparation of all subsequent interconnection layers, a hard mask layer 260 is formed on the top interconnection layer to protect the functional layers below the hard mask layer; Figure 7 shown.

[0095] It should be realized that Figure 7 Only three interconnection layers are used as an example for illustration, but the present invention is not limited thereto, and any number of interconnection layers is within the protection scope of the present invention, such as four layers, five layers, etc.

[0096] As a preferred implementation, the interconnection dielectric layers in all interconnection layers are low dielectric constant dielectric layers or ultra-low dielectric constant dielectric layers to reduce parasitic capacitance and improve switch performance.

[0097] S5: forming a second-level waterproof layer cavity aligned with the first-level waterproof layer cavity in the interconnection layer above the first interconnection layer, and the second-level waterproof cavity is connected to the first-level waterproof layer gap to form a waterproof layer cavity 2542; Fig. 9 shown.

[0098] As an implementation mode, step S5 specifically includes:

[0099] S51: forming a second patterned mask layer 252 on the top layer of the interconnection layer, wherein the second patterned mask layer 252 comprises a waterproof layer pattern; Figure 8 shown.

[0100] S52: using the second patterned mask layer 252 as a mask, forming a second-level waterproof layer cavity aligned with the first-level waterproof layer cavity in the interconnect layer above the first interconnect layer, and the second-level waterproof layer cavity is connected to the first-level waterproof layer gap, forming a waterproof layer cavity 2542; Fig. 9 Specifically, the second-level waterproof layer is etched using the second patterned mask layer 252 as a mask until the first-level waterproof layer gap is connected to form a waterproof layer cavity 2542 .

[0101] It should be noted that during the etching process of the second-level waterproof layer, the second interconnect dielectric layer deposited in the cavity of the first-level waterproof layer will be etched away to form a deep groove, that is, the second-level waterproof cavity and the first-level waterproof layer cavity are connected to form a waterproof layer cavity 2542 as a whole.

[0102] As an example, the material of the second patterned mask layer 252 is photoresist. The method of forming the second patterned mask layer 252 may specifically include:

[0103] S511: coating a photoresist layer on the top layer of the interconnection layer;

[0104] S512 : using a second photomask to expose and develop the photoresist layer to form a patterned photoresist layer as the second patterned mask layer 252 .

[0105] Of course, it should be appreciated that the second patterned mask layer 252 may also be made of other materials and may also be formed in other ways, and the present invention is not limited thereto.

[0106] Among them, since the gaps in the first-level waterproof layer have been formed in advance, the etching depth is greatly reduced when the second-level waterproof layer is etched. Compared with the existing deep groove etching method, the etching difficulty is reduced, and the time occupied by the machine is greatly shortened, thereby improving efficiency. Moreover, since the etching depth is greatly reduced, the number of different material layers that need to be etched through is also greatly reduced, making the etching morphology easy to control.

[0107] S6: Depositing a waterproof medium in the cavity of the waterproof layer to form a waterproof layer, wherein at least one waterproof gap 2552 exists in the waterproof medium; the waterproof layer is arranged around the main body of the RF chip; Fig.11 The waterproof gap 2552 is formed by naturally generating a cavity during the deposition of the waterproof medium. The cavity forms the waterproof gap 2552. The waterproof gap 2552 is used to reduce the diffusion of water vapor into the interconnect medium layer in the interconnect layer. This is because water vapor will generate electronic coupling under the action of high-frequency signals, resulting in signal distortion.

[0108] As an example, the waterproof medium includes a waterproof film and a waterproof medium layer, and the formation of the waterproof medium mainly includes:

[0109] S61: Depositing a waterproof film 290, wherein the waterproof film 290 covers the top interconnect layer and the inner side wall of the waterproof layer cavity 2542; Fig.10 shown.

[0110] S62: Depositing a waterproof dielectric layer 291, wherein the waterproof dielectric layer 291 covers the waterproof film 290 and fills the waterproof layer cavity 2542 to form a waterproof gap 2552 in the waterproof layer cavity; Fig.11 shown.

[0111] As an example, the waterproof film 290 is made of silicon dioxide or silicon nitride. Of course, the present invention is not limited thereto, and the waterproof film 290 may also be made of other materials.

[0112] As an example, the thickness of the waterproof film 290 is As a preferred embodiment, the thickness of the waterproof film 290 is This is because if the waterproof film 290 is too thin, it is difficult to cover the side wall and cannot play a waterproof role; if it is too thick, the waterproof film will seal too quickly during the deposition process, leaving a large gap layer, resulting in insufficient mechanical strength and easy to break during subsequent cutting. Of course, it should be appreciated that the thickness of the waterproof film 290 can be adjusted according to actual needs, and its thickness value is not a factor limiting the scope of protection of the present invention.

[0113] As an example, the material of the waterproof medium layer 291 is silicon dioxide. The thickness of the waterproof medium layer 291 can be, for example, And as a preferred embodiment, the thickness of the waterproof medium layer 291 is It should be noted that when the waterproof film 290 and the waterproof dielectric layer 291 are both made of silicon dioxide, the waterproof film 290 and the waterproof dielectric layer 291 can also be combined into one layer, and the thickness of the silicon dioxide layer only needs to be the sum of the thicknesses of the two layers.

[0114] As a preferred embodiment, after depositing the waterproof medium, the method further comprises:

[0115] S10: performing a surface planarization process on the waterproof medium to make its surface flat. Specifically, performing a surface planarization process on the waterproof medium layer 291 .

[0116] From the above, it can be seen that the method for preparing the waterproof layer in the RF chip provided by the embodiment of the present invention cleverly utilizes the inherent air gap preparation process in the RF chip preparation process, and performs the first-level waterproof layer etching while performing the air gap etching, and forms the first-level waterproof layer gap; and after completing the preparation of all subsequent interconnection layers, the second-level waterproof layer etching is performed until the first-level waterproof layer gap is connected, and finally the waterproof layer cavity is formed; thereby utilizing the graded etching method, avoiding the deep groove etching process in the prior art, reducing the etching difficulty, reducing the etching time, and improving the production efficiency. And because the air gap preparation process is an inherent process step in the RF chip preparation process, there is no additional process, which effectively controls the cost.

[0117] In addition, please continue to refer to Fig.11 The embodiment of the present invention further provides a radio frequency chip structure with a waterproof layer structure, including:

[0118] An SOI substrate 200, wherein the SOI substrate 200 includes a device region and an edge region, wherein a semiconductor device structure is formed in the device region, wherein the semiconductor device structure includes a semiconductor device 210 and an interconnect layer 220. The semiconductor device structure includes an RF device structure, wherein the RF device structure includes an RF device;

[0119] A waterproof layer structure is formed in the edge area, comprising a waterproof layer cavity, a waterproof film 290 and a waterproof dielectric layer 291; wherein the waterproof film 290 covers the top of the RF device structure and the inner wall of the waterproof layer cavity; the waterproof dielectric layer 291 covers the waterproof film 290 and fills the waterproof layer cavity to form a waterproof gap 2551 in the waterproof layer cavity;

[0120] Wherein, the waterproof layer structure is prepared by using the method for preparing the waterproof layer in the radio frequency chip described in any of the aforementioned embodiments.

[0121] It should be noted that the semiconductor device structure may include other types of device structures in addition to the RF device structure. When other types of device structures are included, the waterproof film 290 covers the tops of all semiconductor device structures and the inner sidewalls of the waterproof layer cavity to achieve a good waterproof effect for the entire semiconductor device structure.

[0122] In summary, the method for preparing the waterproof layer in the RF chip and the RF chip structure with the waterproof layer structure provided by the technical solution of the present invention cleverly utilize the inherent air gap preparation process in the RF chip preparation process, and perform the first-level waterproof layer etching while performing the air gap etching, and form the first-level waterproof layer gap; and perform the second-level waterproof layer etching after completing the preparation of all subsequent interconnection layers, until the first-level waterproof layer gap is connected, and finally form the waterproof layer cavity; thereby utilizing the graded etching method to avoid the deep groove etching process in the prior art, reduce the etching difficulty, reduce the etching time, and improve the production efficiency. And because the preparation process of the air gap is an inherent process step in the RF chip preparation process, there is no additional process, which effectively controls the cost.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a waterproof layer in a radio frequency chip, characterized in that: include: Providing an SOI substrate, on which the RF chip front-end process has been completed, and an interlayer dielectric layer and a first interconnect layer have been formed; wherein the SOI substrate includes a device area and an edge area, and an RF device is formed in the device area; the first interconnect layer includes a contact hole formed in the first interlayer dielectric layer, a first metal layer located above the contact hole, and a first interconnect dielectric layer filled between each first metal in the first metal layer; Forming an air gap cavity of a preset depth and a first-level waterproof layer cavity at a first preset position of the device region and a second preset position of the edge region of the first interconnect layer; Depositing a second interconnect dielectric layer on the first interconnect layer, wherein the second interconnect dielectric layer fills the air gap cavity and the first-level waterproof layer cavity to form an air gap and a first-level waterproof layer gap respectively; forming a first through hole and a second metal layer in the second interconnect dielectric layer, and completing the preparation of all subsequent interconnect layers; forming a second-level waterproof layer cavity aligned with the first-level waterproof layer cavity in an interconnection layer above the first interconnection layer, and the second-level waterproof cavity is connected to the first-level waterproof layer gap to form a waterproof layer cavity; A waterproof medium is deposited in the cavity of the waterproof layer to form a waterproof layer, and at least one waterproof gap exists in the waterproof medium; the waterproof layer is arranged around the radio frequency chip body.

2. The method for preparing a waterproof layer in a radio frequency chip according to claim 1, characterized in that: The waterproof medium includes a waterproof film and a waterproof medium layer, and the formation of the waterproof medium mainly includes: Depositing the waterproof film, the waterproof film covers the top layer of the interconnection layer and the inner sidewall of the cavity of the waterproof layer; A waterproof medium layer is deposited, wherein the waterproof medium layer covers the waterproof film and fills the cavity of the waterproof layer to form the waterproof gap in the cavity of the waterproof layer.

3. The method for preparing a waterproof layer in a radio frequency chip according to claim 2, characterized in that: The waterproof film is made of silicon dioxide or silicon nitride.

4. The method for preparing a waterproof layer in a radio frequency chip according to claim 1, characterized in that: Forming an air gap cavity and a first-level waterproof layer cavity of a preset depth at a first preset position of the device area and a second preset position of the edge area of ​​the first interconnect layer specifically includes: forming a first patterned mask layer on the first interconnect layer, wherein the first patterned mask layer comprises an air gap pattern and a waterproof layer pattern, the air gap pattern is located in the device area, the waterproof layer pattern is located in the edge area, and the waterproof layer pattern is arranged around the RF chip body; The air gap etching and the first waterproof layer etching are performed using the first patterned mask layer as a mask until the first interlayer dielectric layer is etched to the preset depth and then stopped to form an air gap cavity and a first waterproof layer cavity.

5. The method for preparing a waterproof layer in a radio frequency chip according to claim 4, characterized in that: Before forming the first patterned mask layer on the first interconnect layer, the method further includes forming a hard mask layer on the first interconnect layer, wherein the first patterned mask layer is formed on the hard mask layer.

6. The method for preparing a waterproof layer in a radio frequency chip according to claim 4, characterized in that: The method further includes: performing surface planarization processing on the deposited second interconnect dielectric layer; A passivation layer is deposited on the second interconnect dielectric layer after surface planarization; the passivation layer includes a first passivation layer film and a second passivation layer film located on the first passivation layer film; wherein the material of the first passivation layer film includes doped silicon carbide or silicon nitride; the material of the second passivation layer film includes SION.

7. The method for preparing a waterproof layer in a radio frequency chip according to claim 1, characterized in that: The step of forming a second-level waterproof layer cavity aligned with the first-level waterproof layer cavity in the interconnection layer above the first interconnection layer, and the second-level waterproof cavity is connected to the first-level waterproof layer gap to form a waterproof layer cavity, specifically includes: forming a second patterned mask layer on the top layer of the interconnect layer, wherein the second patterned mask layer includes a waterproof layer pattern; Using the second patterned mask layer as a mask, a second waterproof layer cavity aligned with the first waterproof layer cavity is formed in the interconnect layer above the first interconnect layer, and the second waterproof layer cavity is connected to the first waterproof layer gap to form a waterproof layer cavity.

8. The method for preparing a waterproof layer in a radio frequency chip according to claim 1, characterized in that: The interconnection dielectric layers in all interconnection layers are low dielectric constant dielectric layers or ultra-low dielectric constant dielectric layers.

9. The method for preparing a waterproof layer in a radio frequency chip according to any one of claims 1 to 8, characterized in that: After the waterproofing medium is deposited, it also includes: The waterproof medium is subjected to a surface flattening treatment.

10. A radio frequency chip structure with a waterproof layer structure, characterized in that: include: An SOI substrate, the SOI substrate comprising a device region and an edge region, an RF device structure is formed in the device region, and the RF device structure comprises an RF device and an interconnection layer; A waterproof layer structure is formed in the edge area, comprising a waterproof layer cavity, a waterproof film and a waterproof dielectric layer; wherein the waterproof film covers the top of the RF device structure and the inner wall of the waterproof layer cavity; the waterproof dielectric layer covers the waterproof film and fills the waterproof layer cavity to form a waterproof gap in the waterproof layer cavity; Wherein, the waterproof layer structure is prepared by using the method for preparing a waterproof layer in a radio frequency chip according to any one of claims 1-9.

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