Epitaxial silicon wafer, preparation method thereof and solar cell

Abstract

The invention provides an epitaxial silicon wafer, a preparation method thereof and a solar cell, and the epitaxial silicon wafer is obtained on the basis that a transition layer is adopted to flatten a silicon substrate and then epitaxy is carried out on one side of the silicon substrate. When the thickness of the epitaxial silicon wafer is 100 [mu] m, the flatness of the epitaxial silicon wafer is less than 5 [mu] m. The epitaxial silicon wafer is low in flatness and suitable for being used as a substrate of a solar cell.

Description

Technical Field

[0001] The present application relates to the technical field of silicon wafer preparation, and in particular to an epitaxial silicon wafer and a preparation method thereof, and a solar cell. Background Art

[0002] The flatness of silicon wafers is a very important quality indicator. Currently, the flatness of silicon wafers is mainly improved through mechanical polishing, chemical mechanical polishing (CMP), surface etching and other process methods, which leads to long process time, low efficiency, and limited effect on improving flatness.

[0003] Therefore, how to further reduce the flatness of epitaxial silicon wafers has become a technical problem that urgently needs to be solved. Summary of the invention

[0004] In view of the problem of high flatness of silicon wafers in the prior art, the embodiments of the present application provide an epitaxial silicon wafer and a preparation method thereof, and a solar cell. By preparing and etching a transition layer to adjust the flatness of the epitaxial silicon wafer, a high-quality epitaxial silicon wafer with low flatness can be obtained.

[0005] One aspect of the present application provides an epitaxial silicon wafer, wherein when the thickness of the epitaxial silicon wafer is 70-150 μm, the flatness of the epitaxial silicon wafer is less than 5 μm.

[0006] According to the embodiment of the present application, the metal impurity content of the epitaxial silicon wafer is less than 1E+9 atom / cm 3 .

[0007] According to an embodiment of the present application, the oxygen content of the epitaxial silicon wafer is less than 7E+15 atom / cm 3 , the carbon content of epitaxial silicon wafer is less than 8E+15 atom / cm 3 .

[0008] Another aspect of the present application provides a method for preparing an epitaxial silicon wafer, comprising: growing a transition layer on the epitaxial side of a silicon substrate; then growing a doped epitaxial layer on a side of the transition layer away from the silicon substrate; and separating the doped epitaxial layer to obtain an epitaxial silicon wafer.

[0009] According to an embodiment of the present application, the method for preparing an epitaxial silicon wafer further includes: before growing the doped epitaxial layer, partially removing the transition layer along the thickness direction of the transition layer.

[0010] According to an embodiment of the present application, before growing the transition layer, the method for preparing an epitaxial silicon wafer further includes: growing a gettering layer on the epitaxial side of the silicon substrate; and removing the gettering layer.

[0011] According to an embodiment of the present application, the transition layer grown on the epitaxial side of the silicon substrate includes at least a first sub-transition layer and a second sub-transition layer, wherein the thickness of the first sub-transition layer is 1-3 μm, and the thickness of the second sub-transition layer is 0.5-2 μm.

[0012] According to an embodiment of the present application, after the gettering layer is removed, an intrinsic epitaxial layer is grown on the surface of the silicon substrate after the gettering layer is removed, wherein the growth temperature of the intrinsic epitaxial layer is 1120-1150° C. Hydrogen is used to transport gaseous trichlorosilane to grow the intrinsic epitaxial layer. The hydrogen flow rate is 120-140 L / min, and the trichlorosilane flow rate is 15-20 slm.

[0013] Another aspect of the present application provides a solar cell, comprising: a silicon substrate, where the silicon substrate is an epitaxial silicon wafer according to any embodiment of the present application.

[0014] Growing an epitaxial layer on a silicon substrate, because epitaxial growth is directly performed on a silicon substrate, the flatness of the doped epitaxial layer grown on the silicon substrate is poor, affecting the quality of the silicon wafer; the applicant further discovered that by growing a transition layer on a silicon substrate, because the lattice parameters of the doped epitaxial layer are not completely the same as the lattice parameters of the silicon substrate, the lattice arrangement in the silicon substrate is adjusted by setting the transition layer, thereby reducing the stress distribution in the silicon substrate, and solving the problem of lattice mismatch caused by growing epitaxial silicon wafers directly on a silicon substrate; by growing an epitaxial silicon wafer on one side of the silicon substrate after growing the transition layer, the flatness of the subsequently grown doped epitaxial layer can be adjusted, and defects on the surface of the silicon substrate can be blocked from entering the doped epitaxial layer, thereby obtaining high-quality epitaxial silicon wafers, overcoming the technical problem of poor flatness of silicon wafers, and thereby achieving the technical effect of efficiently preparing high-quality silicon wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above contents and other purposes, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0016] Figure 1 A flow chart schematically shows a method for preparing an epitaxial silicon wafer according to an embodiment of the present application;

[0017] Figure 2 A schematic diagram of a silicon wafer epitaxial structure according to an embodiment of the present application is shown;

[0018] Figure 3 A flow chart of a method for growing a gettering layer on a silicon substrate before growing a transition layer according to an embodiment of the present application is schematically shown.

[0019] [Description of Reference Numerals]

[0020] 1-silicon substrate; 2-first sub-transition layer; 3-second sub-transition layer; 4-doped epitaxial layer. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0022] It should be noted that in the drawings or descriptions, similar or identical parts use the same figure numbers. The technical features in the various embodiments exemplified in the specification can be freely combined to form a new solution without conflict. In addition, each claim can be used as an embodiment alone or the technical features in each claim can be combined as a new embodiment. In the drawings, the shape or thickness of the embodiment can be expanded and simplified or conveniently indicated. Furthermore, the elements or implementations not shown or described in the drawings are in a form known to a person of ordinary skill in the art. In addition, although demonstrations of parameters containing specific values ​​may be provided herein, it should be understood that the parameters do not need to be exactly equal to the corresponding values, but can be approximated to the corresponding values ​​within an acceptable error tolerance or design constraint.

[0023] Unless there are technical obstacles or contradictions, the above-mentioned various implementation modes of the present application can be freely combined to form other embodiments, and these other embodiments are all within the protection scope of the present application.

[0024] Although the present application is described in conjunction with the accompanying drawings, the embodiments disclosed in the accompanying drawings are intended to exemplify the preferred embodiments of the present application and should not be construed as limiting the present application. The size ratios in the accompanying drawings are merely illustrative and should not be construed as limiting the present application.

[0025] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

[0026] The present application provides an epitaxial silicon wafer, the thickness of the epitaxial silicon wafer is 70-150 μm, and the flatness of the epitaxial silicon wafer is less than 5 μm.

[0027] Optionally, when the thickness of the epitaxial silicon wafer is 100 μm, the flatness of the epitaxial silicon wafer is less than 5 μm, the surface defects of the epitaxial silicon wafer are few, and the product quality is high.

[0028] It should be noted that the surface flatness of silicon wafers refers to the degree of deviation between the surface of the silicon wafer and the sample plane, which is usually expressed as RMS (Root Mean Square). The RMS value is obtained by taking the square root of the sum of the squares of a series of measured values ​​divided by the total number of data. The calculation formula is: RMS = sqrt((Δh12 + Δh2 2 + ··· + Δh n 2 ) / n), where Δh represents the deviation of the measured value from the sample plane, and n represents the number of measurement points. The lower the flatness of the silicon wafer, the flatter the surface of the silicon wafer.

[0029] The thickness and flatness of epitaxial silicon wafers are measured using AFM (Atomic Force Microscope), SEM (Scanning Electron Microscope), stepping interferometer, etc.

[0030] It can be understood that when the thickness of the silicon wafer is 100 μm, the flatness of the epitaxial silicon wafer of the present application can be 4 μm, 3 μm, 2 μm, or 1 μm.

[0031] The present application also provides an epitaxial silicon wafer having a metal impurity content of less than 1E+9 atom / cm 3 Compared with conventional epitaxial silicon wafers, the metal impurity content is lower and the minority carrier lifetime of the silicon wafer is improved to a certain extent. The photoelectric conversion efficiency of solar cells prepared using this silicon wafer is significantly improved.

[0032] It should be noted that the metal impurities in the present application refer to metal impurities other than doping elements in the epitaxial silicon wafer that may cause deep energy level defects, and the metal impurities include, for example, Fe, Cu, Ni, Co, Au, etc.

[0033] The metal impurities in the silicon wafer can be detected by SIMS, ICP-MS, GDMS and the like, preferably by ICP-MS.

[0034] In one embodiment, the oxygen content of the epitaxial silicon wafer is less than 7E+15 atom / cm 3 , the carbon content of epitaxial silicon wafer is less than 8E+15 atom / cm 3 .

[0035] The use of this epitaxial silicon wafer has a lower oxygen content than conventional epitaxial silicon wafers, fewer defects in the silicon wafer, and higher quality silicon wafers. The carbon content of the present application is less than 8E+15 atom / cm 3 The silicon wafers have less lattice defects and higher quality due to the low substitutional carbon content.

[0036] The oxygen content and carbon content in the silicon wafer may be detected by any method known to those skilled in the art, and those skilled in the art may select a method based on their needs. For example, the oxygen content and carbon content in the silicon wafer may be detected by secondary ion mass spectrometry (SIMS).

[0037] In a specific embodiment, the epitaxial silicon wafer is, for example, rectangular, with one side of the rectangle ranging from 156 mm to 300 mm and the other side of the rectangle ranging from 83 mm to 300 mm.

[0038] It is understandable that the rectangle here can be a rectangle with unequal length and width, or a square with equal length and width. It is also understandable that the rectangle here is not necessarily a rectangle with strict geometric definition, and some chamfering or rounding is allowed as long as it is roughly rectangular.

[0039] In a specific embodiment, the epitaxial silicon wafer has a chamfer connecting two adjacent sides of the silicon wafer, and the projection length of the chamfer is 1 mm to 10 mm. The chamfer can be an arc edge or a straight edge.

[0040] The epitaxial silicon wafer preparation method of the present application is further described below in conjunction with the accompanying drawings:

[0041] Figure 1 The flowchart of the method for preparing an epitaxial silicon wafer according to an embodiment of the present application is schematically shown.

[0042] like Figure 1 As shown, the epitaxial silicon wafer preparation method of the present application is used to prepare the epitaxial silicon wafer of the present application. By growing a transition layer on the original silicon substrate, the lattice arrangement of the silicon substrate can be adjusted to obtain a silicon substrate with good flatness, and an epitaxial layer is grown on the substrate. Finally, the epitaxial silicon wafer is peeled off. The epitaxial silicon wafer has good flatness and high quality. When the thickness of the epitaxial silicon wafer is 70-150 μm, its flatness is less than 5 μm, and the solar cell prepared with the epitaxial silicon wafer has high photoelectric conversion efficiency.

[0043] A specific implementation of the present application, for example, includes operations S110 to S130.

[0044] In operation S110 , a transition layer is grown on the epitaxial side of the silicon substrate.

[0045] In operation S120 , a doped epitaxial layer is grown on a side of the transition layer away from the silicon substrate.

[0046] In operation S130 , the doped epitaxial layer is separated to obtain an epitaxial silicon wafer.

[0047] In operation S110, the silicon substrate is the basis for epitaxial growth. This application has no special requirements for the silicon substrate. For example, a silicon substrate with a diameter of 200 mm, a thickness of 625 μm, a resistivity of 0.1 Ω·cm, and a surface crystal orientation of <100> The silicon substrate may be a silicon wafer obtained by single crystal pulling method, direct silicon wafer, etc.

[0048] It should be noted that the epitaxial side of the silicon substrate refers to the surface where the epitaxial layer is to be grown, usually the front side of the silicon wafer.

[0049] It is understood that a transition layer is first grown on the epitaxial side of the silicon substrate. The transition layer is made of silicon (Si) material with a thickness ranging from 0.5 to 2 μm, and can be lightly doped to achieve a doping concentration transition. For example, the lightly doped layer can be a doping concentration of 1E17 cm -3 of phosphorus (P).

[0050] A transition layer is formed on the silicon substrate. Since the lattice parameters of the doped epitaxial layer are not completely the same as those of the silicon substrate, the transition layer is mainly used to adjust the arrangement of the silicon substrate lattice and reduce the stress distribution in the silicon substrate; thereby improving the flatness of the epitaxial doped silicon wafer grown on the silicon substrate with adjusted lattice arrangement.

[0051] In operation S120, the material of the doped epitaxial layer is silicon (Si), the thickness is 150 μm, and the concentration of the doping element is 1E16 cm -3 The doping elements are P-type boron, gallium, etc.; or they can be N-type phosphorus, arsenic, etc.

[0052] In an optional implementation, before growing the doped epitaxial layer, a portion of the thickness of the transition layer is removed along the thickness direction of the transition layer, and then the doped epitaxial layer is grown on the epitaxial side of the silicon substrate. Since defects in the silicon substrate migrate into the transition layer, the transition layer is partially removed, thereby reducing the defects in the transition layer and preventing them from entering the epitaxial doped layer. The specific implementation method includes: using dry etching technology to remove a portion of the thickness of the transition layer, for example, removing about 0.5 μm and leaving a 0.5 μm transition layer. Then, a doped epitaxial layer is grown on the thinned transition layer. This step helps to adjust the flatness of the final silicon wafer.

[0053] In an optional implementation, the present application discloses that the doping concentration of the epitaxial silicon wafer is lower than the doping concentration of the silicon substrate, and the doping concentration of the transition layer is between the doping concentration of the silicon substrate and the doping concentration of the epitaxial silicon wafer.

[0054] The doping concentration of the transition layer is between the doping concentration of the silicon substrate and the doping concentration of the epitaxial silicon wafer, which can form a gradient change in doping concentration in the direction from the silicon substrate to the epitaxial silicon wafer, and can adjust the arrangement between atoms in a gradient, so that the stress gradient changes along the direction from the silicon substrate to the epitaxial layer, thereby buffering these stress mismatches. Through the design of the transition layer, a gradient change in doping concentration is formed between the epitaxial silicon wafer and the silicon substrate, which alleviates the stress distribution of the silicon substrate, which helps to further improve the flatness of the epitaxial silicon wafer surface, thereby forming a higher quality epitaxial silicon wafer.

[0055] In addition, the present application also provides a solution for adding multiple transition layers and etching them. After the transition layer is formed, defects in the silicon substrate migrate to the transition layer, and the transition layer is partially removed, thereby reducing defects in the transition layer; therefore, by adding multiple transition layers with gradients and performing multiple gradient etchings on the multiple transition layers, defects in the transition layer are reduced and prevented from entering the epitaxial doping layer, thereby improving the flatness of the epitaxial wafer and obtaining a high-quality epitaxial wafer.

[0056] Figure 2 The silicon wafer epitaxial structure according to an embodiment of the present disclosure is schematically shown.

[0057] Combined with Figure 2 The steps of growing the transition layer in the present application include: growing a first sub-transition layer 2 on the epitaxial side of the silicon substrate 1; at least partially removing the first sub-transition layer 2; growing a second sub-transition layer 3 on the surface after at least partially removing the first sub-transition layer 2, and the doping concentration of the first sub-transition layer 2 is between the doping concentration of the silicon substrate 1 and the doping concentration of the second sub-transition layer 3.

[0058] In some optional implementations, the transition layer may include at least one sub-transition layer. For example, before growing the second sub-transition layer, a first sub-transition layer may be grown on the epitaxial side of the silicon substrate and partially or completely etched away.

[0059] Optionally, a first sub-transition layer is grown on the epitaxial side of the silicon substrate. Further, the first sub-transition layer can be made of silicon material with a thickness ranging from 1 to 3 μm, and can be lightly doped to reduce its resistivity. For example, the lightly doped layer can be doped at a concentration of 1E18 cm -3 The doping concentration of the first transition sub-layer is between the doping concentration of the silicon substrate and the doping concentration of the second transition sub-layer.

[0060] Since the doping concentration of the transition layer is between the doping concentration of the silicon substrate and the doping concentration of the epitaxial silicon wafer, a gradient change in doping concentration can be formed in the direction from the silicon substrate to the epitaxial silicon wafer, and the arrangement between atoms can be adjusted in a gradient manner, thereby forming a stress gradient change along the direction from the silicon substrate to the epitaxial layer and buffering the mismatch of these stresses. Through the design of a multi-layer transition layer with a gradient change in doping concentration, a gradient change in doping concentration is formed between the epitaxial silicon wafer and the silicon substrate, which can further relieve stress, which helps to further improve the flatness of the surface of the epitaxial silicon wafer, thereby forming a higher quality epitaxial silicon wafer.

[0061] The thickness of the first sub-transition layer can be, for example, 1 μm. Dry etching technology is used to remove part of the thickness of the first sub-transition layer, for example, about 0.5 μm is removed, leaving a 0.5 μm transition layer. The 1 μm first sub-transition layer can also be completely removed. In this step, since defects in the silicon substrate migrate to the transition layer after the transition layer is formed, partial removal of the transition layer reduces defects in the transition layer, helps to adjust the flatness of the silicon wafer, and ensures that the second sub-transition layer grown subsequently has a good contact interface.

[0062] After at least part of the first transition layer is removed, a second sub-transition layer is grown on the silicon substrate after the first sub-transition layer is removed.

[0063] Optionally, the second sub-transition layer may be made of silicon material with a thickness of about 1 μm, and may be slightly doped to reduce the resistivity, for example, the doping concentration is 1E17 cm -3 of phosphorus.

[0064] A dry etching technique is used to remove part of the thickness of the second sub-transition layer, for example, about 0.5 μm is removed, leaving a 0.5 μm transition layer. This step helps to further adjust the flatness of the final silicon wafer.

[0065] Then, a doped epitaxial layer is grown on the partially etched second sub-transition layer to obtain Figure 3 The epitaxial structure shown is finally peeled off to obtain an epitaxial silicon wafer.

[0066] This preparation method can further optimize the doping concentration and flatness before growing the second sub-transition layer by adding a first sub-transition layer, which helps to improve the reliability and consistency of the final product.

[0067] It is understandable that the silicon wafer preparation method of the present application can also directly grow the second sub-transition layer on the epitaxial side of the silicon substrate under different demand scenarios to simplify the production process and improve production efficiency.

[0068] Optionally, in order to further improve the flatness of the epitaxial silicon wafer, more sub-transition layers may be grown to further improve the flatness.

[0069] Preferably, the thickness of the first sub-transition layer is 1-3 μm, and the thickness of the second sub-transition layer is 0.5-2 μm.

[0070] According to the technical solution of the present application, the growth temperature of the doped epitaxial layer is lower than the growth temperature of the second sub-transition layer, and the growth temperature of the doped epitaxial layer is 1080-1100°C.

[0071] In some optional technical solutions, the growth temperature of the doped epitaxial layer is lower than the growth temperature of the second sub-transition layer. After the second sub-transition layer is grown at a temperature of 1120°C, a dry etching technique is used to remove part of the thickness of the second sub-transition layer to adjust the flatness of the final silicon wafer, for example, about 0.5 μm is removed to leave a 0.5 μm transition layer. The doped epitaxial layer is grown on the surface of the silicon substrate from which the second sub-transition layer has been removed using CVD technology, and the growth temperature of the doped epitaxial layer is 1080-1100°C. Furthermore, in order to ensure that the growth temperature of the doped epitaxial layer is lower than the growth temperature of the second sub-transition layer, the growth temperature can be selected to be 1090°C.

[0072] It should be noted that, in this embodiment, by controlling the growth temperature of the doped epitaxial layer to be lower than the growth temperature of the second sub-transition layer, the back diffusion rate of impurities in the phosphorus-doped silicon wafer can be reduced, thereby further optimizing the performance and reliability of the doped epitaxial layer.

[0073] In operation S130, the doped epitaxial layer can be separated from the silicon substrate by laser stripping or other suitable separation techniques, and the doped epitaxial layer after separation is an epitaxial silicon wafer. The epitaxial silicon wafer has a lower doping concentration and better electrical properties, and can be used as a substrate for other semiconductor devices, solar cells, etc.

[0074] By forming a transition layer on a silicon substrate, the surface morphology of the silicon wafer epitaxially grown on the silicon substrate can be improved. By setting multiple transition layers and partially removing the transition layers, since defects in the silicon substrate migrate to the transition layer after the transition layer is formed, the defects in the transition layer can be reduced by partially removing the transition layer, and the defects are prevented from entering the epitaxial doping layer, thereby improving the flatness of the epitaxial wafer and obtaining a high-quality epitaxial wafer. For example, the two transition layers in the present application can effectively improve the flatness of the silicon wafer surface, so that when the thickness of the silicon wafer is 70 to 150 μm, the flatness of the silicon wafer surface is less than 1 μm, which is lower than the flatness of the silicon wafer surface prepared by the conventional epitaxial growth method at the same thickness.

[0075] Figure 3 The flowchart of growing a gettering layer on a silicon substrate before growing a transition layer according to an embodiment of the present application is schematically shown.

[0076] The difference from the above embodiment is that, according to the embodiment of the present application, Figure 3 As shown, before growing the transition layer, the method of the embodiment of the present application includes operations S310 to S320.

[0077] In operation S310 , a gettering layer is grown on an epitaxial side of a silicon substrate.

[0078] In operation S320 , the gettering layer is removed.

[0079] It should be noted that in operation S310, the function of the gettering layer is to make the metal impurities (such as Fe, Cu, Ni, Co, Au, etc.) contained in the silicon substrate itself be absorbed, enriched and fixed by the gettering layer, thereby reducing the content of metal impurities in the silicon substrate; and when the gettering layer is removed, the purity of the entire silicon substrate is high, especially the purity of the position close to the gettering layer is higher, thereby improving the quality of the silicon wafer grown on the silicon substrate.

[0080] In a specific embodiment, the material of the gettering layer may be, for example, silicon germanium alloy (SiGe) or doped silicate glass. Further, the doped silicate glass may be a borosilicate glass layer, a phosphosilicate glass layer or a borophosphosilicate glass layer.

[0081] It is understandable that the present application has no special requirements on the thickness of the gettering layer, which is generally about 2 μm.

[0082] When the gettering layer is a borosilicate glass layer, it can be prepared in the following manner:

[0083] At a temperature of 1100°C, using silicon tetrachloride (SiCl4) and trimethyl boron (TMB) as precursor gases, a borosilicate glass layer (BSG) with a thickness of about 2μm is grown on the epitaxial side of the silicon substrate (usually the front side of the silicon wafer).

[0084] When the gettering layer is a phosphosilicate glass layer, it can be prepared and formed in the following manner:

[0085] A phosphosilicate glass layer (PSG) with a thickness of about 2 μm was grown on the epitaxial side of a silicon substrate at a temperature of 1110°C using silicon tetrachloride and phosphine (PH3) as precursor gases.

[0086] When the gettering layer is a borophosphosilicate glass layer, it can be prepared and formed in the following manner:

[0087] Boron diffusion is performed first, followed by phosphorus diffusion, to obtain borophosphosilicate glass.

[0088] Alternatively, a borophosphosilicate glass layer (BPSG) with a thickness of about 2 μm may be grown on the epitaxial side of the silicon substrate at a temperature of 1120° C. using silicon tetrachloride, trimethylboron and phosphine as precursor gases.

[0089] The use of BPSG can provide better dielectric properties due to its combination of diffusion depth into epitaxial silicon wafers and its ability to dissolve metal impurities, and is more conducive to the removal of metal impurities in the silicon substrate, thereby achieving a better impurity gettering effect.

[0090] It is understandable that, under the same temperature conditions, only borane or phosphine diffusion may be performed to obtain a borosilicate glass layer or a phosphosilicate glass layer as a doping layer to save raw materials or simplify the process.

[0091] The preparation method of the doping layer of the present application can effectively reduce the metal impurity content in the silicon wafer and control the doping concentration. For those skilled in the art, the properties of the material can be adjusted according to specific needs to use different types of doping layers to dope the silicon substrate, and the present application does not limit this.

[0092] In operation S320, the purpose of removing the gettering layer is to remove the metal impurities accumulated in the gettering layer together with the gettering layer, thereby making the epitaxial side of the silicon substrate cleaner. The present application may use dry etching technology to remove the gettering layer, such as plasma etching or gas etching.

[0093] Then, after removing the gettering layer, a doped epitaxial layer is grown on the epitaxial side of the silicon substrate, and a doped epitaxial layer is grown on the surface of the silicon substrate after removing the gettering layer. The material of the doped epitaxial layer is also silicon (Si). In a specific embodiment, the thickness of the doped epitaxial layer is 150 μm, and the doping concentration is 1E16 cm -3 The doping elements can be P-type boron, gallium, etc.; or N-type phosphorus, arsenic, etc. This preparation method can effectively reduce the metal impurity content in the silicon wafer and control the doping concentration, thereby improving the performance and reliability of the final device. The peeled silicon substrate can be reused, which is conducive to improving production efficiency.

[0094] In order to further reduce the flatness of the silicon substrate, the present application also provides a feasible technical solution. On the basis of the above-mentioned preparation method, after removing the doping layer, before growing the doped epitaxial layer on the epitaxial side of the silicon substrate, an intrinsic epitaxial layer is grown on the surface of the silicon substrate after removing the doping layer, and the intrinsic epitaxial layer is removed.

[0095] Specifically, after removing the gettering layer by dry etching, a layer of intrinsic epitaxial layer is grown on the epitaxial side of the silicon substrate by chemical vapor deposition technology. The intrinsic epitaxial layer is composed of undoped silicon and has a thickness of about 1 μm.

[0096] The present application grows an intrinsic layer after doping, and the intrinsic epitaxial layer can wrap the epitaxial growth chamber and the entire silicon substrate, solidify metal impurities, and prevent impurities and dopants from overflowing. After the doping layer is removed, the grown intrinsic epitaxial layer can further capture metal impurities that may exist inside the silicon wafer, achieve further doping of the silicon substrate, and further improve the purity of the silicon substrate, thereby improving the purity of the epitaxial wafer grown on the silicon substrate after doping.

[0097] Optionally, the growth temperature of the intrinsic epitaxial layer is 1120-1150° C. The intrinsic epitaxial layer can be grown by using hydrogen to transport gaseous trichlorosilane, wherein the hydrogen flow rate is 120-140 L / min and the trichlorosilane flow rate is 15-20 slm.

[0098] Then, dry etching techniques are used to remove the intrinsic epitaxial layer, such as plasma etching or etching with hydrogen chloride gas. After etching, the surface of the silicon substrate should be clean and free of impurities. After the initial silicon wafer is processed, most of the metal impurities in it have been removed, and when epitaxial growth is performed on it, the epitaxial wafer grown is of higher purity.

[0099] Finally, a transition layer and a doped epitaxial layer are grown and peeled off to obtain an epitaxial silicon wafer.

[0100] In the preparation method of the epitaxial silicon wafer, an intrinsic epitaxial layer is added as a secondary gettering layer. Since the intrinsic epitaxial layer can quickly encapsulate the entire reaction chamber, the surface and edge of the silicon wafer, the impurities are further solidified and the overflow of impurities and dopants is prevented, and the purity of the silicon wafer can be further improved after the first gettering treatment. This method helps to improve the reliability and consistency of the final product. Through two gettering treatments, the metal impurity content in the silicon wafer can be significantly reduced, thereby improving the performance of the final device.

[0101] In order to reduce the impurity content in the epitaxial silicon wafer, hydrogen gas may be used to purge the silicon substrate and / or the reaction chamber of the epitaxial furnace before or after at least one step of the epitaxial silicon wafer preparation method.

[0102] Before starting any epitaxial growth, the silicon substrate is purged with hydrogen (H2) with a purity of ≥99.9999% to remove contaminants and oxide layers on the surface. The hydrogen purge lasts for about 1 to 2 minutes. After the purge is completed, the surface of the silicon substrate should be clean and free of impurities.

[0103] For those skilled in the art, before growing the intrinsic epitaxial layer, the first sub-transition layer, the second sub-transition layer, and the doped epitaxial layer, the silicon substrate can be purged with hydrogen to remove possible surface contamination. The hydrogen purging lasts for about 8 to 10 minutes. After the purging is completed, the surface of the silicon substrate should be clean and free of impurities.

[0104] It is understandable that by using hydrogen purge, the cleanliness of the silicon wafer surface can be further improved, the impact of pollutants can be reduced, and the reliability and consistency of the final product can be improved. Through two impurity treatments and two transition layer growth and etching, plus multiple hydrogen purges, the metal impurity content in the epitaxial silicon wafer can be significantly reduced, thereby improving the performance of the final device.

[0105] Optionally, the epitaxial furnace is a normal pressure flat-plate epitaxial furnace. The normal pressure flat-plate epitaxial furnace is simple to operate, relatively low in cost, and suitable for large-scale production.

[0106] Optionally, the silicon substrate of the present application is an N-type single crystal silicon wafer or a P-type single crystal silicon wafer. For those skilled in the art, a silicon substrate, a transition layer and an epitaxial silicon wafer with the same doping type can be selected to ensure the electrical characteristics and performance consistency of the final product.

[0107] The epitaxial silicon wafer growth method of the present invention is used to perform a gettering treatment on the silicon substrate, so that the purity of the silicon substrate is high and the metal impurity content is less than 1E+8 atom / cm 3 Compared with the metal impurity content of conventional epitaxial silicon wafers at 1E+10 atom / cm 3 , its metal impurity content is significantly reduced, the purity of the silicon wafer is high, and it is more conducive to the preparation of high-quality epitaxial silicon wafers.

[0108] In an optional technical solution of the present application, a transition layer is grown on the silicon substrate after the doping layer is removed. By growing a transition layer with a gradual doping concentration, and gradually etching the transition layer (i.e., at least partially etching), and purging with hydrogen, the metal impurity content in the epitaxial silicon wafer can be reduced while reducing the flatness of the surface of the epitaxial silicon wafer. Compared with the conventional silicon wafer flatness of about 10 μm, the method of the present application can make the flatness of the silicon wafer surface less than 5 μm. It can be seen that the epitaxial silicon wafer grown by the method of the present application can reduce the metal impurity content and reduce the flatness of the surface of the epitaxial silicon wafer.

[0109] It should be noted that since the lattice parameters of epitaxial silicon wafers are not exactly the same as those of silicon substrates, epitaxial growth directly on silicon substrates will lead to higher stress accumulation, which in turn causes defects such as dislocations. By adding a transition layer between the silicon substrate and the doped epitaxial layer, the stress caused by lattice mismatch can be reduced and buffered, which helps to form higher quality epitaxial silicon wafers.

[0110] The present application also provides another method for preparing epitaxial silicon wafers. By adding a multi-layer transition layer with a gradient doping concentration and etching the multi-layer transition layer with a gradient thickness multiple times, the flatness of the surface of the epitaxial silicon wafer can be improved while reducing the metal impurity content, thereby reducing the defects on the surface of the epitaxial silicon wafer.

[0111] The technical solution of the present application also provides a method of growing a gettering layer on one side of the silicon substrate for epitaxial growth during the preparation process of the epitaxial silicon wafer, taking advantage of the fact that the diffusion coefficient of metal impurity elements in the silicon substrate is usually greater than the self-diffusion coefficient of silicon, and removing the gettering layer after solidifying the metal impurities in the silicon substrate, especially under high temperature conditions, thereby achieving the purpose of removing the metal impurities in the silicon substrate. The epitaxial layer is grown on the silicon substrate after the gettering, and the obtained epitaxial silicon wafer has less metal impurity content and high quality.

[0112] The present application also provides the following four specific examples and one comparative example for specifically illustrating the product performance of the epitaxial silicon wafer provided by the embodiments of the present invention:

[0113] Example 1

[0114] The specific steps of preparing an epitaxial silicon wafer using the epitaxial silicon wafer preparation method of the present application are as follows:

[0115] A phosphorus-doped single crystal silicon wafer with a thickness of 150 μm was loaded into the carrier of the epitaxial furnace. The reaction chamber of the epitaxial furnace was purged with hydrogen with a purity of ≥99.9999% to exhaust and replace the gas in the reaction chamber. The temperature was 1130 °C, the flow rate of hydrogen was set to 100 L / min, and the purging time was set to 2 min.

[0116] Hydrogen is introduced into the reaction chamber to carry trichlorosilane and phosphine as dopants, and a transition layer is grown on the silicon substrate to prevent surface defects (dislocations, stacking faults, and scratches) of the silicon substrate from extending to the doped epitaxial layer. The hydrogen flow rate is set to 140 L / min, the trichlorosilane flow rate is set to 20 slm, the phosphine flow rate is set to 180 sccm, the growth time is set to 30 s, and the growth temperature is 1130 °C.

[0117] The growth of the required doped epitaxial layer is carried out on the side of the transition layer away from the silicon substrate, and the growth temperature is 1100 ° C. It should be noted that the use of a relatively low growth temperature can reduce the back diffusion rate of impurities in the phosphorus-doped silicon wafer, which is conducive to obtaining better thickness uniformity and resistivity uniformity. In this embodiment, hydrogen is used to transport trichlorosilane and phosphine dopants into the reaction chamber, with a hydrogen flow rate of 350 L / min, a trichlorosilane flow rate of 25 slm, a phosphine flow rate of 120 sccm, and an epitaxial layer growth rate of 6.5μm / min.

[0118] When the epitaxial silicon wafer grows to a predetermined thickness, it begins to cool down. The reaction chamber is purged with hydrogen at a flow rate of 370 L / min. The purging time is set to 15 min to remove the reaction byproducts of the growth process from the reaction chamber. After the temperature of the silicon epitaxial wafer drops to room temperature, it is taken out from the carrier.

[0119] Finally, the silicon substrate is cut implicitly by laser to separate the silicon substrate and the epitaxial silicon wafer.

[0120] Example 2

[0121] In order to further improve the flatness of the silicon wafer surface, the present application proposes another feasible technical solution. Different from Embodiment 1, in this embodiment, before growing the doped epitaxial layer, at least a portion of the transition layer (the first sub-transition layer) and the growth of the second sub-transition layer are removed, which specifically includes:

[0122] Hydrogen chloride gas was introduced to etch the first sub-transition layer, the gas flow rate was set to 4-6 L / min, the etching time was set to 150-200 s, and 0.5-1 μm of the first sub-transition layer deposited earlier was removed by etching. Then, hydrogen gas with a flow rate of 250-280 L / min was used to purge the reaction chamber for 5-8 min to remove the reaction by-products from the reaction chamber.

[0123] By introducing hydrogen gas into the reaction chamber with trichlorosilane and phosphine dopants on the silicon wafer, the second sub-transition layer is grown on it to further block defects and adjust the flatness of the epitaxial silicon wafer, and at the same time serve as a buffer layer. The hydrogen flow rate is set to 140 L / min, the gaseous trichlorosilane flow rate is set to 18 slm, the phosphine flow rate is set to 150 sccm, the growth time is set to 25 s, and the growth temperature is 1130 ℃.

[0124] Hydrogen chloride gas was introduced to etch the second sub-transition layer, the gas flow rate was set to 6 L / min, the etching time was set to 150 s, and 0.7 μm of the deposited second sub-transition layer was removed by etching. Then, hydrogen gas with a flow rate of 280 L / min was used to purge the reaction chamber for 8 min to remove the reaction by-products from the reaction chamber.

[0125] Example 3

[0126] The difference from Example 1 is that, in the epitaxial silicon wafer preparation method of the embodiment of the present application, before the transition layer is used to adjust the flatness of the silicon substrate, a gettering layer is grown to remove metal impurities in the silicon substrate, which specifically includes:

[0127] Subsequently, hydrogen is used as a carrier gas to carry BH3 gas, and borane is diffused at high temperature. Then, hydrogen carries PH3 gas, and phosphine is diffused at high temperature to induce doping with silicon oxide on the surface of the silicon wafer to form borophosphosilicate glass to solidify the metal impurities. The temperature is, for example, 1150°C, the flow rate of hydrogen is set to 120 L / min, the flow rate of phosphine is set to 250 sccm, the flow rate of borane is set to 250 sccm, and the growth time is set to 15 min.

[0128] The epitaxial furnace reaction chamber and silicon wafer are subjected to gas etching and polishing at high temperature using hydrogen chloride with a purity of ≥99.9999%, so as to completely remove the borophosphosilicate glass impurities on the surface of the silicon wafer. For example, the temperature is 1150°C, the hydrogen chloride gas flow rate is 8 L / min, and the etching time is 20 min.

[0129] A large flow of hydrogen was used to continuously purge the surface of the silicon wafer to completely remove the byproduct of borophosphosilicate glass produced during hydrogen chloride polishing and the impurities adsorbed on the surface of the silicon wafer and the surface of the base. The hydrogen flow rate was 280 L / min and the time was 10 min.

[0130] Example 4

[0131] The difference from the third embodiment is that after the gettering layer is removed and before the doped epitaxial layer is grown, an intrinsic epitaxial layer is grown on the surface of the silicon substrate from which the gettering layer is removed, which specifically includes:

[0132] Undoped trichlorosilane was used to grow an intrinsic epitaxial layer on the silicon wafer, and the entire reaction chamber, the surface and the edge of the silicon wafer were quickly encapsulated and solidified to prevent the overflow of impurities and dopants. The growth temperature of the intrinsic epitaxial layer was 1150 °C, and the encapsulation was quickly completed using a high-temperature rapid intrinsic growth method. Hydrogen was used to transport gaseous trichlorosilane into the reaction chamber, the hydrogen flow rate was controlled at 140 L / min, the trichlorosilane flow rate was set to 20 slm, the intrinsic layer growth rate was controlled at 5.5μm / min, and the growth time was controlled at 60 s.

[0133] The reaction chamber and the silicon wafer surface are continuously etched and purged with a large flow of hydrogen, so that the impurities volatilized from the reaction chamber and the silicon wafer are taken out of the reaction chamber by the large flow of hydrogen, effectively suppressing the influence of the inactive doping effect. The hydrogen flow rate is 280 L / min and the time is 10 min.

[0134] Comparative Example 1

[0135] The difference from Example 1 is that the transition layer is not grown, and the epitaxial layer is directly grown on the silicon substrate. The growth process of the epitaxial layer is the same as that of Example 1, and an epitaxial silicon wafer is obtained.

[0136] By testing the surface flatness and metal impurity content of 300 pcs epitaxial silicon wafers prepared in Examples 1 to 4 with a thickness of 100 μm, the measurement results are shown in the table:

[0137]

[0138] By comparing the above data, it is found that the flatness of the epitaxial silicon wafer obtained by the silicon wafer preparation method of Examples 1 to 4, growing a transition layer on a silicon substrate and then performing epitaxial growth, is significantly lower than that of the epitaxial silicon wafer obtained in Comparative Example 1 without performing transition layer growth treatment.

[0139] The surface flatness of the epitaxial silicon wafers of Example 2 and Example 1 is significantly reduced compared with Comparative Example 1. The flatness of Example 2 is further improved compared with Example 1, which shows that the flatness of the silicon wafer surface can be effectively and significantly reduced after the preparation of the gradual transition layer.

[0140] The surface flatness of the epitaxial silicon wafers of Examples 3 and 4 is also significantly improved compared with Examples 1, 2, and Comparative Example 1, which indicates that after the silicon substrate is treated with a gettering layer, the metal impurity content of the silicon substrate is reduced, and growing a transition layer on the silicon substrate can further improve the surface flatness of the silicon wafer.

[0141] In summary, the present application introduces a transition layer in the preparation of epitaxial silicon wafers, which can block interface defects. In particular, by adding a gradient multi-layer transition layer and then performing multiple gradient etchings, the defects on the surface of the silicon wafer are reduced, and the flatness of the surface of the silicon wafer is reduced. The solar cell prepared using the epitaxial silicon wafer has the characteristics of high photoelectric conversion efficiency, good electrical properties, etc., and is suitable for manufacturing various high-performance solar panels.

[0142] The unfinished details in the product example section are similar to those in the method example section. Please refer to the method example section and will not be repeated here.

[0143] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present application. The attached method claims present the elements of the various steps in an exemplary order and are not intended to be limited to a specific order or hierarchy.

[0144] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present application. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted when they may cause confusion in the understanding of the present application. In addition, the shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual sizes, proportions, and actual positional relationships.

[0145] In the above detailed description, various features are grouped together in a single embodiment to simplify the present application. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than those clearly stated in each claim. On the contrary, as reflected in the attached claims, the present application is in a state of having less than all the features of the disclosed individual embodiments. Therefore, the attached claims are hereby expressly incorporated into the detailed description, with each claim acting alone as a separate preferred embodiment of the present application.

[0146] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. With respect to the term "comprising" used in the specification or claims, the word is covered in a manner similar to the term "including", just as "including," is explained as a transitional word in the claims. Any term "or" used in the specification of the claims is intended to mean "non-exclusive or".

[0147] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. An epitaxial silicon wafer, characterized in that: When the thickness of the epitaxial silicon wafer is 70-150 μm, the flatness of the epitaxial silicon wafer is less than 5 μm.

2. The epitaxial silicon wafer according to claim 1, characterized in that: The metal impurity content of the epitaxial silicon wafer is less than 1E+9 atom / cm 3 .

3. The epitaxial silicon wafer according to claim 2, characterized in that: The oxygen content of the epitaxial silicon wafer is less than 7E+15atom / cm 3 The carbon content of the epitaxial silicon wafer is less than 8E+15 atom / cm 3 .

4. The epitaxial silicon wafer according to any one of claims 1 to 3, characterized in that: The epitaxial silicon wafer is rectangular, and has a first side and a second side, wherein the first side and the second side are adjacent sides; The length of the first side is 156 mm to 300 mm, and the length of the second side is 83 mm to 300 mm.

5. The epitaxial silicon wafer according to claim 4, characterized in that: The epitaxial silicon wafer is provided with a chamfer connecting the first edge and the second edge, and the projection length of the chamfer is 1 mm to 10 mm.

6. A method for preparing an epitaxial silicon wafer, characterized in that: include: growing a transition layer on the epitaxial side of the silicon substrate; Growing a doped epitaxial layer on a side of the transition layer away from the silicon substrate; The doped epitaxial layer is separated to obtain an epitaxial silicon wafer.

7. The method for preparing an epitaxial silicon wafer according to claim 6, characterized in that: Also includes: Before growing the doped epitaxial layer, the transition layer is partially removed along the thickness direction of the transition layer.

8. The method for preparing an epitaxial silicon wafer according to claim 6, characterized in that: The doping concentration of the epitaxial silicon wafer is less than the doping concentration of the silicon substrate; The doping concentration of the transition layer is between the doping concentration of the silicon substrate and the doping concentration of the epitaxial silicon wafer.

9. The method for preparing an epitaxial silicon wafer according to claim 6, characterized in that: The step of growing a transition layer on the epitaxial side of the silicon substrate comprises: Growing a first sub-transition layer on the epitaxial side of the silicon substrate; at least partially removing the first transition sub-layer; A second sub-transition layer is grown on the surface after at least a portion of the first sub-transition layer is removed, and the doping concentration of the first sub-transition layer is between the doping concentration of the silicon substrate and the doping concentration of the second sub-transition layer.

10. The method for preparing an epitaxial silicon wafer according to claim 9, characterized in that: The thickness of the first sub-transition layer is 1-3 μm, and the thickness of the second sub-transition layer is 0.5-2 μm.

11. The method for preparing an epitaxial silicon wafer according to claim 9 or 10, characterized in that: The growth temperature of the doped epitaxial layer is lower than the growth temperature of the second sub-transition layer, and the growth temperature of the doped epitaxial layer is 1080-1100°C.

12. The method for preparing an epitaxial silicon wafer according to claim 6, characterized in that: Before growing the transition layer, the method further comprises: growing a gettering layer on the epitaxial side of the silicon substrate; The gettering layer is removed.

13. The method for preparing an epitaxial silicon wafer according to claim 12, characterized in that: The gettering layer is made of a borosilicate glass layer, a phosphosilicate glass layer or a borophosphosilicate glass layer.

14. The method for preparing an epitaxial silicon wafer according to claim 13, characterized in that: The step of growing the borophosphosilicate glass layer comprises: Boron diffusion is performed first, and then phosphorus diffusion is performed to obtain the borophosphosilicate glass layer.

15. The method for preparing an epitaxial silicon wafer according to any one of claims 12 to 14, characterized in that: After removing the gettering layer and before growing the doped epitaxial layer, the method further comprises: An intrinsic epitaxial layer is grown on the surface of the silicon substrate after the gettering layer is removed.

16. The method for preparing an epitaxial silicon wafer according to claim 15, characterized in that: The growth temperature of the intrinsic epitaxial layer is 1120-1150°C; Using hydrogen to transport gaseous trichlorosilane to grow the intrinsic epitaxial layer; Among them, the hydrogen flow rate is 120~140 L / min, and the trichlorosilane flow rate is 15~20 slm.

17. A solar cell, characterized in that: include: A silicon substrate, wherein the silicon substrate is the epitaxial silicon wafer according to any one of claims 1 to 5.

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