Preparation method of photovoltaic cell and photovoltaic cell

Abstract

The invention relates to a preparation method of a photovoltaic cell and the photovoltaic cell. The preparation method comprises the following steps: texturing a substrate; manufacturing a PN junction on the textured substrate; removing the borosilicate glass layer on the back surface and the periphery of the substrate, and etching PN junctions on the back surface and the periphery of the substrate; generating a tunneling oxide layer and an amorphous silicon layer on the substrate; performing phosphorus diffusion on the substrate to generate a polycrystalline silicon layer; removing the phosphorosilicate glass layer in a non-grid line area on the back surface of the substrate; etching the polycrystalline silicon layer in the non-grid line area on the back surface of the substrate; and carrying out film coating and printing on the substrate. In this way, the occurrence of parasitic absorption can be reduced by reducing the thickness of the polycrystalline silicon layer in the non-grid line region, so that the efficiency of the photovoltaic cell can be improved. Moreover, a step structure can be formed between the polycrystalline silicon layer of the grid line area and the polycrystalline silicon layer of the non-grid line area through height difference, thereby facilitating the improvement of the utilization rate of light, and further improving the efficiency of the photovoltaic cell.

Description

Technical Field

[0001] The present application relates to the technical field of photovoltaic modules, and in particular to a method for preparing a photovoltaic cell and a photovoltaic cell. Background Art

[0002] With the development of technology, photovoltaic modules are being used more and more widely. Among them, tunnel oxide passivated contact solar cells (TOPcon) have been widely used due to their high conversion efficiency and good adaptability. Photovoltaic cells have a polysilicon layer. When the thickness of the polysilicon layer is large, it will lead to increased parasitic absorption, affecting the efficiency of the photovoltaic cell. When the thickness of the polysilicon layer is small, it will lead to increased contact resistance. It is necessary to upgrade the screen slurry to make up for the efficiency loss, resulting in an increase in the production cost of photovoltaic cells. Summary of the invention

[0003] In view of this, the present application provides a method for preparing a photovoltaic cell and a photovoltaic cell, so as to improve the efficiency of the photovoltaic cell.

[0004] In a first aspect, an embodiment of the present application provides a method for preparing a photovoltaic cell, the method comprising:

[0005] Velveting the substrate;

[0006] Making a PN junction on the substrate after texturing;

[0007] Removing the borosilicate glass layer on the back and surrounding of the substrate, and etching the PN junction on the back and surrounding of the substrate;

[0008] Generating a tunneling oxide layer and an amorphous silicon layer on the substrate;

[0009] Diffusion of phosphorus on the substrate to form a polysilicon layer;

[0010] removing the phosphorus silicon glass layer located in the non-gate line area on the back side of the substrate;

[0011] Etching the polysilicon layer in the non-gate line area on the back side of the substrate;

[0012] The substrate is plated and printed.

[0013] In a possible implementation manner, before the step of etching the polysilicon layer in the non-gate line area on the back side of the substrate, the preparation method includes:

[0014] An oxide layer with a thickness of 1 nm to 3 nm is generated in the non-gate line area.

[0015] In a possible implementation manner, the step of generating an oxide layer in the non-gate line area includes:

[0016] An oxide layer is generated in the non-gate line area by thermal oxidation using a chain oxygen device, with an oxygen flow rate of 5000 sccm to 12000 sccm, a temperature of 200° C. to 350° C., and a belt speed of 3.5 m / min to 4.5 m / min.

[0017] In a possible implementation manner, the step of removing the phosphosilicate glass layer in the non-gate line area on the back side of the substrate includes:

[0018] The thickness of the phosphosilicate glass layer is reduced by 3nm to 10nm by laser, the laser power is 50W to 60W, the speed is 40000mm / s to 70000mm / s, the frequency is 500kHz to 800kHz, the wavelength is 500nm to 600nm, and the pulse width is 0.4 to 0.6.

[0019] In a possible implementation manner, the step of etching the polysilicon layer in the non-gate line area on the back side of the substrate includes:

[0020] The polysilicon layer is etched to reduce the thickness by 90 nm to 120 nm. After etching, the thickness of the polysilicon layer is 30 nm to 60 nm.

[0021] In a possible implementation manner, the step of etching the polysilicon layer in the non-gate line area on the back side of the substrate includes:

[0022] The substrate is placed in a functional tank containing an alkaline solution with a volume concentration of 4% to 8% KOH and 4L to 6L additives, the reaction time is 260s to 310s, the reaction temperature is 55°C to 70°C, and the substrate is cleaned by an industrial standard wet cleaning process.

[0023] In one possible implementation, the step of cleaning the substrate by an industrial standard wet cleaning process includes:

[0024] The polysilicon layer on the front side and the surrounding area of ​​the substrate is removed.

[0025] In a possible implementation, before removing the polysilicon layer on the front side and the surrounding of the substrate, the step of cleaning the substrate by an industrial standard wet cleaning process includes:

[0026] The front side of the substrate and the surrounding phosphosilicate glass layer were removed by chain HF.

[0027] In a possible implementation, the steps of coating and printing the substrate include:

[0028] depositing aluminum oxide on the front side of the substrate by atomic layer deposition;

[0029] A SiN film is plated on the substrate and screen printed.

[0030] A second aspect of the present application provides a photovoltaic cell, wherein the photovoltaic cell is prepared by any of the above methods for preparing a photovoltaic cell;

[0031] The photovoltaic cell includes a substrate, a polysilicon layer is arranged on the back side of the substrate, the back side of the substrate includes a gate line area and a non-gate line area, the thickness of the polysilicon layer in the gate line area is a, the thickness of the polysilicon layer in the non-gate line area is b, and 90mm≤ab≤120㎜.

[0032] The present application provides a method for preparing a photovoltaic cell and a photovoltaic cell, the preparation method comprising: texturing a substrate; making a PN junction on the substrate after texturing; removing the borosilicate glass layer on the back and around the substrate, etching the PN junction on the back and around the substrate; generating a tunneling oxide layer and an amorphous silicon layer on the substrate; diffusing phosphorus on the substrate to generate a polysilicon layer; removing the phosphorus silicon glass layer in the non-gate line area on the back of the substrate; etching the polysilicon layer in the non-gate line area on the back of the substrate; coating and printing the substrate. In this way, the occurrence of parasitic absorption can be reduced by thinning the thickness of the polysilicon layer in the non-gate line area, thereby improving the efficiency of the photovoltaic cell. In addition, a step structure can be formed between the polysilicon layer in the gate line area and the polysilicon layer in the non-gate line area through a height difference, which is beneficial to improving the utilization rate of light and further improving the efficiency of the photovoltaic cell.

[0033] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0035] Figure 1 A schematic diagram of a method for preparing a photovoltaic cell provided in this application;

[0036] Figure 2 A schematic diagram of the steps of generating an oxide layer in a non-gate line area provided in the present application;

[0037] Figure 3 A schematic diagram of the steps of removing the phosphorus silicon glass layer in the non-gate line area provided in the present application;

[0038] Figure 4 A schematic diagram of the steps of coating and printing a substrate provided in this application;

[0039] Figure 5 A schematic diagram of the structure of the photovoltaic cell provided in this application;

[0040] Figure 6 A schematic diagram of the structure of the substrate after texturing provided in an embodiment of the present application;

[0041] Figure 7 A schematic diagram of the structure of the substrate provided in the embodiment of the present application after the PN junction is made;

[0042] Figure 8 This is a schematic diagram of the structure after removing the borosilicate glass layer and the PN junction on the back and surrounding of the substrate provided in the embodiment of the present application;

[0043] Fig. 9 A schematic diagram of the structure after a tunnel oxide layer and an amorphous silicon layer are made on the substrate provided in an embodiment of the present application;

[0044] Fig.10 A schematic diagram of the structure of the substrate after phosphorus diffusion provided in an embodiment of the present application;

[0045] Fig.11 A schematic diagram of the structure of removing the phosphosilicate glass layer in the non-gate line area on the back side of the substrate provided in an embodiment of the present application;

[0046] Fig.12 A schematic diagram of a structure for generating an oxide layer in a non-gate line region of a substrate provided in an embodiment of the present application;

[0047] Fig.13 This is a schematic diagram of the structure of the substrate provided in an embodiment of the present application after the phosphosilicate glass layer on the front and surrounding areas is removed;

[0048] Fig.14 A schematic diagram of the structure of a substrate after RCA cleaning provided in an embodiment of the present application;

[0049] Fig.15 A schematic diagram of the structure after aluminum oxide is deposited on a substrate provided in an embodiment of the present application;

[0050] Fig.16 This is a schematic diagram of the structure of the substrate provided in an embodiment of the present application after coating and printing.

[0051] Reference numerals

[0052] 1- substrate;

[0053] 2-boron doped layer;

[0054] 3- amorphous silicon layer;

[0055] 4-aluminum oxide layer;

[0056] 5-silicon nitride layer;

[0057] 6- Tunneling oxide layer;

[0058] 7-polysilicon layer;

[0059] 8-Electrode;

[0060] 9-phosphosilicate glass layer;

[0061] 10- oxide layer;

[0062] 20-Borosilicate glass layer. DETAILED DESCRIPTION

[0063] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0064] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0065] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0066] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0067] like Figure 1 As shown, the embodiment of the present application provides a method for preparing a photovoltaic cell, which is used to prepare a photovoltaic cell. The photovoltaic cell can be a tunnel oxide passivated contact solar cell (tunnel oxide pass ivated contact, TOPcon) cell. The preparation method includes:

[0068] S1, texturing the substrate 1.

[0069] S2. Making a PN junction on the substrate 1 after texturing.

[0070] S3, removing the borosilicate glass layer on the back and surrounding of the substrate 1.

[0071] S4 , forming a tunnel oxide layer 6 and an amorphous silicon layer 3 on the substrate 1 .

[0072] S5 , diffuse phosphorus into the substrate 1 to form a polysilicon layer 7 .

[0073] S6, removing the phosphosilicate glass layer 9 located in the non-gate line area on the back side of the substrate 1.

[0074] S7, etching the polysilicon layer 7 in the non-gate line area on the back side of the substrate 1.

[0075] S8, coating and printing the substrate 1.

[0076] The substrate 1 can be a silicon wafer. By processing and treating the silicon wafer, a cell can be obtained. The cell can be used in a photovoltaic module for photovoltaic power generation. During processing, the substrate 1 is etched to form a light-trapping velvet structure on the substrate 1. Texturing the substrate 1 can help improve the absorption rate of light on the surface of the substrate 1, thereby helping to improve the photoelectric conversion efficiency. Texturing the substrate 1 can help remove the mechanical damage layer on the surface of the substrate 1, and at the same time can remove oil and metal impurities on the surface, and increase the light-receiving area. The scheme provided in the embodiment of the present application can be used to prepare photovoltaic cells. The front side of the substrate 1 is the direction from the light-receiving surface to the backlight side of the photovoltaic module. The side close to the light-receiving surface is the front side, and the side away from the light-receiving surface is the back side. Usually, along the thickness direction of the substrate 1, the light-receiving surface and the backlight side are located on opposite sides of the substrate 1. The texturized substrate 1 is placed in a diffusion furnace, and impurities are diffused using boron trichloride as a boron source to form a PN junction battery structure on the substrate 1. The borosilicate glass (BSG) layer on the back and around the substrate 1 is removed by alkali etching, and the back of the substrate 1 is polished. The back of the substrate 1 and the PN junction around it are etched. Then, the substrate 1 is subjected to high-temperature oxidation, a tunneling oxide layer 6 is deposited, and an intrinsic amorphous silicon layer 3 is deposited on the front and back of the substrate 1. After the tunneling oxide layer 6 and the amorphous silicon layer 3 are generated on the substrate 1, the substrate 1 is placed in a diffusion furnace, and the amorphous silicon layer 3 is converted into polycrystalline silicon at high temperature, and crystallization is completed. Phosphorus oxychloride is used as a phosphorus source for diffusion, and an n+ doped polycrystalline silicon (poly-Si) layer is formed on the substrate 1, and a phosphate silicon glass (PSG) layer is formed on the surface of the polycrystalline silicon layer 7. The back of the substrate 1 includes a gate line area and a non-gate line area, and the gate line area is used to set the gate line. The phosphorus-doped substrate 1 is processed to remove the phosphorus-silicate glass layer 9 in the non-gate line area on the back of the substrate 1, and the phosphorus-silicate glass layer 9 in the gate line area is retained to protect the polysilicon layer 7 in the gate line area during the step of etching the polysilicon in the non-gate line area. After removing the phosphorus-silicate glass layer 9 in the non-gate line area on the back of the substrate 1, the polysilicon layer 7 in the non-gate line area on the back of the substrate 1 is etched to reduce the thickness of the polysilicon layer 7 in the non-gate line area. Then, the substrate 1 is plated and printed.

[0077] In the solution provided in the embodiment of the present application, by etching the polysilicon layer 7 in the non-gate line area on the back side of the substrate 1, the thickness of the polysilicon layer 7 in the non-gate line area on the back side of the substrate 1 can be reduced, which is beneficial to reduce the parasitic absorption generated by the polysilicon layer 7, so as to increase the utilization of long-wavelength light, so as to improve the efficiency of the photovoltaic cell. The thickness of the polysilicon layer 7 in the gate line area is greater than the thickness of the polysilicon layer 7 in the non-gate line area, so that the gate line area can form a metal-silicide structure low-ohmic contact, and because the thickness of the polysilicon layer 7 in the gate line area and the non-gate line area is different, a step structure can be formed on the back side of the substrate 1. Compared with the planar structure, the step structure can increase the surface area of ​​the substrate 1, and the reflection and reuse of the transmitted light can be used to further improve the efficiency of the photovoltaic cell.

[0078] like Figure 2 As shown, in a possible implementation manner, before performing step S7, the preparation method further includes:

[0079] S70, generating an oxide layer 10 in the non-gate line area.

[0080] By generating an oxide layer 10 in the non-gate line area where the phosphorus silicon glass layer 9 is removed, the speed of etching the polysilicon layer 7 in the non-gate line area can be controlled, and the possibility of damaging the tunnel passivation structure due to excessive etching speed can be reduced. By generating an ultra-thin oxide layer 10 in the non-gate line area on the back of the substrate 1, the reaction: SiO2+2NaOH=Na2SiO3+H2O can be used during the etching process to inhibit the etching speed of the polysilicon layer 7 by the alkaline solution, thereby controlling the etching depth of the polysilicon layer 7, and achieving the purpose of thinning the polysilicon layer 7 in the non-gate line area while reducing the possibility of the passivation structure in the corresponding area being etched and damaged. The etching rate of the polysilicon layer 7 in the non-gate line area on the back side of the substrate 1 is suppressed by the oxide layer 10, so that during the etching process, the etching rate of the polysilicon layer 7 in the non-gate line area on the back side of the substrate 1 can be slower than the etching rate of the polysilicon layer 7 on the front and side surfaces. Therefore, after the polysilicon layer 7 on the front and side surfaces of the substrate 1 are completely etched, a certain thickness of the polysilicon layer 7 can still be retained in the non-gate line area on the back side of the substrate 1, so that the polysilicon layer 7 in the non-gate line area on the back side of the substrate 1 is not completely removed.

[0081] In a possible implementation, step S70 includes:

[0082] S701, generating an oxide layer 10 in the non-gate line area by thermal oxidation using a chain oxygen device, with an oxygen flow rate of 5000 sccm to 12000 sccm, a temperature of 200° C. to 350° C., and a belt speed of 3.5 m / min to 4.5 m / min.

[0083] An oxide layer 10 is generated in the non-gate line area on the back of the substrate 1 by a chain oxygen device to control the etching rate of the polysilicon layer 7. The oxide layer 10 can be used to slow down the corrosion rate of the alkaline solution on the polysilicon layer 7, which is beneficial to prevent the polysilicon layer 7 from being completely consumed while thinning the thickness of the polysilicon layer 7 in the non-gate line area, thereby reducing the possibility of damage to the passivation structure.

[0084] In a possible implementation, step S70 further includes:

[0085] S702 , generating an oxide layer 10 with a thickness of 1 nm to 3 nm in the non-gate line area on the back side of the substrate 1 .

[0086] The thickness of the oxide layer 10 can be 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2.0 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm, 3.0 nm, etc. The etching rate of the polysilicon layer 7 is controlled by generating an ultra-thin oxide layer 10 in the non-gate line area on the back side of the substrate 1. When the thickness of the oxide layer 10 is less than 1 nm, the thickness of the oxide layer 10 is too thin, and the delay effect on etching is small. When etching the polysilicon layer 7 in the non-gate line area on the back side of the substrate 1, it is easy to have an excessively deep etching depth, resulting in the destruction of the passivation structure, which affects the quality of the photovoltaic cell. When the thickness of the oxide layer 10 exceeds 3 nm, the etching delay effect is large due to the excessive thickness of the oxide layer 10. When etching the polysilicon layer 7 in the non-gate line area on the back side of the substrate 1, the etching efficiency is low. The polysilicon layer 7 in the non-gate line area is thicker, which is prone to parasitic absorption, affecting the efficiency of the photovoltaic cell and also affecting the production efficiency of the photovoltaic cell.

[0087] like Figure 3 As shown, in a possible implementation, step S3 includes:

[0088] S31. Remove the phosphosilicate glass layer 9 in the non-gate line area on the back side of the substrate 1 by laser, with a laser power of 50W to 60W, a speed of 40000mm / s to 70000mm / s, a frequency of 500kHz to 800kHz, a wavelength of 500nm to 600nm, and a pulse width of 0.4 to 0.6.

[0089] Removing the phosphosilicate glass layer 9 by laser has higher removal accuracy and higher removal efficiency, which is more in line with actual use requirements. In the process of removing PSG, by using the principle of laser ablation, the purpose of removing only the phosphosilicate glass layer 9 without damaging the tunnel passivation layer can be achieved.

[0090] In a possible implementation, step S3 includes:

[0091] S32. The thickness of the removed phosphosilicate glass layer 9 is 3 nm to 10 nm.

[0092] The thickness of the removed phosphosilicate glass layer 9 can be 3.0nm, 3.5nm, 4.0nm, 4.5nm, 5.0nm, 5.5nm, 6.0nm, 6.5nm, 7.0nm, 7.5nm, 8.0nm, 8.5nm, 9.0nm, 9.5nm, 10.0nm, etc. When the removal depth is less than 3nm, the thickness of the removed phosphosilicate glass layer 9 is small, which easily leads to incomplete removal of the phosphosilicate glass layer 9 in the non-gridline area. When the polysilicon layer 7 in the non-gridline area is etched, the phosphosilicate glass layer 9 easily affects the etching rate, resulting in etching failure, and the polysilicon layer 7 in the non-gridline area cannot be thinned or the thinning rate is slow. When the removal depth is greater than 10nm, the removal depth is too large, and it is easy to destroy the tunnel passivation structure and affect the quality of the photovoltaic cell. The purpose of step S32 is to completely remove the phosphosilicate glass layer 9 in the non-gridline area on the back of the substrate 1, and the specific removal depth can be determined according to the actual thickness of the phosphosilicate glass layer 9 in the non-gridline area.

[0093] In a possible implementation, step S7 includes:

[0094] S71, etching the polysilicon layer 7 to reduce the thickness by 90 nm to 120 nm. After etching, the thickness of the polysilicon layer 7 is 30 nm to 60 nm.

[0095] After etching, the thickness of the polysilicon layer 7 can be 30nm, 33nm, 36nm, 39nm, 42nm, 45nm, 48nm, 51nm, 54nm, 57nm, 60nm, etc. The polysilicon layer 7 in the non-gate line area on the back of the substrate 1 is thinned by etching, which reduces parasitic absorption while protecting the passivation structure, and is beneficial to improving the efficiency of the photovoltaic cell.

[0096] In a possible implementation, step S7 includes:

[0097] S72, placing the substrate 1 into a functional tank containing an alkaline solution with a volume concentration of 4% to 8% KOH and 4L to 6L additives, with a reaction time of 260s to 310s and a reaction temperature of 55°C to 70°C, and cleaning the substrate 1 through the RCA process.

[0098] The volume concentration of KOH can be 4.0%, 4.5%, 5.0%, 5.5%, 6.0%, 6.5%, 7.0%, 7.5%, 8.0%, etc., and the alkaline solution can be 4.0L, 4.5L, 5.0L, 5.5L, 6.0L, etc. The reaction time can be 260, 265, 270, 275, 280, 285, 290, 295, 300, 305, 310s, etc. The reaction temperature is 55°C, 57°C, 59°C, 61°C, 63°C, 65°C, 67°C, 69°C, 70°C, etc. RCA cleaning has high cleaning efficiency, high degree of automation, good cleaning effect, more precise control of the cleaning process during use, which is conducive to ensuring the stability and consistency of the cleaning process and more in line with actual use requirements.

[0099] In a possible implementation, step S72 includes:

[0100] S721 , removing the polysilicon layer 7 on the front surface and surrounding of the substrate 1 .

[0101] The polysilicon layer 7 located on the front and surrounding of the substrate 1 can be removed by RCA cleaning. By removing the polysilicon layer 7 on the front and side surfaces of the substrate 1, parasitic absorption of light can be reduced, which is beneficial to improving the efficiency of the photovoltaic cell.

[0102] In a possible implementation, before step S721, step S72 further includes:

[0103] S720, clear the front surface of the substrate 1 and the phosphosilicate glass layer 9 around it.

[0104] The presence of phosphosilicate glass makes the surface of substrate 1 susceptible to moisture in the air, resulting in reduced current and power attenuation. The presence of the dead layer greatly increases the recombination of electrons in the emission region, which will lead to a reduction in the minority carrier lifetime, thereby reducing the open circuit voltage and short-circuit current. Therefore, in the solution provided in the embodiment of the present application, the overall quality of the photovoltaic cell is improved by removing the phosphosilicate glass layer 9 of the substrate 1, which is more in line with actual usage requirements.

[0105] In a possible implementation, step S721 includes:

[0106] S722, using chain HF to remove the phosphosilicate glass layer 9 on the front and surrounding of the substrate 1.

[0107] The phosphosilicate glass layer 9 of the substrate 1 is removed by chain HF, so that the polysilicon layer 7 on the front and surrounding of the substrate 1 can be removed during RCA cleaning, thereby reducing the influence of the phosphosilicate glass layer 9 on RCA cleaning.

[0108] like Figure 4 As shown, in a possible implementation, step S8 includes:

[0109] S81. Deposit aluminum oxide on the front side of the substrate 1 by atomic layer deposition.

[0110] Aluminum oxide is deposited on the front of the substrate 1 by atomic layer deposition (ALD) to form an aluminum oxide layer 4, which is used to avoid direct contact between the metal electrode 8 and the silicon substrate and to prevent leakage between the doped film layers. The deposited aluminum oxide layer 4 can also be used to increase the coverage area of ​​the doped film layer. ALD deposition can better control the thickness of the deposited layer, with better uniformity, which is more in line with actual usage requirements.

[0111] like Figure 4 As shown, in a possible implementation manner, step S8 further includes:

[0112] S82, coating a SiN film on the substrate 1 and performing screen printing.

[0113] Silicon nitride has high thermal conductivity, high strength and hardness. By depositing a silicon nitride layer 5 on the substrate 1, it can help reduce the operating temperature of the photovoltaic cell, thereby improving the conversion efficiency of the photovoltaic cell and the photovoltaic module. The silicon nitride layer 5 can also play a protective role, reducing the possibility of damage to the photovoltaic cell during use, which is conducive to extending the service life of the photovoltaic cell. The grid line is printed on the surface of the substrate 1 by screen printing. The grid line may include a main grid and a fine grid, wherein the fine grid is used to collect current, and the main grid is used to gather current and provide sufficient pulling force.

[0114] The substrate 1 is sintered in a high-temperature sintering furnace so that the gate line and the substrate 1 can form a good ohmic contact.

[0115] The embodiments of the present application also provide a photovoltaic cell, which can be prepared by the preparation method involved in any of the above embodiments.

[0116] like Figure 5 As shown (the velvet structure is not shown), the photovoltaic cell may include a substrate 1, a polysilicon layer 7 is provided on the back side of the substrate 1, the back side of the substrate 1 includes a gate line area and a non-gate line area, the thickness of the polysilicon layer 7 in the gate line area is a, the thickness of the polysilicon layer 7 in the non-gate line area is b, and a>b.

[0117] By reducing the thickness of the polysilicon layer 7 in the non-gate line area, the parasitic absorption of the photovoltaic cell can be reduced, and the thickness of the polysilicon layer 7 in the gate line area can remain unchanged to provide good contact for metallization. Since the thickness of the polysilicon layer 7 in the gate line area and the non-gate line area is different, a step structure with a height difference can be formed on the substrate 1, which is conducive to the reflection and reuse of the transmitted light, thereby improving the efficiency of the photovoltaic cell.

[0118] In a possible implementation manner, the thickness of the polysilicon layer 7 in the gate line region and the thickness of the polysilicon layer 7 in the non-gate line region satisfy: 90 mm≤ab≤120 mm.

[0119] When the thickness difference between the polysilicon layer 7 in the gate area and the non-gate area is too small, that is, the thickness in the non-gate area is larger, parasitic absorption is likely to occur, affecting the efficiency of the photovoltaic cell. When the thickness difference between the polysilicon layer 7 in the gate area and the non-gate area is too large, the etching depth of the polysilicon layer 7 in the non-gate area is too large, which is likely to cause the polysilicon layer 7 to be too thin or completely removed, thereby causing the passivation structure to be destroyed, affecting the normal use of the photovoltaic cell.

[0120] The photovoltaic cell provided in the embodiment of the present application is prepared by first depositing SiO2 / amorphous silicon structure on the front of the cell by low pressure chemical vapor deposition (LPCVD), and then forming SiO2 / Poly-Si (n+) structure by phosphorus diffusion at high temperature. The phosphorus silicon glass layer 9 in the non-grid area is removed by laser, and an ultra-thin oxide layer 10 is grown by chain oxygen equipment, wherein the ultra-thin oxide layer 10 in the non-grid area suppresses the etching speed of the alkaline solution for poly during the RCA cleaning process to control the etching depth of poly, so as to achieve the purpose of thinning the poly thickness without destroying the passivation structure of the corresponding area. The phosphorus silicon glass layer 9 in the grid area is removed by a post-cleaning tank, and then a subsequent coating-printing process is performed to form a photovoltaic cell structure with different poly thicknesses. Thinning the poly in the non-grid area can reduce the parasitic absorption on the back of the photovoltaic cell. The gate line area can form a metal-silicide structure low-ohmic contact. Since the thickness of the polysilicon layer 7 in the gate line area and the non-gate line area is different, there is a height difference between the gate line area and the non-gate line area. The thickness difference between the gate line area and the non-gate line area is used to reflect light, which can improve the light utilization rate and the efficiency of the photovoltaic cell.

[0121] like Figure 5 As shown, Figure 5 Schematic diagram of the structure of the photovoltaic cell provided in the embodiment of the present application. The photovoltaic cell includes a substrate 1, and a boron-doped layer 2, an aluminum oxide layer 4, and a silicon nitride layer 5 are sequentially arranged on the front side of the substrate 1 in a direction away from the substrate 1. A tunneling oxide layer 6, a polysilicon layer 7, and a silicon nitride layer 5 are sequentially arranged on the back side of the substrate 1 in a direction away from the substrate 1. Electrodes 8 are arranged on the front and back sides of the photovoltaic cell.

[0122] As shown in Table 1, the comparative group in Table 1 is a scheme in which the polysilicon layer 7 is not etched, that is, the thickness of the polysilicon layer 7 in the gate line area and the non-gate line area of ​​the photovoltaic cell is the same. The embodiment is a scheme in which the polysilicon layer 7 is etched, that is, the thickness of the polysilicon layer 7 in the gate line area and the non-gate line area of ​​the photovoltaic cell is different.

[0123] Table 1

[0124] ETA UOC ISC FF Rs R IRev2 Comparison group 26.19 0.7385 13.884 85.61 0.0006 3411 0.042 Example 26.35 0.7394 13.935 85.58 0.0007 3485 0.061

[0125] Among them, ETA is efficiency, UOC is open circuit voltage, I SC is short circuit current, FF is fill factor, Rs is series resistance, Rsh is parallel resistance, and I Rev2 is reverse leakage. It can be seen from the data in the table that by processing the polysilicon layer 7 and thinning the thickness of the polysilicon layer 7 in the non-gate line area, the performance of the back contact photovoltaic cell can be improved, which is more in line with actual use requirements.

[0126] like Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of the substrate 1 after texturing provided in the embodiment of the present application. Texturing the substrate 1 can help reduce the reflection of sunlight on the surface of the photovoltaic cell, thereby helping to increase the absorption rate of sunlight on the surface of the substrate 1, and further improve the photoelectric conversion efficiency of the photovoltaic cell. After texturing, a PN junction is made on the substrate 1, and the obtained structure is as follows Figure 7 As shown, Figure 7 The schematic diagram of the structure of the substrate 1 after the PN junction is made according to the embodiment of the present application. Since a boron-doped layer 2 and a borosilicate glass layer 20 are generated on each surface of the substrate 1 when the PN junction is made, usually, after the PN junction is made, the borosilicate glass layer 20 on the back and sides of the substrate 1 is removed, and the PN junction on the back and sides of the substrate 1 is etched to obtain Figure 8 The structure shown, Figure 8 This is a schematic diagram of the structure after removing the borosilicate glass layer 20 and the PN junction on the back and around the substrate 1 provided in the embodiment of the present application. After removing the borosilicate glass layer 20 and the PN junction on the back and around the substrate 1, a tunneling oxide layer 6 and an amorphous silicon layer 3 are formed on the substrate 1 to obtain the following Fig. 9 The structure shown, Fig. 9 The schematic diagram of the structure after the tunnel oxide layer 6 and the amorphous silicon layer 3 are made on the substrate 1 provided in the embodiment of the present application. Phosphorus is diffused on the substrate 1 to obtain the following Fig.10 The structure shown, Fig.10 Schematic diagram of the structure of the substrate 1 after phosphorus diffusion provided in the embodiment of the present application. After phosphorus diffusion, the amorphous silicon layer 3 is converted into a polycrystalline silicon layer 7, and a phosphorus silicon glass layer 9 is generated on the surface of the polycrystalline silicon layer 7. The phosphorus silicon glass layer 9 in the non-gate line area on the back of the substrate 1 is removed by laser to obtain the following Fig.11 The structure shown, Fig.11 The schematic diagram of the structure of removing the phosphorus-silicate glass layer 9 in the non-gate line area on the back of the substrate 1 provided in the embodiment of the present application. After removing the phosphorus-silicate glass layer 9 in the non-gate line area, an oxide layer 10 is grown in the non-gate line area using a chain oxygen device to obtain the following Fig.12 The structure shown, Fig.12 The schematic diagram of the structure of the oxide layer 10 formed in the non-gate line area of ​​the substrate 1 provided in the embodiment of the present application. The phosphorus silicon glass layer 9 on the front and surrounding of the substrate 1 is removed by chain HF to obtain the following Fig.13 The structure shown, Fig.13 The schematic diagram of the structure of the substrate 1 provided in the embodiment of the present application after the phosphosilicate glass layer 9 on the front and surrounding areas is removed. The phosphosilicate glass layer 9 on the front and surrounding areas of the substrate 1 is first removed by pickling, and then the polysilicon layer 7 on the front and side surfaces of the substrate 1 is removed by alkaline etching in the alkaline washing step in RCA cleaning. At the same time, the polysilicon layer 7 in the non-gate line area on the back side of the substrate 1 is etched by the RCA cleaning step to reduce the thickness of the polysilicon layer 7 in the non-gate line area, and the borosilicate glass layer 20 on the front side of the substrate 1 and the phosphosilicate glass layer 9 in the gate line area on the back side of the substrate 1 are removed by RCA cleaning. Since the non-gate line area on the back side of the substrate 1 is provided with an oxide layer 10, the surface film layer of the polysilicon layer 7 in the gate line area on the back side of the substrate 1 is different from the surface film layer of the polysilicon layer 7 in other positions. Therefore, when RCA cleaning is performed, the cleaning rate is different. The oxide layer 10 in the non-gate line area can be used to slow down the reaction rate. Therefore, when the polysilicon layer 7 on the front side and the surroundings of the substrate 1 is completely removed, the polysilicon layer 7 in the non-gate line area still retains a certain thickness. Since the polysilicon layer 7 in the non-gate line area on the back side of the substrate 1 is thinned, the polysilicon layer 7 in the gate line area and the polysilicon layer 7 in the non-gate line area form a thickness difference, and the obtained structure is as follows: Fig.14 As shown, Fig.14 Schematic diagram of the structure of the substrate 1 after RCA cleaning provided in the embodiment of the present application. After the substrate 1 is cleaned by RCA, aluminum oxide is deposited on the front side of the substrate 1 by ALD to generate an aluminum oxide layer 4. The obtained structure is as follows Fig.15 As shown, Fig.15 Schematic diagram of the structure after aluminum oxide is deposited on the substrate 1 provided in the embodiment of the present application. SiN film is plated on the front and back of the substrate 1 and metallized by screen printing, and the obtained structure is as follows Fig.16 As shown, Fig.16 This is a schematic diagram of the structure of the substrate 1 provided in an embodiment of the present application after coating and printing.

[0127] The embodiment of the present application provides a method for preparing a photovoltaic cell and a photovoltaic cell, the preparation method comprising: texturing a substrate 1; making a PN junction on the substrate 1 after texturing; removing the borosilicate glass layer on the back and around the substrate 1, etching the PN junction on the back and around the substrate 1; generating a tunneling oxide layer 6 and an amorphous silicon layer 3 on the substrate 1; performing phosphorus diffusion on the substrate 1 to generate a polycrystalline silicon layer 7; removing the phosphorus silicon glass layer 9 in the non-gate line area on the back of the substrate 1; etching the polycrystalline silicon layer 7 in the non-gate line area on the back of the substrate 1; coating and printing the substrate 1. In this way, the occurrence of parasitic absorption can be reduced by thinning the thickness of the polycrystalline silicon layer 7 in the non-gate line area, thereby improving the efficiency of the photovoltaic cell. In addition, a step structure can be formed between the polycrystalline silicon layer 7 in the gate line area and the polycrystalline silicon layer 7 in the non-gate line area through a height difference, which is beneficial to improving the utilization rate of light and further improving the efficiency of the photovoltaic cell.

[0128] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a photovoltaic cell, characterized in that: The preparation method comprises: Velveting the substrate; Making a PN junction on the substrate after texturing; Removing the borosilicate glass layer on the back and surrounding of the substrate, and etching the PN junction on the back and surrounding of the substrate; Generating a tunneling oxide layer and an amorphous silicon layer on the substrate; Diffusion of phosphorus on the substrate to form a polysilicon layer; removing the phosphosilicate glass layer located in the non-gate line area on the back side of the substrate; Etching the polysilicon layer in the non-gate line area on the back side of the substrate; The substrate is plated and printed.

2. The method for preparing a photovoltaic cell according to claim 1, characterized in that: Before the step of etching the polysilicon layer in the non-gate line area on the back side of the substrate, the preparation method comprises: An oxide layer with a thickness of 1 nm to 3 nm is generated in the non-gate line area.

3. The method for preparing a photovoltaic cell according to claim 2, characterized in that: The step of generating an oxide layer in the non-gate line area comprises: An oxide layer is generated in the non-gate line area by thermal oxidation using a chain oxygen device, with an oxygen flow rate of 5000 sccm to 12000 sccm, a temperature of 200° C. to 350° C., and a belt speed of 3.5 m / min to 4.5 m / min.

4. The method for preparing a photovoltaic cell according to claim 1, characterized in that: The step of removing the phosphosilicate glass layer in the non-gate line area on the back side of the substrate comprises: The thickness of the phosphosilicate glass layer is reduced by 3nm to 10nm by laser, the laser power is 50W to 60W, the speed is 40000mm / s to 70000mm / s, the frequency is 500kHz to 800kHz, the wavelength is 500nm to 600nm, and the pulse width is 0.4 to 0.

6.

5. The method for preparing a photovoltaic cell according to claim 1, characterized in that: The step of etching the polysilicon layer in the non-gate line area on the back side of the substrate comprises: The polysilicon layer is etched to reduce the thickness by 90 nm to 120 nm. After etching, the thickness of the polysilicon layer is 30 nm to 60 nm.

6. The method for preparing a photovoltaic cell according to claim 1, characterized in that: The step of etching the polysilicon layer in the non-gate line area on the back side of the substrate comprises: The substrate is placed in a functional tank containing an alkaline solution with a volume concentration of 4% to 8% KOH and 4L to 6L additives, the reaction time is 260s to 310s, the reaction temperature is 55°C to 70°C, and the substrate is cleaned by an industrial standard wet cleaning process.

7. The method for preparing a photovoltaic cell according to claim 6, characterized in that: The steps of cleaning the substrate by an industry standard wet cleaning process include: The polysilicon layer on the front side and the surrounding area of ​​the substrate is removed.

8. The method for preparing a photovoltaic cell according to claim 7, characterized in that: Before removing the polysilicon layer on the front side and around the substrate, the step of cleaning the substrate by an industrial standard wet cleaning process includes: The front side of the substrate and the surrounding phosphosilicate glass layer were removed by chain HF.

9. The method for preparing a photovoltaic cell according to any one of claims 1 to 8, characterized in that: The steps of coating and printing the substrate include: depositing aluminum oxide on the front side of the substrate by atomic layer deposition; A SiN film is plated on the substrate and screen printed.

10. A photovoltaic cell, characterized in that: The photovoltaic cell is prepared by the method for preparing a photovoltaic cell according to any one of claims 1 to 9; The photovoltaic cell includes a substrate, a polysilicon layer is arranged on the back side of the substrate, the back side of the substrate includes a gate line area and a non-gate line area, the thickness of the polysilicon layer in the gate line area is a, the thickness of the polysilicon layer in the non-gate line area is b, and 90mm≤ab≤120㎜.

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