Small footprint power switch

Abstract

A power switch comprising: a pair of substantially parallel half-bridges; a printed circuit board (PCB) controller operable to switch the half-bridges on and off; power terminals for coupling a high-energy power source to the half-bridges; and power phase output terminals for connecting a load to the half-bridges; wherein the half-bridges, the PCBs, the power terminals, and the power phase output terminals are encapsulated in the same encapsulation housing having a first surface with a relatively large planar surface, with contact surfaces of the terminals exposed on the first surface.

Description

[0001] Related applications

[0002] This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 63 / 358,886, filed on July 7, 2022, the disclosure of which is incorporated herein by reference.

[0003] field

[0004] Embodiments of the present invention relate to a power switch.

[0005] background

[0006] Almost all types of modern optical and electronic equipment, from computers to powertrains, include power switching circuits for generating timing pulses, data packets, and / or delivering electrical power. In order to deliver power to an electric powertrain, such as a powertrain for delivering power to an electric vehicle, power switches are required that can carry large amounts of current and switch on and off quickly to couple and decouple a high voltage power source to a load. For example, a high power inverter operated to deliver AC power from a DC power source to an automotive traction motor may include a half-bridge having a high-side array of GaN dies connected to a low-side array of GaN dies, and a PCB control circuit for controlling the array to invert the DC power to AC power. Advantageously, the inverter has low inductance, a small footprint, efficient heat dissipation, and is easy to install and scale to meet the electrical and mechanical constraints of different electric vehicle configurations.

[0007] Overview

[0008] One aspect of an embodiment of the present disclosure relates to providing a power switch, also referred to as a Power-Mite, characterized by low inductance and a small footprint, which is easily scalable and can be easily coupled to external circuits and mounted to a heat sink by soldering or sintering. In one embodiment, the Power-Mite includes a pair of half-bridges and a printed circuit board (PCB) controller that is operable to turn the half-bridges on and off to provide voltage and current pulses to a load connected to the Power-Mite. Each half-bridge optionally includes a high-side GaN die connected to a low-side GaN die. In order to provide a Power-Mite with relatively low inductance, the half-bridges are configured such that when the half-bridges are turned on to provide voltage and current pulses to the load, the current flows in substantially the same parallel direction. During transitions between the on and off states, the total power loop inductance of the Power-Mite can be less than about 2.5 nanohenries (nH).

[0009] In one embodiment, the Power-Mite half-bridge, PCB controller and other electrical and mechanical components are encapsulated in a protective polymer package, optionally referred to as an envelope. The envelope has a substantially continuous uniform geometric outer shape, including relatively large parallel plane face surfaces of the same shape and at least one relatively narrow edge surface. For example, the envelope can be substantially a rectangular parallelepiped, a rectangular parallelepiped with rounded parallelogram face surfaces, or a solid figure with square or round face surfaces. In one embodiment, terminals that provide electrical contact to one or more components within the envelope are embedded in the envelope, and these terminals have electrical contact surfaces located on the surface of the envelope for making electrical contact with the terminals. In an embodiment, the terminal contact surface is substantially coplanar with the surface on which it is located. Optionally, the contact surface is recessed or raised relative to the surface on which it is located. In an embodiment, the contact surface is located on the face surface of the envelope. Optionally, the contact surfaces of all terminals are located on the same face surface.

[0010] The Power-Mite may include terminal pins extending from an edge surface of the housing for making electronic contact with one or more components inside the housing. In an embodiment, the terminal pins include terminal pins positioned diagonally opposite each other on opposite edge surfaces of the housing.

[0011] This Summary is provided to introduce some selected concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Non-limiting examples of embodiments of the present invention are described below with reference to the accompanying drawings listed following this paragraph. Identical structures, elements, or parts that appear in more than one figure are generally labeled with the same numerals in all the figures in which they appear. The dimensions of components and features shown in the figures are selected for convenience and clarity of presentation and are not necessarily shown to scale.

[0014] Figure 1A and Figure 1B schematically illustrates top and bottom perspective views of a Power-Mite power switch according to an embodiment of the present disclosure;

[0015] Figure 1C Schematically illustrates a variation of the Power-Mite according to an embodiment of the present disclosure;

[0016] Figures 2A to 2G schematically illustrates features of the construction and assembly of a Power-Mite according to an embodiment of the present disclosure; and

[0017] Figures 3A to 3C The footprints of components of a prior art power switch and components of a Power-Mite according to an embodiment of the present disclosure are schematically compared.

[0018] Detailed description

[0019] When discussing, unless otherwise stated, adjectives such as "substantially" and "approximately" that modify the condition or relationship characteristics of one or more features of the embodiments of the present disclosure should be understood to mean that the condition or feature is defined within an acceptable tolerance for the operation of the embodiment in its intended application. Wherever a general term in the present disclosure is described by reference to an example or a list of example examples, the one or more examples mentioned are non-limiting example examples of the general term, and the general term is not intended to be limited to the one or more specific example examples mentioned. The phrase "in an embodiment," whether or not associated with a loose form such as "may," "optionally," or "by way of example," is used to introduce configurations of possible embodiments of the present disclosure for consideration as examples but not necessarily requirements. Each of the verbs "comprise," "include," and "have" and their variations is used to indicate that one or more objects of the verb are not necessarily a complete list of the parts, elements, or parts of the one or more subjects of the verb. Unless otherwise stated, the word "or" in the specification and claims is to be considered an inclusive "or," not an exclusive "or," and means any combination of at least one or more of the items it combines.

[0020] Figure 1A and Figure 1B The top and bottom perspective views of a Power-Mite 20, which is optionally configured to provide power to a phase of an electric vehicle traction motor, are schematically shown, respectively, according to an embodiment of the present disclosure. The Power-Mite 20 includes an optional rectangular parallelepiped housing 22 having a Figure 1A The top surface 23 shown in Figure 1B The housing 22 may be formed by cutting a plurality of Power-Mites 20 from a common multi-unit encapsulation mold, wherein the Power-Mites are encapsulated in a suitable polymer.

[0021] The terminals (discussed below) provide contact to the components of the Power-Mite 20. Figure 1A and Figure 1BThe motor (not shown) is enclosed in the housing 22 and has contact surfaces 30-1, 30-2, 30-3 and 30-4 exposed on the top surface 23, and may be collectively referred to as contact surfaces 30. The contact surfaces 30-1 and 30-2 are the surfaces of power terminals 41 and 42, respectively, discussed below, which may be used to couple power from a high energy power source (not shown) to the half-bridge enclosed in the housing 22. The contact surface 30-3 is the surface of the power phase output terminal 43, discussed below, which may be used to couple voltage and current to the phases of the motor. The contact surface 30-4 is the surface of the control terminal 44, discussed below, which may be used to couple the control circuit to a PCB controller enclosed in the housing 22, discussed below.

[0022] Alternatively, as Figure 1A The contact surface 30 schematically shown in Figure 1 is coplanar with the top surface 23 and is generally flush. In embodiments, the contact surface 30 can be raised or recessed to electrically isolate the contact surface and / or facilitate electrical contact with the contact surface. The contact surface 30 is formed of a material that is compatible with electrically and mechanically coupling a conductor to a surface, which material is intended to provide electrical contact between an external circuit and the surface and the corresponding terminals that these surfaces are characterized by. In embodiments, the surface 30 is configured such that the conductor can be electrically and mechanically coupled to the contact surface 30 by soldering, laser welding, or ultrasonic welding. Optionally, the surface 30 and its associated underlying terminal are configured such that the conductor can be screwed into or press-fit into a hole formed in the terminal. Figure 1B The bottom surface 24 is shown optionally having formed thereon a thermally conductive interface 26. For example, the thermal interface may be formed from any of a variety of suitable highly thermally conductive materials, such as thermally conductive solder or adhesive, sintering or curing silver paste.

[0023] In an embodiment, the Power-Mite 20 may include terminal pins in addition to or in lieu of the contact surface 30 . Figure 1C A Power-Mite 21 is schematically shown according to an embodiment of the present disclosure, which is similar to the Power-Mite 20, but includes a set 46 of terminal pins 47 and a set 48 of terminal pins 49 instead of terminals having contact surfaces 30 on the top surface 23. In an embodiment, the set 46 of terminal pins 47 and the set 48 of terminal pins 49 are positioned diagonally opposite each other on opposite edge surfaces 25 of the housing 22. As described below with respect to Figure 3A and Figure 3B As discussed, the positioning of terminal pins 46 and 48 diagonally opposite one another facilitates close stacking of multiple Power-Mites 20, as well as conveniently connecting Power-Mites in parallel to provide high current switching.

[0024] It is worth noting that Figure 1C The housing 22 in FIG. 1 shows a parting line 27 along which the terminal pins are arranged. Although it is advantageous to package multiple Power-Mite 20 terminals, such as terminals 41-44 having contact surfaces 30, in a common multi-unit packaging mold and then cut the Power-Mite 20 circuits to release the individual Power-Mite 20 circuits, it is also advantageous to individually package the Power-Mites having terminal pins such as terminal pins 47 and 49 in a single unit mold. Although the process of multi-unit packaging and then cutting results in a housing 22 without a parting line, the individual, single unit packaging typically requires a two-piece release mold, which typically results in Figure 1C The housing 22 is shown in FIG. 2 with a parting line 27 .

[0025] Figure 2A-2G Stages in the construction and assembly of a Power-Mite 20 according to an embodiment of the present disclosure are schematically illustrated.

[0026] Figure 2A The first stage of construction of the Power-Mite 20 is schematically shown, wherein a pattern of conductive traces, generally referred to as traces 50, to which the components of the Power-Mite will be electrically connected are formed on the upper surface 41 of an optional DBC (direct bond copper) substrate 40. In an embodiment, the traces 50 include a positive power terminal trace 51, a negative power terminal trace 52, a power output phase trace 53, a control trace 54, and die contact traces 55, 56, 57, and 58. Connecting pins 60 are mounted on the traces 50, which can be used to electrically connect the circuit components of the Power-Mite to the PCB controller 100 (enclosed in the Power-Mite 20). Figure 2A In an embodiment, a conductive spacer 62 is electrically connected to the power trace 51 to facilitate connecting the power trace to the metallized electrode of the Power-Mite component. Figure 2C As schematically shown in FIG. 5 and discussed below, spacers 62 facilitate the use of planar interconnects to make electrical connections to metallized electrodes of the Power-Mite component that are elevated above the top surface of traces 50 due to the thickness of the component.

[0027] Figure 2BSchematically illustrated are semiconductor dies that are directly connected to corresponding ones of the traces 50 to form two half-bridges 70 and 80 of the Power-Mite 20. In an embodiment, half-bridge 70 includes a high-side (optionally normally-on lateral n-channel) GaN (gallium nitride) die 72, a high-side (optionally p-channel) MOSFET (metal-on-silicon field-effect transistor) die 74, a low-side (optionally normally-on lateral n-channel) GaN die 76, and a low-side (optionally p-channel) MOSFET die 78. Similarly, half-bridge 80 may include a high-side (optionally normally-on lateral n-channel) GaN die 82, a high-side (optionally p-channel) MOSFET die 84, and a low-side (optionally normally-on lateral n-channel) GaN die 86, and a low-side (optionally p-channel) MOSFET die 88.

[0028] Each normally-on GaN die 72, 76, 82, and 86 optionally includes an array (not shown) of multiple rows of optionally normally-on lateral GaN transistors (not shown) connected to a fishbone configuration 90 of metallization layers, including a drain fishbone metallization layer 92-D having ridges 93 that intersect with spines 94 of a source fishbone metallization layer 95-S. The drain (not shown) of the normally-on GaN transistor electrically contacts the ridges 92-D of the drain fishbone 93, and the source of the transistor electrically contacts the ridges 94 of the source fishbone 95-S. The gates of the GaN transistors are optionally electrically connected to a control trace 54 designated "54g" by wire bonds. The gates of the MOSFET transistors are optionally electrically connected to a control trace 54 designated "54g*" by wire bonds. The substrates (not shown) of GaN dies 72 , 76 , 82 , and 86 are electrically connected to the respective die traces 55 , 57 , 56 , and 58 to which the dies are mounted.

[0029] Each MOSFET die 74, 84, 78, and 88 includes an array of MOSFET transistors (not shown), each having its source electrically connected to source metallization layers 74-S, 84-S, 78-S, and 88-S, respectively, and its drain electrically connected to drain metallization layers (not shown). The drain metallization layers of the high-side MOSFET dies 74 and 84 are electrically connected to the power output phase output trace 53. Each drain metallization layer of the low-side MOSFET dies 78 and 88 is electrically connected to the negative power trace 52.

[0030] exist Figure 2C middle, Figure 2B The GaN die and MOSFET die shown in FIG are connected by relatively large area planar interconnect conductors. The drain fishbone metallization layer 92-D ( Figure 2B) is electrically connected to the conductive spacer 62 located on the positive power trace 51 through an optional planar conductive interconnect 73 ( Figure 2B ). Source metallization 95-S of high-side GaN die 72 ( Figure 2B ) is electrically connected to the source metallization 74-S of the high-side MOSFET 70 through an optional planar conductive interconnect 75. Similarly, the drain metallization 92-D ( Figure 2B ) is electrically connected to the conductive spacer 62 positioned and connected to the positive power trace 51 through an optional planar conductive interconnect 83. The source metallization 95-S ( Figure 2B ) is electrically connected to the source metallization 84-S of the high-side MOSFET 84 through an optional planar conductive interconnect 85. The source metallization layer 95-S of the low-side GaN die 76 is electrically connected to the source metallization layer 78-S of the MOSFET 78 through an optional planar interconnect 77, and the source metallization layer 95-S of the low-side GaN die 86 is electrically connected to the source metallization layer 88-S of the MOSFET die 88 through an optional planar interconnect 87. The drain metallization layer 92-D of the low-side GaN dies 76 and 86 is connected together through optional planar conductive interconnects 76-86. The interconnects 76-86 are electrically in contact with the conductive spacers 62 on the power output phase trace 53, thereby electrically contacting the power output phase trace.

[0031] Figure 2D The schematic diagram shows the direction of current flow in half-bridge 70 and half-bridge 80 when the Power-Mite 20 is turned on and the power trace 53 is energized to deliver voltage and current from a power source connected to the positive power terminal trace 51 and the negative power terminal trace 52 to (optionally) a traction motor connected to the Power-Mite 20. In the figure, the arrowed ribbon labeled I-70 schematically represents the current through half-bridge 70. The solid portion of the ribbon represents the current flow of I-70 on interconnects 73, 75 and conductive trace 53. The dashed area of ​​ribbon I-70 represents the "hidden" portion of I-70, which flows "downward" from interconnect 75 through MOSFET 74 ( Figure 2B ) to flow on a portion of conductive trace 53 below interconnects 75 and 85. Similarly, the arrowed ribbon labeled I-80 schematically represents the current through half-bridge 80. The solid portion of the ribbon represents the current of I-80 on interconnects 83, 85, and conductive trace 53. The dashed area of ​​ribbon I-80 represents the "hidden" portion of I-80 that flows "down" from interconnect 85 through MOSFET 84 ( Figure 2B) to flow on conductive trace 53 beneath interconnects 75 and 85. Note that currents I-70 and I-80 flow in parallel with each other in trace 53 and help reduce the inductance of Power-Mite 20 during turn-on and turn-off.

[0032] Figure 2E The schematic diagram shows the direction of current flow in half-bridge 70 and half-bridge 80 when the Power-Mite 20 is turned off by turning off the high-side GaN transistors 72 and 82 and the MOSFETs 74 and 84, and the low-side GaN transistors 76 and 86 and the low-side MOSFETs 78 and 88 are turned on. The current from the negative power terminal trace 52 flows in the current branches represented by the bands I-77 and I-87, through the MOSFETs 78 and 88 to the conductive interconnects 76-86, and combines with the current represented by the current band I-53 to flow along the output phase trace 53 to the Power-Mite 20. The dashed portion of the band represents the current hidden in the Figure 2E The perspective view of the parts of the current.

[0033] In an embodiment, the total power loop inductance of the Power-Mite 20 during transitions between the on and off states may be less than approximately 2.50 nH. Alternatively, the total power loop inductance may be less than approximately 2.25 nH.

[0034] Figure 2F Schematically shows the contact surfaces 30-1 and 30-2 ( Figure 1A ) are mounted to the positive power terminal trace 51 and the negative power terminal trace 52 ( Figure 2A ), having a contact surface 30-3 ( Figure 1A ) of the power phase output terminal 43 is mounted to the power output phase trace 53 ( Figure 2A ), and the optional multi-layer control PCB 100 are mounted to the Power-Mite 20 after the Power-Mite 20. The PCB 100 is connected to the Power-Mite 20 by connecting the pins 60 ( Figure 2A-2E ) contacts the components in the Power-Mite 20 and through an optional cylindrical control terminal 44 ( Figure 1A ) contacts the circuitry external to the Power-Mite 20. In an embodiment, as Figure 2F The Power-Mite 20 schematically shown in FIG. 1 is packaged to provide Figure 1A The Power-Mite 20 in finished form is shown in FIG.

[0035] Figure 2G A Power-Mite variant, Power-Mite 21, is schematically shown, wherein Figure 2FThe cylindrical control terminals 44 shown in FIG are replaced by a set 46 of diagonally opposite terminal pins 47 and a set 48 of terminal pins 49, respectively, and after packaging have Figure 1C The configuration shown in .

[0036] According to the Power-Mite of the embodiment of the present disclosure, for example Figures 1A-2G The designed Power-Mites 20 and 21, schematically shown in FIG, have an exceptionally aesthetic configuration and a relatively small footprint. The small footprint and recessed or diagonally opposed electrical terminals enable Power-Mites according to embodiments of the present disclosure to be easily mounted, optionally by soldering or sintering to a heat sink, and connected in parallel to form a compact, dense "power-pack" array.

[0037] For example, Figure 3A and Figure 3B Schematically illustrates the dimensions of the footprint of power pack arrays 201 and 202 of six Power-Mites 20 and 21, respectively. According to an embodiment of the present disclosure. For comparison, Figure 3C The footprint of power pack 220 is shown according to an embodiment in which the terminal pin arrays are mounted directly opposite each other, rather than diagonally opposite each other as in Power-Mite 21. The footprint of power pack arrays 201 and 202 is significantly smaller than the footprint of power pack array 220.

[0038] The description of the embodiments of the present invention in this application is provided by way of example and is not intended to limit the scope of the invention. The described embodiments include different features, not all of which are required in all embodiments of the invention. Some embodiments utilize only some features or possible combinations of features. Those skilled in the art will appreciate variations of the described embodiments of the invention and embodiments of the invention that include different combinations of the features mentioned in the described embodiments. The scope of the invention is limited only by the claims.

Claims

1. A power switch, comprising: a pair of substantially parallel half-bridges; power terminals for coupling a power source to the half-bridge; power phase output terminals for connecting a load to the half-bridge; a printed circuit board (PCB) controller having a control circuit operable to switch the half-bridge on and off to connect and disconnect the load from the power supply, respectively; a control terminal for connecting the control circuit on the PCB to a circuit outside the power switch; wherein the half bridge, the PCB, the control terminals, the power terminals and the power phase output terminals are packaged in a same packaging housing having a planar first surface and at least one edge surface; The electrical contact surfaces of all the terminals are exposed on the first surface and only on the first surface, and all of the at least one edge surface are free of electrical contact surfaces and terminal pins.

2. The power switch according to claim 1, wherein: Contact surfaces of the power terminal and the power phase output terminal are substantially flush with the first face surface.

3. The power switch according to claim 1, wherein: The electrical contact surfaces of the power terminals and / or the power phase output terminals are elevated or recessed relative to the plane of the first surface.

4. The power switch according to any one of claims 1 to 3, wherein: The contact surface of the control terminal is substantially flush with the first surface.

5. The power switch according to claim 4, wherein: An electrical contact surface of one of the control terminals is elevated or recessed relative to a plane of the first surface.

6. The power switch according to any one of claims 1 to 3 and 5, wherein: The contact surface and the control terminal to which it belongs are configured to be coupled to an electrical conductor by soldering, ultrasonic welding, or laser welding, or by press-fitting or screwing the conductor into a hole in the control terminal.

7. The power switch according to any one of claims 1 to 3 and 5, wherein: The packaging shell is a rectangular parallelepiped that encapsulates all components of the switch. 8 . The power switch according to claim 1 , further comprising a second surface opposite to the first surface, wherein a heat conductive interface is formed on the second surface.

9. The power switch according to any one of claims 1 to 3 and 5, wherein: When the switches are turned on, current flows in parallel in the same direction in each half-bridge toward the power phase output terminals.

10. The power switch according to any one of claims 1 to 3 and 5, having a total power loop inductance of less than 2.5 nH when switching between the on state and the off state.

11. The power switch according to any one of claims 1 to 3 and 5, having a total power loop inductance of less than 2.25 nH when switching between an on state and an off state.

12. The power switch according to any one of claims 1 to 3 and 5, having a total power loop inductance of less than 2.0 nH when switching between an on state and an off state.

13. A power switch comprising: a pair of substantially parallel half-bridges; power terminals for coupling a power source to the half-bridge; power phase output terminals for connecting a load to the half-bridge; a printed circuit board (PCB) controller having a control circuit operable to switch the half-bridge on and off to connect and disconnect the load from the power supply, respectively; a first set and a second set of control terminal pins that make electrical contact with a control circuit on the PCB controller; a packaging case encapsulating all components of the switch except the control terminal pins and having a rectangular parallelepiped shape, the rectangular parallelepiped having a planar first surface and edge surfaces; In which, the contact surfaces of the power terminal and the power phase output terminal are exposed on the first surface, and the first set and the second set of control terminal pins extend from the opposite first edge surface and the second edge surface at diagonally opposite positions, respectively, so that the orthographic projections of the first set and the second set onto the same plane parallel to the plane of the first edge and the second edge do not overlap. 14 . The power switch according to claim 13 , comprising a second surface opposite to the first surface, and a thermally conductive interface is formed on the second surface.

15. The power switch according to claim 13 or 14, wherein: When the switches are turned on, current flows in parallel in the same direction in each half-bridge toward the power phase output terminals.

16. The power switch according to claim 13 or 14, having a total power loop inductance of less than 2.5 nH when switching between the on state and the off state.

17. The power switch according to claim 13 or 14, having a total power loop inductance of less than 2.25 nH when switching between the on state and the off state.

18. The power switch according to claim 13 or 14, having a total power loop inductance of less than 2.0 nH when switching between the on state and the off state.

19. A power pack array comprising a plurality of power switches according to any one of the preceding claims in close proximity to each other.

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