Manufacturing method of three-dimensional NAND flash memory array

Abstract

According to one embodiment of the present invention, a method for manufacturing a three-dimensional NAND flash memory array including a vertical NAND channel in which polysilicon vertically extends on a substrate may comprise: a metal film forming step of forming a metal film along a side wall of the polysilicon by injecting metal; a crystal phase growth step for growing crystalline silicon between the metal and the polycrystalline silicon by irradiation with microwaves; and a crystalline phase transport step in which the crystalline silicon is transported in the direction of the bottom surface of the vertical NAND channel by irradiating microwaves.

Description

Technical Field

[0001] The present invention relates to a semiconductor technology, and in particular to a method for manufacturing a three-dimensional NAND flash memory array. Background Art

[0002] With the development of technology and the increase in demand for mobile devices such as smartphones and tablet computers, the demand for storage devices with improved integration will also increase dramatically. In order to improve the integration in a small area, storage devices are replaced by solid state memory (SSD) instead of existing hard disk drives (HDD). Among solid state memories, the demand for non-volatile storage devices has increased dramatically. As non-volatile storage devices, NAND (NAND) flash memory devices are widely used to improve integration and save costs.

[0003] Three-dimensional NAND flash memory devices are made by vertically stacking cells, which are the basic storage units. In this case, as the number of stacked layers increases, the bit density will increase and the cost per bit can be reduced.

[0004] Currently, three-dimensional NAND flash memory devices are stacked with more than 100 layers, and as capacity continues to increase, the number of stacked layers is expected to expand to more than four digits.

[0005] Furthermore, using polysilicon as a channel material in a three-dimensional NAND flash memory device will save costs.

[0006] When polysilicon is used to form a channel, the resistance will increase during the reading operation, causing the reading current in the cell to become smaller than the minimum current that can be detected in the sensing circuit, thereby making it difficult to read the working band. When the number of stacked layers is high, there is a problem of relatively reduced electric field mobility in the channel.

[0007] The limitations of polysilicon have become a stumbling block that restricts the long-term expansion of three-dimensional NAND flash memory devices.

[0008] In order to improve the device characteristics of this amorphous polysilicon, crystallization technology is used. Crystallization technology includes solid phase crystallization (SPC) that raises the temperature above the melting point of silicon to perform recrystallization, eximer laser crystallization (ELC) that targets only amorphous polysilicon to achieve crystallization in a local area, and metal induced lateral crystallization (MILC) that performs crystallization at low temperature.

[0009] Since solid phase crystallization (SPC) is carried out at high temperature, the process will face great difficulties. Excimer laser crystallization (ELC) can achieve crystallization in local areas, so there are fewer process restrictions, but there are problems such as the need for laser equipment, which increases costs and low yields of crystallized polysilicon.

[0010] The crystallization of amorphous polysilicon based on metal-induced lateral crystallization (MILC) will form polysilicon. After metal is injected and NiSi2 crystals are grown, a series of process steps such as NiSi2 transport will be carried out.

[0011] Korean Patent Publication No. 10-2021-0117522 (publication date: September 29, 2021) discloses a first semiconductor pattern crystallized based on the above metal-induced lateral crystallization (MILC). This metal-induced lateral crystallization also requires a long process time. As the process is carried out at a high temperature, there are problems such as high heat load. Summary of the invention

[0012] Technical issues

[0013] The present disclosure provides a method for manufacturing a three-dimensional NAND flash memory array that can improve the reduction of read current even if the number of cells is increased to improve integration.

[0014] Solutions to the problem

[0015] In order to solve the above technical problems, the present invention provides a method for manufacturing a three-dimensional NAND flash memory array.

[0016] According to one embodiment of the present invention, a method for manufacturing a three-dimensional NAND flash memory array including a vertical NAND channel in which polycrystalline silicon extends vertically on a substrate may include: a metal film forming step of forming a metal film along the sidewalls of the polycrystalline silicon by injecting metal; a crystal phase growth step of irradiating a first microwave to grow crystalline silicon between the metal and the polycrystalline silicon; and a crystal phase transport step of irradiating a second microwave to transport the crystalline silicon toward the bottom surface of the vertical NAND channel.

[0017] According to one embodiment, before the metal film forming step, the method for manufacturing a three-dimensional NAND flash memory array may further include: a polysilicon pretreatment step of irradiating a third microwave to pretreat the polysilicon.

[0018] According to one embodiment, after the crystal phase transporting step, the manufacturing method may further include: a defect removing step of performing annealing in a hydrogen environment to remove defects on the crystalline silicon.

[0019] According to one embodiment, the defect removal step may be performed at a pressure ranging from 2 atmospheres to 50 atmospheres.

[0020] According to one embodiment, the defect removal step may be performed at a temperature ranging from 200°C to 800°C.

[0021] According to one embodiment, the first microwave may output 1 KW to 10 KW.

[0022] According to one embodiment, the first microwave may be irradiated within a frequency band ranging from 2.4 GHz to 2.5 GHz.

[0023] According to one embodiment, the crystal growth step may be performed at a temperature ranging from 200°C to 600°C.

[0024] According to one embodiment, the metal may be one selected from nickel (Ni), titanium (Ti), molybdenum (Mo), cobalt (Co) and aluminum (Al).

[0025] Effects of the Invention

[0026] According to an embodiment of the present invention, by performing metal induced lateral crystallization (MILC) at a relatively low temperature by combining microwave annealing and hydrogen annealing, there is an advantage of reducing heat load in the manufacturing process of a three-dimensional NAND flash memory array.

[0027] According to an embodiment of the present invention, there is an advantage of improving the reduction of the read current of a three-dimensional NAND flash memory array by performing metal induced lateral crystallization (MILC) at a relatively low temperature by combining microwave annealing and hydrogen annealing.

[0028] According to another embodiment of the present invention, the present invention has the following advantages: in the crystal phase growth step, the first microwave is irradiated to the metal film to induce the resistance conduction absorption of the metal, so that the metal atoms quickly penetrate the interface of the polysilicon, thereby shortening the manufacturing process time of the three-dimensional NAND flash memory array.

[0029] According to another embodiment of the present invention, the present invention has the following advantages. In the crystal phase transport step, a second microwave is irradiated to the vertical NAND channel to provide kinetic energy, thereby rapidly transporting crystalline silicon to the ground of the vertical NAND channel to shorten the manufacturing process time of the three-dimensional NAND flash memory array.

[0030] According to another embodiment of the present invention, the present invention has the following advantages: in the polysilicon pretreatment step, the polysilicon is irradiated with a third microwave to pretreat the polysilicon, thereby removing impurities in the polysilicon and improving the bonding stability of the metal film formed on the interface of the polysilicon.

[0031] According to still another embodiment of the present invention, the present invention has the following advantages: in the polycrystalline silicon pretreatment step, the polycrystalline silicon is pretreated by irradiating the third microwave to the polycrystalline silicon, thereby minimizing thermal deformation of the polycrystalline silicon as the pretreatment is performed at a relatively low temperature.

[0032] According to still another embodiment of the present invention, the present invention has the advantage that in the defect removal step, defects on polysilicon are removed by high pressure heat treatment in a hydrogen environment, thereby reducing defects in crystalline silicon throughout the entire region of the vertical NAND channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 The figure is a cross-sectional perspective view briefly showing a three-dimensional NAND flash memory array according to an embodiment of the present invention.

[0034] Figure 2 To enlarge Figure 1 Front cross-sectional view of A in FIG.

[0035] Figure 3 (a) to Figure 3 Part (e) is a diagram briefly illustrating a vertical NAND channel crystallization (MILC) process according to an embodiment of the present invention.

[0036] Figure 4 FIG. 4 is a flow chart showing a method for manufacturing a three-dimensional NAND flash memory array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] Hereinafter, with reference to the accompanying drawings, the preferred embodiments of the present invention are described in detail. However, the technical concept of the present invention is not limited to the embodiments described herein, but can be embodied in other forms. On the contrary, the embodiments described herein are provided to make the disclosed content complete and to fully convey the concept of the present invention to ordinary technicians in the technical field to which the present invention belongs.

[0038] In this specification, when it is mentioned that a structural element is located on other structural elements, it means that it can be directly formed on other structural elements or a third structural element can be formed between them. In addition, in the drawings, the shapes and sizes are exaggerated for effective description of the contents.

[0039] Furthermore, in the multiple embodiments in this specification, the terms such as first, second, and third are used to describe multiple structural elements, and these structural elements are not limited to these terms. These terms are only used to distinguish between two structural elements. Therefore, what is referred to as the first structural element in one embodiment can be referred to as the second structural element in other embodiments. Each embodiment described and illustrated herein includes its complementary embodiment. Furthermore, in this specification, "and / or" means including at least one of the structural elements listed before and after.

[0040] In the specification, unless the context clearly indicates otherwise, singular expressions include plural expressions. Furthermore, terms such as "including" or "having" are used to specify the existence of features, numbers, steps, structural elements, or combinations thereof recorded in the specification, and should not be understood to exclude the existence or additional possibility of one or more other features, numbers, steps, structural elements, or combinations thereof. Furthermore, in this specification, "connected" includes the meaning of directly or indirectly connecting multiple structural elements.

[0041] Furthermore, in the following description of the present invention, when it is determined that the detailed description of a related well-known function or structure makes the gist of the present invention unclear, the detailed description thereof will be omitted.

[0042] Figure 1 To briefly illustrate a cross-sectional perspective view of a three-dimensional NAND flash memory array 10 according to an embodiment of the present invention, Figure 2 To enlarge Figure 1 Front cross-sectional view of A in FIG.

[0043] A three-dimensional NAND flash memory array 10 according to one embodiment of the present invention may include a vertical NAND channel 300 .

[0044] Reference Figure 1 and Figure 2 The vertical NAND channel 300 may extend vertically on the substrate 100 in the Z-axis direction of the XYZ orthogonal coordinate system. The vertical NAND channel 300 may be a channel for carriers such as holes or electrons to flow.

[0045] The vertical NAND channel 300 may include polysilicon 310 and an oxide film 320. The vertical NAND channel 300 has a macaroni structure in which the polysilicon 310 forms a main body and the oxide film 320 is filled inside. That is, the oxide film 320 may be buried in the center of the polysilicon 310.

[0046] As the vertical NAND channel 300 has a macaroni structure, the thickness of the cross section (cross section on the XY plane) of the vertical NAND channel 300 can be reduced. When the thickness of the cross section of the vertical NAND channel 300 is reduced, the leakage current (OffCurrent Leakage Current or Subthreshold Leakage Current) is reduced, and the subthreshold swing (SS) can be improved.

[0047] exist Figure 1On the XY plane, the polysilicon 310 may have a ring-shaped cross section in which the oxide film 320 exists at the center.

[0048] According to a method of manufacturing a three-dimensional NAND flash memory array described later, amorphous silicon 312 constituting polysilicon 310 is crystallized and becomes crystalline silicon 311 .

[0049] Refer again Figure 1 and Figure 2 The substrate 100 may have a main surface that is a horizontal plane. The horizontal plane may face the XY plane.

[0050] The polysilicon gate 200 may include a plurality of gates 210 and gate insulating layers 220 that are alternately stacked and stacked in multiple layers. The polysilicon gate 200 may face the substrate 100 and have a horizontal surface. The polysilicon gate 200 may surround at least a portion of the vertical NAND channel 300 .

[0051] The gate insulating layer 220 may be formed between the gates 210 and alternately stacked with the gates 210 .

[0052] Figure 3 (a) to Figure 3 Part (e) is a diagram briefly showing a vertical NAND channel crystallization (MILC) process according to an embodiment of the present invention. Figure 4 FIG. 4 is a flow chart showing a method for manufacturing a three-dimensional NAND flash memory array according to an embodiment of the present invention.

[0053] Hereinafter, a method for manufacturing a three-dimensional NAND flash memory array according to an embodiment of the present invention will be described in detail in chronological order.

[0054] Reference Figure 3 (a) to Figure 3 Part (e) and Figure 4 The method for manufacturing a three-dimensional NAND flash memory array may include a metal film forming step S20, a crystal phase growing step S30, and a crystal phase transporting step S40. In another embodiment, the method for manufacturing a three-dimensional NAND flash memory array may also include a polysilicon pretreatment step S10 and a defect removal step S50.

[0055] In the polysilicon gate forming step (not shown), gate electrodes and gate insulating layers may be alternately stacked on a substrate to form a polysilicon gate.

[0056] In the opening forming step (not shown), an opening may be formed to form a vertical NAND channel. The opening may correspond to a region where polysilicon described later is formed. In the opening forming step (not shown), at least one opening may be formed in any region of the polysilicon gate.

[0057] In the polysilicon forming step (not shown), silicon (Si) and an oxide filling material may be deposited in the opening to form polysilicon. More specifically, in the polysilicon forming step (not shown), after silicon (Si) is deposited to a predetermined thickness in the opening, the oxide filling material may be sequentially filled into the hollow portion inside the silicon (Si).

[0058] The oxide filling material may be an insulating material such as silicon oxide (SixNy, x and y are positive integers). For example, the oxide filling material may be SiO2.

[0059] In the polysilicon forming step (not shown), silicon (Si) and oxide filling material may be evaporated to vertically extend in the opening to form a ring-shaped polysilicon surrounding the oxide film. The polysilicon formed in the polysilicon forming step (not shown) may be amorphous silicon (a-Si). The oxide film may be used to reduce the thickness of the polysilicon. The oxide film may be an insulating material such as silicon oxide (SixNy, x and y are positive integers). For example, the oxide film may be SiO2.

[0060] Reference Figure 3 Part (a) and Figure 4 In the polycrystalline silicon pretreatment step S10, the polycrystalline silicon (amorphous silicon) may be pretreated. In the polycrystalline silicon pretreatment step S10, the third microwave may be irradiated to remove incomplete bonds such as SiOH and unbonded molecules, dangling bonds, and oxygen vacancies on the polycrystalline silicon (amorphous silicon).

[0061] In the polysilicon pretreatment step S10, a metal film is formed in the metal film forming step S20 described later (see Figure 3 Before step (b) 313), the polycrystalline silicon (amorphous silicon) may be pre-treated. Through the polycrystalline silicon pre-treatment step S10, the fluidity of the carrier in the polycrystalline silicon (amorphous silicon) may be improved.

[0062] In the polysilicon pretreatment step S10, the third microwave may be locally irradiated to the end of the vertical NAND channel. More specifically, in the polysilicon pretreatment step S10, electromagnetic wave energy based on the irradiated third microwave may be injected into the polysilicon (amorphous silicon) to guide resistance conduction absorption in the polysilicon.

[0063] The polysilicon pretreatment step S10 may be performed at a temperature ranging from 200°C to 600°C.

[0064] The third microwave according to one embodiment may have an output value of 1 KW to 10 KW, preferably, has an output value of 4 KW.

[0065] The third microwave according to one embodiment may have a frequency band of 2.4 GHz to 2.5 GHz, preferably, a frequency band of 2.45 GHz. Also, the third microwave according to another embodiment may have a frequency band of 5.8 GHz to 5.9 GHz, preferably, a frequency band of 5.85 GHz.

[0066] Reference Figure 3 Part (b) and Figure 4 In the metal film forming step S20, a metal film 313 may be formed by injecting metal in the upper end region of the vertical NAND channel. In the metal film forming step S20, a thin metal film may be formed along the sidewall of the polysilicon (amorphous silicon) forming the vertical NAND channel. The metal film may be formed in a film form between the polysilicon (amorphous silicon) and the oxide film.

[0067] In the metal film forming step S20 according to one embodiment, the application of metal atoms to the inside of the vertical NAND channel may be accelerated by applying an external magnetic field.

[0068] According to one embodiment, the metal constituting the metal film 313 may be one selected from nickel (Ni), titanium (Ti), molybdenum (Mo), cobalt (Co) and aluminum (Al). According to one embodiment, when nickel (Ni) is injected, the crystal structure of the vertical NAND channel may be densified after crystallization. Figure 3 Part (b) shows the injection of nickel (Ni), which corresponds to only one embodiment and the type of metal is not limited thereto.

[0069] Reference Figure 3 Part (c) and Figure 4 In the crystal phase growth step S30, crystalline silicon may be grown in the upper end region of the vertical NAND channel. In the crystal phase growth step S30, metal and polycrystalline silicon (amorphous silicon) may be combined with each other to form crystalline silicon. In the crystal phase growth step S30, polycrystalline silicon (amorphous silicon) located in the upper end region of the vertical NAND channel begins to crystallize into crystalline silicon at the interface between the polycrystalline silicon (amorphous silicon) and the metal film. In the crystal phase growth step S30, at the interface of the polycrystalline silicon in the end region of the vertical NAND channel, crystallized silicon is grown in the direction of the polycrystalline silicon inside as the Z-direction. In the crystal phase growth step S30, a first microwave may be irradiated. When the first microwave is irradiated, metal atoms are combined with silicon (Si) atoms and crystalline silicon may be grown. According to one embodiment, when the metal is nickel (Ni), the crystalline silicon may be nickel silicide (NiSi2).

[0070] In the crystal phase growth step S30, the first microwave may be locally irradiated to the end of the vertical NAND channel. More specifically, in the crystal phase growth step S30, electromagnetic wave energy based on the first microwave irradiation is injected into the metal film to guide the resistance conduction absorption, thereby accelerating the penetration speed of metal atoms in the metal film into the polysilicon at the interface between the metal film and the polysilicon.

[0071] In another embodiment, in the crystal phase growth step S30, heat may also be applied to the three-dimensional NAND flash memory array to grow crystalline silicon. For example, heat may be applied to the three-dimensional NAND flash memory array to grow crystalline silicon within 7 to 20 minutes. Preferably, heat may be applied to the three-dimensional NAND flash memory array to grow crystalline silicon within 30 to 120 minutes.

[0072] When the crystal phase growth step S30 is performed at a low temperature, the damage applied to the polysilicon and the metal film can be minimized. In the crystal phase growth step S30, when heat of about 700°C is applied to the three-dimensional NAND flash memory array, a high heat load may be caused. In order to reduce the heat load, in the crystal phase growth step S30, the first microwave may be irradiated to the three-dimensional NAND flash memory array in a temperature range of 200°C to 600°C. In the crystal phase growth step S30, the first microwave may have an output value of 1KW to 10KW, preferably, an output value of 4KW.

[0073] In the crystal phase growth step S30, the first microwave may have a frequency band of 2.4 GHz to 2.5 GHz, preferably, a frequency band of 2.45 GHz. In another embodiment, the first microwave may have a frequency band of 5.8 GHz to 5.9 GHz, preferably, a frequency band of 5.85 GHz.

[0074] Reference Figure 3 Part (d) and Figure 4 In the crystal phase transport step S40, the second microwave is irradiated at the end of the vertical NAND channel to transport the crystalline silicon to the bottom surface of the vertical NAND channel having a specified thickness. In the crystal phase transport step S40, polycrystalline silicon reacts with the metal so that the polycrystalline silicon can be crystallized into crystalline silicon until the bottom surface of the vertical NAND channel. In the crystal phase transport step S40, the second microwave can be irradiated along the Z-direction toward the bottom surface of the vertical NAND channel. In the crystal phase transport step S40, the second microwave can be irradiated to provide kinetic energy, so that the crystalline silicon can be transported to the bottom surface of the vertical NAND channel.

[0075] In the crystalline phase transport step S40, a second microwave may be irradiated to transport the crystalline silicon to the bottom surface layer of the vertical NAND channel in a relatively fast time.

[0076] More specifically, in the crystal phase transport step S40, kinetic energy in the form of electromagnetic waves based on the second microwaves is provided to the crystalline silicon, so that the crystalline silicon can be transported to the entire region of the vertical NAND channel.

[0077] In the crystal phase transport step S40, the process of irradiating the second microwave can be performed in a relatively short process time compared to a method of applying heat to the three-dimensional NAND flash memory array.

[0078] In one embodiment, heat of 500° C. may be applied to the three-dimensional NAND flash memory array for 720 minutes to transport crystalline silicon. As described above, when the three-dimensional NAND flash memory array is exposed to high temperatures for a long time, it may cause high heat load on the vertical NAND channels.

[0079] Therefore, in order to minimize the damage of polysilicon and metal, the crystal phase transporting step S40 may be performed within a temperature range of 200° C. to 400° C.

[0080] Preferably, the crystal phase transporting step S40 may be performed for 30 minutes to 120 minutes.

[0081] In this case, the second microwave may have an output value of 1 KW to 10 KW, preferably, an output value of 4 KW. In the crystal phase transport step S40, the second microwave may be locally irradiated toward the end of the vertical NAND channel.

[0082] The second microwave WM according to one embodiment may have a frequency band of 2.4 GHz to 2.5 GHz, preferably, a frequency band of 2.45 GHz. Also, the second microwave WM according to another embodiment may have a frequency band of 5.8 GHz to 5.9 GHz, preferably, a frequency band of 5.85 GHz.

[0083] Reference Figure 3 Part (e) and Figure 4 In the defect removal step S50, the three-dimensional NAND flash memory array is annealed in a hydrogen environment to remove defects on the crystalline silicon.

[0084] When a portion of the metal forming the crystalline silicon is not bonded but remains in the form of metal atoms, it may become a defect of the vertical NAND channel itself. In the defect removal step S50, in order to remove defects such as non-bonded metal atoms in the crystalline silicon, the three-dimensional NAND flash memory array can be annealed in a hydrogen environment.

[0085] The defect removal step S50 can be performed for a relatively short time. Preferably, the defect removal step S50 can be performed for 10 minutes to 60 minutes.

[0086] In the defect removal step S50, annealing may be performed in a state where 3% to 10% of hydrogen (H2) or deutrone (D2) is provided as a reaction gas. Gases other than the reaction gas may be nitrogen (N2). In particular, when the concentration of hydrogen (H2) is above 10%, the risk of explosion in a flammable environment may increase. In the design of the annealing device, it can be used as long as the risk of explosion is controlled. Therefore, the use of hydrogen (H2) or deutrone (D2) at a concentration above this (for example, above 10% or 100%) is not excluded. According to an embodiment, in the defect removal step S50, a reaction gas including oxygen (O), fluorine (F) or nitrogen (N) may also be provided.

[0087] In the defect removing step S50 , annealing may be performed within a pressure range of 2 atmospheres to 50 atmospheres, preferably, within a pressure range of 2 atmospheres to 20 atmospheres.

[0088] In the defect removing step S50 , annealing may be performed in a temperature range of 200° C. to 800° C., preferably, in a temperature range of 200° C. to 600° C., and more preferably, in a temperature range of 350° C. to 450° C.

[0089] The present invention is described in detail using preferred embodiments above, and the scope of the present invention is not limited to the specific embodiments, but needs to be interpreted by the scope of the appended claims. Moreover, as long as one is a person of ordinary skill in the art to which the present invention belongs, various modifications and variations can be made without exceeding the scope of the present invention.

Claims

1. A method for manufacturing a three-dimensional NAND flash memory array, the three-dimensional NAND flash memory array comprising a vertical NAND channel with polysilicon extending vertically on a substrate, wherein: The manufacturing method of the three-dimensional NAND flash memory array comprises: a metal film forming step of forming a metal film along the sidewalls of the polysilicon by injecting metal; a crystal phase growth step of irradiating a first microwave to grow crystalline silicon between the metal and the polycrystalline silicon; and In the crystal phase transport step, second microwaves are irradiated to transport the crystal silicon toward the bottom surface of the vertical NAND channel.

2. The method for manufacturing a three-dimensional NAND flash memory array according to claim 1, wherein: Before the metal film forming step, the manufacturing method further includes: a polysilicon pretreatment step of irradiating a third microwave to pretreat the polysilicon.

3. The method for manufacturing a three-dimensional NAND flash memory array according to claim 1, wherein: After the crystal phase transport step, the manufacturing method further comprises: In the defect removal step, annealing is performed in a hydrogen environment to remove defects on the crystalline silicon.

4. The method for manufacturing a three-dimensional NAND flash memory array according to claim 3, wherein: The defect removal step is performed at a pressure ranging from 2 atmospheres to 50 atmospheres.

5. The method for manufacturing a three-dimensional NAND flash memory array according to claim 3, wherein: The defect removal step is performed at a temperature ranging from 200°C to 800°C.

6. The method for manufacturing a three-dimensional NAND flash memory array according to claim 1, wherein: The first microwave output is 1 KW to 10 KW.

7. The method for manufacturing a three-dimensional NAND flash memory array according to claim 1, wherein: The first microwave is irradiated within a frequency band of 2.4 GHz to 2.5 GHz.

8. The method for manufacturing a three-dimensional NAND flash memory array according to claim 1, wherein: The crystal phase growth step is performed at a temperature ranging from 200°C to 600°C.

9. The method for manufacturing a three-dimensional NAND flash memory array according to claim 1, wherein: The metal is one selected from nickel (Ni), titanium (Ti), molybdenum (Mo), cobalt (Co) and aluminum (Al).

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