Finished product testing method, method for measuring loss of testing system, equipment, medium and product

Abstract

The invention relates to a method for measuring loss of a test system in a radio frequency chip finished product test. The method comprises the following steps: providing a standard chip with a standard test value; inputting a radio frequency signal to the standard chip through the test machine; measuring the output end of the test circuit board to obtain an output test value; and determining a test difference value between the output test value and the standard test value, and performing judgment to determine the system output loss. The invention further relates to a finished product testing method and equipment for the radio frequency chip, a medium and a product.

Description

Technical Field

[0001] The present application relates to the field of radio frequency technology, and in particular to a method for testing a finished radio frequency chip, and a method, device, medium, and product for measuring the loss of a test system in testing a finished radio frequency chip. Background Art

[0002] Finished product testing (FT) refers to the use of programmed mass production programs to perform batch screening tests on automated test equipment (ATE) to distinguish good performance products from defective products. Especially in ATE's FT of radio frequency chips such as power amplifiers (PA) and low noise amplifiers (LNA), even if the same test equipment is used, there will be errors in the construction of different test environments while ensuring the same program. The errors in the test environment construction between different devices of the same type will be even greater. Figure 1 The figure shows the test results of one RF test item (such as gain) of the same batch of chips after the test environment was set up three times on the same test machine, where the horizontal axis is the input RF signal and the vertical axis is the RF test item. It can be seen that there is a certain deviation in the distribution of the three test results. This problem arises because the RF test item is sensitive to the test environment. Each time the test environment is set up, the tightness of the RF cable and the contact between the socket and the test circuit board (LoadBoard, LB) will cause errors and losses in different tests. In order to ensure that the results of each test of the same batch of chips are basically the same, the test system (test machine + RF cable + LB + Socket) needs to be calibrated to achieve smooth mass production of FT. Summary of the invention

[0003] In order to solve the above problems and realize accurate calibration of the loss of the test system, the present application proposes a method for measuring the loss of the test system in the test of the finished radio frequency chip, wherein the test system comprises a test machine, a test circuit board connected to the test machine, and a socket arranged on the test circuit board, wherein the socket is used to install the chip to electrically connect the chip to the test circuit board;

[0004] The test system loss includes: system output loss, and the system output loss includes: output contact loss between the output end of the socket and the output circuit board, and output path loss between the output end of the chip and the output end of the test circuit board;

[0005] The test machine stores an initial output loss, wherein the initial output loss includes an initial output contact loss between the output end of the socket and the test circuit board and / or an initial output path loss between the output end of the chip and the output end of the test circuit board;

[0006] The method comprises:

[0007] Providing a standard chip, wherein the test items of the standard chip meet the test standards of the finished product test, and the standard chip has a standard test value;

[0008] Inputting a radio frequency signal to the standard chip through the test machine, wherein the power of the input radio frequency signal is the sum of the lossless input power and the stored output loss;

[0009] Measuring the output terminal of the test circuit board to obtain an output test value;

[0010] Determine the test difference between the output test value and the standard test value, and make a judgment:

[0011] When the test difference is within a set error range, determining the initial output loss as the system output loss;

[0012] When the test difference exceeds a set error range, a first compensation deviation is applied to the stored output loss to obtain an adjusted output loss, and the steps of inputting a radio frequency signal, measuring an output test value, and determining a test difference are repeated until the test difference is within an error range, and the adjusted output loss is determined as the system output loss, wherein the adjusted output loss is the sum of the first compensation deviation and the stored output loss, and the stored output loss includes the initial output loss and the adjusted output loss.

[0013] Optionally, the test system loss further includes: system input loss, the system input loss including: input path loss of the RF signal from the input end of the test circuit board to the input end of the chip, and input contact loss between the input end of the socket and the test circuit board;

[0014] The test machine stores an initial input loss, wherein the initial input loss includes an initial input contact loss between the input end of the socket and the test circuit board and / or an initial input path loss between the input end of the test circuit board and the chip input end;

[0015] The method further comprises:

[0016] Obtaining a standard gain value of the standard chip;

[0017] Test the output end of the chip to obtain the test output power P out1 The actual output power P is determined by the following formula: out2 :P out2 = System output loss + P out1 ;

[0018] Get the input power P sent by the test machine in1 The actual input power P received by the standard chip is determined by the following formula in2 :P in2 =P in1 - Input loss of storage;

[0019] Based on the actual output power and the actual input power, the test gain value N of the standard chip is determined by the following formula: N=P out2 -P in2 ;

[0020] Determine the gain difference between the test gain value and the standard gain value, and make a judgment:

[0021] When the gain difference is within a set error range, determining the initial input loss as the system input loss;

[0022] When the gain difference exceeds the set error range, a second compensation deviation is applied to the stored input loss to obtain an adjusted input loss, and the steps of testing Pin2 and determining the gain value N are repeated until the gain difference is within the error range, and the adjusted input loss is determined as the system input loss, wherein the adjusted input loss is the sum of the second compensation deviation and the stored input loss, and the stored input loss includes the initial input loss and the adjusted input loss.

[0023] Optionally, the standard test value is one of a standard error vector amplitude value, a standard current, and a standard saturation power;

[0024] The output test value is one of an output error vector amplitude value, an output current, and an output power.

[0025] Optionally, the adjustment may include one of an ergodic accumulation method, a binary search method, and a linear prediction method.

[0026] Optionally, adjusting the initial output loss includes:

[0027] adjusting the initial contact loss and / or the initial output path loss; or

[0028] adjusting the sum of the initial contact loss and the initial output path loss;

[0029] Adjusting the initial input loss includes:

[0030] adjusting the initial contact loss and / or the initial input path loss; or

[0031] The sum of the initial contact loss and the initial input path loss is adjusted.

[0032] Optionally, the method further comprises:

[0033] Setting a test difference form to record the initial output loss, the adjusted output loss, the output test value, and the test difference; and / or

[0034] A gain difference form is set to record the initial input loss, the adjusted input loss, the test gain value, and the gain difference.

[0035] Optionally, the testing machine comprises:

[0036] A multimeter or a power meter or a power board, used to test the output current;

[0037] The radio frequency test module is used to test the output error vector amplitude value and the output power.

[0038] Optionally, the input power P sent by the test machine is obtained. in1 , the test output power P out1 and the actual output power P out2 It is stored when needed and can be called up when needed.

[0039] The present application also proposes a finished product testing method for radio frequency chips, using any of the aforementioned methods to measure the test system loss;

[0040] Based on the test system error, the power of the RF signal to be sent by the tester is adjusted to obtain a calibration RF signal for testing, where the power of the calibration RF signal is the power of the RF signal to be sent plus the test system loss.

[0041] The present application also proposes an electronic device, which includes a memory storing computer-executable instructions and a processor; when the instructions are executed by the processor, the device implements any of the methods described above.

[0042] The present application also proposes a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the methods described above are implemented.

[0043] The present application also proposes a computer program product, comprising a computer program, which implements the steps of any of the aforementioned methods when executed by a processor.

[0044] By using the above method, the present application realizes a more accurate calibration of the test system by mutual verification of the output test items and the input test items, such as the method of output test current and input test gain. In the FT mass production test, the input loss and output loss obtained by calibration can be used for testing, so that the obtained measurement results will be more accurate and more precise, and the possibility of misjudgment during chip testing caused by directly adding deviations to the test results can be effectively avoided, while excluding the possibility of unreasonable situations caused by direct linear compensation of the test items. The present application can also be expanded according to different products. For different types of RF products, test items such as current and gain, error vector magnitude (EVM) and gain can be selected. For the transmitting RF component (TX) and the receiving RF component (RX), the gain of the TX Gain transmission channel and the saturated power of the TX Psat transmission channel can be used, and the gain of the RX Gain receiving channel and the input 1dB compression point of the RX IP1 receiving channel can be used. The basic principle is that the result of the chip meeting one of the parameters is only related to the Loss of the input quotient or the output quotient. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a schematic diagram of the test results of the chip after the test environment was set up three times on the same test machine.

[0046] Figure 2 It is a schematic diagram of the structure of a test system according to an embodiment of the present application.

[0047] Figure 3 It is a schematic plan view of a testing system according to an embodiment of the present application.

[0048] Figure 4 The present invention is a flow chart of a method for measuring the loss of a test system according to an embodiment of the present application.

[0049] Figure 5 is a curve diagram showing the relationship between current and output power according to an embodiment of the present application.

[0050] Figure 6 Graph showing current, EVM and output power according to an embodiment of the present application.

[0051] Figure 7 It is a curve diagram showing the relationship between input power and output power according to an embodiment of the present application.

[0052] Figure 8 The flowchart is a method for measuring an input terminal test system error according to an embodiment of the present application.

[0053] Fig. 9 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0055] First reference Figure 2 The test system used in this application is described below. The test system 200 includes a test machine 201, a test circuit board 202 disposed on the test machine 201 and electrically connected thereto, and a socket 203, wherein the socket is used to mount a chip 204 to electrically connect the chip to the test circuit board 202. It can be understood that the bracket shown in the figure is used to support the test machine, and the sorting machine is used to load the chip.

[0056] Combined with reference Figure 3 As shown in the planar schematic diagram of the test system, the RF input signal sent by the test machine 201 is input into the test circuit board 202 through the RF cable and the input end of the test circuit board 202, and then input into the chip 204 through the wiring input path 303 and the chip input end 304 on the test circuit board 202. After that, the RF signal passes through the chip 204, the chip output end 301, and the wiring output path 302 on the test circuit board 202, and is output at the output end of the test circuit board.

[0057] The test system includes losses, and the test system losses include system output losses. The system output losses include output contact losses caused by installation between the socket 203 and the test circuit board 202 (i.e., when the socket 203 is inserted into the test circuit board 202, the loss caused by contact between the output end of the socket 203 and the test circuit board 202), and output path losses of the output path 302 between the output end of the chip 204 and the output end of the test circuit board 202 (i.e., the loss on the path of the RF signal transmitted from the output end of the chip to the output end of the test circuit board).

[0058] It is to be understood that the contact and output path 302 shown in the figure are merely examples and do not represent actual contact positions and paths.

[0059] In addition, the initial output loss is also stored in the test machine 201, which is used to perform initial calibration on the test system at the beginning of the test. The initial output loss includes the initial output contact loss between the socket 203 and the test circuit board and / or the initial output path loss between the output end of the chip 204 and the output end of the test circuit board. For the convenience of explanation, in the following, the loss used for calibration at the beginning of the test is referred to as the initial output loss, and the loss determined for calibrating the system when the calibration is completed is referred to as the system output loss, which is obtained by continuously adjusting the adjusted output loss during the calibration process.

[0060] In the actual test process, a more reasonable initial output path loss can be obtained through experimental experience based on the material and length of the test circuit board on the signal output path. However, the loss caused by the contact between the socket and the test circuit board is difficult to estimate, so the initial output path loss is usually used as the initial output loss. It can also be simulated based on the circuit board model to obtain a more accurate initial output loss.

[0061] It can be understood that the various losses in the present application all refer to the power loss of the radio frequency signal during the transmission process, and the unit is dBm.

[0062] based on Figure 3 The test system shown in Figure 2 is referenced Figure 4 The flowchart is used to illustrate the method for measuring the test system loss in the finished RF chip test proposed in this application.

[0063] In step 401, a standard chip is provided. The standard chip is the GU chip mentioned above, and its test items all meet the test standards of finished product testing, so the standard chip has a standard test value X, which is directly readable information stored in a test machine or other storage device.

[0064] It is understandable that the test standard is a range of values, and the test values ​​of each test item of the standard chip that meets the test standard are all fixed values, and the test values ​​of appropriate test items are selected from each test item as the standard test value.

[0065] In this embodiment, a suitable test item may be current. Figure 5 The relationship curve between current and output power is shown in Figure 2. When the current is between 0 and i 1 When the current is in the linear working area, the chip under test is in the linear working area; when the current is in the linear working area, the chip under test is in the linear working area. 1 ~i 2 When the current is greater than i 2When the current increases, the output power decreases rapidly, and the chip may even burn out. That is, when the chip is in the linear region, as the current increases, its output power will gradually increase; in the saturation region, even if the current continues to increase, the output power will not increase significantly; after the saturation region, the current increases and the output power decreases rapidly, and the chip may even burn out. The present application scheme implements calibration based on the correlation between current and output power in the linear region. In addition, since gain (Gain) = output power (Pout) - input power (Pin), and Pin is a known small signal sent by the test machine during the calibration process, which ensures that the chip works in the linear region, it is used Figure 5 The relationship diagram in can be used to convert power into gain, so that the relationship between current and power can be used to test system loss.

[0066] Therefore, in the embodiment of the present application, the current that makes the chip in the linear working area can be selected as a suitable test item according to the linear correlation between the current and the output power, that is, the standard current value of the GU chip is used as the standard test value.

[0067] In addition, reference Figure 6 The relationship diagrams of current and output power and error vector magnitude (EVM) and output power show that, similar to current and output power, EVM also has a certain linear relationship with output power. In the linear working range, the greater the output power, the greater the EVM. Therefore, the standard EVM value of the GU chip can also be selected as the standard test value, and the same method can be used to measure the system output loss.

[0068] refer to Figure 7 It is a curve diagram of input power and output power. When the chip is in the saturation region, changing the input power will not change the output power, that is, the loss of the test system will not affect the output power. Therefore, by adjusting the loss at the output end, the output power (saturation power) obtained by the test can be equal to the saturation power of the GU, thereby obtaining the loss that needs to be compensated at the output end. Therefore, the standard saturation power can also be used as a standard test value.

[0069] In step 402, a radio frequency signal is input to the standard chip through the test machine, and the power of the input radio frequency signal is the sum of the lossless input power and the stored system output loss. After receiving the input radio frequency signal, the standard chip can output a corresponding signal at the output end.

[0070] Lossless input power refers to the power that the tester inputs to the standard chip without considering the loss. For example, before the system is adjusted for loss (it can also be considered that there is no system loss), the power of the RF signal to be sent is A, and the power received at the output end of the test circuit board under ideal conditions (no loss) is B; but due to the loss of the test system, the signal power received at the output end of the test circuit board is less than B. In order to compensate for the loss, the power of the RF signal to be sent needs to be adjusted to the sum of A and the loss. Before calibration, the loss is the initial output loss stored in the tester; after the loss is calibrated, the loss stored in the tester is adjusted accordingly as the adjusted output loss.

[0071] The implementation of this step specifically includes the following steps:

[0072] The power M of the RF signal to be transmitted without considering the loss can be called the lossless transmission power. It can be understood that the lossless transmission power is the aforementioned lossless input power. The lossless input power is described from the perspective of the input standard chip, and the lossless transmission power is described from the perspective of the test machine.

[0073] Call the stored system output loss N;

[0074] The lossless transmission power is calculated and summed with the stored system output loss (M+N) to obtain the calibrated transmission power;

[0075] The tester is made to send a radio frequency signal with a calibrated transmission power to perform the test.

[0076] In step 403, the output end of the test circuit board is measured to obtain an output test value Y. Since the signal output from the output end of the standard chip will have a certain loss after passing through the socket and the test circuit board, the output test value is not the standard test value of the GU, but the value obtained by measuring the standard test value of the GU under the influence of the initial output loss, which is smaller than the standard test value of the GU.

[0077] In step 404, a test difference (i.e., XY) between the output test value and the standard test value is determined, and the test difference is judged: when the test difference is within the set error range, the initial output loss is determined as the output loss; when the test difference exceeds the set error range, a first compensation deviation is applied to the stored output loss to obtain an adjusted output loss, and the steps of inputting an RF signal, measuring the output test value, and determining the test difference are repeated until the test difference is within the error range. In this way, the output test value is considered to be equal to the standard test value, and the adjusted output loss is determined as the system output loss, wherein the adjusted output loss is the sum of the first compensation deviation and the stored output loss.

[0078] Corresponding to the standard test value, the output test value can be one of the output EVM value, output current, and output power. In the present application, the output test value at the output end of the test circuit board is adjusted by applying a corresponding deviation to the RF signal emitted by the test machine. The calibrated output test value should be equal to the standard test value, that is, the calibrated output test value is equal to the sum of the output test value before calibration and the first compensation deviation.

[0079] It is understandable that the output loss can be adjusted through multiple iterations. For example, the first adjustment is made based on the initial output loss, and each subsequent adjustment is made based on the output loss after the last adjustment until the test difference is within the error range. Further, the output loss stored in steps 402 to 404 includes the initial output loss and the adjusted output loss during the adjustment process. When the adjustment is made for the first time, the stored output loss is the initial output loss, and in subsequent adjustments, the stored output loss is the adjusted output loss obtained during the adjustment process.

[0080] The test difference is the deviation between the output test value of the test item of the standard chip and the standard test value under the influence of the current initial output loss. The set error range is used to determine whether the test item meets the test standard for finished product testing under the deviation. When the test difference is within the set error range, it means that even under the influence of the initial output loss, the test value of the test item still meets the test standard, so the initial output loss can be determined as the system output loss for finished product testing.

[0081] It is understandable that since the initial output loss is completely based on the intrinsic loss of the test system and has not been manually adjusted, when the test difference is within the set error range, it can be considered that the current test system can be directly used for finished product testing without additional adjustment. When the test difference exceeds the set error range, it is considered that the current initial output error causes the corresponding test item to fail to meet the test standard, so it is necessary to apply the first compensation deviation to the initial output loss for adjustment to obtain the adjusted output loss so that the test item meets the test standard, wherein the final adjusted system output loss = first compensation deviation + stored output loss.

[0082] Based on the test experience and the test environment, the output loss can be adjusted by applying the first compensation deviation to the RF signal to adjust the initial contact loss and / or the initial output path loss respectively, or the sum of the initial contact loss and the initial output path loss can be adjusted as a whole. Specifically, the adjustment can be performed using methods such as the ergodic accumulation method, the dichotomy method, and the linear prediction method.

[0083] Traversal accumulation method: Assuming the initial value is 0, the traversal range is 5, and the step length is 0.1, the change of the first compensation deviation is: 0, 0.1, 0.2, 0.3, ..., 4.9, 5 (the direction can be positive or negative, that is, from 0, -0.1, -0.2, ... -4.9, -5). The other methods are similar. It can be understood that it is not necessary to completely traverse all values. It is only necessary to obtain the next test difference that is less than the error range to confirm that the current value is the first compensation deviation.

[0084] Binary method: Assume that the minimum value min=0 and the maximum value max=5; then the first compensation deviation=(min+max) / 2=2.5; if under the current first compensation deviation, the test difference is less than the lower limit of the error range, it means that the required first compensation deviation is too small and should be between the current first compensation deviation and max, then the first compensation deviation=(2.5+max) / 2=3.75; if under the current first compensation deviation, the test difference is greater than the lower limit of the error range, it means that the required first compensation deviation is too large and should be between the current first compensation deviation and min, then the first compensation deviation=(0+2.5) / 2=1.25; continue in this way until the test difference is within the error range.

[0085] Linear prediction method: that is, based on the linear relationship between current and output power, such as the simplest y=x+b, where y is the output power and x is the current; assuming that the coefficient of x is 1, if the output of one of the test results is 3 different from the target when the input is x0; then the next input is x+3 until the test difference is within the error range. Since the current is controlled by the input RF signal, it is necessary to adjust the current by adjusting the RF signal, thereby obtaining the power deviation value of the RF signal, which is the first compensation deviation.

[0086] Thus, the loss of the test system can be measured by testing the output end, so as to be used for calibration of the system finished product test. It can be understood that the test method is universal for different test items.

[0087] In order to achieve more accurate calibration, the present application also proposes a method of combining output end testing and input end testing, that is, testing system loss also includes system input loss, so as to obtain a more accurate loss value through joint verification of the output end and the input end.

[0088] The system input loss needs to be determined by adjusting the output loss, so the output loss needs to be adjusted first, and then the system input loss can be determined through the following steps.

[0089] refer to Figure 3Similar to the output loss, the system input loss includes: the input path loss of the input path 303 between the RF signal passing through the input end of the test circuit board and the input end of the chip, and the contact loss between the socket 203 and the test circuit board 202; the test machine also stores the initial input loss, which includes the contact loss between the socket and the test circuit board and / or the initial input path loss between the input end of the test circuit board and the input end of the chip. A more accurate loss can be obtained by mutual verification of the output end and the input end. For the same reason, the initial input path loss is usually taken as the initial input loss, which will not be repeated here.

[0090] Figure 8 Flowchart for testing system input loss at the input end.

[0091] In step 801, the standard gain value M of the standard chip is obtained. It can be understood by those skilled in the art that the test items of the output end: current, EVM value and saturation power, cannot be used for the test of the input end. Therefore, in this embodiment, the gain, which is related to both output power and input power (that is, the gain value is the difference between output power and input power), is selected to test the system input loss of the input end, where the standard gain value is directly readable information stored in the test machine or other storage devices.

[0092] In step 802, the test chip output terminal obtains the test output power P out1 The actual output power P is determined by the following formula: out2 :P out2 = System output loss + P out1 . The actual output power can be understood as the lossless output power, that is, the output power of the chip is tested without considering the system output loss. It can also be said to be the ideal output power. This power value can be stored in the tester or other storage devices. It can be understood that the test output power described here is the difference between the lossless output power at the chip output end and the system output loss, and the test system output loss is obtained after the output loss measurement. Therefore, the test system output loss is added to the RF signal emitted by the tester. Therefore, the test output power obtained in this step is the calibrated output power, which is the difference between the ideal output power and the adjusted output loss. The result is the same as the standard output power or within the error range.

[0093] In step 803, the input power P sent by the test machine is obtained. in1 The actual input power P received by the standard chip is determined by the following formula in2 :P in2 =P in1-Stored input loss. Due to the existing system input loss, the input power received by the input pin of the standard chip is not equal to the input power sent by the tester. It can be understood that in this embodiment, since the existing initial input loss may not necessarily make the test item (i.e., gain) meet the test standard, the actual input power determined based on the initial input loss is not necessarily absolutely accurate. It is only used to determine an initial gain obtained by the test for subsequent adjustments. Similar to the determination of the initial output loss described above, the initial input loss can also be determined based on a large amount of experimental experience or by simulation based on the circuit board model, which will not be repeated here.

[0094] Input power P in1 , actual input power P in2 The value can be stored in the test machine or other storage device. When used, it is called.

[0095] In step 804, based on the actual output power and the actual input power, the test gain value N of the standard chip is determined by the following formula: N=P out2 -P in2 = System output loss + P out1 -(P in1 - storage input loss), where P out1 , P in1 The lossless output power and the lossless input power are both determined values. The adjusted output loss is determined by the above-mentioned test output loss.

[0096] In step 805, the gain difference (ie, MN) between the test gain value and the standard gain value is determined, and a judgment is made:

[0097] When the gain difference is within the set error range, the initial input loss is determined as the system input loss;

[0098] When the gain difference exceeds the set error range, a second compensation deviation is applied to the stored input loss to obtain an adjusted input loss, and the steps of testing Pin2 and determining the gain value N are repeated until the gain difference is within the error range, and the adjusted input loss is determined as the system input loss. The adjusted input loss is the sum of the second compensation deviation and the stored input loss. In the present application, the test gain value of the test circuit board is adjusted by applying a corresponding deviation to the RF signal emitted by the test machine. The calibrated test gain value should be equal to the standard gain value, that is, the calibrated test gain value is equal to the sum of the test gain value before calibration and the second compensation deviation.

[0099] It is understandable that the adjustment of input loss can be performed through multiple iterations. For example, the first adjustment is performed based on the initial input loss, and each subsequent adjustment is performed based on the input loss after the last adjustment until the gain difference is within the error range. Similar to the adjustment of output loss, the final input loss can be determined by traversal accumulation method, dichotomy method and linear prediction method. The iterative principle is the same and will not be repeated here. Furthermore, the input loss stored in steps 803-805 includes the initial input loss and the adjusted input loss during the adjustment process. When adjusting for the first time, the stored input loss is the initial input loss. In subsequent adjustments, the stored input loss is the adjusted input loss obtained during the adjustment process.

[0100] In addition, in order to improve measurement efficiency, the test machine is also provided with a test difference form to record the initial output loss, adjusted output loss, output test value, and test difference; and / or a gain difference form is provided to record the initial input loss, adjusted input loss, test gain value, and gain difference, and the input power, test output power, and actual output power sent by the test machine during the measurement process are stored in real time, so that the above parameters can be directly called when in use.

[0101] For the testing of each test item, external test equipment can be used for testing, or test equipment integrated in the test machine can be used. For example, the test machine may include: a multimeter or a power meter or a power board for testing the output current; an RF test module for testing the output EVM value and the power of the RF signal output by the test machine.

[0102] The present application also proposes a finished product testing method for radio frequency chips. First, the test system loss is measured using the aforementioned method. Then, based on the test system loss, the power of the radio frequency signal to be sent by the tester is adjusted to obtain a calibrated radio frequency signal for testing. The power of the calibrated radio frequency signal is the power of the radio frequency signal to be sent plus the measured test system error.

[0103] Reference now Fig. 9 , shown is a block diagram of an electronic device 900 according to an embodiment of the present application, the electronic device is used to perform any of the aforementioned methods, and the electronic device can be integrated into a test machine or can be independent of the test machine. The electronic device 900 may include one or more processors 902, a system control logic 908 connected to at least one of the processors 902, a system memory 904 connected to the system control logic 908, a non-volatile memory (NVM) 906 connected to the system control logic 908, and a network interface 910 connected to the system control logic 908.

[0104] The processor 902 may include one or more single-core or multi-core processors. The processor 902 may include any combination of a general-purpose processor and a dedicated processor (e.g., a graphics processor, an application processor, a baseband processor, etc.). In the embodiments of this document, the processor 902 may be configured to execute one or more embodiments of the various embodiments proposed in this application, including but not limited to operations on values ​​such as actual output power and actual input power, and calls to data.

[0105] In some embodiments, the system control logic 908 may include any suitable interface controller to provide any suitable interface to at least one of the processors 902 and / or any suitable device or component communicating with the system control logic 908, including but not limited to controlling radio frequency signals emitted by the test machine.

[0106] In some embodiments, the system control logic 908 may include one or more memory controllers to provide an interface to the system memory 904. The system memory 904 may be used to load and store data and / or instructions. In some embodiments, the system memory 904 of the electronic device 900 may include any suitable volatile memory, such as a suitable dynamic random access memory (DRAM).

[0107] The non-volatile memory 906 may include one or more tangible, non-temporary computer-readable media for storing data and / or instructions. In some embodiments, the non-volatile memory 906 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as at least one of a HDD (Hard Disk Drive), a CD (Compact Disc) drive, and a DVD (Digital Versatile Disc) drive. Both the system memory 904 and the non-volatile memory 906 may be used to store and read various data during the test process, including but not limited to the input power P sent by the test machine. in1 , the test output power P out1 and the actual output power P out2 All the data required for the testing process.

[0108] The non-volatile memory 906 may include a portion of storage resources installed on a device of the electronic device 900, or it may be accessible by the device but not necessarily a portion of the device. For example, the non-volatile memory 906 may be accessed over a network via the network interface 910.

[0109] In particular, the system memory 904 and the non-volatile memory 906 may include: a temporary copy and a permanent copy of the instruction 920, respectively. The instruction 920 may include: an instruction that causes the electronic device 900 to implement the method provided by the present application when executed by at least one of the processors 902. In some embodiments, the instruction 920, hardware, firmware and / or its software components may be additionally / alternatively placed in the system control logic 908, the network interface 910 and / or the processor 902.

[0110] In some embodiments, the network interface 910 may be integrated with other components of the electronic device 900. For example, the network interface 910 may be integrated with at least one of the processor 902, the system memory 904, the non-volatile memory 906, and a firmware device (not shown) having instructions, and when at least one of the processors 902 executes the instructions, the electronic device 900 implements one or more of the various embodiments described herein. The network interface 910 may further include any suitable hardware and / or firmware to provide a multiple-input multiple-output radio interface.

[0111] In one embodiment, at least one of the processors 902 may be packaged together with logic for one or more controllers of the system control logic 908 to form a system in package (SiP). In one embodiment, at least one of the processors 902 may be integrated on the same die with logic for one or more controllers of the system control logic 908 to form a system on chip (SoC).

[0112] The electronic device 900 may further include an input / output (I / O) device 912. The input / output (I / O) device 912 may include a user interface, so that a user can interact with the device 900; the design of the peripheral component interface enables peripheral components to interact with the electronic device 900.

[0113] In some embodiments, the user interface may include, but is not limited to, a display (e.g., an LCD display, a touch screen display, etc.), a speaker, a microphone, one or more cameras (e.g., a still image camera and / or a video camera), a flashlight (e.g., an LED flash), and a keyboard.

[0114] In some embodiments, the peripheral component interface may include, but is not limited to, a non-volatile memory port, an audio jack, and a power interface.

[0115] It will be understood by those skilled in the art that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on the electronic device 900. In other embodiments of the present application, the electronic device 900 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0116] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0117] Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described herein is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

[0118] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a computer-readable storage medium, which represent various logic in a processor, and when the instructions are read by a machine, cause the machine to fabricate logic for performing the techniques described herein. These representations, known as "IP cores," may be stored on a tangible computer-readable storage medium and supplied to multiple customers or manufacturing facilities to load into a manufacturing machine that actually manufactures the logic or processor.

[0119] An embodiment of the present application discloses a computer-readable medium storing one or more programs executable by one or more processors to implement the method of the present application.

[0120] An embodiment of the present application discloses a computer program product, including a computer program, which implements the method of the present application when executed by a processor.

[0121] The above specific embodiments illustrate the implementation of the present application, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Although the description of the present application will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this invention are limited to the implementation. In addition, in order to avoid confusion or blurring the focus of the present application, some specific details will be omitted in the description. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0122] Furthermore, various operations will be described as multiple discrete operations in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations do not need to be performed in the order presented.

[0123] Unless the context dictates otherwise, the terms "comprising," "having," and "including" are synonymous. The phrase "A / B" means "A or B." The phrase "A and / or B" means "(A and B) or (A or B)."

[0124] As used herein, the term "module" or "unit" may refer to, be or include: an application specific integrated circuit (ASIC), an electronic circuit, a (shared, dedicated or group) processor and / or memory that executes one or more software or firmware programs, a combinational logic circuit and / or other suitable components that provide the described functionality.

[0125] In the accompanying drawings, some structural or method features are shown in a specific arrangement and / or order. However, it should be understood that such specific arrangement and / or ordering may not be required. In some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a specific figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0126] It should be understood that although the terms "first", "second", etc. may be used here to describe various units or data, these units or data should not be limited by these terms. These terms are used only to distinguish one feature from another. For example, without departing from the scope of the exemplary embodiment, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature.

[0127] It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0128] While the present invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. A method for measuring the loss of a test system in a finished radio frequency chip test, the test system comprising a test machine, a test circuit board connected to the test machine, and a socket arranged on the test circuit board, the socket being used to install a chip to electrically connect the chip to the test circuit board; The test system losses include: System output loss, the system output loss comprising: output contact loss between the output end of the socket and the output end of the test circuit board, and output path loss between the output end of the chip and the output end of the test circuit board; The test machine stores an initial output loss, wherein the initial output loss includes an initial output contact loss between the output end of the socket and the test circuit board and / or an initial output path loss between the output end of the chip and the output end of the test circuit board; Characterized in that the method comprises: Providing a standard chip, wherein the test items of the standard chip meet the test standards of the finished product test, and the standard chip has a standard test value; Inputting a radio frequency signal to the standard chip through the test machine, wherein the power of the input radio frequency signal is the sum of the lossless input power and the stored output loss; Measuring the output terminal of the test circuit board to obtain an output test value; Determine the test difference between the output test value and the standard test value, and make a judgment: When the test difference is within a set error range, determining the initial output loss as the system output loss; When the test difference exceeds a set error range, a first compensation deviation is applied to the stored output loss to obtain an adjusted output loss, and the steps of inputting a radio frequency signal, measuring an output test value, and determining a test difference are repeated until the test difference is within an error range, and the adjusted output loss is determined as the system output loss, wherein the adjusted output loss is the sum of the first compensation deviation and the stored output loss, and the stored output loss includes the initial output loss and the adjusted output loss.

2. The method according to claim 1, wherein the testing system loss further comprises: System input loss, the system input loss comprising: input path loss of the RF signal from the input end of the test circuit board to the input end of the chip, and input contact loss between the input end of the socket and the test circuit board; The test machine stores an initial input loss, wherein the initial input loss includes an initial input contact loss between the input end of the socket and the test circuit board and / or an initial input path loss between the input end of the test circuit board and the chip input end; Characterized in that the method further comprises: Obtaining a standard gain value of the standard chip; Test the output end of the chip to obtain the test output power P out1 The actual output power P is determined by the following formula: out2 :P out2 = System output loss + P out1 ; Get the input power P sent by the test machine in1 The actual input power P received by the standard chip is determined by the following formula in2 :P in2 =P in1 - Input loss of storage; Based on the actual output power and the actual input power, the test gain value N of the standard chip is determined by the following formula: N=P out2 -P in2 ; Determine the gain difference between the test gain value and the standard gain value, and make a judgment: When the gain difference is within a set error range, determining the initial input loss as the system input loss; When the gain difference exceeds the set error range, a second compensation deviation is applied to the stored input loss to obtain an adjusted input loss, and the steps of testing Pin2 and determining the gain value N are repeated until the gain difference is within the error range, and the adjusted input loss is determined as the system input loss, wherein the adjusted input loss is the sum of the second compensation deviation and the stored input loss, and the stored input loss includes the initial input loss and the adjusted input loss.

3. The method according to claim 1 or 2, characterized in that: The standard test value is one of a standard error vector amplitude value, a standard current, and a standard saturation power; The output test value is one of an output error vector amplitude value, an output current, and an output power.

4. The method according to claim 1 or 2, characterized in that: The adjustment includes one of an ergodic accumulation method, a binary search method, and a linear prediction method.

5. The method according to claim 2, characterized in that: Adjusting the initial output loss includes: adjusting the initial contact loss and / or the initial output path loss; or adjusting the sum of the initial contact loss and the initial output path loss; Adjusting the initial input loss includes: adjusting the initial contact loss and / or the initial input path loss; or The sum of the initial contact loss and the initial input path loss is adjusted.

6. The method according to claim 2, characterized in that Also includes: Setting a test difference form to record the initial output loss, the adjusted output loss, the output test value, and the test difference; and / or A gain difference form is set to record the initial input loss, the adjusted input loss, the test gain value, and the gain difference.

7. The method according to claim 3, characterized in that The testing machine comprises: A multimeter or a power meter or a power board, used to test the output current; The radio frequency test module is used to test the output error vector amplitude value and the output power.

8. The method according to claim 2, characterized in that: Get the input power P sent by the test machine in1 , the test output power P out1 and the actual output power P out2 It is stored when needed and can be called up when needed.

9. A finished product testing method for radio frequency chips, characterized in that: Measuring the test system loss using the method described in any one of claims 1 to 8; Based on the test system error, the power of the RF signal to be sent by the tester is adjusted to obtain a calibration RF signal for testing, where the power of the calibration RF signal is the power of the RF signal to be sent plus the test system loss.

10. An electronic device, characterized in that: The device comprises a memory storing computer executable instructions and a processor; when the instructions are executed by the processor, the device implements the method according to any one of claims 1 to 9.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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