Analog signal acquisition and processing circuit and method

Abstract

The invention belongs to the technical field of analog signal conversion, and particularly relates to an analog signal collecting and processing circuit and method. The analog signal receiving interface is provided with dozens of analog signal receiving end points for distributed parallel analog signal receiving. The data processing module is integrated with an ARM processor and an FPGA chip. Complex data processing and logic control tasks are executed through the data processing module, high-integration-level analog signal receiving is achieved, hardware design is structured, data receiving cost and power consumption are reduced, and data receiving accuracy is improved. Dozens of ports are designed for simultaneous receiving, and parallel processing is performed through the data processing module, so that conversion from analog signals to digital signals of a receiving end is realized, the real-time performance of time-sensitive change data processing is greatly improved, and meanwhile, through a method for performing step-by-step calibration on multi-channel analog signal data, the accuracy of calibration is greatly improved. Accurate calibration of analog signal information is achieved, and the precision and reliability of the analog signal collecting and processing circuit are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog signal reception, and in particular relates to an analog signal acquisition and processing circuit and method. Background Art

[0002] The analog signal acquisition and processing circuit is an electronic circuit used to measure and record analog signal information. It can convert analog signals on the surface of an object into electrical signals, and process and transmit them through digital circuits. The analog signal sensor is a core component that can physically sense analog signals in the environment and convert the sensed analog signals into electrical signals for output. These electrical signals are then converted into digital signals by analog-to-digital converters, and the internal processing chip further processes the digital signals and sends them to the host computer or controller.

[0003] However, due to the influence of environmental factors, the existing analog signal acquisition and processing circuit may cause the received analog signal value to be too high or too low when receiving analog signals in various environments, and the received analog signal value may also have a large error. In addition, the accuracy of the analog signal acquisition and processing circuit is limited by the hardware of the receiving module and the changes of the analog signal.

[0004] Therefore, how to improve the accuracy of the analog signal receiving results of the analog signal acquisition and processing circuit, reduce the errors existing in the analog signal receiving process, simplify the hardware structure design, and reduce the cost of the system is a technical problem that urgently needs to be solved. Summary of the invention

[0005] The purpose of the present invention is to provide an analog signal acquisition and processing circuit to improve the accuracy of the analog signal receiving result of the analog signal acquisition and processing circuit, reduce the error existing in the analog signal receiving process, simplify the hardware structure design, and reduce the cost of the system.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is as follows: In a first aspect, an analog signal acquisition and processing circuit is provided, comprising a power module, a storage module, a communication module, an analog signal receiving interface and a data processing module; the power module, the storage module, the communication module and the analog signal receiving interface are all connected to the data processing module; The analog signal receiving interface is provided with dozens or hundreds of analog signal receiving endpoints for distributed parallel analog signal reception, and the data processing module is integrated with an ARM processor and an FPGA chip; The power supply module is used to provide working voltage to the analog signal acquisition and processing circuit; The analog signal receiving interface is used to receive the analog signal collected by the sensor; The data processing module is used to perform local parallel processing on the analog signals received by each analog signal receiving interface and convert them into digital signals; The storage module is used to store the received analog signal, the digital signal converted from the analog signal, and the processing program; The communication module is used to transmit the received analog signal to the data processing module and to transmit the converted digital signal to a remote end.

[0007] Preferably, the analog signal receiving interface is used to receive temperature analog signals, voltage analog signals, current analog signals, pressure analog signals, flow analog signals, liquid analog signals, vibration analog signals, displacement analog signals, speed analog signals and angle analog signals.

[0008] Preferably, the analog signal receiving interface is provided with N channels, the N channels are tens or hundreds of channels, and each endpoint is connected to a sensor chip, the N channels of the analog signal receiving interface are respectively connected to the FORCE21, FORCE-P1 ports of the first sensor chip through the first interface FORCE2 1, FORCE_P1, the second interface FORCE2 2, FORCE_P2 is connected to the FORCE22, FORCE_P2 ports of the second sensor chip, the third interface FORCE2 3, FORCE_P3 is connected to the FORCE23, FORCE_P3 ports of the first sensor chip, and so on, the Nth interface FORCE2 N, FORCE_PN is connected to the FORCE2N, FORCE_PN ports of the Nth sensor chip; The analog signal receiving interface also includes an 855 capacitor, an 854 capacitor, and a 418 resistor. The RTDIN+ and RTDIN- ports of the sensor chip are connected through the 855 capacitor, BIAS, REFIN- and REFIN-, and ISENSOR are connected through the 418 resistor, and the VDD and DVDD ports are grounded through the 854 capacitor.

[0009] Preferably, the storage module includes a storage chip, and the / CS port, DO port, / WP port, HOLD port, CLK port and DI port of the storage chip are respectively connected to the QSPI_CS port, QSPI_DAT1 port, QSPI_DAT2 port, QSPI_DAT3 port, QSPI_CLK port and QSPI_DAT0 port of the data processing module.

[0010] Preferably, the storage module is externally equipped with N' DDR storage chips used as program cache, and N' is a positive integer greater than or equal to 1.

[0011] Preferably, the communication module includes a communication chip and an Ethernet communication interface, the communication chip is connected to the data processing module, and the communication chip is connected to the Ethernet communication interface for transmitting analog signal information and receiving remote control commands; The communication chip includes a 381 resistor, a 382 resistor, a 383 resistor, a 391 resistor, a 392 resistor, a 393 resistor, a 394 resistor, a 395 resistor, a 396 resistor, a 397 resistor, a 398 resistor, a 399 resistor, a 400 resistor, a 401 resistor, a 402 resistor, a 18th diode, and a 24th diode; The SCSN port, INTN port, RSTN port, SPDLED port, DUPLED port, PMODE0 port, PMODE1 port, PMODE2 port, RSVD1 port, RSVD2 port, RSVD3 port, RSVD4 port, and RSVD5 port of the communication chip are respectively connected to the 381 resistor, the 382 resistor, the 383 resistor, the 18th diode, the 24th diode, the 393rd resistor, the 394th resistor, the 395th resistor, the 397th resistor, the 398th resistor, the 399th resistor, the 400th resistor, the 401st resistor, and the 402nd resistor, and the 18th diode and the 24th diode are respectively connected to the 391st resistor and the 392nd resistor.

[0012] Preferably, the power supply module includes a first power supply conversion module, a second power supply conversion module, a third power supply conversion module, a fourth power supply conversion module and a fifth power supply conversion module; The first power conversion module is used to realize the conversion from 24V voltage to 5V voltage, including a first conversion chip, a 939th capacitor, an 842nd capacitor, a 938th capacitor, an 847th capacitor, a 940th capacitor, a 941st capacitor, a 364th resistor, a 365th resistor, a 366th resistor, a 402nd resistor, and an inductor; The 939th capacitor, the 842nd capacitor, and the 938th capacitor are connected in parallel with each other, one end of which is connected to the 24V voltage output terminal, and the other end is connected to the VIN port of the first conversion chip, the ON#OFF port of the first conversion chip is connected to the 364th resistor, and the VOUT port of the first conversion chip is connected to the 365th resistor, the 366th resistor, and the 402nd resistor in series through an inductor, and the inductor is respectively connected to the 847th capacitor, the 940th capacitor, and the 941st capacitor and then grounded.

[0013] Preferably, the second power conversion module is used to realize the conversion from 5V voltage to 1V voltage, and includes a second conversion chip, a 461st resistor, a 464th resistor, a 465th resistor, a 942nd capacitor, a 943rd capacitor, a 945th capacitor, and a 944th capacitor; One end of the 942nd capacitor is grounded, and the other ends are respectively connected to a 5V voltage, a VIN port of the second conversion chip and a 461st resistor, the 461st resistor is connected to an EN port of the second conversion chip, and the SS port of the second conversion chip is grounded through a 943rd capacitor; The VOUT port of the second conversion chip is respectively connected to the 464th resistor and the 945th capacitor. After the 945th capacitor and the 944th capacitor are connected in parallel, one end is connected to the 1V voltage output end and the other end is grounded; the 464th resistor and the 465th resistor are connected to the ADJ port of the second conversion chip and are grounded.

[0014] Preferably, the electronic components and connection relationships of the third power conversion module, the fourth power conversion module and the fifth power conversion module are the same as those of the second power conversion module.

[0015] It also includes a display module, which is connected to the data processing module and is used to display the measured real-time analog signal information and perform parameter configuration through the visual interface of the display module.

[0016] In a second aspect, a method for collecting and processing analog signals is provided, comprising the following steps: S1: N analog signal collection ports simultaneously receive analog signals transmitted by sensors and add receiving tags; S2: Each analog signal collection port synchronously and in parallel transmits the received analog signals to the data processing module, and the data processing module synchronously and in parallel processes the acquired analog signals locally and converts them into digital signals; S3: Built-in monitoring algorithm for the device or object being processed, and handle abnormal conditions of the device or object being monitored in real time; S4: storing the converted digital signal in the storage module and transmitting it synchronously and in parallel to the remote digital platform for digital construction; S5: The communication interface of the communication module receives instructions from the remote digital platform and controls or intervenes in the received monitoring equipment or objects; Before the conversion of each analog signal in step S2, the data processing module performs synchronous parallel calibration processing on each received analog signal using a preset calibration coefficient.

[0017] Preferably, step S2 also includes the following steps: S21: The data processing module calibrates the first channel digital signal information using the converted second channel digital signal information; S22: the data processing module uses the converted third-channel digital signal information to perform a second-level calibration on the first-channel digital signal information after the first-level calibration; S23: the data processing module uses the converted fourth-channel digital signal information to perform a third-level calibration on the first-channel digital signal information after the second-level calibration; S24: Similarly, the last channel of converted digital signal information is used to perform the last level of calibration on the digital signal information after the previous calibration; S25: Acquire the last calibrated digital signal information as the current digital signal information, and display the digital signal information through the display module.

[0018] The data processing module pre-stores the digital signal information calibration coefficients for each level, and during the calibration of the digital signal information for each level, the digital signal information calibration coefficients for the corresponding level are used for calibration.

[0019] The beneficial effects of the present invention include: The analog signal acquisition and processing circuit provided by the present invention includes a power module, a storage module, a communication module, an analog signal receiving interface and a data processing module. The analog signal receiving interface is provided with dozens of analog signal receiving endpoints for distributed parallel analog signal reception. The data processing module integrates an ARM processor and an FPGA chip. The data processing module performs complex data processing and logic control tasks to achieve highly integrated analog signal reception, structured hardware design, reduce data reception costs and power consumption, and improve data reception accuracy. By designing dozens of ports for simultaneous reception and performing parallel processing through the data processing module, the conversion of analog signals at the receiving end to digital signals is achieved, which greatly improves the real-time processing of time-sensitive changing data. At the same time, by performing step-by-step calibration of multi-channel analog signal data, accurate calibration of analog signal information is achieved, and the accuracy and reliability of the analog signal acquisition and processing circuit are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention is a schematic diagram of the circuit structure of the first analog signal receiving interface of the analog signal acquisition and processing circuit.

[0021] Figure 2 The present invention is a schematic diagram of the circuit structure of the second analog signal receiving interface of the analog signal acquisition and processing circuit.

[0022] Figure 3 The present invention is a schematic diagram of the circuit structure of the communication module of the analog signal acquisition and processing circuit.

[0023] Figure 4 The schematic diagram of the circuit structure of the first power conversion module of the analog signal acquisition and processing circuit of the present invention is shown in FIG.

[0024] Figure 5 The schematic diagram of the circuit structure of the second power conversion module of the analog signal acquisition and processing circuit of the present invention. Figure 6 The schematic diagram of the circuit structure of the second power conversion module of the analog signal acquisition and processing circuit of the present invention. DETAILED DESCRIPTION

[0025] The following is combined with Figure 1 to Figure 6 The present invention is further described in detail: Example 1 An analog signal acquisition and processing circuit comprises a power module, a storage module, a communication module, an analog signal receiving interface and a data processing module; the power module, the storage module, the communication module and the analog signal receiving interface are all connected to the data processing module.

[0026] The analog signal receiving interface is provided with dozens or hundreds of analog signal receiving endpoints for distributed parallel analog signal reception, and the data processing module integrates an ARM processor and an FPGA chip; the power supply module is used to provide working voltage to the analog signal acquisition and processing circuit; the analog signal receiving interface is used to receive analog signals collected by sensors; the data processing module is used to perform local parallel processing on the analog signals received by each analog signal receiving interface and convert them into digital signals; the storage module is used to store the received analog signals, the digital signals converted from the analog signals, and the processing program; the communication module is used to transmit the received analog signals to the data processing module and transmit the converted digital signals to the remote end.

[0027] The analog signal receiving interface is used to receive temperature analog signals, voltage analog signals, current analog signals, pressure analog signals, flow analog signals, liquid analog signals, vibration analog signals, displacement analog signals, speed analog signals and angle analog signals.

[0028] The data processing module integrates an ARM processor and an FPGA chip to perform complex data processing and logic control tasks on the same module, thereby realizing a highly integrated analog signal receiving system. In addition, distributed parallel analog signal reception is performed through dozens of channels, and the analog signals received on each channel are processed simultaneously, which greatly improves the real-time performance of data processing. It is particularly suitable for analog signal reception in application scenarios where analog signals are time-sensitive. The number of analog signal collection ports can be adjusted as needed, and the number of channels, data processing algorithms, and communication protocols and other parameters are set in the display module, thereby improving the flexibility and scalability of the analog signal acquisition and processing circuit. There is no need to change the hardware when adding new functions in the future, thereby improving the overall performance.

[0029] The communication module also integrates a data encryption transmission module and a remote monitoring module, which increases the security of the system and makes it more adaptable. Example 2 Based on Example 1, see Figure 1 and Figure 2 The analog signal receiving interface is provided with N channels, wherein the N channels are dozens or hundreds of channels, and each endpoint is connected to a sensor chip. The N channels of the analog signal receiving interface are respectively connected to the FORCE21, FORCE-P1 ports of the first sensor chip through the first interface FORCE2 1, FORCE_P1, the second interface FORCE2 2, FORCE_P2 is connected to the FORCE22, FORCE_P2 ports of the second sensor chip, the third interface FORCE2 3, FORCE_P3 is connected to the FORCE23, FORCE_P3 ports of the first sensor chip, and so on. The Nth interface FORCE2 N, FORCE_PN is connected to the FORCE2N, FORCE_PN ports of the Nth sensor chip.

[0030] The analog signal receiving interface also includes an 855 capacitor, an 854 capacitor, and a 418 resistor. The RTDIN+ and RTDIN- ports of the sensor chip are connected through the 855 capacitor, BIAS, REFIN- and REFIN-, ISENSOR are connected through the 418 resistor, and the VDD and DVDD ports are grounded through the 854 capacitor. The analog signal receiving interface is convenient and fast as an analog signal endpoint connection interface, and supports hot swapping and plug-and-play.

[0031] The analog signal receiving interface is an SPI interface extended from the FPGA chip, which can realize 2-wire, 3-wire, and 4-wire PT100 / PT1000 measurements. Users can also connect endpoints of different quantities and performances according to actual needs on site.

[0032] See also Figure 3 The storage module includes a storage chip, and the / CS port, DO port, / WP port, HOLD port, CLK port, and DI port of the storage chip are respectively connected to the QSPI_CS port, QSPI_DAT1 port, QSPI_DAT2 port, QSPI_DAT3 port, QSPI_CLK port, and QSPI_DAT0 port of the data processing module. The storage module is externally mounted with N' pieces of DDR storage chips as program cache, and N' is a positive integer greater than or equal to 1.

[0033] On the one hand, the storage module is used to store the startup program, data processing program and analog signal reception information during the analog signal reception process.

[0034] The communication module includes a communication chip and an Ethernet communication interface. The communication chip is connected to the data processing module. The communication chip is connected to the Ethernet communication interface and is used to transmit analog signal information and receive remote control commands.

[0035] The communication chip includes a 381 resistor, a 382 resistor, a 383 resistor, a 391 resistor, a 392 resistor, a 393 resistor, a 394 resistor, a 395 resistor, a 396 resistor, a 397 resistor, a 398 resistor, a 399 resistor, a 400 resistor, a 401 resistor, a 402 resistor, a 18th diode, and a 24th diode; The SCSN port, INTN port, RSTN port, SPDLED port, DUPLED port, PMODE0 port, PMODE1 port, PMODE2 port, RSVD1 port, RSVD2 port, RSVD3 port, RSVD4 port, and RSVD5 port of the communication chip are respectively connected to the 381 resistor, the 382 resistor, the 383 resistor, the 18th diode, the 24th diode, the 393rd resistor, the 394th resistor, the 395th resistor, the 397th resistor, the 398th resistor, the 399th resistor, the 400th resistor, the 401st resistor, and the 402nd resistor, and the 18th diode and the 24th diode are respectively connected to the 391st resistor and the 392nd resistor. Using FPGA to expand one SPI interface is used to expand one 100M network, which is used to upload analog signal information and receive remote control commands.

[0036] Example 3 Based on Example 1 or Example 2, see Figure 5 , the power module includes a first power conversion module, a second power conversion module, a third power conversion module, a fourth power conversion module and a fifth power conversion module.

[0037] The first power conversion module is used to realize the conversion from 24V voltage to 5V voltage, and includes a first conversion chip, a No. 939 capacitor, a No. 842 capacitor, a No. 938 capacitor, a No. 847 capacitor, a No. 940 capacitor, a No. 941 capacitor, a No. 364 resistor, a No. 365 resistor, a No. 366 resistor, a No. 402 resistor, and an inductor.

[0038] The 939th capacitor, the 842nd capacitor, and the 938th capacitor are connected in parallel with each other, one end of which is connected to the 24V voltage output terminal, and the other end is connected to the VIN port of the first conversion chip, the ON#OFF port of the first conversion chip is connected to the 364th resistor, and the VOUT port of the first conversion chip is connected to the 365th resistor, the 366th resistor, and the 402nd resistor in series through an inductor, and the inductor is respectively connected to the 847th capacitor, the 940th capacitor, and the 941st capacitor and then grounded.

[0039] The second power conversion module is used to realize the conversion from 5V voltage to 1V voltage, and includes a second conversion chip, a 461st resistor, a 464th resistor, a 465th resistor, a 942nd capacitor, a 943rd capacitor, a 945th capacitor, and a 944th capacitor.

[0040] One end of the 942nd capacitor is grounded, and the other end is respectively connected to a 5V voltage, the VIN port of the second conversion chip and the 461st resistor. The 461st resistor is connected to the EN port of the second conversion chip, and the SS port of the second conversion chip is grounded through the 943rd capacitor.

[0041] The VOUT port of the second conversion chip is respectively connected to the 464th resistor and the 945th capacitor. After the 945th capacitor and the 944th capacitor are connected in parallel, one end is connected to the 1V voltage output end and the other end is grounded; the 464th resistor and the 465th resistor are connected to the ADJ port of the second conversion chip and are grounded.

[0042] The electronic components and connection relationships of the third power conversion module, the fourth power conversion module and the fifth power conversion module are the same as those of the second power conversion module.

[0043] The voltage input of the overall circuit of the analog signal acquisition and processing circuit is 24V, but different modules require different voltages for normal operation. Therefore, multiple voltage conversion modules are provided in the power supply module to supply each module with a suitable voltage.

[0044] The analog signal acquisition and processing circuit also includes a display module, which is connected to the data processing module and is used to display the measured real-time analog signal information and perform parameter configuration through a visual interface of the display module.

[0045] A method for collecting and processing analog signals comprises the following steps: S1: N analog signal collection ports simultaneously receive analog signals transmitted by sensors and add receiving tags; S2: Each analog signal collection port synchronously and in parallel transmits the received analog signal to the data processing module. The data processing module synchronously and in parallel processes the acquired analog signals locally and converts them into digital signals, which can greatly simplify the transmission line of the analog signal and greatly reduce the hardware cost. In addition, since there is no need for long-distance analog signal transmission, there is almost no transmission loss of the analog signal, which effectively improves the accuracy of the final receiving result. S3: Built-in monitoring algorithm for the device or object being processed, and handle abnormal conditions of the device or object being monitored in real time; S4: storing the converted digital signal in the storage module and transmitting it synchronously and in parallel to the remote digital platform for digital construction; S5: The communication interface of the communication module receives instructions from the remote digital platform to control or intervene in the received monitoring equipment or objects Before the conversion of each analog signal in step S2, the data processing module performs synchronous and parallel calibration processing on each received analog signal using a preset calibration coefficient.

[0046] In the above scheme, the data processing module presets the normal operating status data of the monitored equipment or object, and compares it with the analog signal collected and transmitted by the monitored equipment or object in real time. When it is detected that the monitored equipment or object exceeds the set safety status range, the data processing module uploads instructions to the remote digital platform through the communication module to shut down the monitored equipment or object for protection, push alarm information, etc.

[0047] Wherein, step S2 also includes the following steps: S21: The data processing module calibrates the first channel digital signal information using the converted second channel digital signal information; S22: the data processing module uses the converted third-channel digital signal information to perform a second-level calibration on the first-channel digital signal information after the first-level calibration; S23: the data processing module uses the converted fourth-channel digital signal information to perform a third-level calibration on the first-channel digital signal information after the second-level calibration; S24: Similarly, the last channel of converted digital signal information is used to perform the last level of calibration on the digital signal information after the previous calibration; S25: Acquire the last calibrated digital signal information as the current digital signal information, and display the digital signal information through the display module.

[0048] The data processing module pre-stores the digital signal information calibration coefficients for each level, and during the calibration of the digital signal information for each level, the digital signal information calibration coefficients for the corresponding level are used for calibration.

[0049] In another embodiment, the analog calibration coefficient can be preset in the data processing module of the analog signal acquisition and processing circuit. The built-in processing module samples the power supply and compares the analog signal of the calibration processing module in real time to convert it into a digital signal coefficient to ensure the accuracy of the conversion.

[0050] In summary, the analog signal acquisition and processing circuit provided by the present invention performs complex data processing and logic control tasks through the data processing module, realizes high-integration analog signal reception, and synchronously receives the analog signals collected by the sensor through dozens or hundreds of ports; the data processing module processes them in parallel into digital signals; the data processing module has built-in conversion and state algorithms for the monitored acquisition equipment or objects; the converted data is synchronously stored and transmitted to the digital platform through the communication module for digital construction and receiving instructions sent back by the digital platform, which is used for real-time intervention in the operating status of the monitored acquisition equipment or objects, such as safety. This system can be directly arranged on the equipment or objects that the sensor needs to collect and monitor, and receives the analog signals of the acquisition equipment or object status nearby and processes them in parallel to convert them into unattenuated digital signals, avoiding signal attenuation during the transmission of analog signals, ensuring the accuracy and real-time performance of the acquired equipment or object signals, and providing a reliable guarantee for the digital construction platform to provide accurate equipment or object status data.

Claims

1. An analog signal acquisition and processing circuit, characterized in that: It includes a power module, a storage module, a communication module, an analog signal receiving interface and a data processing module; the power module, the storage module, the communication module and the analog signal receiving interface are all connected to the data processing module; The analog signal receiving interface is provided with dozens or hundreds of analog signal receiving endpoints for distributed parallel analog signal reception, and the data processing module is integrated with an ARM processor and an FPGA chip; The power supply module is used to provide working voltage to the analog signal acquisition and processing circuit; The analog signal receiving interface is used to receive the analog signal collected by the sensor; The data processing module is used to perform local parallel processing on the analog signals received by each analog signal receiving interface and convert them into digital signals; The storage module is used to store the received analog signal, the digital signal converted from the analog signal, and the processing program; The communication module is used to transmit the received analog signal to the data processing module and to transmit the converted digital signal to a remote end.

2. The analog signal acquisition and processing circuit according to claim 1, characterized in that: The analog signal receiving interface is used to receive temperature analog signals, voltage analog signals, current analog signals, pressure analog signals, flow analog signals, liquid analog signals, vibration analog signals, displacement analog signals, speed analog signals and angle analog signals.

3. The analog signal acquisition and processing circuit according to claim 1, characterized in that: The analog signal receiving interface is provided with N channels, the N channels are tens or hundreds of channels, and each endpoint is connected to a sensor chip, the N channels of the analog signal receiving interface are respectively connected to the FORCE2 1, FORCE-P1 ports of the first sensor chip through the first interface FORCE2 1, FORCE_P1, the second interface FORCE2 2, FORCE_P2 is connected to the FORCE22, FORCE_P2 ports of the second sensor chip, the third interface FORCE2 3, FORCE_P3 is connected to the FORCE2 3, FORCE_P3 ports of the first sensor chip, and so on, the Nth interface FORCE2 N, FORCE_PN is connected to the FORCE2 N, FORCE_PN ports of the Nth sensor chip; The analog signal receiving interface also includes an 855 capacitor, an 854 capacitor, and a 418 resistor. The RTDIN+ and RTDIN- ports of the sensor chip are connected through the 855 capacitor, BIAS, REFIN- and REFIN-, and ISENSOR are connected through the 418 resistor, and the VDD and DVDD ports are grounded through the 854 capacitor.

4. The analog signal acquisition and processing circuit according to claim 1, characterized in that: The storage module includes a storage chip, and the / CS port, DO port, / WP port, HOLD port, CLK port, and DI port of the storage chip are respectively connected to the QSPI_CS port, QSPI_DAT1 port, QSPI_DAT2 port, QSPI_DAT3 port, QSPI_CLK port, and QSPI_DAT0 port of the data processing module.

5. The analog signal acquisition and processing circuit according to claim 4, characterized in that: The storage module is externally mounted with N' pieces of DDR storage chips used as program cache, wherein N' is a positive integer greater than or equal to 1.

6. The analog signal acquisition and processing circuit according to claim 1, characterized in that: The communication module includes a communication chip and an Ethernet communication interface, the communication chip is connected to the data processing module, and the communication chip is connected to the Ethernet communication interface for transmitting analog signal information and receiving remote control commands; The communication chip includes a 381 resistor, a 382 resistor, a 383 resistor, a 391 resistor, a 392 resistor, a 393 resistor, a 394 resistor, a 395 resistor, a 396 resistor, a 397 resistor, a 398 resistor, a 399 resistor, a 400 resistor, a 401 resistor, a 402 resistor, a 18th diode, and a 24th diode; The SCSN port, INTN port, RSTN port, SPDLED port, DUPLED port, PMODE0 port, PMODE1 port, PMODE2 port, RSVD1 port, RSVD2 port, RSVD3 port, RSVD4 port, and RSVD5 port of the communication chip are respectively connected to the 381 resistor, the 382 resistor, the 383 resistor, the 18th diode, the 24th diode, the 393rd resistor, the 394th resistor, the 395th resistor, the 397th resistor, the 398th resistor, the 399th resistor, the 400th resistor, the 401st resistor, and the 402nd resistor, and the 18th diode and the 24th diode are respectively connected to the 391st resistor and the 392nd resistor.

7. The analog signal acquisition and processing circuit according to claim 1, characterized in that: The power module includes a first power conversion module, a second power conversion module, a third power conversion module, a fourth power conversion module and a fifth power conversion module, and the electronic components and connection relationship of the third power conversion module, the fourth power conversion module and the fifth power conversion module are the same as those of the second power conversion module; The first power conversion module is used to realize the conversion from 24V voltage to 5V voltage, including a first conversion chip, a 939th capacitor, an 842nd capacitor, a 938th capacitor, an 847th capacitor, a 940th capacitor, a 941st capacitor, a 364th resistor, a 365th resistor, a 366th resistor, a 402nd resistor, and an inductor; The 939th capacitor, the 842nd capacitor, and the 938th capacitor are connected in parallel with each other, one end of which is connected to the 24V voltage output terminal, and the other end is connected to the VIN port of the first conversion chip, the ON#OFF port of the first conversion chip is connected to the 364th resistor, and the VOUT port of the first conversion chip is connected to the 365th resistor, the 366th resistor, and the 402nd resistor in series through an inductor, and the inductor is respectively connected to the 847th capacitor, the 940th capacitor, and the 941st capacitor and then grounded.

8. The analog signal acquisition and processing circuit according to claim 7, characterized in that: The second power conversion module is used to realize the conversion from 5V voltage to 1V voltage, including a second conversion chip, a 461st resistor, a 464th resistor, a 465th resistor, a 942nd capacitor, a 943rd capacitor, a 945th capacitor, and a 944th capacitor; One end of the 942nd capacitor is grounded, and the other ends are respectively connected to a 5V voltage, a VIN port of the second conversion chip and a 461st resistor, the 461st resistor is connected to an EN port of the second conversion chip, and the SS port of the second conversion chip is grounded through a 943rd capacitor; The VOUT port of the second conversion chip is respectively connected to the 464th resistor and the 945th capacitor. After the 945th capacitor and the 944th capacitor are connected in parallel, one end is connected to the 1V voltage output end and the other end is grounded; the 464th resistor and the 465th resistor are connected to the ADJ port of the second conversion chip and are grounded.

9. A method for collecting and processing analog signals, characterized in that: An analog signal acquisition and processing circuit according to any one of claims 1 to 8, comprising the following steps: S1: N analog signal collection ports simultaneously receive analog signals transmitted by sensors and add receiving tags; S2: Each analog signal collection port synchronously and in parallel transmits the received analog signals to the data processing module, and the data processing module synchronously and in parallel processes the acquired analog signals locally and converts them into digital signals; S3: Built-in monitoring algorithm for the device or object being processed, and handle abnormal conditions of the device or object being monitored in real time; S4: storing the converted digital signal in the storage module and transmitting it synchronously and in parallel to the remote digital platform for digital construction; S5: The communication interface of the communication module receives instructions from the remote digital platform and controls or intervenes in the received monitoring equipment or objects; Before the conversion of each analog signal in step S2, the data processing module performs synchronous parallel calibration processing on each received analog signal using a preset calibration coefficient.

10. The analog signal acquisition and processing method according to claim 9, characterized in that: Step S2 also includes the following steps: S21: The data processing module calibrates the first channel digital signal information using the converted second channel digital signal information; S22: the data processing module uses the converted third-channel digital signal information to perform a second-level calibration on the first-channel digital signal information after the first-level calibration; S23: the data processing module uses the converted fourth-channel digital signal information to perform a third-level calibration on the first-channel digital signal information after the second-level calibration; S24: Similarly, the last channel of converted digital signal information is used to perform the last level of calibration on the digital signal information after the previous calibration; S25: Acquire the last calibrated digital signal information as the current digital signal information, and display the digital signal information through the display module. The data processing module pre-stores the digital signal information calibration coefficients for each level, and during the calibration of the digital signal information for each level, the digital signal information calibration coefficients for the corresponding level are used for calibration.

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