PCIe forking method and device

Abstract

The invention provides a PCIe bifurcation method and device, and the method comprises the steps: carrying out the bifurcation mapping convergence of a to-be-processed signal of which the conversion type is from a channel to a port, carrying out the channel overturning or channel degradation in the port, and outputting the to-be-processed signal; for a to-be-processed signal of which the conversion type is a port-to-channel separation type, after channel overturning or channel degradation is carried out in the port to which the to-be-processed signal belongs, the to-be-processed signal is subjected to bifurcation mapping splitting and then is output to the corresponding channel; and copying the to-be-processed signal of which the conversion type is a port-to-channel copy type according to the number of channels supported by the port, and outputting the to-be-processed signal to the corresponding channel after the to-be-processed signal is subjected to bifurcation mapping splitting. According to the technical scheme, Lane logic resources can be reused to the maximum extent, interaction signals between multiple Ports and multiple Lanes can be flexibly self-defined, classification and batch processing of the interaction signals between the multiple Ports and the multiple Lanes are supported, and codes are automatically generated.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a PCIe bifurcation method and device. Background Art

[0002] PCI Express (Peripheral Component Interconnect Express), referred to as PCIe, is a high-speed, serial, full-duplex, computer expansion bus standard that uses a high-speed differential bus and a point-to-point connection for communication between two devices. Multiple PCI Express devices are interconnected by using a switch, so a large number of devices can be connected together in one system. PCIe Bifurcation is a function that divides data channels in a PCIe slot. Summary of the invention

[0003] The purpose of this application is to provide a PCIe bifurcation method and device, aiming to solve the problems that the existing PCIe bifurcation technology requires customized special development and design, resulting in a long chip development cycle and difficulty in verification convergence.

[0004] According to a first aspect of the present application, a PCIe bifurcation method is provided, comprising:

[0005] For the signals to be processed whose conversion type is channel to port, after forking mapping and convergence, the channels are flipped or downgraded inside the corresponding ports before being output;

[0006] For the signal to be processed whose conversion type is port-to-channel separation type, after performing channel flipping or channel degradation inside the corresponding port, it is split through bifurcation mapping and output to the corresponding channel;

[0007] For the signal to be processed whose conversion type is the port-to-channel copy type, it is copied according to the number of channels supported by the port to which it belongs, and is output to the corresponding channel after being split by fork mapping.

[0008] In an optional implementation, the method further includes:

[0009] A convergence module pre-designed for forked mapping convergence, and a degradation flip module pre-designed for channel flipping or channel degradation;

[0010] The signal to be processed whose conversion type is channel to port is output after being forked, mapped and converged, and then channel flipped or downgraded inside the corresponding port, including:

[0011] Instantiate the convergence module, and connect the internal signals of the instantiated convergence module according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping convergence of the received signal to be processed;

[0012] According to the maximum number of ports supported, the downgrade flip module is instantiated, and the internal signal of the instantiated downgrade flip module is connected to realize channel flipping or channel downgrade of the to-be-processed signal after the forked mapping convergence within the port.

[0013] In an optional embodiment, the method further comprises:

[0014] A split module is pre-designed to split the fork mapping according to the fork mode, and a downgrade flip module is pre-designed to perform channel flipping or channel downgrading;

[0015] For the signal to be processed whose conversion type is a port-to-channel separation type, after performing channel flipping or channel degradation inside the corresponding port, the signal is output to the corresponding channel after splitting through bifurcation mapping, including:

[0016] Instantiate the downgrade flip module according to the maximum number of ports supported, and connect the internal signal of the instantiated downgrade flip module to implement channel flipping or channel downgrade of the received signal to be processed inside the port;

[0017] The splitting module is instantiated, and the internal signals of the instantiated splitting module are connected according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping splitting of the signal to be processed with channel flipping or channel degradation.

[0018] In an optional embodiment, the method further comprises:

[0019] A splitting module is pre-designed to split the bifurcation map according to the bifurcation pattern, and a replication module is pre-designed to replicate the signal;

[0020] For the signal to be processed whose conversion type is a port-to-channel replication type, the signal is replicated according to the number of channels supported by the corresponding port, and is output to the corresponding channel after being split by fork mapping, including:

[0021] Instantiating the replication module according to the maximum number of ports supported, and connecting internal signals of the instantiated replication module to implement replication of the received signal to be processed;

[0022] The splitting module is instantiated, and the internal signals of the instantiated splitting module are connected according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping splitting of the copied signal to be processed.

[0023] In an optional embodiment, the method further comprises:

[0024] Obtain configuration information of the PCIe bifurcation system; wherein the configuration information includes: the conversion type of the signal to be processed, the bifurcation mode of the signal to be processed, the width of the signal to be processed, the maximum number of channels supported, the maximum number of ports supported, and the number of channels supported by each port; wherein the number of bifurcation mapping splits is equal to the maximum number of channels supported.

[0025] According to a second aspect of the present application, a PCIe bifurcation device is provided, comprising:

[0026] The channel-to-port conversion module is configured to perform channel flipping or channel degradation inside the corresponding port and then output the to-be-processed signal whose conversion type is channel-to-port after forking mapping and convergence;

[0027] The first port-to-channel conversion module is configured to perform channel flipping or channel degradation inside the corresponding port for a signal to be processed whose conversion type is a port-to-channel separation type, and then output the signal to the corresponding channel after splitting through bifurcation mapping;

[0028] The second port-to-channel conversion module is configured to copy the to-be-processed signal of the port-to-channel copy type according to the number of channels supported by the corresponding port, and output it to the corresponding channel after splitting through fork mapping.

[0029] In an optional embodiment, the device further comprises:

[0030] A first design module is configured as a convergence module for pre-designing forked mapping convergence, and a degradation flip module for pre-designing channel flipping or channel degradation;

[0031] The channel-to-port conversion module is implemented as follows:

[0032] Instantiate the convergence module, and connect the internal signals of the instantiated convergence module according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping convergence of the received signal to be processed;

[0033] According to the maximum number of ports supported, the downgrade flip module is instantiated, and the internal signal of the instantiated downgrade flip module is connected to realize channel flipping or channel downgrade of the to-be-processed signal after the forked mapping convergence within the port.

[0034] In an optional embodiment, the device further comprises:

[0035] The second design module is configured to pre-design a splitting module for splitting a bifurcation map according to a bifurcation mode, and a downgrade flipping module for pre-designing channel flipping or channel downgrade;

[0036] The first port to channel conversion module is implemented as follows:

[0037] Instantiate the downgrade flip module according to the maximum number of ports supported, and connect the internal signal of the instantiated downgrade flip module to implement channel flipping or channel downgrade of the received signal to be processed inside the port;

[0038] The splitting module is instantiated, and the internal signals of the instantiated splitting module are connected according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping splitting of the signal to be processed with channel flipping or channel degradation.

[0039] In an optional embodiment, the device further comprises:

[0040] A third design module is configured to pre-design a splitting module for splitting a bifurcation map according to a bifurcation pattern, and a replication module for replicating a signal;

[0041] The second port-to-channel conversion module is implemented as follows:

[0042] Instantiating the replication module according to the maximum number of ports supported, and connecting internal signals of the instantiated replication module to implement replication of the received signal to be processed;

[0043] The splitting module is instantiated, and the internal signals of the instantiated splitting module are connected according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping splitting of the copied signal to be processed.

[0044] In an optional embodiment, the device further comprises:

[0045] An acquisition module is configured to acquire configuration information of a PCIe bifurcation system; wherein the configuration information includes: a conversion type of the signal to be processed, a bifurcation mode of the signal to be processed, a width of the signal to be processed, a maximum number of channels supported, a maximum number of ports supported, and a number of channels supported by each port; wherein the number of bifurcation mapping splits is equal to the maximum number of channels supported.

[0046] Compared with the related art, the technical solution of this application has the following advantages:

[0047] This application solves the problem that the traditional PCIe multi-port controller design requires special customized development of Bifurcation function logic, which prolongs the chip development cycle and increases the difficulty of verification convergence. It can maximize the reuse of Lane logic resources, support flexible customization of interaction signals between multiple ports and multiple lanes, support classification batch processing (standardization, scalability, accuracy) of interaction signals between multiple ports and multiple lanes, automatically generate code, and support flexible configuration of the mapping relationship between multiple ports and multiple lanes to meet various needs. The code has strong maintainability and scalability, and can shorten the code delivery cycle by about 2 to 3 weeks. If frequent changes and iterations are required, the effect is more significant, greatly reducing the amount of interaction signals, reducing the difficulty and cycle of timing convergence, reducing the difficulty of verification coverage convergence, and shortening product development time.

[0048] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 The figure is an example effect diagram of the working of a 16-channel PCIe device under different Bifurcation configurations according to the related art.

[0051] Figure 2 It is a schematic diagram of the PCIe Bifurcation structure with 16 channels designed based on relevant technologies.

[0052] Figure 3 It is a schematic diagram of the MAC layer sending and receiving structure according to an exemplary embodiment of the present application.

[0053] Figure 4 It is a flowchart of a PCIe bifurcation method according to an exemplary embodiment of the present application.

[0054] Figure 5A It is a schematic diagram of the RTL automatic generation process according to an exemplary embodiment of the present application.

[0055] Figure 5B-5Dis a schematic diagram of bifurcation patterns of signals to be processed according to different conversion types according to an exemplary embodiment of the present application.

[0056] Figure 6 It is a schematic diagram of the code structure of automatically generating RTL according to an exemplary embodiment of the present application.

[0057] Figure 7 4 is a schematic diagram of the structure of a p2l_split unit for automatically generating RTL according to an exemplary embodiment of the present application.

[0058] Figure 8 It is a schematic diagram of the structure of a p2l_replication unit for automatically generating RTL according to an exemplary embodiment of the present application.

[0059] Fig. 9 It is a schematic diagram of the structure of an l2p unit for automatically generating RTL according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0061] With the rapid development of information technologies such as big data, the Internet of Things, and artificial intelligence, as well as the digital transformation of traditional industries, these trends have promoted the rapid development of PCIe chips. A PCIe link can be composed of multiple Lanes (physical channels). Usually, a PCIe link can support 1, 2, 4, 8, 12, 16, and 32 Lanes, that is, PCIe links with widths of x1, x2, x4, x8, x12, x16, and x32. However, due to the limited number of PCIe physical channels in the motherboard card slot, in order to meet the usage requirements of different users for multiple devices and multiple scenarios, the motherboard card slot can be flexibly configured through Bifurcation (fork), supporting multiple combinations or split PCIe channel modes to meet different usage scenarios. For example, a PCIe x16 slot can be configured as 2 PCIe x8 Lanes, or 4 PCIe x4 Lanes, or 8 PCIe x2 Lanes, or 16 PCIe x1 Lanes and other working modes. This bifurcation feature does not affect overall speed and allows a larger slot to be used independently like multiple smaller slots, eliminating the need for an additional PCIe bridge chip.

[0062] like Figure 1As shown in the figure, a 16-lane PCIe device can connect 1 x16, 2 x8, and 4 x4 PCIe devices to work independently in different Bifurcation configuration modes, where the PHY of these 16 lanes is shared. PHY is a module used by PCIe to connect the protocol layer and link, including all circuits related to port operations such as driver and phase-locked loop, serial-to-parallel, and parallel-to-serial.

[0063] Related technologies to implement the bifurcation functions of multiple PCIe controllers and multiple PHYs require customized special development and design, which lacks versatility and scalability, which will inevitably extend the chip development cycle and increase the difficulty of verification convergence.

[0064] Based on the above analysis, this application proposes a PCIe bifurcation method and device, which can maximize the reuse of Lane logic resources, accelerate verification coverage convergence, reduce the difficulty of mid- and back-end physical implementation, and shorten the chip development cycle.

[0065] like Figure 2 As shown in the figure, in the 16-lane PCIe Bifurcation structure designed in the related art, 1 x16, 2 x8 and 4 x4 PCIe controllers are instantiated, each outputting 16 lanes, a total of 48 lanes, and then 16 of the lanes are output through the MUX selection logic to connect to the peer device, thereby realizing the Bifurcation function. Although this design can realize the basic Bifurcation function, it has the following disadvantages and shortcomings:

[0066] 1. Lane logical resources cannot be reused, resulting in resource waste. Each Port (physical port) uses an exclusive PHY and cannot be shared.

[0067] 2. Bifurcation module (Bifurcation mode), the mapping relationship does not support flexible configuration and cannot meet various needs. It requires special MUX design each time, which increases the difficulty of development.

[0068] 3. The amount of interactive signals between multiple ports and multiple lanes is huge, and maintenance and processing are complex.

[0069] 4. Difficulty in timing convergence: Since the MUX selection logic needs to process a large number of signals and their types are not uniform, the combinational path is too long and the back-end wiring is more difficult.

[0070] 5. Poor maintainability and scalability: If the signal is increased or decreased later, the MUX selection logic needs to be modified again, which has a large scope of modification and is prone to errors and risks.

[0071] 6. Verification coverage is difficult: Each design change iteration requires additional targeted verification, which increases verification risk and convergence time.

[0072] like Figure 3 As shown, the PCIe bifurcation method and device exemplarily proposed in this application realizes the port to channel (Port to Lane) and channel to port (Lane to Port) conversion function of the entire MAC layer of PCIe. Among them, the conversion from port to channel is to output each signal in the Port to the corresponding physical channel through Bifurcation mode mapping processing, and the conversion from channel to port is to aggregate the signals of each physical channel into the data of each Port through Bifurcation mapping. The above port to channel (Port to Lane) and channel to port (Lane to Port) conversion units are all parameterized and support flexible configuration. In this application, after the relevant information of all signals to be processed can be entered into the configuration file, the corresponding PCIe bifurcation logic can be output with one click according to the configuration file.

[0073] like Figure 3 As shown, the present application exemplarily provides a structure for defining a Port and Lane interaction signal, but is not limited thereto, and the Port and Lane interaction signal can also be flexibly customized.

[0074] Figure 3 In the figure, N is the number of ports and M is the number of lanes. The design features are:

[0075] 1. Support any combination of Bifurcation configurations; that is, for N ports, each port can be converted to any of the M channels through the P2L_split unit, P2L_replication unit and L2P unit in the PCIe bifurcation device (Bifurcation in the figure).

[0076] 2. Maximize multiple lane reuse and save resources; Figure 3 The M channels in can be multiplexed by N ports.

[0077] 3. Classify and batch process interactive signals between multiple ports and multiple lanes to reduce the amount of interactive signals, reduce the difficulty of timing convergence, and achieve strong maintainability and scalability.

[0078] 4. Reduce the difficulty of verification coverage and shorten the convergence time.

[0079] The PCIe bifurcation method and device designed by the present application realize the P2L conversion and L2P conversion functions of the entire MAC layer. Among them, the P2L conversion is to first perform Lane flipping and Lane downgrading operations in the Port, and then output to the corresponding Lane through Bifurcation mode (bifurcation mode). L2P conversion is to first aggregate the signals of each Lane into the data of each Port through Bifurcation mapping, and then perform Lane flipping and Lane downgrading operations in each Port. In this way, corresponding processing is performed according to the interactive signal type, and Bifurcation RTL code is automatically generated.

[0080] For example, see Figure 4 As shown, a PCIe bifurcation method proposed in the present application includes:

[0081] In step S401, for a signal to be processed whose conversion type is channel to port, after forking mapping and convergence, the channel is flipped or downgraded inside the corresponding port and then output;

[0082] In step S402, for a signal to be processed whose conversion type is a port-to-channel separation type, after performing channel flipping or channel degradation inside the corresponding port, the signal is split through bifurcation mapping and then output to the corresponding channel;

[0083] In step S403, for the to-be-processed signal whose conversion type is the port-to-channel replication type, the signal is replicated according to the number of channels supported by the corresponding port, and is output to the corresponding channel after being split through fork mapping.

[0084] See also Figure 5A As shown, according to the PCIe MAC layer structure mentioned above, the signals to be processed are divided into two conversion types: port to lane and lane to port.

[0085] Port to Lane conversion type: According to the actual bifurcation requirements of the input signal to be processed, it can be divided into two subtypes: Split and Replication.

[0086] Split: The signal to be processed input in the Port covers the signal status of each Lane to which it belongs, and the signal of each Lane is independent, that is, one-to-one mapping. Then the bifurcation mapping of the signal to be processed input from each Port is split and output to the corresponding physical channel Lane, where the port to which the signal to be processed belongs is the Port that receives the signal to be processed. For example: Each Lane receives the status mark signal of TS (the data packet format of PCIe link training, used to initialize synchronization and optimize link parameters). Each bit value represents the receiving TS status of all Lanes. Taking X8 as an example, Lane0~7 inputs need to be taken from the corresponding bits of the status mark signal respectively. When TS is received, the bit position corresponding to the status mark signal is set to 1, and all four lanes must receive the TS status. The port end performs aggregation.

[0087] Replication: For each lane in a port with a common input to-be-processed signal, i.e. one-to-many mapping, first replicate the number of lanes to-be-processed signals according to the number of lanes contained in the port, and then split and output each signal to-be-processed to the corresponding physical channel by bifurcation mapping. For example: the LTSSM status signal of the current port needs to be replicated to each lane to which the current port belongs, so the input of each lane in the port is taken from the same LTSSM status signal.

[0088] Lane to Port conversion: First, the bifurcation mapping of the signals to be processed corresponding to each Lane is aggregated into the data of each Port, and then the channels are flipped or downgraded inside the Ports to which they belong before output. The signals to be processed corresponding to each Lane can be understood as the signals to be processed output from the corresponding Lane, and the Ports to which they belong can be understood as the ports to which the signals to be processed need to be converted.

[0089] In some optional implementations, the method further includes:

[0090] A convergence module pre-designed for forked mapping convergence, and a degradation flip module pre-designed for channel flipping or channel degradation;

[0091] The signal to be processed whose conversion type is channel to port is output after being forked, mapped and converged, and then channel flipped or downgraded inside the corresponding port, including:

[0092] Instantiate the convergence module, and connect the internal signals of the instantiated convergence module according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping convergence of the received signal to be processed;

[0093] According to the maximum number of ports supported, the downgrade flip module is instantiated, and the internal signal of the instantiated downgrade flip module is connected to realize channel flipping or channel downgrade of the to-be-processed signal after the forked mapping convergence within the port.

[0094] Exemplarily, in the present application, a convergence module l2p_bif_convert for forking mapping and convergence may be pre-designed to realize that the to-be-processed signals entering each Lane are forked mapped and converged into signals at the Port end through a forking mode.

[0095] The following takes X8 as an example to illustrate the fork mode:

[0096] P2L separation type:

[0097] See also Figure 5B As shown in the figure, the bit width of signal_a output by the port is 8 bits in total, and it interacts with lane0 to lane7 in order from low to high. Therefore, the fork mode required for this type of signal to be processed is the separation type, that is, the port outputs all signal groups that have covered the interactive signals of each lane, and needs to be split (one-to-one mapping) to each lane.

[0098] P2L replication type:

[0099] See also Figure 5C As shown in the figure, the bit width of signal_b output by the port is 1 bit, and lane0 to lane7 all need to use this signal for interaction. Therefore, the fork mode required for this type of signal to be processed is the replication type, that is, the same interactive signal output by the port is replicated (one-to-many mapping) and transmitted to each lane for interaction.

[0100] L2P Type:

[0101] See also Figure 5D As shown in the figure, lane0~lane7 all output signal_c with the same purpose, and the bit width is 1 bit. Since the output of each lane has different states, Port needs to use the signal output by each lane for overall judgment and interaction. Therefore, the processing mode required for this type of signal to be processed is L2P type, that is, the different interactive signals output by each lane are aggregated into a group of signals signal_c[7:0] (arranged from low to high in bit order, corresponding to lane0~lane7) and transmitted to Port for interaction.

[0102] Exemplarily, the present application may also pre-design a lane flip or lane downgrade downgrade flip module lane_flip_convert for implementing Lane flip and downgrade functions within each port. When implementing the solution of the present application, the convergence module and downgrade flip module may be temporarily designed as digital circuit modules, and subsequently hardware circuit design may be performed together with the PCIe bifurcation device of the present application.

[0103] When designing a PCIe bifurcation circuit, for channel-to-port type signals to be processed, the pre-designed aggregation module can be directly instantiated so that the internal signals of the instantiated aggregation module can be connected according to the bifurcation mode corresponding to the signals to be processed of multiple channels that need to be aggregated to the same port, so that the instantiated aggregation module can realize the bifurcation mapping aggregation of the signals to be processed of the multiple channels from channel to port.

[0104] For each port, a degradation flip module may be instantiated to perform channel flipping or channel degradation inside the port on the signal converged to the port.

[0105] In some optional implementations, the method further includes:

[0106] A split module is pre-designed to split the fork mapping according to the fork mode, and a downgrade flip module is pre-designed to perform channel flipping or channel downgrading;

[0107] For the signal to be processed whose conversion type is a port-to-channel separation type, after performing channel flipping or channel degradation inside the corresponding port, the signal is output to the corresponding channel after splitting through bifurcation mapping, including:

[0108] According to the maximum number of ports supported, the downgrade flip module is instantiated, and the internal signal of the instantiated downgrade flip module is connected to realize channel flipping or channel downgrade of the received signal to be processed inside the port.

[0109] The splitting module is instantiated, and the internal signals of the instantiated splitting module are connected according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping splitting of the signal to be processed with channel flipping or channel degradation.

[0110] Exemplarily, in the present application, a splitting module p2l_bif_convert for performing fork mapping splitting may be pre-designed to implement splitting of to-be-processed signals of the same port into signals of corresponding channels by fork mapping through a fork mode.

[0111] Exemplarily, the present application may also pre-design a downgrade flip module lane_flip_convert for channel flipping or channel downgrading, which is used to implement Lane flipping and downgrading functions inside each port. It is understandable that if the downgrade flip module lane_flip_convert has been pre-designed, it can be directly used in this implementation without the need for redesign. When implementing the solution of the present application, the split module and the downgrade flip module can be temporarily designed as a digital circuit module, and the hardware circuit design can be performed together with the PCIe bifurcation device of the present application later.

[0112] When designing a PCIe bifurcation circuit, for the signal to be processed of the port-to-channel separation type, a downgrade flip module can be instantiated first. If the signal to be processed includes multiple signals and corresponds to multiple ports, a downgrade flip module is instantiated for each port, so that the instantiated downgrade flip module performs channel flipping or channel downgrading on the signal to be processed of the corresponding port, and then outputs it to the instantiated split module.

[0113] When the split module is instantiated, the internal signal of the instantiated split module is connected according to the bifurcation mode of the signal to be processed that needs to be mapped, so that the instantiated split module can split the signal to be processed of the same port into signals of multiple channels.

[0114] In some optional implementations, the method further includes:

[0115] A splitting module pre-designed to split the bifurcation map according to the bifurcation pattern, and a replication module pre-designed to replicate the signal;

[0116] For the signal to be processed whose conversion type is a port-to-channel replication type, the signal is replicated according to the number of channels supported by the corresponding port, and is output to the corresponding channel after being split by fork mapping, including:

[0117] Instantiating the replication module according to the maximum number of ports supported, and connecting the internal signals of the instantiated replication module to implement replication of the received signal to be processed;

[0118] The splitting module is instantiated, and the internal signals of the instantiated splitting module are connected according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping splitting of the copied signal to be processed.

[0119] Exemplarily, in the present application, a splitting module p2l_bif_convert for splitting by bifurcation mapping can be pre-designed to realize that the to-be-processed signal of the same port is split into signals of corresponding channels by bifurcation mapping through bifurcation mode. It is understandable that if the splitting module p2l_bif_convert has been pre-designed, it can be directly used in the implementation without the need for re-design.

[0120] For example, the present application may also pre-design a replication module for signal replication, which is used to implement the replication of the input signal at the Port end according to the maximum number of supported Lanes. When implementing the solution of the present application, the splitting module and the replication module may be temporarily designed as digital circuit modules, and subsequently the hardware circuit design may be performed together with the PCIe bifurcation device of the present application.

[0121] When designing a PCIe bifurcation circuit, for a signal to be processed of a port-to-channel separation type, a replication module can be instantiated first. If there are multiple signals to be processed and they correspond to multiple ports, a replication module is instantiated for each port, so that the instantiated replication module replicates the signal to be processed of the corresponding port. The number of copies is related to the maximum number of channels supported by the corresponding port, and the multiple replicated signals are output to the instantiated splitting module.

[0122] When the split module is instantiated, the internal signals of the instantiated split module are connected according to the bifurcation mode of the signal to be processed that needs to be mapped, so that the instantiated split module can split multiple copy signals of the same port into signals of multiple channels.

[0123] In some optional implementations, the method further includes:

[0124] Obtain configuration information of the PCIe bifurcation system; wherein the configuration information includes: the conversion type of the signal to be processed, the bifurcation mode of the signal to be processed, the width of the signal to be processed, the maximum number of channels supported, the maximum number of ports supported, and the number of channels supported by each port; wherein the number of bifurcation mapping splits is equal to the maximum number of channels supported.

[0125] Exemplarily, the present application supports the configuration of the number of Ports and Lanes. It only requires connecting all the signals to be processed to the input and output ports during integration and instantiation, and the corresponding code logic can be generated with one click.

[0126] in:

[0127] 1. Support Bifurcation mode parameter configuration.

[0128] 2. Support parameter configuration of the number of input and output ports and lanes, and the maximum number of lanes in each port.

[0129] 3. Support parameter configuration of the total bit width of the signal to be processed.

[0130] 4. Support invalid output port signal processing as fixed value parameter configuration.

[0131] 5. Automatic RTL generation. That is, after digital design, RTL code can be automatically generated, and then the PCIe circuit structure can be realized based on the RTL code.

[0132] This application can generate the corresponding RTL code with one click by filling the corresponding .xlsx configuration file with the signal to be processed according to the conversion type and selecting the configuration parameters. The configuration file is shown in Table 1 below:

[0133]

[0134] Table 1

[0135] Among them, "Port Name": is the name of the signal to be processed. If it is the port name connected to the Port end, the signal name is suffixed with "_P", and the other port names connected to the Lane end are consistent, which is convenient for the automated RTL generation script to extract signals and generate codes; "Single Lane Width": indicates the width of the signal to be processed; "Width": the total bit width of the signal to be processed, which is determined by the parameters MNL (maximum number of lanes supported), MNP (maximum number of ports supported), NL_P (number of lanes supported by the current Port) and "Single Lane Width". The script will generate the number of internal selection logics and generate internal signals and corresponding connections based on this information; "Conversion Type": indicates that the type of signal to be processed needs to be selected, including the channel to port type L2P, the port to channel separation type P2L_split and the port to channel replication type P2L_replication. The script will call different functional components based on this information; "laneflip": indicates whether the lane_flip_convert component needs to be called and connected. If it is configured that the lane_flip_convert component does not need to be called and connected, this component can be omitted.

[0136] The following takes the instantiation of the p2l_split module as an example to illustrate the above parameters:

[0137] 1. The script sets the corresponding parameters of the p2l_split module instantiation according to MNL and NL_P, that is, the corresponding input and output port signal widths required for the signal to be processed are determined.

[0138] 2. According to MNP, the corresponding parameters of the p2l_split module instantiation are set, that is, the number of input and output ports mentioned above has been determined, and the number of lane_flip_convert instantiations has also been determined.

[0139] 3. Then the script is written according to the Verilog syntax rules, instantiates and calls the above modules, and connects the internal module signals according to the signal feature names and the set logical connection rules.

[0140] See also Figure 6 As shown, illustratively, the hierarchical structure of the RTL code generated by the present application is described as follows:

[0141] The script extracts all L2P type signals to be processed and generates l2p_wrapper for unified processing. Determine whether the "lanneflip" parameter in the configuration file is configured as l2p_lf or l2p_nlf. Regardless of whether it is configured as l2p_lf or l2p_nlf, l2p_bif_convert (aggregation module) must be called to perform MUX mapping processing from Lane signals to Port signals. If l2p_lf is configured, lane_flip_convert (downgrade flip module) is additionally called to perform Lane downgrade processing. If l2p_nlf is configured, lane_flip_convert (downgrade flip module) is not called to perform Line downgrade processing.

[0142] The script extracts all P2L type signals to be processed, generates p2l_wrapper for unified processing, and then selects p2l_split branch or p2l_replication branch for processing according to whether split (separation type) or replication (replication type) is configured in the configuration file. In addition, it is necessary to determine whether the "laneflip" parameter in the configuration file is configured as p2l_split_lf or p2l_split_nlf. Regardless of whether p2l_split_lf or p2l_splitn_nlf is configured, p2l_bif_convert (split module) must be called to perform MUX mapping processing from Port signal to Lane signal. If p2l_split_lf is configured, lane_flip_convert is additionally called for Lane downgrade processing. If p2l_split_nlf is configured, the lane_flip_convert component is not called for Lane downgrade processing.

[0143] The above l2p_bif_convert and p2l_bif_convert are respectively instantiated with parameters according to the total bit width of the signal to be processed, and the internal selector mapping processing connection is performed according to the Bifurcation mode configuration.

[0144] For example, the present application uses the P2L_split unit to implement input signals in units of Port, firstly performs Lane flipping or downgrading processing through lane_flip_convert of the corresponding Port (if the configuration information is configured not to call lane_flip_convert, the lane_flip_convert component is omitted here), and then splits the signal and outputs it to the corresponding Lane after mapping according to Bifurcation through p2l_bif_convert. Figure 7 As shown in the figure, the unit consists of 1 p2l_bif_convert and multiple lane_flip_convert. In the figure, cfg_bif_mode indicates the bifurcation mode, flip_ctrl indicates the input control signal of lane_flip_convert, which determines how to perform flipping or degradation processing, port*_din[DL×NL_P*-1:0] is the input signal to be processed, where DL indicates the width of the signal to be processed, port*_data is the data after channel flipping or degradation in the port, and lane*_dout[DL-1:0] indicates the signal output to the channel after splitting.

[0145] Exemplarily, the present application uses the P2L_replication unit to implement the input signal in units of Ports. The data is first copied by replication according to the number of Lanes contained in the Port, and then the signal is split and output to the corresponding Lane after being mapped by Bifurcation by p2l_bif_convert. Figure 8 As shown in the figure, the unit consists of one p2l_bif_convert and multiple replications. In the figure, cfg_bif_mode indicates the bifurcation mode, port*_din[DL-1:0] is the input signal to be processed, port*_data[DL×NL_P*-1:0] indicates the replicated data, and lane*_dout[DL-1:0] indicates the signal output to the channel after splitting.

[0146] Exemplarily, the present application uses the L2P conversion unit to realize the function of first aggregating each Lane signal into each Port data through Bifurcation mapping, and then performing Lane flipping or degradation operation processing inside each Port before outputting. Fig. 9As shown in the figure, the unit consists of 1 l2p_bif_convert and multiple lane_flip_convert (if the configuration information is configured not to call lane_flip_convert, the lane_flip_convert component is omitted here). In the figure, cfg_bif_mode represents the bifurcation mode, flip_ctrl represents the input control signal of lane_flip_convert, lane*_din[DL-1:0] is the input signal to be processed, where port*_data represents the data corresponding to the port after aggregation, and port*_dout[DL×NL_P*-1:0] represents the output data after channel flipping or degradation in the port.

[0147] in:

[0148] p2l_bif_convert: Maps the input signal of the Port end to the corresponding Lane signal through Bifurcation mode.

[0149] l2p_bif_convert: realizes the aggregation of Lane signals into Port signals through Bifurcation mode mapping.

[0150] replication: implements the replication of common information of port input signals according to the maximum number of supported lanes.

[0151] lane_flip_convert: implements Lane flip and downgrade functions.

[0152] The beneficial effects of this application are as follows:

[0153] This application solves the problem that the traditional PCIe multi-port controller design requires special customized development of Bifurcation function logic, which prolongs the chip development cycle and increases the difficulty of verification convergence. It can maximize the reuse of Lane logic resources, support flexible customization of interaction signals between multiple ports and multiple lanes, support classification batch processing (standardization, scalability, accuracy) of interaction signals between multiple ports and multiple lanes, automatically generate code, and support flexible configuration of the mapping relationship between multiple ports and multiple lanes to meet various needs. The code has strong maintainability and scalability, and can shorten the code delivery cycle by about 2 to 3 weeks. If frequent changes and iterations are required, the effect is more significant, greatly reducing the amount of interaction signals, reducing the difficulty and cycle of timing convergence, reducing the difficulty of verification coverage convergence, and shortening product development time.

[0154] The effect of maximizing Lane logic resource reuse is further explained as follows:

[0155] Taking 8 ports multiplexing 8 lanes as an example, if the traditional design method is used, 8*8=64 lane logics may need to be instantiated. The present application can save up to (64-8) / 64=87.5% of lane logic resources.

[0156] Exemplarily, the present application also proposes a PCIe bifurcation device, which includes:

[0157] The channel-to-port conversion module is configured to perform channel flipping or channel degradation inside the corresponding port and then output the to-be-processed signal whose conversion type is channel-to-port after forking mapping and convergence;

[0158] The first port-to-channel conversion module is configured to perform channel flipping or channel degradation inside the corresponding port for a signal to be processed whose conversion type is a port-to-channel separation type, and then output the signal to the corresponding channel after splitting through bifurcation mapping;

[0159] The second port-to-channel conversion module is configured to copy the to-be-processed signal of the port-to-channel copy type according to the number of channels supported by the corresponding port, and output it to the corresponding channel after splitting through fork mapping.

[0160] In some optional implementations, the device further includes:

[0161] A first design module is configured as a convergence module for pre-designing forked mapping convergence, and a degradation flip module for pre-designing channel flipping or channel degradation;

[0162] The channel-to-port conversion module is implemented as follows:

[0163] Instantiate the convergence module, and connect the internal signals of the instantiated convergence module according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping convergence of the received signal to be processed;

[0164] According to the maximum number of ports supported, the downgrade flip module is instantiated, and the internal signal of the instantiated downgrade flip module is connected to realize channel flipping or channel downgrade of the to-be-processed signal after the forked mapping convergence within the port.

[0165] In some optional implementations, the device further includes:

[0166] The second design module is configured to pre-design a splitting module for splitting a bifurcation map according to a bifurcation mode, and a downgrade flipping module for pre-designing channel flipping or channel downgrade;

[0167] The first port to channel conversion module is implemented as follows:

[0168] Instantiate the downgrade flip module according to the maximum number of ports supported, and connect the internal signal of the instantiated downgrade flip module to implement channel flipping or channel downgrade of the received signal to be processed inside the port;

[0169] The splitting module is instantiated, and the internal signals of the instantiated splitting module are connected according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping splitting of the signal to be processed with channel flipping or channel degradation.

[0170] In some optional implementations, the device further includes:

[0171] A third design module is configured to pre-design a splitting module for splitting a bifurcation map according to a bifurcation pattern, and a replication module for replicating a signal;

[0172] The second port-to-channel conversion module is implemented as follows:

[0173] Instantiating the replication module according to the maximum number of ports supported, and connecting the internal signals of the instantiated replication module to implement replication of the received signal to be processed;

[0174] The splitting module is instantiated, and the internal signals of the instantiated splitting module are connected according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping splitting of the copied signal to be processed.

[0175] In some optional implementations, the device further includes:

[0176] An acquisition module is configured to acquire configuration information of a PCIe bifurcation system; wherein the configuration information includes: a conversion type of the signal to be processed, a bifurcation mode of the signal to be processed, a width of the signal to be processed, a maximum number of channels supported, a maximum number of ports supported, and a number of channels supported by each port; wherein the number of bifurcation mapping splits is equal to the maximum number of channels supported.

[0177] The above device can be implemented by the PCIe bifurcation method provided in the above embodiment. The specific implementation method can refer to the description of the PCIe bifurcation method in the above embodiment, which will not be repeated here.

[0178] It is understood that the circuit structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above embodiments according to the use requirements, and should not limit the concept of the present application to the specific details of the above examples.

[0179] Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that he or she may still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A PCIe bifurcation method, characterized in that: include: For the signals to be processed whose conversion type is channel to port, after forking mapping and convergence, the channels are flipped or downgraded inside the corresponding ports before being output; For the signal to be processed whose conversion type is port-to-channel separation type, after performing channel flipping or channel degradation inside the corresponding port, it is split through bifurcation mapping and output to the corresponding channel; For the signal to be processed whose conversion type is the port-to-channel copy type, it is copied according to the number of channels supported by the port to which it belongs, and is output to the corresponding channel after being split by fork mapping.

2. The PCIe bifurcation method according to claim 1, characterized in that: The method further comprises: A convergence module pre-designed for forked mapping convergence, and a degradation flip module pre-designed for channel flipping or channel degradation; The signal to be processed whose conversion type is channel to port is output after being forked, mapped and converged, and then channel flipped or downgraded inside the corresponding port, including: Instantiate the convergence module, and connect the internal signals of the instantiated convergence module according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping convergence of the received signal to be processed; According to the maximum number of ports supported, the downgrade flip module is instantiated, and the internal signal of the instantiated downgrade flip module is connected to realize channel flipping or channel downgrade of the to-be-processed signal after the forked mapping convergence within the port.

3. The PCIe bifurcation method according to claim 1, characterized in that: The method further comprises: A split module is pre-designed to split the fork mapping according to the fork mode, and a downgrade flip module is pre-designed to perform channel flipping or channel downgrading; For the signal to be processed whose conversion type is a port-to-channel separation type, after performing channel flipping or channel degradation inside the corresponding port, the signal is output to the corresponding channel after splitting through bifurcation mapping, including: Instantiate the downgrade flip module according to the maximum number of ports supported, and connect the internal signal of the instantiated downgrade flip module to implement channel flipping or channel downgrade of the received signal to be processed inside the port; The splitting module is instantiated, and the internal signals of the instantiated splitting module are connected according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping splitting of the signal to be processed with channel flipping or channel degradation.

4. The PCIe bifurcation method according to claim 1, characterized in that: The method further comprises: A splitting module is pre-designed to split the bifurcation map according to the bifurcation pattern, and a replication module is pre-designed to replicate the signal; For the signal to be processed whose conversion type is a port-to-channel replication type, the signal is replicated according to the number of channels supported by the corresponding port, and is output to the corresponding channel after being split by fork mapping, including: Instantiating the replication module according to the maximum number of ports supported, and connecting internal signals of the instantiated replication module to implement replication of the received signal to be processed; The splitting module is instantiated, and the internal signals of the instantiated splitting module are connected according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping splitting of the copied signal to be processed.

5. The PCIe bifurcation method according to any one of claims 1 to 4, characterized in that: The method further comprises: Obtain configuration information of the PCIe bifurcation system; wherein the configuration information includes: the conversion type of the signal to be processed, the bifurcation mode of the signal to be processed, the width of the signal to be processed, the maximum number of channels supported, the maximum number of ports supported, and the number of channels supported by each port; wherein the number of bifurcation mapping splits is equal to the maximum number of channels supported.

6. A PCIe bifurcation device, characterized in that: include: The channel-to-port conversion module is configured to perform channel flipping or channel degradation inside the corresponding port and then output the to-be-processed signal whose conversion type is channel-to-port after forking mapping and convergence; The first port-to-channel conversion module is configured to perform channel flipping or channel degradation inside the corresponding port for a signal to be processed whose conversion type is a port-to-channel separation type, and then output the signal to the corresponding channel after splitting through bifurcation mapping; The second port-to-channel conversion module is configured to copy the to-be-processed signal of the port-to-channel copy type according to the number of channels supported by the corresponding port, and output it to the corresponding channel after splitting through fork mapping.

7. The PCIe bifurcation device according to claim 6, characterized in that: The device also includes: A first design module is configured as a convergence module for pre-designing forked mapping convergence, and a degradation flip module for pre-designing channel flipping or channel degradation; The channel-to-port conversion module is implemented as follows: Instantiate the convergence module, and connect the internal signals of the instantiated convergence module according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping convergence of the received signal to be processed; According to the maximum number of ports supported, the downgrade flip module is instantiated, and the internal signal of the instantiated downgrade flip module is connected to realize channel flipping or channel downgrade of the to-be-processed signal after the forked mapping convergence within the port.

8. The PCIe bifurcation device according to claim 6, characterized in that: The device also includes: The second design module is configured to pre-design a splitting module for splitting a bifurcation map according to a bifurcation mode, and a downgrade flipping module for pre-designing a channel flipping or channel downgrading; The first port to channel conversion module is implemented as follows: Instantiate the downgrade flip module according to the maximum number of ports supported, and connect the internal signal of the instantiated downgrade flip module to implement channel flipping or channel downgrade of the received signal to be processed inside the port; The splitting module is instantiated, and the internal signals of the instantiated splitting module are connected according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping splitting of the signal to be processed with channel flipping or channel degradation.

9. The PCIe bifurcation device according to claim 6, characterized in that: The device also includes: A third design module is configured to pre-design a splitting module for splitting a bifurcation map according to a bifurcation pattern, and a replication module for replicating a signal; The second port-to-channel conversion module is implemented as follows: Instantiating the replication module according to the maximum number of ports supported, and connecting internal signals of the instantiated replication module to implement replication of the received signal to be processed; The splitting module is instantiated, and the internal signals of the instantiated splitting module are connected according to the bifurcation mode corresponding to the signal to be processed, so as to realize the bifurcation mapping splitting of the copied signal to be processed.

10. The PCIe bifurcation device according to any one of claims 6 to 9, characterized in that: The device also includes: An acquisition module is configured to acquire configuration information of a PCIe bifurcation system; wherein the configuration information includes: a conversion type of the signal to be processed, a bifurcation mode of the signal to be processed, a width of the signal to be processed, a maximum number of channels supported, a maximum number of ports supported, and a number of channels supported by each port; wherein the number of bifurcation mapping splits is equal to the maximum number of channels supported.

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