Low-complexity full-duplex DMA communication method, device, equipment and medium

Abstract

The invention discloses a low-complexity full-duplex DMA communication method and device, equipment and a medium, and belongs to the technical field of communication. Firstly, a register is defined and used for controlling bidirectional interaction of a PL and a PS, and then the PL realizes communication on different channels by controlling the register. On a channel in the direction from the PL to the PS, the PL sends write length and write data to the data mover DATAMOVER in sequence, then the PS reads the data from the DDR in the PS, and after the PS completes reading, the PL initiates communication again, and circulation is repeated; on a channel in the direction from the PS to the PL, the PL sends a read length to the DATAMOVER, the PS writes data to the PS DDR according to the read length transmitted by the DATAMOVER, after the PS finishes writing, the PL reads the data from the DATAMOVER, after the PL finishes reading, the PS writes the data to the PS DDR again, and the steps are repeated.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a low-complexity full-duplex DMA communication method, device, equipment and medium. Background Art

[0002] In the DMA communication system, the system needs to call the high-end performance HP interface in the interaction between PL and PS, which makes the system complex and difficult for developers to develop, thus extending the development cycle. In addition, when calling the HP interface on the PS side, the AXI FULL bus needs to be used. Compared with the AXI STREAM bus, the read and write channel signals are more numerous and more complex. The system data capture tool SYMTEM ILA also needs to be called for debugging, and more resources are needed. In some cost-reduction projects, there is often no more memory resource RAM for developers to use. At the same time, although the traditional DMA system uses PL as the host and PS as the slave for interaction, the drivers are all in the PS, which makes the controllability of PL particularly insufficient, and it is more of a channel provider. Summary of the invention

[0003] In view of the problems existing in the prior art, the purpose of the present invention is to provide a low-complexity full-duplex DMA communication method, device, equipment and medium for data interaction between programmable logic PL and processing system PS, using a direct memory access system DMA data interaction method, which adopts a full-duplex communication mode.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is: The present invention provides a low-complexity full-duplex DMA communication method, comprising the following steps: Step 1, define register signals, including PL write enable signal, PL write length signal, PL write address signal, PS write enable signal, PS write length signal, PS write address signal; Step 2: When the PL write enable signal is set to a high level, proceed to step 3; when the PS write enable signal is set to a high level, proceed to step 8; Step 3, when PL captures the ready signal S_AXIS_S2MM_CMD_tready in the command channel S2MM_CMD from PL to PS of DATAMOVER as high, assign the PL write length signal and the PL write address signal to the data signal S_AXIS_S2MM_CMD_tdata, and set it and the valid signal S_AXIS_S2MM_CMD_tvalid to high and send them to DATAMOVER; Step 4, when PL captures the data channel S_AXIS_S2MM from PL to PS of DATAMOVER, and the preparation signal S_AXIS_S2MM_tready is high, the PL write length signal and the PL write address signal are assigned to S_AXIS_S2MM_tdata, and the valid bit indication S_AXIS_S2MM_tkeep, the valid signal S_AXIS_S2MM_tvalid and the last data indication S_AXIS_S2MM_tlast are sent to DATAMOVER; Step 5: After PL has sent a whole frame of data, the signal pl_wr_done is set to a pulse signal and output to PS as an interrupt trigger of the rising edge; Step 6: When the PS captures the rising edge of the pl_wr_done signal, it reads data from the address corresponding to the PS DDR. When the PS reads the complete frame data, it pulls the signal ps_rd_done high and outputs it to the PL. Step 7: When PL captures the rising edge of the signal ps_rd_done, it continues to send data to PS and returns to step 3; Step 8. When PL captures the ready signal S_AXIS_MM2S_CMD_tready in the command channel MM2S_CMD from PS to PL of DATAMOVER as high, PL assigns the PS write length signal and the PS write address signal to the data signal S_AXIS_MM2S_CMD_tdata, sets it and the valid signal S_AXIS_MM2S_CMD_tvalid to high and sends them to DATAMOVER; Step 9. After the PS captures the read address and read length in the data channel M_AXI_MM2S from the PS to the PL of DATAMOVER, it writes data to the PS DDR. After the PS finishes writing a whole frame of data, it sets the signal ps_wr_done to a high level and outputs it to the PL. Step 10, when PL captures the ready signal S_AXIS_MM2S_tready in the data channel S_AXIS_MM2S from PS to PL of DATAMOVER as high level, read the data S_AXIS_MM2S_tdata, the valid bit indication S_AXIS_MM2S_tkeep, the valid signal S_AXIS_MM2S_tvalid and the last data indication S_AXIS_MM2S_tlast; Step 11: After PL has read a whole frame of data, the signal pl_rd_done is set as a pulse signal and output to PS as a rising edge interrupt trigger; Step 12: When the PS captures the rising edge of the signal pl_rd_done, it continues to write data to the PS DDR and returns to step 8.

[0005] Optionally, the PL write enable signal, the PL write length signal and the PL write address signal are respectively a permission signal, a data length signal and an address signal for controlling the PL to send data to the PS; The PS write enable signal, the PS write length signal, and the PS write address signal are respectively a permission signal, a data length signal, and an address signal for controlling the PS to send data to the PL.

[0006] Optionally, the data signal S_AXIS_S2MM_CMD_tdata is 72 bits in total; [22:0] is BIT, indicating the byte length of the transmitted data;

[23] is TYPE, indicating the burst type of AXI;

[30] is EOF, indicating whether the frame sent this time is the last frame; [N+31:32] is SADDR, indicating the starting address of the transmission, where N indicates the address depth of the memory mapping; the remaining bits are 0.

[0007] In a second aspect, the present invention provides a low-complexity full-duplex DMA communication device, the device comprising: A register definition module, configured to define register signals, including a PL write enable signal, a PL write length signal, a PL write address signal, a PS write enable signal, a PS write length signal, and a PS write address signal; The communication selection module is configured to enter the PL-PS communication module when the PL write enable signal is set to a high level, and enter the PS-PL communication module when the PS write enable signal is set to a high level; The PL-PS communication module is configured to assign the PL write length signal and the PL write address signal to the data signal S_AXIS_S2MM_CMD_tdata when the PL captures the ready signal S_AXIS_S2MM_CMD_tready in the command channel S2MM_CMD from PL to PS of DATAMOVER as high, and set it and the valid signal S_AXIS_S2MM_CMD_tvalid to high and send them to DATAMOVER; When PL captures the data channel S_AXIS_S2MM from PL to PS of DATAMOVER, and the preparation signal S_AXIS_S2MM_tready is high, the PL write length signal and the PL write address signal are assigned to S_AXIS_S2MM_tdata, and the valid bit indication S_AXIS_S2MM_tkeep, the valid signal S_AXIS_S2MM_tvalid and the last data indication S_AXIS_S2MM_tlast are sent to DATAMOVER; When PL has sent a whole frame of data, the signal pl_wr_done is set to a pulse signal and output to PS as a rising edge interrupt trigger; When the PS captures the rising edge of the pl_wr_done signal, it reads data from the address corresponding to the PS DDR. When the PS reads the complete frame data, it pulls the signal ps_rd_done high and outputs it to the PL. When PL captures the rising edge of the signal ps_rd_done, it continues to send data to PS; The PS-PL communication module is configured such that when the PL captures the ready signal S_AXIS_MM2S_CMD_tready in the command channel MM2S_CMD from the PS to the PL of the DATAMOVER as high, the PL assigns the PS write length signal and the PS write address signal to the data signal S_AXIS_MM2S_CMD_tdata, sets it and the valid signal S_AXIS_MM2S_CMD_tvalid to high levels and sends them to the DATAMOVER; When PS captures the read address and read length in the data channel M_AXI_MM2S from PS to PL of DATAMOVER, it writes data to PS DDR. When PS finishes writing a whole frame of data, it sets the signal ps_wr_done to a high level and outputs it to PL. When PL captures the ready signal S_AXIS_MM2S_tready in the data channel S_AXIS_MM2S from PS to PL of DATAMOVER as high, it reads the data S_AXIS_MM2S_tdata, the valid bit indication S_AXIS_MM2S_tkeep, the valid signal S_AXIS_MM2S_tvalid and the last data indication S_AXIS_MM2S_tlast; When PL finishes reading a whole frame of data, it sets the signal pl_rd_done to a pulse signal and outputs it to PS as a rising edge interrupt trigger; When the PS captures the rising edge of the signal pl_rd_done, it continues to write data to the PS DDR.

[0008] In a third aspect, the present invention provides an electronic device, including a processor and a storage medium; The storage medium is used to store instructions; The processor is used to operate according to the instructions to execute the steps according to the above method.

[0009] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0010] In a fifth aspect, the present invention provides a computer program product, comprising a computer program / instruction, which implements the steps of the above method when executed by a processor.

[0011] Compared with the prior art, the present invention has the following beneficial effects: The present invention adopts the method of replacing DMA IP with XILINX DATAMOVER IP, replaces the complex AXI FULL protocol with the simple AXI STREAM protocol, simplifies the interface signal, makes the encoding, simulation and debugging processes simpler and more convenient, and enhances the convenience of the system.

[0012] The present invention adopts full-duplex mode, and the directions from PL to PS and from PS to PL are independent channels. After the read and write status is completed by PL or PS, the read and write identification is performed to perform subsequent operations, thereby enhancing the transmission rate and logic of the system.

[0013] The present invention adopts PL as the main logic and PS configures PL registers, thereby increasing the application ratio of PL in the control logic, replacing the traditional method of calling PS official drivers, and increasing the independent development and portability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A flow chart of a communication method for sending data from a PL to a PS provided in an embodiment of the present invention.

[0015] Figure 2 A flow chart of a communication method for sending data from a PS to a PL provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0017] The present invention is further described below in conjunction with the accompanying drawings.

[0018] DATAMOVER IP is a free IP core provided by Xilinx, which is specially used to move data between FPGA (PL side) and DDR (PS side) at high speed; S_AXIS_S2MM: indicates the bus connected to the PL logic, using the AXI STREAM protocol, which is the channel for PL to send data to DATAMOVER; S_AXIS_S2MM_CMD: indicates the bus connected to the PL logic, using the AXI STREAM protocol, and is the channel for the PL to send the write address and write length to the DATAMOVER; S_AXIS_MM2S_CMD: indicates the bus connected to the PL logic, using the AXI STREAM protocol, and is the channel for the PL to send the read address and read length to the DATAMOVER; M_AXI_MM2S: indicates the bus connected to PS HP. When the M_AXI_S2MM bus is used, it needs to be connected to AXI_INTERCONNECT. It uses the AXI FULL protocol and is the channel for DATAMOVER to transmit the read address and read length to PS, and for PS to transmit data to DATAMOVER. M_AXI_S2MM: represents the bus connected to PS HP. When the M_AXI_MM2S bus is used, it needs to be connected to AXI_INTERCONNECT. It uses the AXI FULL protocol and is the channel for DATAMOVER to transmit write address, write length and write data to PS.

[0019] Embodiment 1:

[0020] See also Figure 1 and Figure 2 , the present invention comprises the following steps: Step 1, define registers, including defining a PL write enable signal pl_wr_en, which is used to control the authority of the PL to send data to the PS. Only when this signal is set to a high level, the PL has the authority to send data to the PS; defining a PL write length signal pl_wr_len, which is used to control the signal of the data length sent by the PL to the PS; defining a PL write address signal pl_wr_addr, which is used to control the address signal of the data sent by the PL to the PS; defining a PS write enable signal ps_wr_en, which is used to control the authority of the PS to send data to the PL. Only when this signal is at a high level, the PS has the authority to send data to the PL; defining a PS write length signal ps_wr_len, which is used to control the signal of the data length sent by the PS to the PL, and defining a PS write address signal ps_wr_addr, which is used to control the signal of the data address sent by the PS to the PL.

[0021] Step 2: When pl_wr_en is set to a high level, go to step 3; when ps_wr_en is set to a high level, go to step 8. When data communication from PL to PS is required, pl_wr_en is set to a high level; when data communication from PS to PL is required, ps_wr_en is set to a high level; when full-duplex communication in both directions is required, both pl_wr_en and ps_wr_en are set to a high level, indicating bidirectional communication between PL and PS, and one of the two signals is set to a high level, indicating unidirectional communication between PL and PS.

[0022] Step 3. When PL captures the command channel S2MM_CMD from PL to PS of DATAMOVER, and the signal S_AXIS_S2MM_CMD_tready is high, pl_wr_len and pl_wr_addr are assigned to the data signal S_AXIS_S2MM_CMD_tdata, and set it and the valid signal S_AXIS_S2MM_CMD_tvalid to high and send them to DATAMOVER. In the direction of PL sending data to PS, PL continuously captures the S_AXIS_S2MM_CMD_tready signal of the S2MM_CMD channel in DATAMOVER. When it is captured and set to high, it means that the S2MM_CMD channel from PL to PS of DATAMOVER is ready, and the data signal S_AXIS_S2MM_CMD_tdata can be sent to DATAMOVER. The data signal S_AXIS_S2MM_CMD_tdata of the S2MM_CMD channel is 72 bits in total, [22:0] is BIT indicating the byte length of the transmitted data, in bytes. If the length of the transmitted data is 2048 and the data bit width is 64 bits, then the length needs to be set to 2048*64bit / 8byte=16384 according to the format, which is converted to hexadecimal 4000, that is, the programmable logic write length signal pl_wr_len is hexadecimal 4000.

[23] is TYPE, indicating the burst type of AXI. The value 0 indicates that the burst transmission type is fixed, and the data is stored in the starting address and the old value will be overwritten. The value 1 indicates that the burst transmission type is INCR, and the data will be stored in the address that increases from the starting address, that is, according to the burst length, only the starting address of the current burst needs to be written at the first burst each time, and TYPE is fixed to 1.

[30] is EOF, which distinguishes whether the frame sent this time is the last frame. The value 0 indicates that the frame sent this time is not the last frame, and the value 1 indicates that the frame sent this time is the last frame. Since PL sends data first, and waits for PS to read it, PL sends data again. In this way, each frame sent is a complete frame for the S2MM_CMD channel, and EOF is fixed to 1. [N+31:32] is SADDR, which indicates the starting address of the transmission, where N indicates the address depth of the memory mapping, which should be a multiple of 8. Since PL sends data to PS and PS sends data to PL in both directions, the addresses cannot conflict, so it is necessary to divide it into different address segments. The address segment written by PS is 2a000000~2a7fffff, and the address segment written by PL is 2a800000~2affffff. The starting address is 2a800000, and the programmable logic write address signal pl_wr_addr is 2a800000 in hexadecimal.Fill the remaining unused bits with 0. Assign pl_wr_len and pl_wr_addr to S_AXIS_S2MM_CMD_tdata according to the format, and the value is hexadecimal 72'h2a80000040804000. At the same time, set the signal S_AXIS_S2MM_CMD_tvalid indicating that the S_AXIS_S2MM_CMD_tdata signal is valid to a high level and send it to DATAMOVER.

[0023] Step 4. When PL captures the data channel S_AXIS_S2MM from PL to PS of DATAMOVER and the preparation signal S_AXIS_S2MM_tready is high, the data is assigned to S_AXIS_S2MM_tdata, and it is sent to DATAMOVER along with the valid bit indication S_AXIS_S2MM_tkeep, the valid signal S_AXIS_S2MM_tvalid and the last data indication S_AXIS_S2MM_tlast. After PL sends a whole frame of data to the S2MM_CMD channel of DATAMOVER, give the S2MM_CMD channel enough response time, such as 64 units of time, and then capture the ready signal S_AXIS_S2MM_tready of the data channel S2MM_DATA. When the ready signal is high, according to business needs, control PL to send data to DATAMOVER. This data can be a test stimulus generated by itself, such as an increasing sequence or a decreasing sequence, or real business data. At the same time, this data needs to meet the AXI_STREAM protocol. When the receiver is ready to receive the signal, it sends a high-level ready signal to the sender. At the same time, after the sender receives the high-level ready signal from the receiver, it assigns the data to S_AXIS_S2MM_tdata, and sends it and the valid indication S_AXIS_S2MM_tvalid, the data valid bit indication S_AXIS_S2MM_tkeep and the last data indication S_AXIS_S2MM_tlast to DATAMOVER.

[0024] Step 5. When PL has sent a whole frame of data, the signal pl_wr_done is set to a pulse signal, and this signal is output to PS as a rising edge interrupt trigger. When PL has sent a whole frame of data to DATAMOVER, the signal pl_wr_done is set to a high level for one unit clock cycle, and this signal is output to PS as a rising edge interrupt trigger, indicating that PL has sent a whole frame of data to DATAMOVER.

[0025] Step 6. When the PS captures the rising edge of the pl_wr_done signal, it reads from the address corresponding to the PS DDR. When the PS reads a complete frame of data, it pulls the signal ps_rd_done high and outputs it to the PL through the register. When the PS captures the rising edge of the pl_wr_done signal, it reads from the address corresponding to the PS DDR. When the PS reads a complete frame of data, it pulls the signal ps_rd_done high and outputs it to the PL through the register.

[0026] Step 7. When PL captures the rising edge of the ps_rd_done signal, it continues to send data to the PS and repeats the operation of step 3. When PL captures the rising edge of the ps_rd_done signal, it continues to send the next frame of data to the DATAMOVER IP and repeats the operation of step 3.

[0027] Step 8. When PL captures the command channel MM2S_CMD from PS of DATAMOVER to PL, and the preparation signal S_AXIS_MM2S_CMD_tready is high, PL assigns ps_wr_len and ps_wr_addr to the data signal S_AXIS_MM2S_CMD_tdata, sets it and the valid signal S_AXIS_MM2S_CMD_tvalid to high and sends them to DATAMOVER. When PL captures the command channel MM2S_CMD from PS of DATAMOVER to PL, when the S_AXIS_MM2S_CMD_tready signal is high, it means that the MM2S_CMD channel is ready. At this time, PL can send the relevant data signal S_AXIS_MM2S_CMD_tdata to DATAMOVER IP. Because its format is defined by XILINX, it is 72 bits in total, where [22:0] is BIT indicating the byte length of the transmitted data in bytes. If the length of the data to be sent is 2048 and the data bit width is 64 bits, the length needs to be set to 2048*64bit / 8byte=16384 according to the format, which is converted to hexadecimal 4000, that is, the PS write length signal ps_wr_len is hexadecimal 4000.

[23] is TYPE, which indicates the burst type of AXI. The value 0 indicates that the burst transmission type is fixed. The data is stored in the starting address and the old value will be overwritten. The value 1 indicates that the burst transmission type is INCR. The data will be stored in the address that increases from the starting address, that is, according to the burst length, only the starting address of the current burst needs to be written at the first burst each time. TYPE is fixed to 1.

[30] is EOF, which indicates whether the frame sent this time is the last frame. The value 0 indicates that the frame sent this time is not the last frame, and the value 1 indicates that the frame sent this time is the last frame. Since PL sends data first, and waits for PS to read it, PL sends data again. In this way, the frame is sent and read one by one. For the MM2S_CMD channel, each frame sent is a complete frame. EOF is fixed to 1. [N+31:32] is SADDR, which indicates the starting address of the transmission, where N indicates the address depth of the memory mapping, which should be a multiple of 8. Since the data sent from PL to PS and from PS to PL are bidirectional, the addresses cannot conflict, so they need to be divided into different address segments. The address segment written by PS is divided into 2a000000~2a7fffff, and the address segment written by PL is divided into 2a800000~2affffff. The starting address is 2a800000, and the PS write address signal ps_wr_addr is hexadecimal 2a000000. The remaining unused bits are filled with 0.Assign ps_wr_len and ps_wr_addr to S_AXIS_MM2S_CMD_tdata in the format of 72'h2a00000040804000 in hexadecimal. It indicates whether the frame sent this time is the last frame, where the value 1 indicates that the frame sent this time is the last frame, [N+31:32] indicates the starting address of the transmission, where N indicates the address depth of the memory mapping, which should be a multiple of 8, and the remaining bits are not used and are filled with 0. At the same time, the signal S_AXIS_MM2S_CMD_tvalid indicating that the S_AXIS_MM2S_CMD_tdata signal is valid is sent to DATAMOVER.

[0028] Step 9. When the PS captures the read address and read length in the data channel M_AXI_MM2S from the PS to the PL of the DATAMOVER, the PS writes data to the PS DDR. When the PS finishes writing a whole frame of data, it sets the ps_wr_done signal to a high level through the register and outputs it to the PL. When the PS is ready to receive the read address and read length in the data channel M_AXI_MM2S from the PS to the PL of the DATAMOVER, it first sends a high-level preparation signal M_AXI_MM2S_arready to the DATAMOVER IP, and then receives the read address M_AXI_MM2S_araddr and read length M_AXI_MM2S_arlen. The PS writes data of a specified length to the address specified by the PS DDR according to the read address and read length. When the PS finishes writing a whole frame of data, it sets the ps_wr_done signal to a high level through the register and outputs it to the PL. When PL captures ps_wr_done as high level, since PS has no concept of clock and cannot accurately control the time when the signal ps_wr_done is set to high level or low level, PL needs to take its rising edge as the judgment condition for reading data from DATAMOVER IP, indicating that PS has completed writing a whole frame of data to the address corresponding to PS DDR.

[0029] Step 10. When PL captures the data channel S_AXIS_MM2S from PS to PL of DATAMOVER and the preparation signal S_AXIS_MM2S_tready is high, the data S_AXIS_MM2S_tdata, the valid bit indication S_AXIS_MM2S_tkeep, the valid signal S_AXIS_MM2S_tvalid and the last data indication S_AXIS_MM2S_tlast are read. Give the MM2S_CMD channel enough response time, for example, 64 unit clock cycles, and then PL sends the ready signal S_AXIS_MM2S_tready in the data channel MM2S_DATA from PS to PL to DATAMOVER, and sets it to a high level. At the same time, the received data needs to follow the AXI_STREAM protocol. When DATAMOVER receives the high-level ready signal sent by PL, it sends the data, data valid indication, data valid bit indication and the last data indication to PL, that is, PL reads the data S_AXIS_MM2S_tdata, the valid bit indication S_AXIS_MM2S_tkeep, the valid signal S_AXIS_MM2S_tvalid and the last data indication S_AXIS_MM2S_tlast from DATAMOVER.

[0030] Step 11. When PL has finished reading a whole frame of data, the signal pl_rd_done is set to a pulse signal and output to PS as a rising edge interrupt trigger. When PL has finished reading a whole frame of data from DATAMOVER, the signal pl_rd_done is set to a high level for one unit clock cycle and output to PS as a rising edge interrupt trigger. At this time, PL has finished reading a whole frame of data from DATAMOVER.

[0031] Step 12: When the PS captures the rising edge of the pl_rd_done signal, continue to write data to the PS DDR and repeat the operation of step 8. When the PS captures the rising edge of the pl_rd_done signal, decide whether to continue writing the next frame of data to the PS DDR according to business needs. If you need to continue writing data to the PS DDR, repeat the operation of step 8.

[0032] Embodiment 2:

[0033] An embodiment of the present invention provides a low-complexity full-duplex DMA communication device, the device comprising: A register definition module, configured to define register signals, including a PL write enable signal, a PL write length signal, a PL write address signal, a PS write enable signal, a PS write length signal, and a PS write address signal; The communication selection module is configured to enter the PL-PS communication module when the PL write enable signal is set to a high level, and enter the PS-PL communication module when the PS write enable signal is set to a high level; The PL-PS communication module is configured to assign the PL write length signal and the PL write address signal to the data signal S_AXIS_S2MM_CMD_tdata when the PL captures the ready signal S_AXIS_S2MM_CMD_tready in the command channel S2MM_CMD from PL to PS of DATAMOVER as high, and set it and the valid signal S_AXIS_S2MM_CMD_tvalid to high and send them to DATAMOVER; When PL captures the data channel S_AXIS_S2MM from PL to PS of DATAMOVER, and the preparation signal S_AXIS_S2MM_tready is high, the PL write length signal and the PL write address signal are assigned to S_AXIS_S2MM_tdata, and the valid bit indication S_AXIS_S2MM_tkeep, the valid signal S_AXIS_S2MM_tvalid and the last data indication S_AXIS_S2MM_tlast are sent to DATAMOVER; When PL has sent a whole frame of data, the signal pl_wr_done is set to a pulse signal and output to PS as a rising edge interrupt trigger; When the PS captures the rising edge of the pl_wr_done signal, it reads data from the address corresponding to the PS DDR. When the PS reads the complete frame data, it pulls the signal ps_rd_done high and outputs it to the PL. When PL captures the rising edge of the signal ps_rd_done, it continues to send data to PS; The PS-PL communication module is configured such that when the PL captures the ready signal S_AXIS_MM2S_CMD_tready in the command channel MM2S_CMD from the PS to the PL of the DATAMOVER as high, the PL assigns the PS write length signal and the PS write address signal to the data signal S_AXIS_MM2S_CMD_tdata, sets it and the valid signal S_AXIS_MM2S_CMD_tvalid to high levels and sends them to the DATAMOVER; When PS captures the read address and read length in the data channel M_AXI_MM2S from PS to PL of DATAMOVER, it writes data to PS DDR. When PS finishes writing a whole frame of data, it sets the signal ps_wr_done to a high level and outputs it to PL. When PL captures the ready signal S_AXIS_MM2S_tready in the data channel S_AXIS_MM2S from PS to PL of DATAMOVER as high, it reads the data S_AXIS_MM2S_tdata, the valid bit indication S_AXIS_MM2S_tkeep, the valid signal S_AXIS_MM2S_tvalid and the last data indication S_AXIS_MM2S_tlast; When PL finishes reading a whole frame of data, it sets the signal pl_rd_done to a pulse signal and outputs it to PS as a rising edge interrupt trigger; When the PS captures the rising edge of the signal pl_rd_done, it continues to write data to the PS DDR.

[0034] Embodiment three:

[0035] Based on the low-complexity full-duplex DMA communication method provided in Embodiment 1, an embodiment of the present invention provides an electronic device, including a processor and a storage medium; The storage medium is used to store instructions; The processor is used to operate according to the instructions to execute the steps according to the above method.

[0036] Embodiment 4:

[0037] Based on the low-complexity full-duplex DMA communication method provided in the first embodiment, an embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps of the above method are implemented.

[0038] Embodiment five:

[0039] Based on the low-complexity full-duplex DMA communication method provided in the first embodiment, an embodiment of the present invention provides a computer program product, including a computer program / instruction, which implements the steps of the above method when executed by a processor.

[0040] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0041] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0042] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0043] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0044] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A low-complexity full-duplex DMA communication method, characterized in that: The following steps are involved: Step 1, define register signals, including PL write enable signal, PL write length signal, PL write address signal, PS write enable signal, PS write length signal, PS write address signal; Step 2: When the PL write enable signal is set to a high level, proceed to step 3; when the PS write enable signal is set to a high level, proceed to step 8; Step 3, when PL captures the ready signal S_AXIS_S2MM_CMD_tready in the command channel S2MM_CMD from PL to PS of DATAMOVER as high, assign the PL write length signal and the PL write address signal to the data signal S_AXIS_S2MM_CMD_tdata, and set it and the valid signal S_AXIS_S2MM_CMD_tvalid to high and send them to DATAMOVER; Step 4, when PL captures the data channel S_AXIS_S2MM from PL to PS of DATAMOVER, and the preparation signal S_AXIS_S2MM_tready is high, the PL write length signal and the PL write address signal are assigned to S_AXIS_S2MM_tdata, and the valid bit indication S_AXIS_S2MM_tkeep, the valid signal S_AXIS_S2MM_tvalid and the last data indication S_AXIS_S2MM_tlast are sent to DATAMOVER; Step 5: After PL has sent a whole frame of data, the signal pl_wr_done is set to a pulse signal and output to PS as an interrupt trigger of the rising edge; Step 6: When the PS captures the rising edge of the pl_wr_done signal, it reads data from the address corresponding to the PS DDR. When the PS reads the complete frame data, it pulls the signal ps_rd_done high and outputs it to the PL. Step 7: When PL captures the rising edge of the signal ps_rd_done, it continues to send data to PS and returns to step 3; Step 8. When PL captures the ready signal S_AXIS_MM2S_CMD_tready in the command channel MM2S_CMD from PS to PL of DATAMOVER as high, PL assigns the PS write length signal and the PS write address signal to the data signal S_AXIS_MM2S_CMD_tdata, sets it and the valid signal S_AXIS_MM2S_CMD_tvalid to high and sends them to DATAMOVER; Step 9. After the PS captures the read address and read length in the data channel M_AXI_MM2S from the PS to the PL of DATAMOVER, it writes data to the PS DDR. After the PS finishes writing a whole frame of data, it sets the signal ps_wr_done to a high level and outputs it to the PL. Step 10, when PL captures the ready signal S_AXIS_MM2S_tready in the data channel S_AXIS_MM2S from PS to PL of DATAMOVER as high level, read the data S_AXIS_MM2S_tdata, the valid bit indication S_AXIS_MM2S_tkeep, the valid signal S_AXIS_MM2S_tvalid and the last data indication S_AXIS_MM2S_tlast; Step 11: After PL has read a whole frame of data, the signal pl_rd_done is set as a pulse signal and output to PS as a rising edge interrupt trigger; Step 12: When the PS captures the rising edge of the signal pl_rd_done, it continues to write data to the PS DDR and returns to step 8.

2. A low-complexity full-duplex DMA communication method according to claim 1, characterized in that: The PL write enable signal, the PL write length signal and the PL write address signal are respectively a permission signal for controlling the PL to send data to the PS, a data length signal and an address signal; The PS write enable signal, the PS write length signal, and the PS write address signal are respectively a permission signal, a data length signal, and an address signal for controlling the PS to send data to the PL.

3. A low-complexity full-duplex DMA communication method according to claim 1, characterized in that: The data signal S_AXIS_S2MM_CMD_tdata has a total of 72 bits; [22:0] is BIT, indicating the byte length of the transmitted data; [23] is TYPE, indicating the burst type of AXI; [30] is EOF, indicating whether the frame sent this time is the last frame; [N+31:32] is SADDR, indicating the starting address of the transmission, where N indicates the address depth of the memory mapping; the remaining bits are 0.

4. A low-complexity full-duplex DMA communication device, characterized in that: The device comprises: A register definition module, configured to define register signals, including a PL write enable signal, a PL write length signal, a PL write address signal, a PS write enable signal, a PS write length signal, and a PS write address signal; The communication selection module is configured to enter the PL-PS communication module when the PL write enable signal is set to a high level, and enter the PS-PL communication module when the PS write enable signal is set to a high level; The PL-PS communication module is configured to assign the PL write length signal and the PL write address signal to the data signal S_AXIS_S2MM_CMD_tdata when the PL captures the ready signal S_AXIS_S2MM_CMD_tready in the command channel S2MM_CMD from PL to PS of DATAMOVER as high, and set it and the valid signal S_AXIS_S2MM_CMD_tvalid to high and send them to DATAMOVER; When PL captures the data channel S_AXIS_S2MM from PL to PS of DATAMOVER, and the preparation signal S_AXIS_S2MM_tready is high, the PL write length signal and the PL write address signal are assigned to S_AXIS_S2MM_tdata, and the valid bit indication S_AXIS_S2MM_tkeep, the valid signal S_AXIS_S2MM_tvalid and the last data indication S_AXIS_S2MM_tlast are sent to DATAMOVER; When PL has sent a whole frame of data, the signal pl_wr_done is set to a pulse signal and output to PS as a rising edge interrupt trigger; When the PS captures the rising edge of the pl_wr_done signal, it reads data from the address corresponding to the PS DDR. When the PS reads the complete frame data, it pulls the signal ps_rd_done high and outputs it to the PL. When PL captures the rising edge of the signal ps_rd_done, it continues to send data to PS; The PS-PL communication module is configured such that when the PL captures the ready signal S_AXIS_MM2S_CMD_tready in the command channel MM2S_CMD from the PS to the PL of the DATAMOVER as high, the PL assigns the PS write length signal and the PS write address signal to the data signal S_AXIS_MM2S_CMD_tdata, sets it and the valid signal S_AXIS_MM2S_CMD_tvalid to high levels and sends them to the DATAMOVER; When PS captures the read address and read length in the data channel M_AXI_MM2S from PS to PL of DATAMOVER, it writes data to PS DDR. When PS finishes writing a whole frame of data, it sets the signal ps_wr_done to a high level and outputs it to PL. When PL captures the ready signal S_AXIS_MM2S_tready in the data channel S_AXIS_MM2S from PS to PL of DATAMOVER as high, it reads the data S_AXIS_MM2S_tdata, the valid bit indication S_AXIS_MM2S_tkeep, the valid signal S_AXIS_MM2S_tvalid and the last data indication S_AXIS_MM2S_tlast; When PL finishes reading a whole frame of data, it sets the signal pl_rd_done to a pulse signal and outputs it to PS as a rising edge interrupt trigger; When the PS captures the rising edge of the signal pl_rd_done, it continues to write data to the PS DDR.

5. An electronic device, characterized in that: including processor and storage medium; The storage medium is used to store instructions; The processor is configured to operate according to the instructions to execute the steps of the method according to any one of claims 1-3.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

7. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

Images