Chip pin multiplexing system, SOC chip and method

Abstract

This invention relates to a chip pin multiplexing system, a System-on-a-Chip (SoC) chip, and a method. By designing a PINMUX component and adding a PINMUX mode pin, the value of the PINMUX mode pin is automatically latched into a pin mode register upon chip startup. The hardware reads the value in the pin mode register to determine the configuration mode of the PINMUX register, thus allowing for flexible selection of the pin multiplexing configuration mode. Simultaneously, the pin multiplexing configuration of each component is combined with the component's gated clock. While switching the component's gated clock, the hardware automatically configures the corresponding component's pin multiplexing configuration register. In hardware configuration mode, the pin multiplexing configuration process is streamlined, solving the technical problems of complex pin multiplexing configuration and manual configuration errors at the hardware level. It also avoids errors caused by hot switching of components during use, improves post-silicon testing efficiency, and significantly enhances the efficiency of chip pin multiplexing.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and relates to a chip pin multiplexing system, a SOC chip, and a method. Background Technology

[0002] With advancements in process technology, the performance of System on Chip (SoC) continues to improve while its circuit area shrinks, limiting the number of chip pins. Therefore, given the limited number of pins and package size, multiplexers are often used in complex SoC designs to multiplex chip pins to optimize resource utilization for different operating scenarios, thereby improving chip resource utilization through flexible resource allocation.

[0003] Clock gating, a commonly used low-power control technique, is prevalent in digital circuit design. Turning off the clock signals of idle or non-functional components in a design via clock gating is one of the most successful and widely applied methods for reducing power consumption. The goal of clock gating is to disable temporarily unused chip components (such as flip-flops, clock networks, and logic gates) under certain conditions. The power savings primarily come from reducing the number of switched capacitors and the switching coefficient, because some non-essential transistors are turned off when the clock frequency is idle.

[0004] Currently, some traditional technologies related to pin multiplexing have emerged, such as object-oriented chip-level port interconnect circuits and their port interconnection methods, and custom integrated circuits that include one or more sets of hardwired connections, allowing communication between any input / output (I / O) pins and onboard peripherals. Other examples include chip pin multiplexing communication methods and chips using them, automatic pin multiplexing circuit generation methods implemented using scripting languages, and chip pin function multiplexing circuit generation methods. However, these traditional technologies still suffer from the technical problem of low pin multiplexing efficiency. Summary of the Invention

[0005] To address the problems existing in the above-mentioned traditional technologies, this invention proposes a chip pin multiplexing system, a SOC chip, and a chip pin multiplexing method, which can significantly improve the efficiency of chip pin multiplexing.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0007] On the one hand, a chip pin multiplexing system is provided, including a PINMUX register module and a pin control module. The PINMUX register module is used to connect to the chip's internal host and clock gating respectively, and is used to output valid values ​​to the pin control module. The pin control module is used to connect the chip's PAD and components that interact with the outside via the chip pin multiplexing system.

[0008] When the chip starts up, the value of the PINMUX mode pin of the PINMUX register module is automatically latched in the pin mode register; the value in the pin mode register is used to determine the configuration mode of the PINMUX register module after being read by the hardware. The configuration mode includes software configuration mode and hardware configuration mode.

[0009] In software configuration mode, the valid value output by the PINMUX register module is selected by the internal host through software configuration. In hardware configuration mode, the valid value output by all PINMUX registers in the PINMUX register module is the pre-configured value of the PINMUX register corresponding to the target component, which is automatically selected based on the clock gating enable of the target component.

[0010] The pin control module uses one-hot encoding to control the behavior of the chip's PADs and the pins that interact with external components via the chip's pin multiplexing system, based on the valid value output by the PINMUX register module. The pin control module is equipped with an input isolation signal to ensure that data and control signals input from components that are not currently configured with PINMUX register strobe are invalid.

[0011] On the other hand, a SOC chip is also provided, including an internal host, a clock gating system, a PAD, and the aforementioned chip pin multiplexing system.

[0012] On the other hand, a chip pin multiplexing method is also provided, which is applied to a chip pin multiplexing system. The chip pin multiplexing system includes a PINMUX register module and a pin control module. The PINMUX register module is used to connect the chip's internal host and clock gating respectively, and is used to output valid values ​​to the pin control module. The pin control module is used to connect the chip's PAD and components that interact with the outside via the chip pin multiplexing system.

[0013] When the chip starts up, the value of the PINMUX mode pin of the PINMUX register module is automatically latched in the pin mode register; the value in the pin mode register is used to determine the configuration mode of the PINMUX register module after being read by the hardware. The configuration mode includes software configuration mode and hardware configuration mode.

[0014] In software configuration mode, the valid value output by the PINMUX register module is selected by the internal host through software configuration. In hardware configuration mode, the valid value output by all PINMUX registers in the PINMUX register module is the pre-configured value of the PINMUX register corresponding to the target component, which is automatically selected based on the clock gating enable of the target component.

[0015] The pin control module uses one-hot encoding to control the behavior of the chip's PADs and the pins that interact with external components via the chip's pin multiplexing system, based on the valid value output by the PINMUX register module. The pin control module is equipped with an input isolation signal to ensure that data and control signals input from components that are not currently configured with PINMUX register strobe are invalid.

[0016] The chip pin multiplexing method includes the following steps:

[0017] Determine the configuration mode of the PINMUX register in the PINMUX register module;

[0018] When the PINMUX register is in software configuration mode, the PINMUX register is read and written through the chip's internal host to route the signal corresponding to the target component to the corresponding pin.

[0019] One of the above technical solutions has the following advantages and beneficial effects:

[0020] The aforementioned chip pin multiplexing system, SOC chip, and method, by designing a PINMUX component consisting of a PINMUX register module and a pin control module, adds a PINMUX mode pin. This allows the chip to automatically latch the value of the PINMUX mode pin into the PINMODE register upon startup. The hardware reads the value in the PINMODE register to determine the configuration mode of the PINMUX register, thus enabling flexible selection of the pin multiplexing configuration mode. Simultaneously, the pin multiplexing configuration of each component is combined with the component's gated clock. While switching the component's gated clock, the hardware automatically configures the corresponding component's pin multiplexing configuration register. In hardware configuration mode, this saves on the multiplexing pin configuration process, solving the technical problems of complex multiplexing pin configuration and manual configuration errors at the hardware level. It also avoids errors caused by hot switching during component use, improves post-silicon testing efficiency, and, combined with clock gating technology, effectively optimizes power consumption and reduces unnecessary signal toggling. In addition, for each multiplexed pin, an input isolation signal is added to the pin control module based on the valid state of the multiplexed signal. This ensures that the input data and control signals are invalid when the PINMUX register is not configured for strobing, thus avoiding functional abnormalities caused by external inputs at the hardware level and significantly improving the efficiency of pin multiplexing. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the overall structure of a chip pin multiplexing system in one embodiment;

[0023] Figure 2 This is a schematic diagram of the implementation structure of the PINMUX register module in one embodiment;

[0024] Figure 3 This is a schematic diagram of the input and output signals of a single pin control module in one embodiment;

[0025] Figure 4 This is a schematic diagram illustrating the usage process of a chip pin multiplexing system in one embodiment;

[0026] Figure 5 This is a schematic diagram of the software configuration mode workflow of a chip pin multiplexing method in one embodiment. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0028] It should be noted that, in this document, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items, and all possible combinations thereof.

[0029] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0030] In complex system-on-chip (SoC) designs, multiplexers are used to multiplex signals from chip pins. When using a target component, the corresponding pin multiplexing (PINMUX) register needs to be configured in software to select the pin as the signal of the target component. However, in large-scale SoC designs, the multiplexing situation is often quite complex, leading to problems such as complex pin multiplexing configurations and the inability to control the pins with only software configuration. If the pin multiplexing configuration is incorrect, the target component will not function properly, and the resulting anomalies are difficult to troubleshoot. When performing post-silicon testing on components with complex multiplexing situations, configuration or usage errors are often caused by human factors, which slows down the chip debugging progress and affects the project development cycle.

[0031] However, in object-oriented chip-level port interconnect circuits and their port interconnection methods, the pin multiplexing configuration is fixed and does not support automatic configuration. To control the connection path between the PAD module and each IP (Intellectual Property Core) core in the circuit, the IOCTRL control unit of the PINMUX unit needs to be configured by the CPU, resulting in a cumbersome configuration process. This method is actually a widely applicable pin multiplexing design method, used to quickly and efficiently complete the interconnection requirements between various IP core ports during chip development, but it does not consider implementing automatic configuration of the connection path between the PAD module and each IP core in the logic design to reduce the cumbersome configuration process. Custom integrated circuits containing one or more hardwired connections, allowing communication between any input / output (I / O) pins and onboard peripherals, and traditional technologies such as chip pin multiplexing communication methods and chips using these methods, do not involve pin multiplexing configuration methods. Their focus is on solving various problems caused by pin multiplexing, such as the limited use of various peripheral combinations due to pin multiplexing conflicts, and the inability to directly reuse existing chip pins due to limitations such as the chip's pin operating environment and chip performance requirements, without considering pin multiplexing configuration methods. Traditional technologies, such as automatic pin multiplexing circuit generation methods based on scripting languages ​​and chip pin function multiplexing circuit generation methods, require manual configuration of pin multiplexing according to the pin function correspondence. They cannot achieve automatic configuration of the pin multiplexing control module and therefore do not take into account the convenience of the pin multiplexing configuration process.

[0032] In one embodiment, such as Figure 1As shown, a chip pin multiplexing system is provided, including a PINMUX register module and a pin control module. The PINMUX register module is used to connect to the chip's internal host and clock gating respectively, and is used to output valid values ​​to the pin control module. The pin control module is used to connect the chip's PADs and components that interact with the outside world via the chip pin multiplexing system. During chip startup, the values ​​of the PINMUX mode pins of the PINMUX register module are automatically latched in the pin mode register; the values ​​in the pin mode register are used by the hardware to determine the configuration mode of the PINMUX register module, which includes a software configuration mode and a hardware configuration mode.

[0033] In software configuration mode, the valid values ​​output by the PINMUX register module are selected by the internal host through software configuration. In hardware configuration mode, the valid values ​​output by all PINMUX registers in the PINMUX register module are automatically selected based on the clock gating enable of the target component, choosing the corresponding pre-configured PINMUX register value. The pin control module uses one-hot encoding to control the behavior of the chip's PADs and the multiplexed pins between the chip and external components via the chip's pin multiplexing system, based on the valid values ​​output by the PINMUX register module. The pin control module includes an input isolation signal to ensure that data and control signals input from components not currently configured with PINMUX register gating are invalid.

[0034] It is understood that this embodiment proposes a chip pin multiplexing design scheme that supports flexible configuration (hereinafter referred to as PINMUX component). Pin multiplexing supports software configuration mode or hardware configuration mode. In software configuration mode, the multiplexing status of each pin can be flexibly configured by software. In hardware configuration mode, by combining clock gating technology with pin multiplexing, the pin multiplexing system can support hardware configuration mode. Through clock gating enable, the hardware automatically completes the pin multiplexing configuration, eliminating the complex pin multiplexing configuration process in traditional technology. It solves the technical problems of complex pin multiplexing configuration and configuration or usage errors caused by human factors from the hardware level, avoids errors caused by hot switching of components during use, improves post-silicon testing efficiency, and can effectively optimize system power consumption when combined with clock gating technology.

[0035] Specifically, the designed PINMUX component consists of two parts: the PINMUX register module and the pin control module, with the overall structure as follows: Figure 1As shown, the PINMUX component serves as an intermediary for communication between the chip and the external environment. Internally, it connects all components that interact with the outside world via the PINMUX. Externally, it interacts with external devices through PADs (such as PAD0 to PADn, where n is the total number of pins). Here, PAD refers to a pin on the silicon wafer, which is packaged inside the chip. The type of PAD is determined by the tape-out process. There can be multiple pin control modules, such as pin control 0 to pin control n.

[0036] The aforementioned chip pin multiplexing system, through the design of a PINMUX component consisting of a PINMUX register module and a pin control module, adds a PINMUX mode pin. This allows the chip to automatically latch the value of the PINMUX mode pin into the PINMODE register upon startup. The hardware reads the value in the PINMODE register to determine the configuration mode of the PINMUX register, thus enabling flexible selection of the pin multiplexing configuration mode. Simultaneously, the pin multiplexing configuration of each component is combined with the component's gated clock. While switching the component's gated clock, the hardware automatically configures the corresponding component's pin multiplexing configuration register. In hardware configuration mode, this saves on the multiplexing pin configuration process, solving the technical problems of complex multiplexing pin configuration and manual configuration errors at the hardware level. It also avoids errors caused by hot switching of components during use, improves post-silicon testing efficiency, and, combined with clock gating technology, effectively optimizes power consumption and reduces unnecessary signal toggling. In addition, for each multiplexed pin, an input isolation signal is added to the pin control module based on the valid state of the multiplexed signal. This ensures that the input data and control signals are invalid when the PINMUX register is not configured for strobing, thus avoiding functional abnormalities caused by external inputs at the hardware level and significantly improving the efficiency of pin multiplexing.

[0037] In one embodiment, such as Figure 2 As shown, the PINMUX register module includes a pin mode register (i.e., the PINMODE register), a PINMUX register corresponding to the software configuration mode (which can be denoted as RG1), a PINMUX register corresponding to the hardware configuration mode (which can be denoted as RG2), and an output register (which can be denoted as RG3). The input terminal of the pin mode register is connected to the PINMUX mode pin, and the output terminal of the pin mode register is connected to the control terminal of the output register. The PINMUX register corresponding to the software configuration mode stores the value configured by the internal host through software and is connected to the first input channel of the output register.

[0038] The PINMUX register corresponding to the hardware configuration mode is used to store the PINMUX register pre-configuration value corresponding to the target component and is connected to the second input channel of the output register. The output terminal of the output register is connected to the pin control module. When the value in the pin mode register corresponds to the software configuration mode, the output terminal of the output register is connected to the first input channel. When the value in the pin mode register corresponds to the hardware configuration mode, the output terminal of the output register is connected to the second input channel.

[0039] It is understandable that the PINMUX register module is used to implement the selection of PINMUX configuration mode, handle register read and write requests from the internal host (such as the CPU or other processors), and control the output of valid PINMUX register values.

[0040] The implementation structure of the PINMUX register module can be as follows: Figure 2 As shown. The configuration mode of the PINMUX register module is selected by the PINMUX mode pin (an external pin of the chip). During chip startup, the value of the PINMUX mode pin is automatically latched into the PINMODE (pin mode) register. The hardware reads the value in the PINMODE register to determine the configuration mode of the PINMUX register module. The settings of the PINMODE register are described in Table 1 below:

[0041] Table 1

[0042]

[0043] In Table 1, the domain control R indicates read-only.

[0044] The PINMUX register module supports read and write requests from internal hosts such as the CPU. The value of the PINMUX register can be arbitrarily configured via the CPU, such as... Figure 2 The CPU reads and writes to the PINMUX register, which is referred to as the PINMUX register RG1 corresponding to the software configuration mode. The valid values ​​output by the PINMUX register module are controlled by the value read from the PINMODE register. If the value read from the PINMODE register is high (i.e., level 1), the software configuration mode is selected. In this mode, all valid values ​​output by the PINMUX register module are selected from the values ​​configured by the software (i.e., the PINMUX register values ​​configured by the CPU).

[0045] If the value of the PINMODE register is low (i.e., level 0), the hardware configuration mode is selected. In this mode, the hardware pre-configures the PINMUX registers on a component-by-component basis. All PINMUX registers automatically select the pre-configured value corresponding to the target component based on the clock gating enable of each target component (i.e., each functional component that currently needs to use pin multiplexing). The clock gating enable of each target component comes from the module-level clock gating controller, which is used to control the enabling and disabling of the gating clock transmitted to each target component. For example, when the clock gating enable of component A is turned on, the value of the PINMUX register used by component A is simultaneously rewritten to the pre-configured value of the PINMUX register corresponding to component A. These PINMUX registers used at this time are called PINMUX register RG2 corresponding to the hardware configuration mode.

[0046] In one embodiment, optionally, the configuration mode of the PINMUX register selected corresponding to the value of the PINMODE register can also be the opposite of the above implementation. For example, if the value of the PINMODE register is high, the hardware configuration mode is selected; if the value of the PINMODE register is low, the software configuration mode is selected. As long as it can be used to achieve the desired control effect, it is acceptable.

[0047] In one embodiment, the pin control module includes multiple modules, and each pin control module includes:

[0048] The judgment signal originates from the PINMUX register module and is used to control the selection of multiplexed pins.

[0049] The pad_c signal originates from PAD and indicates that data has been received from the chip's internal components via the pin.

[0050] An input isolation signal is connected to a fixed value according to the signal polarity to ensure that data and control signals input to components that are not currently configured with PINMUX register strobe are invalid.

[0051] The signal_ren signal originates from the PINMUX register module and is used to enable the pull-up and pull-down resistors of the PAD corresponding to the switch multiplexing pin.

[0052] The signal_x_en signal originates from all components that interact with the outside world via the chip pin multiplexing system and is used to indicate the signal transmission direction of each component.

[0053] The signal_x_u2p signal originates from all components that interact with the outside world via the chip pin multiplexing system and is used to indicate the data that each component needs to send to the pin; x is a positive integer.

[0054] The pad_i signal is the signal output to the PAD, indicating the data that the target component needs to send to the pin;

[0055] The pad_ren signal is the signal output to the PAD, indicating that the pull-up and pull-down resistors of the PAD corresponding to the switch multiplexing pin are enabled;

[0056] The signal_x_p2u signal represents the data input to all components that interact with the outside world via the chip pin multiplexing system.

[0057] It can be understood that the pin control module is used to control the behavior of multiplexed pins. It uses the valid value of the PINMUX register module output as the judgment signal for the multiplexer to select the signal used by each multiplexed pin of the chip at the current moment. A schematic diagram of the input / output signals of a single pin control module is shown below. Figure 3 As shown, the multiplexer used can be flexibly determined based on the number of pin multiplexed signals.

[0058] Taking a 5-to-1 multiplexer as an example, using one-hot encoding, each 4 bits of the PINMUX register controls one multiplexed pin. Figure 3 In the code, the judgment signal pins pinmux[3:0] originate from the PINMUX register module and represent the judgment signal that controls which function the multiplexed pin selects. pad_c originates from PAD and represents the data received from the pin inside the chip. pad_effect[4:0] is a fixed value representing the effective value of the 5 multiplexed signals. signal_ren originates from the PINMUX register module and represents the enable / disable of the pull-up / pull-down resistors of the PAD corresponding to the multiplexed pin. signal_x_en and signal_x_u2p (where x=0 / 1 / 2 / 4 / 8) originate from all components that interact with the outside world through PINMUX and represent the signal transmission direction and the data to be sent to the pin at this moment, respectively. pad_i is the signal output to PAD, representing the data that the target component needs to send to the pin. pad_oen is the signal output to PAD, representing the signal transmission direction of the target component. pad_ren is the signal output to PAD, representing the enable / disable of the pull-up / pull-down resistors of the PAD corresponding to the multiplexed pin. signal_x_p2u (x=0 / 1 / 2 / 4 / 8) represents the data input to all components that interact with the outside world via PINMUX.

[0059] When a multiplexed pin is used as an output, the target component's relevant output signal (such as signal_x_u2p) is routed to the multiplexed pin (pad_i); when a multiplexed pin is used as an input, the signal input from the pin (such as pad_c) is routed to the target component's relevant input signal (such as signal_x_p2u), and an input isolation signal (pad_effect) is added. For components that are not currently configured with PINMUX register strobe, the input data and control signals are ensured to be in an invalid state, thus avoiding functional abnormalities caused by external inputs from a hardware perspective. That is, when pinmux[3:0] is configured as 0, signal_0_p2u comes from pad_c, and the remaining signal_x_p2u (x=1 / 2 / 4 / 8) comes from the inversion of the corresponding bits of pad_effect.

[0060] In some implementations, the workflow of the above-described chip pin multiplexing system can be as follows: Figure 4 As shown:

[0061] Step 1: Determine the configuration mode of the PINMUX register in the PINMUX register module. When the chip starts up, it automatically latches the value of the PINMUX mode pin into the PINMODE register. The hardware reads the value in the PINMODE register to determine the configuration mode of the PINMUX register. If the read value is high, the software configuration mode is selected, proceeding to Step 2; if the read value is low, the hardware configuration mode is selected, proceeding to Step 3.

[0062] Step 2: The current PINMUX register is in software configuration mode. PINMUX register reads and writes are performed through the chip's internal host. The programmer needs to configure the corresponding PINMUX register through the internal host according to the pin multiplexing situation to route the signal corresponding to the target component to the corresponding pin. Assuming a pin has 5 multiplexed signals, the function description and usage of the PINMUX register are shown in Table 2. Each 4 bits control one multiplexed pin. A 32-bit PINMUX register can control 8 multiplexed pins. Taking PINMUX0[3:0] as an example, when these 4 bits are 0x2, function B is selected;

[0063] Table 2

[0064]

[0065] Step 3: The current PINMUX register is in hardware configuration mode. Taking a single component as the smallest unit, the hardware automatically configures the PINMUX register of the target component based on the on / off status of the component's clock gating enable. When the clock gating enable is on, all PINMUX registers automatically select the pre-configured value of the PINMUX register corresponding to the component based on the component's clock gating enable. All multiplexed pins involving the component are selected to function as the component.

[0066] In one embodiment, a SOC chip is also provided, including an internal host, a clock gating system, a PAD, and the aforementioned chip pin multiplexing system.

[0067] It is understood that the descriptions of components such as the internal host, clock gating, and PAD in this embodiment can be understood by referring to the same components already existing in the SOC in this field, and will not be elaborated further in this specification. For a detailed explanation of the chip pin multiplexing system, please refer to the corresponding limitations of the chip pin multiplexing system in the above embodiments, which will not be repeated here.

[0068] By applying the aforementioned chip pin multiplexing system, the SOC chip can effectively improve post-silicon testing efficiency and optimize system power consumption.

[0069] In one embodiment, a chip pin multiplexing method is also provided, applied to a chip pin multiplexing system. The chip pin multiplexing system includes a PINMUX register module and a pin control module. The PINMUX register module is used to connect to the chip's internal host and clock gating respectively, and is used to output valid values ​​to the pin control module. The pin control module is used to connect the chip's PADs and components that interact with the outside world via the chip pin multiplexing system. During chip startup, the values ​​of the PINMUX mode pins of the PINMUX register module are automatically latched in a pin mode register. The values ​​in the pin mode register are used by the hardware to determine the configuration mode of the PINMUX register module, including a software configuration mode and a hardware configuration mode.

[0070] In software configuration mode, the valid values ​​output by the PINMUX register module are selected by the internal host through software configuration. In hardware configuration mode, the valid values ​​output by all PINMUX registers in the PINMUX register module are automatically selected based on the clock gating enable of the target component and the corresponding PINMUX register pre-configured value.

[0071] The pin control module uses one-hot encoding to control the behavior of the chip's PADs and the pins that interact with external components via the chip's pin multiplexing system, based on the valid value output by the PINMUX register module. The pin control module is equipped with an input isolation signal to ensure that data and control signals input from components that are not currently configured with PINMUX register strobe are invalid.

[0072] like Figure 5 As shown, the above-mentioned chip pin multiplexing method may include the following processing steps S10 and S12:

[0073] S10, Determine the configuration mode of the PINMUX register in the PINMUX register module;

[0074] S12, when the PINMUX register is in software configuration mode, the PINMUX register is read and written through the chip's internal host to route the signal corresponding to the target component to the corresponding pin.

[0075] In one embodiment, the above-described chip pin multiplexing method may further include the following steps:

[0076] When the PINMUX register is in hardware configuration mode, a single component is used as the smallest unit. When the clock gating enable of the target component is turned on, the PINMUX register corresponding to the target component automatically selects the pre-configured value of the PINMUX register corresponding to the target component; all multiplexed pins involving the target component are selected as the function of the target component.

[0077] The aforementioned chip pin multiplexing method, through the design of a PINMUX component consisting of a PINMUX register module and a pin control module, adds a PINMUX mode pin. This allows the chip to automatically latch the value of the PINMUX mode pin into the PINMODE register upon startup. The hardware reads the value in the PINMODE register to determine the configuration mode of the PINMUX register, thus enabling flexible selection of the pin multiplexing configuration mode. Simultaneously, the pin multiplexing configuration of each component is combined with the component's gated clock. While switching the component's gated clock, the hardware automatically configures the corresponding component's pin multiplexing configuration register. In hardware configuration mode, this saves on the multiplexing pin configuration process, solving the technical problems of complex multiplexing pin configuration and manual configuration errors at the hardware level. It also avoids errors caused by hot switching during component use, improves post-silicon testing efficiency, and, combined with clock gating technology, effectively optimizes power consumption and reduces unnecessary signal toggling. In addition, for each multiplexed pin, an input isolation signal is added to the pin control module based on the valid state of the multiplexed signal. This ensures that the input data and control signals are invalid when the PINMUX register is not configured for strobing, thus avoiding functional abnormalities caused by external inputs at the hardware level and significantly improving the efficiency of pin multiplexing.

[0078] In one embodiment, the PINMUX register module includes a pin mode register, a PINMUX register corresponding to the software configuration mode, a PINMUX register corresponding to the hardware configuration mode, and an output register.

[0079] The input of the pin mode register is connected to the PINMUX mode pin, and the output of the pin mode register is connected to the control terminal of the output register. The PINMUX register corresponding to the software configuration mode stores the value configured by the internal host through software and is connected to the first input channel of the output register.

[0080] The PINMUX register corresponding to the hardware configuration mode is used to pre-configure the PINMUX register value corresponding to the target component and is connected to the second input channel of the output register. The output terminal of the output register is connected to the pin control module. When the value in the pin mode register corresponds to the software configuration mode, the output terminal of the output register is connected to the first input channel. When the value in the pin mode register corresponds to the hardware configuration mode, the output terminal of the output register is connected to the second input channel.

[0081] In one embodiment, the pin control module includes multiple modules, and each pin control module includes:

[0082] The judgment signal originates from the PINMUX register module and is used to control the selection of multiplexed pins.

[0083] The pad_c signal originates from PAD and indicates that data has been received from the chip's internal components via the pin.

[0084] An input isolation signal is connected to a fixed value according to the signal polarity to ensure that data and control signals input to components that are not currently configured with PINMUX register strobe are invalid.

[0085] The signal_ren signal originates from the PINMUX register module and is used to enable the pull-up and pull-down resistors of the PAD corresponding to the switch multiplexing pin.

[0086] The signal_x_en signal originates from all components that interact with the outside world via the chip pin multiplexing system and is used to indicate the signal transmission direction of each component.

[0087] The signal_x_u2p signal originates from all components that interact with the outside world via the chip pin multiplexing system and is used to indicate the data that each component needs to send to the pin; x is a positive integer.

[0088] The pad_i signal is the signal output to the PAD, indicating the data that the target component needs to send to the pin;

[0089] The pad_ren signal is the signal output to the PAD, indicating that the pull-up and pull-down resistors of the PAD corresponding to the switch multiplexing pin are enabled;

[0090] The signal_x_p2u signal represents the data input to all components that interact with the outside world via the chip pin multiplexing system.

[0091] For a detailed explanation and limitation of the above-mentioned chip pin multiplexing method, please refer to the corresponding limitation of the chip pin multiplexing system in the above text, which will not be repeated here.

[0092] It should be understood that although Figure 5 The steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Figure 5 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0093] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus DRAM (RDRAM), and interface DRAM (DRDRAM), etc.

[0094] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A chip pin multiplexing system, characterized in that, It includes a PINMUX register module and a pin control module. The PINMUX register module is used to connect to the chip's internal host and clock gating respectively, and is used to output valid values ​​to the pin control module. The pin control module is used to connect the chip's PAD and components that interact with the outside via the chip's pin multiplexing system. When the chip starts up, the value of the PINMUX mode pin of the PINMUX register module is automatically latched in the pin mode register; the value in the pin mode register is used to determine the configuration mode of the PINMUX register module after being read by the hardware, and the configuration mode includes software configuration mode and hardware configuration mode. In the software configuration mode, the valid value output by the PINMUX register module is selected by the internal host through software configuration. In the hardware configuration mode, the valid value output by all PINMUX registers in the PINMUX register module is the pre-configured value of the PINMUX register corresponding to the target component, which is automatically selected based on the clock gating enable of the target component. The pin control module uses one-hot encoding to control the behavior of the chip's PADs and the pins that interact with external components via the chip's pin multiplexing system, based on the valid value output by the PINMUX register module. The pin control module includes an input isolation signal to ensure that data and control signals input from components that are not currently configured with PINMUX register strobe are invalid.

2. The chip pin multiplexing system according to claim 1, characterized in that, The PINMUX register module includes a pin mode register, a PINMUX register corresponding to the software configuration mode, a PINMUX register corresponding to the hardware configuration mode, and an output register. The input terminal of the pin mode register is connected to the PINMUX mode pin, and the output terminal of the pin mode register is connected to the control terminal of the output register. The PINMUX register corresponding to the software configuration mode stores the value configured by the internal host through software and is connected to the first input channel of the output register. The PINMUX register corresponding to the hardware configuration mode is used to store the PINMUX register pre-configuration value corresponding to the target component and is connected to the second input channel of the output register. The output terminal of the output register is connected to the pin control module. When the value in the pin mode register corresponds to the software configuration mode, the output terminal of the output register is connected to the first input channel. When the value in the pin mode register corresponds to the hardware configuration mode, the output terminal of the output register is connected to the second input channel.

3. The chip pin multiplexing system according to claim 1 or 2, characterized in that, The pin control module includes multiple modules, and each pin control module includes: The judgment signal originates from the PINMUX register module and is used to control the selection of multiplexed pins. The pad_c signal originates from PAD and indicates that data has been received from the chip's internal components via the pin. An input isolation signal is connected to a fixed value according to the signal polarity to ensure that data and control signals input to components that are not currently configured with PINMUX register strobe are invalid. The signal_ren signal originates from the PINMUX register module and is used to enable the pull-up and pull-down resistors of the PAD corresponding to the switch multiplexing pin. The signal_x_en signal originates from all components that interact with the outside world via the chip's pin multiplexing system and is used to indicate the signal transmission direction of each component. The signal_x_u2p signal originates from all components that interact with the outside world via the chip's pin multiplexing system and is used to indicate the data that each component needs to send to the pin; x is a positive integer. The pad_i signal is the signal output to the PAD, indicating the data that the target component needs to send to the pin; The pad_ren signal is a signal output to the PAD, indicating that the pull-up and pull-down resistors of the PAD corresponding to the switch multiplexing pin are enabled. The signal_x_p2u signal represents the data input to all components that interact with the outside world via the chip's pin multiplexing system.

4. A SOC chip, characterized in that, It includes an internal host, a clock gating system, a PAD, and a chip pin multiplexing system as described in any one of claims 1 to 3.

5. A method for multiplexing chip pins, characterized in that, This invention relates to a chip pin multiplexing system, which includes a PINMUX register module and a pin control module. The PINMUX register module is used to connect to the chip's internal host and clock gating respectively, and to output valid values ​​to the pin control module. The pin control module is used to connect the chip's PAD and components that interact with the outside via the chip pin multiplexing system. When the chip starts up, the value of the PINMUX mode pin of the PINMUX register module is automatically latched in the pin mode register; the value in the pin mode register is used to determine the configuration mode of the PINMUX register module after being read by the hardware, and the configuration mode includes software configuration mode and hardware configuration mode. In the software configuration mode, the valid value output by the PINMUX register module is selected by the internal host through software configuration. In the hardware configuration mode, the valid value output by all PINMUX registers in the PINMUX register module is the pre-configured value of the PINMUX register corresponding to the target component, which is automatically selected based on the clock gating enable of the target component. The pin control module uses one-hot encoding to control the behavior of the chip's PADs and the pins that interact with external components via the chip's pin multiplexing system, based on the valid value output by the PINMUX register module. The pin control module includes an input isolation signal to ensure that data and control signals input from components that are not currently configured with PINMUX register strobe are invalid. The chip pin multiplexing method includes the following steps: Determine the configuration mode of the PINMUX register in the PINMUX register module; When the PINMUX register is in software configuration mode, the PINMUX register is read and written through the chip's internal host to route the signal corresponding to the target component to the corresponding pin.

6. The chip pin multiplexing method according to claim 5, characterized in that, It also includes the following steps: When the PINMUX register is in hardware configuration mode, a single component is used as the smallest unit. When the clock gating enable of the target component is turned on, the PINMUX register corresponding to the target component automatically selects the pre-configured value of the PINMUX register corresponding to the target component; all multiplexed pins involving the target component are selected as the function of the target component.

7. The chip pin multiplexing method according to claim 5 or 6, characterized in that, The PINMUX register module includes a pin mode register, a PINMUX register corresponding to the software configuration mode, a PINMUX register corresponding to the hardware configuration mode, and an output register. The input terminal of the pin mode register is connected to the PINMUX mode pin, and the output terminal of the pin mode register is connected to the control terminal of the output register. The PINMUX register corresponding to the software configuration mode stores the value configured by the internal host through software and is connected to the first input channel of the output register. The PINMUX register corresponding to the hardware configuration mode is used to store the PINMUX register pre-configuration value corresponding to the target component and is connected to the second input channel of the output register. The output terminal of the output register is connected to the pin control module. When the value in the pin mode register corresponds to the software configuration mode, the output terminal of the output register is connected to the first input channel. When the value in the pin mode register corresponds to the hardware configuration mode, the output terminal of the output register is connected to the second input channel.

8. The chip pin multiplexing method according to claim 7, characterized in that, The pin control module includes multiple modules, and each pin control module includes: The judgment signal originates from the PINMUX register module and is used to control the selection of multiplexed pins. The pad_c signal originates from PAD and indicates that data has been received from the chip's internal components via the pin. An input isolation signal is connected to a fixed value according to the signal polarity to ensure that data and control signals input to components that are not currently configured with PINMUX register strobe are invalid. The signal_ren signal originates from the PINMUX register module and is used to enable the pull-up and pull-down resistors of the PAD corresponding to the switch multiplexing pin. The signal_x_en signal originates from all components that interact with the outside world via the chip's pin multiplexing system and is used to indicate the signal transmission direction of each component. The signal_x_u2p signal originates from all components that interact with the outside world via the chip's pin multiplexing system and is used to indicate the data that each component needs to send to the pin; x is a positive integer. The pad_i signal is the signal output to the PAD, indicating the data that the target component needs to send to the pin; The pad_ren signal is a signal output to the PAD, indicating that the pull-up and pull-down resistors of the PAD corresponding to the switch multiplexing pin are enabled. The signal_x_p2u signal represents the data input to all components that interact with the outside world via the chip's pin multiplexing system.

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