Integrated circuit delay determination method and device, equipment, medium and product
By obtaining the clock network and timing exception set in the integrated circuit delay determination method, determining the impact area and micro-instructions, and analyzing the delay based on the GPU platform, efficient timing exception analysis is finally achieved, solving the inefficient efficiency in the existing technology question.
Patent Information
- Application Number
- CN202411597634.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-11
- Publication Date
- 2025-02-18
AI Technical Summary
The inefficiency of the integrated circuit delay determination method in the prior art is mainly due to the complexity of the data structure in timing exception analysis and the increase in GPU memory pressure, which makes it difficult to fully utilize the GPU heterogeneous platform to achieve high-speed analysis of timing exceptions.
By obtaining the directed acyclic diagram of the clock network of the target integrated circuit, the preset timing path set and the timing exception set, the influence area corresponding to each timing exception path is determined, and the influence area is determined according to the preset micro-instruction compilation method. micro-instructions that affect nodes within each node. Then, based on the GPU platform and timing exception label diagram, the delay corresponding to each timing path in the timing path set is determined to determine the delay minimum and delay maximum values of the target integrated circuit.
By accurately limiting the impact range of timing exceptions, simplifying circuit diagrams and reducing storage requirements, reducing the complexity and cost of timing exception analysis, improving timing analysis efficiency, and ensuring the accuracy and reliability of calculating the impact of timing exceptions on signal propagation. .
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Figure CN119476155A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit design automation, and in particular to an integrated circuit delay determination method, device, equipment, medium and product. Background Art
[0002] Most current timing analysis tools use the technology of "timing exception analysis" to make up for the omissions in the static timing analysis process. Timing exception analysis requires chip design engineers to specify a series of timing exception rules so that the timing analysis tool can better understand the intentions of chip design engineers and perform reasonable verification of chip circuits, thereby making the timing analysis results more consistent with the functional goals of the chip.
[0003] In the related art, in order to reduce the cost of timing exception analysis, graph analysis and path analysis are usually used to accelerate various tasks in timing analysis using GPU heterogeneous platforms. However, due to the wide variety of timing exceptions, the timing analysis data structure after classification discussion is very complex, which increases the pressure on the GPU memory, making it difficult for the timing exception analysis method in the related art to fully utilize the GPU heterogeneous platform to achieve high-speed analysis of timing exceptions, that is, the efficiency of the integrated circuit delay determination method in the related art is low. Summary of the invention
[0004] Based on this, it is necessary to provide an integrated circuit delay determination method, device, equipment, medium and product to address the technical problem of low efficiency of the integrated circuit delay determination method in the above-mentioned related technologies.
[0005] In a first aspect, the present application provides a method for determining an integrated circuit delay, the method comprising:
[0006] Obtaining a directed acyclic graph of a clock network of a target integrated circuit, a preset timing path set, and a timing exception set, wherein the timing exception set includes subgraph rules corresponding to various timing exceptions, and the subgraph rules include a plurality of matching key nodes;
[0007] According to the key nodes, determine the impact area corresponding to each timing exception path, and according to the preset microinstruction compilation method, determine the microinstructions of each impact node in the impact area;
[0008] Classify and discuss each influencing node according to the microinstructions, and determine one or more labels corresponding to each influencing node according to the results of the classification discussion, so as to obtain a timing exception label graph according to each label and the influencing area, wherein the label stores the behavior characteristics and corresponding delay of each influencing node;
[0009] Based on the GPU platform and the timing exception label graph, the delay corresponding to each timing path in the timing path set is determined to determine the minimum delay value and the maximum delay value of the target integrated circuit.
[0010] In one embodiment, each key node in each subgraph rule is sorted according to the topological order of the directed acyclic graph, and the impact area corresponding to each timing exception is determined according to the key node, including:
[0011] According to each target key node in the target subgraph rule, determine the corresponding target timing exception path;
[0012] According to a preset minimum boundary point determination method, the minimum boundary point of the target timing exception path is determined, and based on each minimum boundary point and the target graph node on the target timing exception path, the target impact area corresponding to the target subgraph rule is determined.
[0013] In one embodiment, determining the minimum boundary point of the target timing exception path according to a preset minimum boundary point determination method includes:
[0014] According to the target key nodes, the directed acyclic graph where the target timing exception path is located is layered to obtain a layered directed acyclic graph;
[0015] Forward traverse the target graph nodes, determine the candidate nodes of the previous level of each target graph node, and store first traversal information on each target graph node and the candidate node respectively, the first traversal information is used to indicate whether the corresponding node can be forward accessed through each level;
[0016] Traversing the target graph nodes and the candidate nodes backwards, and storing second traversal information on each target graph node and each candidate node, respectively, the second traversal information being used to indicate whether the corresponding node can be accessed backwards through each level;
[0017] According to each of the first traversal information and the second traversal information, a minimum boundary point of the target timing exception path is determined.
[0018] In one embodiment, determining the minimum boundary point of the target timing exception path according to each of the first traversal information and the second traversal information includes:
[0019] The first traversal information and the second traversal information are compared, and a candidate node that can be accessed forward but cannot be accessed backward is determined as a minimum boundary point of the target timing exception path.
[0020] In one embodiment, according to a preset microinstruction compilation method, determining the microinstructions of each influencing node in the influencing area includes:
[0021] In a preset mapping relationship table between microinstruction compilation strategies and timing exception path types, searching and determining a target microinstruction compilation strategy corresponding to the type of the target timing exception path, the target microinstruction compilation strategy including microinstruction compilation sub-strategies of the influencing nodes at each level in the target timing exception path;
[0022] According to the level of each influencing node, the corresponding microinstruction is determined and stored.
[0023] In one embodiment, after determining one or more labels corresponding to each influencing node according to the results of the classification discussion, the method further includes:
[0024] If there are labels of the same type among a plurality of labels affecting a node, the labels of the same type are merged.
[0025] In a second aspect, the present application further provides an integrated circuit delay determination device, the device comprising:
[0026] A circuit data acquisition module, used to acquire a directed acyclic graph of a clock network of a target integrated circuit, a preset timing path set, and a timing exception set, wherein the timing exception set includes subgraph rules corresponding to various timing exceptions, and the subgraph rules include multiple matching key nodes;
[0027] A microinstruction determination module is used to determine the impact area corresponding to each timing exception path according to the key node, and determine the microinstructions of each impact node in the impact area according to a preset microinstruction compilation method;
[0028] A label graph generation module is used to classify and discuss each influencing node according to the microinstructions, and determine one or more labels corresponding to each influencing node according to the results of the classification discussion, so as to obtain a timing exception label graph according to each label and the influencing area, in which the behavior characteristics and corresponding delays of each influencing node are stored;
[0029] The circuit delay determination module is used to determine the delay corresponding to each timing path in the timing path set based on the GPU platform and the timing exception label map, so as to determine the minimum delay value and the maximum delay value of the target integrated circuit.
[0030] In a third aspect, the present application further provides a computer device, the computer device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the following steps when executing the computer program:
[0031] Obtaining a directed acyclic graph of a clock network of a target integrated circuit, a preset timing path set, and a timing exception set, wherein the timing exception set includes subgraph rules corresponding to various timing exceptions, and the subgraph rules include a plurality of matching key nodes;
[0032] According to the key nodes, determine the impact area corresponding to each timing exception path, and according to the preset microinstruction compilation method, determine the microinstructions of each impact node in the impact area;
[0033] Classify and discuss each influencing node according to the microinstructions, and determine one or more labels corresponding to each influencing node according to the results of the classification discussion, so as to obtain a timing exception label graph according to each label and the influencing area, wherein the label stores the behavior characteristics and corresponding delay of each influencing node;
[0034] Based on the GPU platform and the timing exception label graph, the delay corresponding to each timing path in the timing path set is determined to determine the minimum delay value and the maximum delay value of the target integrated circuit.
[0035] In a fourth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:
[0036] Obtaining a directed acyclic graph of a clock network of a target integrated circuit, a preset timing path set, and a timing exception set, wherein the timing exception set includes subgraph rules corresponding to various timing exceptions, and the subgraph rules include a plurality of matching key nodes;
[0037] According to the key nodes, determine the impact area corresponding to each timing exception path, and according to the preset microinstruction compilation method, determine the microinstructions of each impact node in the impact area;
[0038] Classify and discuss each influencing node according to the microinstructions, and determine one or more labels corresponding to each influencing node according to the results of the classification discussion, so as to obtain a timing exception label graph according to each label and the influencing area, wherein the label stores the behavior characteristics and corresponding delay of each influencing node;
[0039] Based on the GPU platform and the timing exception label graph, the delay corresponding to each timing path in the timing path set is determined to determine the minimum delay value and the maximum delay value of the target integrated circuit.
[0040] In a fifth aspect, the present application further provides a computer program product, the computer program product comprising a computer program, and when the computer program is executed by a processor, the following steps are implemented:
[0041] Obtaining a directed acyclic graph of a clock network of a target integrated circuit, a preset timing path set, and a timing exception set, wherein the timing exception set includes subgraph rules corresponding to various timing exceptions, and the subgraph rules include a plurality of matching key nodes;
[0042] According to the key nodes, determine the impact area corresponding to each timing exception path, and according to the preset microinstruction compilation method, determine the microinstructions of each impact node in the impact area;
[0043] Classify and discuss each influencing node according to the microinstructions, and determine one or more labels corresponding to each influencing node according to the results of the classification discussion, so as to obtain a timing exception label graph according to each label and the influencing area, wherein the label stores the behavior characteristics and corresponding delay of each influencing node;
[0044] Based on the GPU platform and the timing exception label graph, the delay corresponding to each timing path in the timing path set is determined to determine the minimum delay value and the maximum delay value of the target integrated circuit.
[0045] The above-mentioned integrated circuit delay determination method, device, computer equipment, storage medium and computer program product obtain a directed acyclic graph of the clock line network of the target integrated circuit, a preset timing path set and a timing exception set, wherein the timing exception set includes subgraph rules corresponding to various timing exceptions, and the subgraph rules include multiple matching key nodes; according to the key nodes, the impact area corresponding to each timing exception path is determined, and according to the preset microinstruction compilation method, the microinstructions of each impact node in the impact area are determined; according to the microinstructions, each impact node is classified and discussed, and one or more labels corresponding to each impact node are determined according to the results of the classification discussion, so as to obtain a timing exception label map according to each label and the impact area, and the label stores the behavioral characteristics and corresponding delays of each impact node; based on the GPU platform and the timing exception label map, the delay corresponding to each timing path in the timing path set is determined to determine the minimum delay and the maximum delay of the target integrated circuit. The present application adopts the above method, by expressing various preset timing exceptions as sub-graph rules, and then determining the corresponding impact area according to the key nodes in each sub-graph rule, so as to accurately limit the actual impact range of each timing exception on the circuit diagram, avoid unnecessary classification discussions outside the actual impact range, and then define the classification discussion behavior of each impact node in each impact area through a preset microinstruction compilation method, so that the comprehensive effect of all microinstructions passed by any timing path can be equivalent to the behavior that should be possessed when the timing exception is designed, and the complexity of modeling the mutual influence between timing exceptions can be effectively reduced, thereby helping to improve the efficiency of timing analysis; in addition, through the final timing exception label diagram, the minimum delay and maximum delay of the integrated circuit can be accurately calculated, thereby ensuring the accuracy and reliability of calculating the impact of timing exceptions on signal propagation. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] FIG1 is a diagram showing an application environment of a method for determining delay of an integrated circuit in one embodiment;
[0047] FIG2 is a flow chart of a method for determining an integrated circuit delay in one embodiment;
[0048] FIG3 is a schematic diagram of various timing exceptions and their corresponding subgraph rules in one embodiment;
[0049] FIG4 is a flow chart of determining a target impact area according to a target key node in one embodiment;
[0050] FIG5 is an example diagram of determining an impact area of a timing exception in one embodiment;
[0051] FIG6 is a flow chart of determining the minimum boundary point of a timing exception path in one embodiment;
[0052] FIG7 is a flow chart of determining microinstructions corresponding to a node in one embodiment;
[0053] FIG8 is a schematic diagram of a timing exception label diagram in one embodiment;
[0054] FIG9 is a block diagram of a structure of an integrated circuit delay determination device according to an embodiment;
[0055] FIG10 is a diagram showing the internal structure of a computer device in one embodiment;
[0056] FIG. 11 is a diagram showing the internal structure of a computer device in another embodiment. DETAILED DESCRIPTION
[0057] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0058] Static timing analysis (STA) is an important step in the integrated circuit chip design process, and plays a decisive role in the verification and optimization of circuit functions and performance. The standard STA process in a field usually simulates and calculates the signal propagation of the circuit according to the topological order of various components on the circuit diagram through "timing propagation", and then evaluates the timing of the circuit. However, the topology of the circuit diagram cannot fully reflect the actual working conditions of the chip design. For example, the topology may mistakenly introduce false timing paths that are logically impossible to trigger. In addition, the topology cannot reflect the interaction between multiple different clock domains of the chip and the logical paths that span multiple clock cycles. Therefore, timing analysis based solely on simple topological propagation may cause inaccurate timing analysis, which in turn has a significant negative impact on chip optimization.
[0059] In order to accurately analyze the timing of the chip, the current timing analysis tools use the technology of "timing exception analysis". Timing exception analysis requires chip design engineers to specify a series of timing exception rules, including requiring to ignore the timing paths that meet specific patterns, requiring to treat the timing paths that meet specific patterns as paths that span multiple clock cycles, etc. The timing exception rules enable the timing analysis tools to better understand the intentions of chip design engineers, and then reasonably verify the chip circuits, so that the timing analysis results and the functional goals of the chip are more consistent.
[0060] However, since each node on the circuit diagram needs to conduct a strict classification discussion on the compliance of the timing exception, the timing exception analysis will cause the data structure size of the timing propagation algorithm to increase by more than 10 times, and the running time can reach more than 3 times that of not turning on the timing exception analysis, resulting in a very high cost for the timing exception analysis. Therefore, in order to reduce the cost of timing exception analysis, in the related art, graph analysis and path analysis are usually used to accelerate various tasks in timing analysis using GPU heterogeneous platforms. However, due to the wide variety of timing exceptions, the timing analysis data structure after the classification discussion is very complex, which increases the pressure on the GPU video memory, making it difficult for the timing exception analysis method in the related art to fully utilize the GPU heterogeneous platform to achieve high-speed analysis of timing exceptions, that is, the efficiency of the integrated circuit delay determination method in the related art is low.
[0061] In order to solve the problem of low efficiency of the integrated circuit delay determination method in the related art, an embodiment of the present application provides an integrated circuit delay determination method, which can be applied in an application environment as shown in Figure 1, wherein the terminal 102 communicates with the server 104 through a network. The data storage system can store data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on the cloud or other network servers. Among them, the terminal 102 can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, Internet of Things devices and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart car-mounted devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The server 104 can be implemented as an independent server or a server cluster consisting of multiple servers.
[0062] This method is a method for using GPU to accelerate the analysis of integrated circuit timing exceptions, which mainly includes three steps: limiting the impact area of timing exceptions, compiling timing exception microinstructions, and propagating timing exception label graphs. Among them, the timing exception impact reduction step aims to accurately limit the actual impact range of each timing exception on the circuit diagram, avoid unnecessary classification discussions outside the actual impact range, and achieve the purpose of simplifying the circuit diagram and saving storage. It includes sub-steps: forward traversal, backward traversal, and minimum boundary point set construction. The timing exception microinstruction compilation aims to split various timing exceptions into multiple microinstructions according to matching subgraph patterns. Each microinstruction defines the classification discussion behavior of a single node on the circuit diagram, which can effectively reduce the complexity of modeling the mutual influence between timing exceptions and simplify the implementation of timing analysis tools. The timing exception label graph propagation step aims to automatically classify and discuss the microinstructions stored on each node according to the topological order of the circuit diagram, and use the hash algorithm to split the nodes on the circuit diagram into one or more labels to construct the timing exception label graph. The final timing exception label graph is the result of the timing exception analysis. On the final timing exception label graph, the fastest arrival time and slowest arrival time of the signal of each node label can be obtained through the graph traversal algorithm, so that the highest operating frequency of the chip can be calculated based on the fastest arrival time and the slowest arrival time, that is, the performance analysis of the chip is completed. On this basis, the signal transmission path corresponding to the fastest arrival time and the slowest arrival time can be further searched to find the performance bottleneck of the chip, which can be used to guide the chip design automation algorithm to perform targeted performance optimization.
[0063] In one embodiment, as shown in FIG2 , the method is described by taking the method applied to a terminal such as a computer as an example. It is understandable that the method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:
[0064] Step 202, obtaining a directed acyclic graph of the clock network of the target integrated circuit, a preset timing path set and a timing exception set, wherein the timing exception set includes subgraph rules corresponding to various timing exceptions, and the subgraph rules include multiple matching key nodes.
[0065] The target integrated circuit is the integrated circuit to be analyzed for timing. In integrated circuit design, timing refers to the time relationship between signal propagation and processing in the circuit, including the delay time for the signal to propagate from one point to another. The goal of timing analysis is to ensure that these signals meet the predetermined timing requirements when transmitted and processed, thereby ensuring the normal operation and performance of the circuit.
[0066] A directed acyclic graph includes multiple nodes and directed edges. Nodes are used to represent various electrical components in an integrated circuit, such as clock sources, buffers, gating units, and registers. Directed edges are used to represent the propagation path of a clock signal from one node to another. The preset timing path set is a set of timing detection paths used to verify chip performance. These paths are used to ensure the timing accuracy of the chip under different working conditions.
[0067] Subgraph rules are used to describe the specific location and impact range of timing exceptions in the clock network. Each subgraph rule usually includes multiple matching key nodes. In addition, subgraph rules can be set in advance according to the performance test requirements of the target integrated circuit. The key nodes in the subgraph rules are usually the starting point, middle point and end point corresponding to the path matched by the timing exception, and each subgraph rule includes at least one starting point and end point.
[0068] Exemplarily, as shown in FIG3, timing exceptions mainly include false paths, multi-cycle paths, paths across synchronous clock domains, path fine-tuning, and local delay constraints, and each type of timing exception corresponds to a specific subgraph rule, i.e., an expression method. The rules for timing exceptions are usually given in the Synopsys Design Constraint format (SDC), and can also be given in other formats. In this embodiment, the SDC format is adopted, and the rules for various timing exceptions are given as shown in (a)-(e) in FIG3. For example, the general format of a false path is "set_false_path -from X -through Y -to Z", where set_false_path is the type of the timing exception, -from, -through, and -to represent the source node, the passing node, and the arrival node, respectively. -from -through -to together constitute a subgraph rule of a timing exception. -from, -through, and -to are all optional, and each can give a set of nodes, and -through can also have multiple stages. For example, -through {AB} -through {CD} means passing through one of the two nodes A and B first, and then passing through one of the two nodes C and D.
[0069] Specifically, for example, the subgraph rule corresponding to a multi-cycle path is "set_multicycle_path -setup2 -from FF0 -to FF1", where "-setup" is used to specify the setup timing check of the path, for example, "-setup 2" is used to indicate that the setup timing check of the specified path is completed within 2 clock cycles; "-from FF0" is used to indicate that the starting point of the path is the trigger FF0; and "to FF1" is used to indicate that the end point of the path is the trigger FF1.
[0070] Step 204 , determining the impact area corresponding to each timing exception path according to the key node, and determining the microinstructions of each impact node in the impact area according to a preset microinstruction compilation method.
[0071] Among them, the impact area is the part of the circuit that can be affected by a specific timing exception path, the affected nodes are the nodes within the circuit part, and the impact area is related to the area where the key nodes and the nodes associated with the key nodes are located. In the entire circuit, the timing exception may only affect a small part of the path, while most of the paths still follow the conventional timing rules. Therefore, by first analyzing the impact area of the timing exception, it can be clear which paths require special treatment and which paths can be analyzed according to the conventional timing. Through this narrowing operation, unnecessary global analysis can be avoided, which helps to improve the efficiency of timing analysis.
[0072] The preset microinstruction compilation method aims to compile the timing exception information, path classification and other information in the circuit design into a set of microinstructions that can be automatically executed. The microinstructions act on a single circuit diagram node and determine the subsequent classification discussion behavior of this circuit diagram node. There is no need to split the instruction annotations, including "immediately terminate timing propagation", "terminate timing propagation after the current label is completed", "create a label with signal delay starting from 0", "start matching the i-th timing exception", "abandon the i-th timing exception being matched", "make the i-th timing exception effective and clear the invalid rules according to priority", where i represents the number of a timing exception. These microinstructions can be used to automatically handle tasks such as classification discussion in timing analysis, so that the comprehensive effect of any path passing through all microinstructions is equivalent to the behavior that should be possessed when designing timing exceptions.
[0073] Step 206, classify and discuss each influencing node according to the microinstructions, and determine one or more labels corresponding to each influencing node according to the results of the classification discussion, so as to obtain a timing exception label diagram according to each label and the impact area, and the label stores the behavioral characteristics and corresponding delays of each influencing node.
[0074] Specifically, the purpose of the classification discussion is to correctly handle timing exceptions when checking path delays. Since the timing exception paths and normal paths are handled differently, in order to perform accurate timing analysis, these paths need to be classified and marked (labeled), and microinstruction compilation can automate this process. Labels are used to characterize the signal arrival time of different classification states and the matching of timing exceptions. Therefore, the behavioral characteristics in this embodiment are used to characterize the matching of the affecting nodes and timing exceptions. The delay is the time required for the signal to travel from one node to another. The timing exception label graph stores label information on each node based on the directed acyclic graph, but during the data storage process, it is still stored through the topological connection relationship between the nodes.
[0075] Step 208 , based on the GPU platform and the timing exception label graph, determine the delay corresponding to each timing path in the timing path set to determine the minimum delay value and the maximum delay value of the target integrated circuit.
[0076] Among them, the GPU platform has powerful computing power and can process tasks in parallel. Based on the GPU platform and the timing exception label graph, the speed of timing path analysis can be accelerated, thereby improving the efficiency of timing analysis. According to the above content, delay data is stored on each node in the timing exception label graph. These delay data include minimum delay and maximum delay. Based on these delay data, the minimum and maximum delay values of the target integrated circuit can be determined, which facilitates the subsequent calculation of the highest operating frequency of the chip and completes the performance analysis of the chip.
[0077] In the above-mentioned integrated circuit delay determination method, various preset timing exceptions are represented as sub-graph rules, and then the corresponding impact areas are determined according to the key nodes in each sub-graph rule, so as to accurately limit the actual impact range of each timing exception on the circuit diagram, avoid unnecessary classification discussions outside the actual impact range, and then define the classification discussion behavior of each impact node in each impact area through a preset microinstruction compilation method, so that the comprehensive effect of all microinstructions passed by any timing path can be equivalent to the behavior that should be possessed when the timing exception is designed, and the complexity of modeling the mutual influence between timing exceptions can be effectively reduced, thereby helping to improve the efficiency of timing analysis; in addition, through the final timing exception label diagram, the minimum delay and maximum delay of the integrated circuit can be accurately calculated, thereby ensuring the accuracy and reliability of calculating the impact of timing exceptions on signal propagation.
[0078] In one embodiment, as shown in FIG4 , each key node in each subgraph rule is sorted according to the topological order of the directed acyclic graph, and the impact area corresponding to each timing exception is determined according to the key node, including:
[0079] Step 402: Determine the corresponding target timing exception path according to each target key node in the target subgraph rule.
[0080] The target subgraph rule is any one of the multiple subgraph rules, and the target key node is the key node in the target subgraph rule. After connecting each target key node and the associated nodes passed in sequence in topological order, the corresponding target timing exception path is obtained.
[0081] Exemplarily, as shown in Figure 5, Figure 5 is an example diagram for determining the corresponding impact area according to the subgraph rule "-from 1-through{4,5}-to 8", wherein node 1, node 4, node 5 and node 8 are key nodes in the subgraph rule. Since node 1 must pass through node 3 to reach node 4 and node 5 in sequence, and node 4 and node 5 must pass through node 7 to reach node 8, node 3 and node 7 are associated nodes related to the key nodes, and the path formed by node 1, node 3, node 4, node 7 and node 8 and the path formed by node 1, node 3, node 5, node 7 and node 8 are the timing exception paths corresponding to the subgraph rule.
[0082] Step 404, determine the minimum boundary point of the target timing exception path according to a preset minimum boundary point determination method, and determine the target impact area corresponding to the target subgraph rule based on each minimum boundary point and the target graph nodes on the target timing exception path.
[0083] Specifically, determining the minimum boundary point of the timing exception path helps to further limit the impact range of the timing path in the integrated circuit, thereby avoiding unnecessary classification discussions outside the actual impact range, thereby achieving the purpose of simplifying the circuit diagram and saving storage.
[0084] Exemplarily, still taking the example graph in FIG5 as an example, it can be seen from FIG5 that the minimum boundary points are nodes 2, 6 and 9. That is to say, as long as any timing path passes through any one of nodes 2, 6 and 9, it is impossible to match the subgraph rule "-from 1-through{4,5}-to 8". Therefore, the influence of the timing exception corresponding to this subgraph rule on this timing path can be excluded; accordingly, the affected area corresponding to this subgraph rule is the area formed by nodes 1-9 and the directed edges between them.
[0085] In this embodiment, a preset minimum boundary point determination method is used to construct a minimum boundary point set corresponding to each timing exception path, thereby determining the impact area corresponding to each timing exception path, which helps to further limit the impact range of the timing path in the integrated circuit, so as to avoid unnecessary classification discussions outside the actual impact range, thereby achieving the purpose of simplifying the circuit diagram and saving storage.
[0086] In one embodiment, as shown in FIG6 , determining the minimum boundary point of the target timing exception path according to a preset minimum boundary point determination method includes:
[0087] Step 602: hierarchize the directed acyclic graph where the target timing exception path is located according to the target key node to obtain a hierarchical directed acyclic graph.
[0088] Specifically, the present application splits the timing exceptions into microinstructions according to the hierarchy of subgraph rules, so that the combined effect of all microinstructions passed by any path is equivalent to the behavior that should be possessed when the timing exception is designed.
[0089] Exemplarily, as shown in FIG5 , according to key nodes 1 , 4 , 5 and 8 , the subgraph rules can be divided into three layers, wherein node 1 is in the first layer, nodes 4 and 5 are in the second layer, and node 8 is in the third layer.
[0090] Step 604, forward traverse the target graph nodes, determine the candidate nodes of the previous level of each target graph node, and store first traversal information on each target graph node and candidate node respectively, the first traversal information is used to indicate whether the corresponding node can be forward accessed through each level.
[0091] After obtaining the hierarchical directed acyclic graph, we start from the i-th layer to the i+1-th layer, use the graph search algorithm to perform forward traversal, and mark the nodes visited during the forward traversal, where i=1,2,…,N-1. Candidate nodes are predecessor nodes obtained during forward traversal, and some nodes are both graph nodes and candidate nodes.
[0092] Exemplarily, as shown in FIG5, forward traversal from node 1 of the first layer can reach node 2 and node 3, forward traversal from node 3 can reach node 4 and node 5 of the second layer, forward traversal from nodes 4 and 5 can reach node 7, and forward traversal from node 4 can also reach node 6, and forward traversal from node 7 can reach node 8 and node 9 of the third layer. The first traversal information of nodes 1-9 can be expressed in the form of marks, as shown in FIG5, each node is marked with a mark B: X1X2X3, where X1, X2, and X3 are 0 or 1, respectively indicating whether the node can be reached by forward traversal from the 1st, 2nd, and 3rd layers, 1 for yes, and 0 for no. For example, node 1 from layer 1 in Figure 5 can be obtained by forward traversal from the first layer, but cannot be obtained by forward traversal from the second and third layers, so the label B of node 1 is 100, and node 8 can be obtained by forward traversal from the first to third layers, so the label B of node 8 is 111. That is to say, the first traversal information of node 1 is 100, and the first traversal information of node 8 is 111.
[0093] Step 606, backward traverse the target graph nodes and candidate nodes, and store second traversal information on each target graph node and candidate node respectively, the second traversal information is used to indicate whether the corresponding node can be backward accessed through each level.
[0094] Among them, when traversing backward, we start from the i+1th layer of the hierarchical subgraph rule and go back to the ith layer, use the graph search algorithm to traverse backward on the circuit graph, and mark the nodes visited during the backward traversal. Backward traversal refers to traversing the reverse graph of the circuit graph in topological order. The reverse graph of the circuit graph refers to the graph obtained by reversing each edge in the directed acyclic graph of the circuit, where i=1,2,…,N-1.
[0095] Exemplarily, as shown in FIG5 , backward traversal from node 8 of the third layer can reach node 7, backward traversal from node 7 can reach nodes 4 and 5 of the second layer, but cannot reach node 9, backward traversal from nodes 4 and 5 can reach node 3, and backward traversal from node 3 can reach node 1 of the first layer, but cannot reach node 2. Similarly, the second traversal information of nodes 1-9 can also be expressed in the form of marks, as shown in FIG5 , each node is marked next to F: Y1Y2Y3, where Y1, Y2, and Y3 are 0 or 1, respectively indicating whether this node can be reached by reverse traversal from the 1st, 2nd, and 3rd layers, 1 for yes, and 0 for no. For example, node 8 from the third layer in Figure 5 can be obtained by backward traversal from the third layer, but cannot be obtained by backward traversal from the second and first layers. Therefore, the mark F of node 8 is 001, and node 1 can be obtained by backward traversal from the first to third layers, so the mark F of node 1 is 111. In other words, the second traversal information of node 8 is 001, and the second traversal information of node 1 is 111.
[0096] Step 608: Determine the minimum boundary point of the target timing exception path according to each of the first traversal information and the second traversal information.
[0097] Specifically, by comparing the first traversal information and the second traversal information, it can be determined that a node that is not visited by the backward traversal process but can be visited by the forward traversal process can be defined as a boundary point. The meaning of a boundary point is that when a timing path visits a boundary point, it means that the timing path can no longer meet the rules of this timing exception, so there is no need to conduct a classification discussion on this timing exception. In addition, further, the simplification rule is executed: if a boundary point A already has a preceding node B on the graph that is also a boundary point, then point A can be removed from the boundary points, because when the path visits the boundary point A, the need for classification discussion can be eliminated. This simplification rule is executed on the set of all boundary points, and the minimum set obtained is the minimum boundary point set.
[0098] For example, still taking the example graph of FIG5 as an example, the minimum boundary point set is composed of nodes 2, 6, and 9, which means that any path, as long as it passes through any of nodes 2, 6, and 9, can no longer match the subgraph rule "-from 1-through{4,5}-to 8". Therefore, the impact of the timing exception corresponding to this subgraph rule on this path can be excluded.
[0099] In this embodiment, the minimum boundary points of the timing exception path are determined by forward traversal and backward traversal methods, which helps to improve the efficiency and reliability of constructing the minimum boundary point set.
[0100] In one embodiment, determining the minimum boundary point of the target timing exception path according to each of the first traversal information and the second traversal information includes:
[0101] The first traversal information and the second traversal information are compared, and a candidate node that can be accessed forward but cannot be accessed backward is determined as a minimum boundary point of the target timing exception path.
[0102] Specifically, according to the above content, by comparing the mark B and the mark F of each influencing node in the influencing area, the minimum boundary point corresponding to each timing exception path can be quickly determined, so that the corresponding minimum boundary point set can be quickly constructed.
[0103] In one embodiment, as shown in FIG. 7 , according to a preset microinstruction compilation method, determining the microinstructions of each influencing node in the influencing area includes:
[0104] Step 702, in the preset mapping relationship table between microinstruction compilation strategies and timing exception path types, search and determine the target microinstruction compilation strategy corresponding to the type of the target timing exception path, the target microinstruction compilation strategy includes the microinstruction compilation sub-strategies of the influencing nodes at each level in the target timing exception path.
[0105] The mapping relationship table between the preset microinstruction compilation strategy and the timing exception path type can be preset according to the actual timing detection requirements of the target integrated circuit. The microinstruction compilation sub-strategy is the instruction that needs to be executed independently for each affected node.
[0106]
[0107] Table 1
[0108] Exemplarily, the mapping relationship table between the preset microinstruction compilation strategy and the timing exception path type in this embodiment is shown in Table 1 above.
[0109] Step 704 , determining and storing corresponding microinstructions according to the level of each influencing node.
[0110] Exemplarily, as shown in FIG8 , FIG8 is a schematic diagram of a timing exception label graph, and the subgraph rule corresponding to the timing exception is “e1:set_multicycle_path -through 1- through 4”, that is, the subgraph rule corresponds to the multi-cycle path timing exception e1, and according to the subgraph rule, it can be determined that node 1 and node 4 are the key nodes corresponding to the subgraph rule, and the level where node 1 is located is the first level, and the level where node 4 is located is the second level. The microinstruction of node 1 is “start matching the e1th timing exception”, and the corresponding label is {e1:1}, which means that the current state is “timing exception e1 has matched to the first stage”; node 2 has no timing exception associated with it, so the timing exception number set RuleSet of node 2 is an empty set {}; node 3 has two predecessor nodes 1 and node 4. Point 2, because the RuleSets of the two are different, they need to be discussed in categories, and two timing exception labels are created, namely {e1:1} and {}; Node 4 executes the microinstruction on Node 4 on the basis of Node 3, "advancing the matching status of the e1th timing exception rule by one level", so the label {e1:1} is updated to {e1:2}, which means that the matching status of e1 is advanced by one level, and {} remains unchanged; and since Node 5 is one of the minimum boundary points of the timing exception e1, the microinstruction on Node 5 is "abandon the e1th timing exception being matched", and the label is {}.
[0111] In addition, each label also stores the corresponding delay time, which is the propagation time from the predecessor node of a node to the node. For example, the predecessor nodes of node 3 are node 1 and node 2, and the time from node 1 to node 3 is 15ps. Accordingly, according to the label of each node, the signal transmission path corresponding to the fastest time and the slowest time can also be searched, so as to facilitate the subsequent identification of the performance bottleneck of the chip and to know the chip design automation algorithm for targeted performance optimization.
[0112] In this embodiment, by setting microinstructions for each node, the process of subsequent classification discussion can be accelerated, thereby helping to speed up the rate of timing exception analysis.
[0113] In one embodiment, after determining one or more labels corresponding to each influencing node according to the results of the classification discussion, the method further includes: when there are labels of the same type among the multiple labels of the influencing nodes, merging the labels of the same type.
[0114] Specifically, during the classification discussion, the same classification is merged using a hash algorithm. Two classifications are considered the same if and only if the signal arrival times of the two classifications are defined on the same clock domain (referred to as ClockSet) and the set of timing exception numbers in the matching process is the same (referred to as RuleSet). The hash value of each classification is calculated as Digest(ClockSet, RuleSet), where the result of Digest is an integer or other summary result that can be quickly compared. When the digests of two classifications are the same, the two classifications are considered equivalent and merged into the same classification, reducing the number of classifications in the final classification discussion results.
[0115] In the process of matching the new classification summary with the existing classification summary, the GPU storage hierarchy is used to open a software cache in the local memory to cache the recent classification summaries for fast matching. In the case that the ClockSet and RuleSet have not changed substantially, pointer technology is used to avoid unnecessary copy operations, and the two sets are copied only when they need to be modified.
[0116] For each final classification, a tag is created. A directed edge is established between the labels a and b of each pair of adjacent nodes A->B on the circuit diagram. The specific method is that if label b can be obtained from label a through classification discussion, a directed edge of a->b is established. The timing exception label graph obtained by the above process is shown in Figure 8. The final timing exception label graph can provide a basis for further timing exception analysis.
[0117] Exemplarily, as shown in FIG8 , node 5 in FIG8 has two predecessor nodes, namely node 3 and node 2, so the labels of the two predecessors are {e1:1} and {}, respectively. Since node 5 is one of the minimum boundary points of timing exception e1, the label on node 5 is to abandon the state of timing exception e1 being matched. Therefore, the labels of the two predecessors, {e1:1} and {}, respectively, will be converted to {}. Since the two classifications are the same, they are merged, leaving a unique label {}. The final timing exception label graph, after combining with existing timing analysis tools, can be independently maintained during classification discussion according to the separate signal arrival time maintained by each label during timing propagation, and the maximum or minimum value is taken according to the analysis mode when the classification is merged, so that the minimum delay and maximum delay of the target integrated circuit can be quickly obtained.
[0118] This embodiment adopts the above method, by accurately analyzing the impact range of timing exceptions, splitting complex timing exception types into simple microinstructions for simplified processing, and using hash algorithms, write-time copy and other technologies to greatly reduce the time and memory usage of classification discussions, thereby realizing a timing exception analysis calculation mode that is friendly to heterogeneous GPU platforms; in addition, the efficiency of completing the timing exception analysis in this application can be improved by more than 10 times as a whole, saving the computational cost of static timing analysis of integrated circuits, and facilitating a more efficient chip design automation process.
[0119] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.
[0120] Based on the same inventive concept, the embodiment of the present application also provides an integrated circuit delay determination device for implementing the integrated circuit delay determination method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more integrated circuit delay determination device embodiments provided below can refer to the limitations of the integrated circuit delay determination method above, and will not be repeated here.
[0121] In one embodiment, as shown in FIG. 9 , an integrated circuit delay determination device is provided, comprising: a circuit data acquisition module 902 , a microinstruction determination module 904 , a label map generation module 906 and a circuit delay determination module 908 , wherein:
[0122] The circuit data acquisition module 902 is used to obtain the directed acyclic graph of the clock network of the target integrated circuit, the preset timing path set and the timing exception set, wherein the timing exception set includes subgraph rules corresponding to various timing exceptions, and the subgraph rules include multiple matching key nodes.
[0123] The microinstruction determination module 904 is used to determine the impact area corresponding to each timing exception path according to the key node, and determine the microinstructions of each impact node in the impact area according to a preset microinstruction compilation method.
[0124] The label map generation module 906 is used to classify and discuss each influencing node according to the microinstructions, and determine one or more labels corresponding to each influencing node according to the results of the classification discussion, so as to obtain a timing exception label map according to each label and the impact area, and the label stores the behavioral characteristics and corresponding delays of each influencing node.
[0125] The circuit delay determination module 908 is used to determine the delay corresponding to each timing path in the timing path set based on the GPU platform and the timing exception label map, so as to determine the minimum delay value and the maximum delay value of the target integrated circuit.
[0126] In one embodiment, the label graph generation module 906 is also used to: determine the corresponding target timing exception path according to each target key node in the target subgraph rule; determine the minimum boundary point of the target timing exception path according to a preset minimum boundary point determination method, and determine the target impact area corresponding to the target subgraph rule based on each minimum boundary point and the target graph nodes on the target timing exception path.
[0127] In one embodiment, the label graph generation module 906 is also used to: layer the directed acyclic graph where the target timing exception path is located according to the target key nodes to obtain a layered directed acyclic graph; forward traverse the target graph nodes to determine the candidate nodes at the previous level of each target graph node, and store first traversal information on each target graph node and the candidate node, respectively, and the first traversal information is used to characterize whether the corresponding node can be forward accessed through each level; backward traverse the target graph nodes and the candidate nodes, and store second traversal information on each target graph node and the candidate node, respectively, and the second traversal information is used to characterize whether the corresponding node can be backward accessed through each level; determine the minimum boundary point of the target timing exception path based on each first traversal information and the second traversal information.
[0128] In one embodiment, the label graph generation module 906 is further used to compare the first traversal information with the second traversal information, and determine the candidate nodes that can be accessed forward but not backward as the minimum boundary points of the target timing exception path.
[0129] In one embodiment, the label map generation module 906 is also used to: search and determine the target microinstruction compilation strategy corresponding to the type of the target timing exception path in a mapping relationship table between preset microinstruction compilation strategies and timing exception path types, the target microinstruction compilation strategy including microinstruction compilation sub-strategies for the influencing nodes at each level in the target timing exception path; determine and store the corresponding microinstructions according to the level at which each influencing node is located.
[0130] In one embodiment, the label graph generation module 906 is further configured to: merge labels of the same type when there are labels of the same type among multiple labels affecting a node.
[0131] Each module in the above integrated circuit delay determination device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.
[0132] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be shown in FIG10. The computer device includes a processor, a memory, and a network interface connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data such as identification and delay of each node in the target integrated circuit. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a method for determining an integrated circuit delay is implemented.
[0133] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be shown in FIG11. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a method for determining an integrated circuit delay is implemented. The display screen of the computer device may be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device may be a touch layer covered on the display screen, or a key, a trackball or a touchpad provided on the housing of the computer device, or an external keyboard, touchpad or mouse, etc.
[0134] Those skilled in the art will understand that the structures shown in FIGS. 10 and 11 are merely block diagrams of partial structures related to the scheme of the present application, and do not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device may include more or fewer components than those shown in the figures, or combine certain components, or have a different arrangement of components.
[0135] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.
[0136] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.
[0137] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.
[0138] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.
[0139] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.
[0140] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0141] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A method for determining integrated circuit delay, characterized in that: The method comprises: Obtaining a directed acyclic graph of a clock network of a target integrated circuit, a preset timing path set, and a timing exception set, wherein the timing exception set includes subgraph rules corresponding to various timing exceptions, and the subgraph rules include a plurality of matching key nodes; According to the key nodes, determining the impact area corresponding to each of the timing exception paths, and according to a preset microinstruction compilation method, determining the microinstructions of each impact node in the impact area; Classify and discuss each of the influencing nodes according to the microinstructions, and determine one or more labels corresponding to each of the influencing nodes according to the results of the classification discussion, so as to obtain a timing exception label graph according to each of the labels and the influencing areas, wherein the labels store the behavior characteristics and corresponding delays of each of the influencing nodes; Based on the GPU platform and the timing exception label map, the delay corresponding to each timing path in the timing path set is determined to determine the minimum delay value and the maximum delay value of the target integrated circuit.
2. The method according to claim 1, characterized in that The key nodes in the subgraph rules are sorted according to the topological order of the directed acyclic graph, and the affected area corresponding to each timing exception is determined according to the key nodes, including: According to each target key node in the target subgraph rule, determine the corresponding target timing exception path; According to a preset minimum boundary point determination method, the minimum boundary point of the target timing exception path is determined, and based on each of the minimum boundary points and the target graph nodes on the target timing exception path, the target impact area corresponding to the target subgraph rule is determined.
3. The method according to claim 2, characterized in that The step of determining the minimum boundary point of the target timing exception path according to a preset minimum boundary point determination method includes: According to the target key node, the directed acyclic graph where the target timing exception path is located is layered to obtain a layered directed acyclic graph; Forward traversing the target graph nodes, determining candidate nodes at the previous level of each target graph node, and storing first traversal information on each target graph node and the candidate nodes, respectively, wherein the first traversal information is used to indicate whether the corresponding node can be forward accessed through each level; Traversing the target graph node and the candidate node backward, and storing second traversal information on each of the target graph node and the candidate node respectively, wherein the second traversal information is used to indicate whether the corresponding node can be accessed backward through each level; The minimum boundary point of the target timing exception path is determined according to each of the first traversal information and the second traversal information.
4. The method according to claim 2, characterized in that: The step of determining the minimum boundary point of the target timing exception path according to each of the first traversal information and the second traversal information includes: The first traversal information and the second traversal information are compared, and a candidate node that can be accessed forward but cannot be accessed backward is determined as a minimum boundary point of the target timing exception path.
5. The method according to claim 3, characterized in that: The step of determining the microinstructions of each influencing node in the influencing area according to a preset microinstruction compiling method includes: In a preset mapping relationship table between microinstruction compilation strategies and timing exception path types, searching and determining a target microinstruction compilation strategy corresponding to the type of the target timing exception path, wherein the target microinstruction compilation strategy includes microinstruction compilation sub-strategies of the influencing nodes at each level in the target timing exception path; According to the level at which each of the influencing nodes is located, the corresponding microinstructions are determined and stored.
6. The method according to claim 5, characterized in that After determining one or more labels corresponding to each of the influencing nodes according to the results of the classification discussion, the method further includes: When there are labels of the same type among the multiple labels of the influencing node, the labels of the same type are merged.
7. An integrated circuit delay determination device, characterized in that: The device comprises: A circuit data acquisition module, used to acquire a directed acyclic graph of a clock network of a target integrated circuit, a preset timing path set, and a timing exception set, wherein the timing exception set includes subgraph rules corresponding to various timing exceptions, and the subgraph rules include a plurality of matching key nodes; A microinstruction determination module, used to determine the impact area corresponding to each of the timing exception paths according to the key nodes, and determine the microinstructions of each impact node in the impact area according to a preset microinstruction compilation method; A label graph generating module is used to classify and discuss each of the influencing nodes according to the microinstructions, and determine one or more labels corresponding to each of the influencing nodes according to the results of the classification discussion, so as to obtain a timing exception label graph according to each of the labels and the influencing area, wherein the labels store the behavior characteristics and corresponding delays of each of the influencing nodes; The circuit delay determination module is used to determine the delay corresponding to each timing path in the timing path set based on the GPU platform and the timing exception label map, so as to determine the minimum delay value and the maximum delay value of the target integrated circuit.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.
10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.