Method for designing number of gate balls of packaging chip power supply

Abstract

The invention relates to the technical field of semiconductor chip packaging, in particular to a method for designing the number of packaged chip power grid balls. The design method comprises the following steps that a packaging substrate is divided into at least two power source gate ball areas along a current path, a bare chip is correspondingly divided into at least two chip areas according to the positions of the at least two power source gate ball areas, and the at least two chip areas and the at least two power source gate ball areas are arranged in a one-to-one correspondence mode; respectively obtaining the total current amount required by each chip area, respectively calculating the total current passing through each power supply gate ball area according to the total current amount required by each chip area, and calculating the number of power supply gate balls required by each power supply gate ball area according to the total current; and the number of the power grid balls required by the packaging chip is obtained by adding the number of the power grid balls required by each power grid ball area. According to the invention, uniform distribution of current among the power grid balls is realized, and some grid balls are prevented from bearing excessive current, so that the phenomenon of electron migration is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor chip packaging, and in particular to a method for designing the number of power grid balls of a packaged chip. Background Art

[0002] In chip packaging design, the number of power grid balls plays a vital role in the long-term stable operation of the chip. If the current carried by the grid ball exceeds its allowable value, it may cause electron migration (EM), further leading to short circuit or open circuit inside the chip, seriously affecting its service life and functional stability. Electron migration refers to the electrons in the metal wire, under the action of current and temperature, forcing metal atoms to move along the direction of electron flow, thereby forming voids or protrusions in the metal structure. This phenomenon will cause the failure of the internal circuit of the chip, and in severe cases, even make the chip unusable.

[0003] The existing power ball number design method is usually based on a simple maximum current distribution rule, that is, the number of balls is obtained by dividing the chip design current with the maximum current allowed for each ball. However, this method ignores the uneven distribution of current between balls, resulting in excessive current load in some areas and too little current in other areas, which leads to local hot spots causing electron migration. Summary of the invention

[0004] The purpose of the present invention is to at least solve the problem of how to accurately determine the number of power grid balls in the design of packaged chips, and avoid the problem of electron migration caused by uneven current distribution without designing too many redundant power grid balls. This purpose is achieved through the following technical solutions:

[0005] The present invention proposes a method for designing the number of power grid balls of a packaged chip, comprising the following steps:

[0006] Dividing the package substrate into at least two power grid ball areas along the current path;

[0007] According to the positions of the at least two power ball grid regions, the chip bare die is divided into at least two chip regions, and the at least two chip regions and the at least two power ball grid regions are arranged in a one-to-one correspondence;

[0008] respectively obtaining the total amount of current required by each chip region;

[0009] The total current passing through each of the power ball regions is calculated according to the total current required by each of the chip regions;

[0010] Calculating the number of power grid balls required for each power grid ball area according to the total current;

[0011] The number of power grid balls required by all the power grid ball areas is added together to obtain the number of power grid balls required by the packaged chip.

[0012] The method for designing the number of power grid balls of a packaged chip according to the present invention has the following advantages:

[0013] Balanced current distribution to avoid local overload: By dividing the package substrate into multiple power grid ball areas and matching them with the corresponding areas of the chip die, the current demand of each area can be calculated more accurately, thereby achieving uniform current distribution among the power grid balls, avoiding some grid balls from carrying too much current, thereby reducing electron migration and extending the service life of the chip;

[0014] Optimize the number of gate balls and control the packaging cost: The design method of this embodiment avoids the design of too many or too few gate balls by accurately calculating the number of gate balls required for each power gate ball area, which can not only ensure the long-term stable operation of the chip, but also reduce unnecessary gate balls, control the size of the packaging substrate, and thus reduce the manufacturing cost;

[0015] Improve chip reliability: By precisely controlling the current distribution in each power ball area, local hot spots are avoided, effectively preventing the electron migration phenomenon (EM) caused by excessive current, reducing the open circuit or short circuit problems caused by electromigration in long-term use of the chip, and ensuring the long-term stable operation and reliability of the chip.

[0016] In addition, the method for designing the number of power grid balls of a packaged chip according to the present invention may also have the following additional technical features:

[0017] In some embodiments of the present invention, the number of the power grid ball regions is three, which are respectively a first power grid ball region, a second power grid ball region and a third power grid ball region along the current path;

[0018] The number of the chip regions arranged corresponding to the power ball region is also three, which are the first chip region, the second chip region and the third chip region along the current path.

[0019] In some embodiments of the present invention, the step of respectively obtaining the total amount of current required by each chip region includes:

[0020] Respectively obtain the type and quantity of circuit modules included in each chip area and the current consumed by each type of circuit module;

[0021] The total current I required by the first chip area is calculated based on the type and quantity of the circuit modules and the current consumed by each type of circuit module. A , the total current I required by the second chip area Band the total current I required by the third chip region C .

[0022] In some embodiments of the present invention, the step of calculating the total current passing through the first power ball region according to the total current required by the three chip regions comprises:

[0023] respectively calculating the currents flowing from the first power ball area to the first chip area, the second chip area and the third chip area in sequence;

[0024] According to the formula: I1=I 1A +I 1B +I 1C , calculating the total current of the first power grid ball area;

[0025] Where I1 is the total current of the first power ball area, I 1A is the current flowing from the first power ball area to the first chip area, I 1B is the current flowing from the first power ball area to the second chip area, I 1C is the current flowing from the first power ball area to the third chip area.

[0026] In some embodiments of the present invention, the step of calculating the total current passing through the second power ball region according to the total currents respectively required by the second chip region and the third chip region comprises:

[0027] respectively calculating the currents flowing from the second power ball area to the second chip area and the third chip area in sequence;

[0028] According to the formula: I2=I 2B +I 2C , calculating the total current of the second power grid ball area;

[0029] Where I2 is the total current of the second power ball area, I 2B is the current flowing from the second power ball region to the second chip region, I 2C is the current flowing from the second power ball region to the third chip region.

[0030] In some embodiments of the present invention, the step of calculating the total current passing through the third power ball region according to the total current required by the third chip region comprises:

[0031] calculating a current flowing from the third power ball region to the third chip region;

[0032] According to the formula: I3=I 3C, calculating the total current of the third power grid ball area;

[0033] Where I3 is the total current of the third power ball area, I 3C is the current flowing from the third power ball region to the third chip region.

[0034] In some embodiments of the present invention, the formula for calculating the current flowing from the first power ball area to the first chip area in sequence is: A =I 1A , obtaining a current flowing from the first power ball region to the first chip region;

[0035] And / or, the formula for calculating the current flowing from the first power ball area and from the second power ball area to the second chip area is I B =I 1B +I 2B , obtaining a current flowing from the first power ball region to the second chip region and a current flowing from the second power ball region to the second chip region;

[0036] And / or, the formula for calculating the current flowing from the first power ball region, the second power ball region and the third power ball region to the third chip region is I C =I 1C +I 2C +I 3C , obtaining the current flowing from the first power gate ball area to the third chip area, the current flowing from the second power gate ball area to the third chip area, and the current flowing from the third power gate ball area to the third chip area.

[0037] In some embodiments of the present invention, the step of obtaining the current flowing from the first power ball region to the second chip region and the current flowing from the second power ball region to the second chip region comprises:

[0038] The resistor R through which the current is obtained from the first power ball area to the second chip area 1B and the current flows from the second power ball area to the second chip area through the resistor R 2B ;

[0039] According to Ohm's law I 2B / I 1B =R 1B / R 2B , we get the formula and formula

[0040] According to the formula The current flowing from the first power ball area to the second chip area is obtained according to the formula A current flowing from the second power ball area to the second chip area is obtained.

[0041] In some embodiments of the present invention, the step of obtaining the current flowing from the first power ball region to the third chip region, the current flowing from the second power ball region to the third chip region, and the current flowing from the third power ball region to the third chip region comprises:

[0042] The resistor R through which the current is obtained from the first power ball area to the third chip area 1C , the current flows from the second power ball area to the third chip area through the resistor R 2C and the current flows from the third power ball area to the third chip area through the resistor R 3C ;

[0043] According to Ohm's law Get the formula formula and formula

[0044] According to the formula The current flowing from the first power ball area to the third chip area is obtained according to the formula The current flowing from the second power ball area to the third chip area is obtained according to the formula A current flowing from the third power ball region to the third chip region is obtained.

[0045] In some embodiments of the present invention, the step of calculating the number of power grid balls required for each power grid ball area according to the total current includes:

[0046] Get the maximum carrying current value I of each grid ball MAX ;

[0047] According to the formula N1=I1 / I MAX , the number of power grid balls required for the first power grid ball area is obtained, according to the formula N2 = I2 / I MAX , the number of power grid balls required for the second power grid ball area is obtained, according to the formula N3=I3 / I MAX , obtaining the number of power grid balls required for the third power grid ball area;

[0048] Wherein, N1 is the number of power balls required in the first power ball area, N2 is the number of power balls required in the second power ball area, and N3 is the number of power balls required in the third power ball area. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0050] Figure 1 A flow chart schematically shows a method for designing the number of power grid balls of a packaged chip according to an embodiment of the present invention;

[0051] Figure 2 The schematic diagram shows the structure of the current path when the chip die and the package substrate are divided according to the embodiment of the present invention;

[0052] Figure 3 Schematically showing a current path diagram flowing through a first power grid ball region according to an embodiment of the present invention;

[0053] Figure 4 Schematically showing a current path diagram flowing through a second power grid ball region according to an embodiment of the present invention;

[0054] Figure 5 Schematically showing a current path diagram flowing through a third power ball region according to an embodiment of the present invention;

[0055] Figure 6 Schematically shows a schematic diagram of chip area segmentation according to an embodiment of the present invention;

[0056] Figure 7 A schematic diagram schematically shows the division of the power grid ball area of ​​the packaging substrate according to an embodiment of the present invention;

[0057] Figure 8 The schematic diagram schematically shows the total transmission path of current on a chip, a packaging substrate, and a circuit board in the prior art;

[0058] Fig. 9 The schematic diagram schematically shows the local transmission path of current on a chip, a packaging substrate, and a circuit board in the prior art.

[0059] The reference numerals are as follows:

[0060] 10. Chip bare die; 11. First chip region; 12. Second chip region; 13. Third chip region;

[0061] 20. packaging substrate; 21. first power grid ball region; 22. second power grid ball region; 23. third power grid ball region;

[0062] 30. Circuit board; 31. Power supply plane; 32. Power supply;

[0063] 40. Power grid ball; 50. Power ball convex. DETAILED DESCRIPTION

[0064] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0065] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0066] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0067] For ease of description, spatial relative terms may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure, such as "inside", "outside", "inner side", "outer side", "below", "below", "above", "above", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, then the elements described as "below other elements or features" or "below other elements or features" will subsequently be oriented as "above other elements or features" or "above other elements or features". Therefore, the example term "below..." can include both above and below orientations.

[0068] like Figures 2 to 9 As shown, the packaged chip of the present invention includes a PCB circuit board 30, a package substrate 20 and a chip bare die 10. The PCB circuit board 30 has a power supply plane 31 for power transmission. The PCB circuit board 30 supplies power to the package substrate 20 through the power grid ball 40, and the package substrate 20 supplies power to the chip bare die 10 through the power ball protrusion 50. The power supply 32 of the PCB circuit board 30 is arranged on one side of the chip bare die 10 and the package substrate 20. The power supply 32 transmits current to the package substrate 20 through the power supply plane 31. The current path in the package substrate 20 flows from the side close to the power supply 32 to the side away from the power supply 32.

[0069] In a specific embodiment, the chip die 10 is divided into three equally divided chip areas, namely the first chip area 11, the second chip area 12 and the third chip area 13, and the core power and ground areas of the packaging substrate 20 are divided into three equally divided areas, namely the first power gate ball area 21, the second power gate ball area 22 and the third power gate ball area 23. The first power gate ball area 21 is close to the power supply 32, and the third power gate ball area 23 is far away from the power supply 32. Then, the current path of the current in the packaging substrate 20 is from the first power gate ball area 21 to the third power gate ball area 23.

[0070] It can be understood that, since the first chip region 11 and the first power ball region 21 are close to the power supply 32, the current of the first chip region 11 is basically supplied by the first power ball region 21. Similarly, the current of the second chip region 12 is supplied by the first power ball region 21 and the second power ball region 22. The current of the third chip region 13 is supplied by the first power ball region 21, the second power ball region 22 and the third power ball region 23.

[0071] Specifically, the core power supply area of ​​the package substrate 20 is substantially the same size as the chip die 10 (eg Figure 6As shown in FIG. 1 , from a top view, the core power supply area of ​​the package substrate 20 substantially overlaps with the chip die 10 .

[0072] like Figure 1 As shown, according to an embodiment of the present invention, a method for designing the number of power grid balls of a packaged chip is proposed, comprising the following steps:

[0073] Dividing the package substrate 20 into at least two power grid ball areas along the current path;

[0074] According to the positions of the at least two power ball grid regions, the chip die 10 is divided into at least two chip regions, and the at least two chip regions and the at least two power ball grid regions are arranged in a one-to-one correspondence;

[0075] Obtain the total amount of current required for each chip area separately;

[0076] The total current through each power ball area is calculated based on the total current required by each chip area;

[0077] The number of power grid balls required for each power grid ball area is calculated based on the total current;

[0078] The number of power balls 40 required for all power ball areas is added together to obtain the number of power balls required for the packaged chip.

[0079] The method for designing the number of power grid balls 40 of the packaged chip according to the present invention has the following advantages:

[0080] Balanced current distribution to avoid local overload: By dividing the packaging substrate 20 into multiple power grid ball areas and matching them with the corresponding areas of the chip die 10, the current demand of each chip area can be calculated more accurately, thereby achieving uniform distribution of current among the power grid balls, avoiding some grid balls from carrying too much current, thereby reducing electron migration and extending the service life of the chip.

[0081] Optimize the number of gate balls and control packaging costs: The method of this embodiment avoids the design of too many or too few gate balls by accurately calculating the number of gate balls required for each power gate ball area. This can not only ensure the long-term stable operation of the chip, but also reduce unnecessary power gate balls 40, control the size of the packaging substrate 20, and thus reduce manufacturing costs.

[0082] Improve design flexibility: Since the current requirements of different chip areas can be calculated and matched to the corresponding power ball areas, this design method can better adapt to the design requirements of different types of chips and provide more flexible packaging solutions for different applications.

[0083] Improve chip reliability: By precisely controlling the current distribution in each power ball area, local hot spots are avoided, effectively preventing the electron migration phenomenon (EM) caused by excessive current, reducing the open circuit or short circuit problems caused by electromigration in long-term use of the chip, and ensuring the long-term stable operation and reliability of the chip.

[0084] Improve power efficiency: Since the design method of this embodiment optimizes the distribution of power grid balls, the current transmission path is more reasonable, effectively reducing the loss in the power transmission process. Each power grid ball area can be designed according to the actual current demand, thereby improving the efficiency of the power transmission network and optimizing the energy efficiency of the chip.

[0085] Enhanced thermal management capabilities: By properly dividing the power grid ball area, overheating problems caused by excessive local current can be avoided and hot spots can be reduced. This optimized thermal management design further improves the overall heat dissipation performance of the chip and ensures the stability and performance of the chip under high power load.

[0086] Support for complex circuit design: Since each ball area can correspond to different areas of the chip, this method is particularly suitable for complex circuit design and highly integrated chip structures. For example, in high-density ASIC (application-specific integrated circuit) design, this method can provide corresponding current support for different modules, improving the flexibility and scalability of the design.

[0087] In a specific embodiment, the number of power grid ball regions is three, which are respectively a first power grid ball region 21, a second power grid ball region 22 and a third power grid ball region 23 along the current path;

[0088] The number of chip regions arranged corresponding to the power ball region is also three, which are a first chip region 11, a second chip region 12 and a third chip region 13 along the current path.

[0089] It can be understood that the steps of respectively obtaining the total amount of current required for each chip region include:

[0090] Respectively obtain the type and quantity of circuit modules included in each chip area and the current consumed by each type of circuit module;

[0091] The total current I required by the first chip region 11 is calculated based on the type and quantity of the circuit modules and the current consumed by each type of circuit module. A , the total current I required by the second chip region 12 B and the total current I required by the third chip region 13 C .

[0092] It can be understood that the step of calculating the total current passing through the first power ball region 21 according to the total current required by the three chip regions includes:

[0093] respectively calculating the currents flowing from the first power ball region 21 to the first chip region 11, the second chip region 12 and the third chip region 13 in sequence;

[0094] According to the formula: I1=I 1A +I 1B +I 1C , calculate the total current of the first power grid ball area 21;

[0095] Where I1 is the total current of the first power ball region 21, I 1A is the current flowing from the first power ball region 21 to the first chip region 11, I 1B is the current flowing from the first power ball region 21 to the second chip region 12, I 1C is the current flowing from the first power ball region 21 to the third chip region 13 .

[0096] It can be understood that the step of calculating the total current passing through the second power ball area 22 according to the total currents required by the second chip area 12 and the third chip area 13 respectively includes:

[0097] respectively calculating the currents flowing from the second power ball region 22 to the second chip region 12 and the third chip region 13 in sequence;

[0098] According to the formula: I2=I 2B +I 2C , calculate the total current of the second power grid ball area 22;

[0099] Where I2 is the total current of the second power ball region 22, I 2B is the current flowing from the second power ball region 22 to the second chip region 12, I 2C is the current flowing from the second power ball region 22 to the third chip region 13 .

[0100] It can be understood that the step of calculating the total current passing through the third power ball area 23 according to the total current required by the third chip area 13 includes:

[0101] Calculating the current flowing from the third power ball region 23 to the third chip region 13;

[0102] According to the formula: I3=I 3C , calculate the total current of the third power grid ball area 23;

[0103] Wherein, I3 is the total current of the third power ball region 23, I 3Cis the current flowing from the third power ball region 23 to the third chip region 13 .

[0104] It can be understood that the formula for calculating the current flowing from the first power ball region 21 to the first chip region 11 is I A =I 1A , obtaining a current flowing from the first power gate ball region 21 to the first chip region 11;

[0105] And / or, the formula for calculating the current flowing from the first power ball region 21 and from the second power ball region 22 to the second chip region 12 is I B =I 1B +I 2B , obtaining the current flowing from the first power ball region 21 to the second chip region 12 and the current flowing from the second power ball region 22 to the second chip region 12;

[0106] And / or, the formula for calculating the current flowing from the first power ball region 21, the second power ball region 22 and the third power ball region 23 to the third chip region 13 is I C =I 1C +I 2C +I 3C , the current flowing from the first power ball area 21 to the third chip area 13 , the current flowing from the second power ball area 22 to the third chip area 13 , and the current flowing from the third power ball area 23 to the third chip area 13 are obtained.

[0107] It can be understood that the steps of obtaining the current flowing from the first power ball region 21 to the second chip region 12 and the current flowing from the second power ball region 22 to the second chip region 12 include:

[0108] The resistor R through which the current is obtained from the first power ball region 21 to the second chip region 12 1B and the resistor R through which the current flows from the second power ball region 22 to the second chip region 12 2B ;

[0109] According to Ohm's law I 2B / I 1B =R 1B / R 2B , we get the formula and formula

[0110] According to the formula The current flowing from the first power ball area 21 to the second chip area 12 is obtained according to the formula The current flowing from the second power ball region 22 to the second chip region 12 is obtained.

[0111] It can be understood that the steps of obtaining the current flowing from the first power ball area 21 to the third chip area 13, the current flowing from the second power ball area 22 to the third chip area 13, and the current flowing from the third power ball area 23 to the third chip area 13 include:

[0112] The resistor R through which the current is obtained from the first power ball region 21 to the third chip region 13 1C , the current flows from the second power ball area 22 to the third chip area 13 through the resistor R 2C and the resistor R through which the current flows from the third power ball region 23 to the third chip region 13 3C ;

[0113] According to Ohm's law Get the formula formula and formula

[0114] According to the formula The current flowing from the first power ball area 21 to the third chip area 13 is obtained according to the formula The current flowing from the second power ball area 22 to the third chip area 13 is obtained according to the formula A current is obtained which flows from the third power ball region 23 to the third chip area 13 .

[0115] Combining the above formulas, the current flowing through the first power ball area is

[0116]

[0117] The current flowing through the second power ball area is

[0118]

[0119] The current flowing through the third power ball area is

[0120]

[0121] It can be understood that the step of calculating the number of power grid balls 40 required for each power grid ball area according to the total current includes:

[0122] Get the maximum carrying current value I of each grid ball MAX ;

[0123] According to the formula N1=I1 / I MAX , the number of power grid balls required for the first power grid ball area 21 is obtained, according to the formula N2 = I2 / I MAX , the number of power grid balls required for the second power grid ball area 22 is obtained, according to the formula N3 = I3 / I MAX, obtaining the number of power grid balls required for the third power grid ball area 23;

[0124] N1 is the number of power balls required in the first power ball region 21 , N2 is the number of power balls 40 required in the second power ball region 22 , and N3 is the number of power balls 40 required in the third power ball region 23 .

[0125] It can be understood that the number of power grid balls 40 required for the packaged chip is obtained by adding the number of power grid balls 40 required for each power grid ball area to obtain the number of power grid balls 40 required for the packaged chip: N total =N1+N2+N3, where N total The total number of power balls 40 required for packaging the chip.

[0126] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for designing the number of power grid balls of a packaged chip, characterized in that: The steps include: Dividing the package substrate into at least two power grid ball areas along the current path; According to the positions of the at least two power ball grid regions, the chip bare die is divided into at least two chip regions, and the at least two chip regions and the at least two power ball grid regions are arranged in a one-to-one correspondence; respectively obtaining the total amount of current required by each chip region; The total current passing through each power ball area is calculated according to the total current required by each chip area; Calculating the number of power grid balls required for each power grid ball area according to the total current; The number of power grid balls required by all the power grid ball areas is added together to obtain the number of power grid balls required by the packaged chip.

2. The method for designing the number of power grid balls of a packaged chip according to claim 1, characterized in that: The number of the power grid ball regions is three, which are respectively a first power grid ball region, a second power grid ball region and a third power grid ball region along the current path; The number of the chip regions corresponding to the power ball region is also three, which are the first chip region, the second chip region and the third chip region along the current path.

3. The method for designing the number of power grid balls of a packaged chip according to claim 2, characterized in that: The step of respectively obtaining the total amount of current required by each chip region comprises: Respectively obtain the type and quantity of circuit modules included in each chip area and the current consumed by each type of circuit module; The total current I required by the first chip area is calculated based on the type and quantity of the circuit modules and the current consumed by each type of circuit module. A , the total current I required by the second chip area B and the total current I required by the third chip region C .

4. The method for designing the number of power grid balls of a packaged chip according to claim 3, characterized in that: The step of calculating the total current passing through the first power ball area according to the total current required by the three chip areas comprises: respectively calculating the currents flowing from the first power ball area to the first chip area, the second chip area and the third chip area in sequence; According to the formula: I1=I 1A +I 1B +I 1C , calculating the total current of the first power grid ball area; Where I1 is the total current of the first power ball area, I 1A is the current flowing from the first power ball area to the first chip area, I 1B is the current flowing from the first power ball area to the second chip area, I 1C is the current flowing from the first power ball area to the third chip area.

5. The method for designing the number of power grid balls of a packaged chip according to claim 4, characterized in that: The total current passing through the second power ball region is calculated according to the total currents respectively required by the second chip region and the third chip region, comprising: respectively calculating the currents flowing from the second power ball region to the second chip region and the third chip region in sequence; According to the formula: I2=I 2B +I 2C , calculating the total current of the second power grid ball area; Where I2 is the total current of the second power ball area, I 2B is the current flowing from the second power ball region to the second chip region, I 2C is the current flowing from the second power ball region to the third chip region.

6. The method for designing the number of power grid balls of a packaged chip according to claim 5, characterized in that: The total current passing through the third power ball region is calculated according to the total current required by the third chip region, comprising: calculating a current flowing from the third power ball region to the third chip region; According to the formula: I3=I 3C , calculating the total current of the third power grid ball area; Where I3 is the total current of the third power ball area, I 3C is the current flowing from the third power ball region to the third chip region.

7. The method for designing the number of power grid balls of a packaged chip according to claim 6, characterized in that: The formula for calculating the current flowing from the first power ball area to the first chip area in sequence is I A =I 1A , obtaining a current flowing from the first power ball region to the first chip region; And / or, the formula for calculating the current flowing from the first power ball area and from the second power ball area to the second chip area is I B =I 1B +I 2B , obtaining a current flowing from the first power ball region to the second chip region and a current flowing from the second power ball region to the second chip region; And / or, the formula for calculating the current flowing from the first power ball region, the second power ball region and the third power ball region to the third chip region is I C =I 1C +I 2C +I 3C , obtaining the current flowing from the first power gate ball area to the third chip area, the current flowing from the second power gate ball area to the third chip area, and the current flowing from the third power gate ball area to the third chip area.

8. The method for designing the number of power grid balls of a packaged chip according to claim 7, characterized in that: The step of obtaining the current flowing from the first power ball region to the second chip region and the current flowing from the second power ball region to the second chip region comprises: The resistor R through which the current is obtained from the first power ball area to the second chip area 1B and the current flows from the second power ball area to the second chip area through the resistor R 2B ; According to Ohm's law I 2B / I 1B =R 1B / R 2B , we get the formula and formula According to the formula The current flowing from the first power ball area to the second chip area is obtained according to the formula A current flowing from the second power ball area to the second chip area is obtained.

9. The method for designing the number of power grid balls of a packaged chip according to claim 8, characterized in that: The steps of obtaining the current flowing from the first power ball region to the third chip region, the current flowing from the second power ball region to the third chip region, and the current flowing from the third power ball region to the third chip region include: The resistor R through which the current is obtained from the first power ball area to the third chip area 1C , the resistor R through which the current flows from the second power ball area to the third chip area 2C and the current flows from the third power ball area to the third chip area through the resistor R 3C ; According to Ohm's law Get the formula formula and formula According to the formula The current flowing from the first power ball area to the third chip area is obtained according to the formula The current flowing from the second power ball area to the third chip area is obtained according to the formula A current flowing from the third power ball region to the third chip region is obtained.

10. The method for designing the number of power grid balls of a packaged chip according to claim 9, characterized in that: The step of calculating the number of power grid balls required for each power grid ball area according to the total current comprises: Get the maximum carrying current value I of each grid ball MAX ; According to the formula N1=I1 / I MAX , the number of power grid balls required for the first power grid ball area is obtained, according to the formula N2 = I2 / I MAX , the number of power grid balls required for the second power grid ball area is obtained, according to the formula N3=I3 / I MAX , obtaining the number of power grid balls required for the third power grid ball area; Wherein, N1 is the number of power balls required in the first power ball area, N2 is the number of power balls required in the second power ball area, and N3 is the number of power balls required in the third power ball area.

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