Memory and operating method thereof

Abstract

The embodiment of the invention discloses a memory and an operation method thereof. The memory comprises a memory cell array and a peripheral circuit coupled with the memory cell array, the memory cell array comprises a plurality of bit lines, a plurality of word lines and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines; the peripheral circuit is configured to: in response to a write command, apply a first voltage to a selected word line, apply a second voltage to a selected bit line, apply a ground voltage to an unselected word line, and apply a supply voltage to the unselected bit line, such that a target memory cell coupled to the selected word line and the selected bit line is in a conductive state, and enabling the non-target storage unit coupled with the unselected word line and / or the unselected bit line to be in a non-conducting state.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, for example, to a memory and an operating method thereof. Background Art

[0002] Semiconductor memories can be roughly divided into two categories, depending on whether they retain stored data when power is off; the two categories of semiconductor memories are: volatile memory, which loses stored data when power is off, and non-volatile memory, which retains stored data when power is off.

[0003] As an emerging non-volatile memory device, phase change memory has great advantages over flash memory in many aspects such as read and write speed, read and write times, data retention time, unit area, and multi-value realization. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a memory is provided, comprising a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines; the peripheral circuit is configured to: in response to a write command, apply a first voltage to a selected word line, apply a second voltage to a selected bit line, apply a ground voltage to an unselected word line, and apply a power supply voltage to an unselected bit line, so that a target memory cell coupled to the selected word line and the selected bit line is in a conductive state, and a non-target memory cell coupled to the unselected word line and / or the unselected bit line is in a non-conductive state.

[0005] In some optional embodiments, the plurality of memory cells in the memory cell array are configured to have a set state and a reset state; the set state corresponds to a first threshold voltage distribution, the reset state corresponds to a second threshold voltage distribution, the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution; the difference between the first voltage and the second voltage is greater than the maximum value of the second threshold voltage distribution.

[0006] In some optional embodiments, the first voltage is greater than 0, the second voltage is less than 0, and the first voltage is greater than the absolute value of the second voltage.

[0007] In some optional embodiments, the difference between the first voltage and the power supply voltage is a first value, the difference between the ground voltage and the second voltage is a second value, and both the first value and the second value are smaller than the minimum value of the first threshold voltage distribution.

[0008] In some optional embodiments, an absolute value of a difference between the first value and the second value is less than or equal to 0.2V.

[0009] In some optional embodiments, the absolute value of the difference between the first value and the second value is equal to 0.

[0010] In some optional embodiments, the first voltage ranges from 4V to 5V, the second voltage ranges from -4V to -3V, and the power supply voltage ranges from 1.1V to 1.2V.

[0011] In some optional embodiments, the peripheral circuit is configured to: perform a set operation or a reset operation on the target memory cell based on the target memory cell being in a conductive state.

[0012] In some optional embodiments, the memory cell comprises a phase change memory cell; the phase change memory cell comprises a phase change element and a gating element connected in series with the phase change element.

[0013] According to a second aspect of an embodiment of the present disclosure, a method for operating a memory is provided, the method comprising: in response to a write command, applying a first voltage to a selected word line, applying a second voltage to a selected bit line, applying a ground voltage to an unselected word line, and applying a power supply voltage to an unselected bit line, so that a target memory cell coupled to the selected word line and the selected bit line is in a conductive state, and a non-target memory cell coupled to the unselected word line and / or the unselected bit line is in a non-conductive state.

[0014] In the disclosed embodiment, a first voltage is applied to a selected word line and a second voltage is applied to a selected bit line so that the target memory cell is in a conducting state, and a ground voltage is applied to an unselected word line and a power supply voltage is applied to an unselected bit line so as to further make the non-target memory cell coupled to the unselected word line and / or the unselected bit line in a non-conducting state. In the scheme of the disclosed embodiment, in the first aspect, a dual-rail power supply is adopted to apply voltages to the selected word line and the selected bit line at the same time, so that the problems of the single-rail power supply scheme that a high-voltage resistant process is required, the power consumption is large, and the high voltage will accelerate the threshold voltage drift of the storage data of the non-target memory cell can be improved; in the second aspect, the first voltage and the second voltage are applied to the selected word line and the selected bit line coupled to the target memory cell respectively, so that the problems of the need to use a high-voltage resistant process and high power consumption caused by applying a higher voltage only to the selected word line or the selected bit line can be avoided; in the third aspect, a ground voltage is applied to the unselected word line and a power supply voltage is applied to the unselected bit line. A power supply voltage is applied to the neutral line to perform voltage compensation on the unselected word line and the unselected bit line, so that the non-target memory cell is in a non-conducting state, thereby avoiding the problem that the non-target memory cell is mistakenly opened and the data of the non-target memory cell is mistakenly rewritten; fourthly, the ground voltage applied to the unselected word line and the power supply voltage applied to the unselected bit line can be provided by the existing logic circuit power supply in the memory, and no additional voltage is added, thereby avoiding the problem of adding too many voltage sources in the memory due to the addition of additional voltage and the more complicated routing of the power supply in the memory cell array, which can save the area and cost of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structure of an exemplary system provided in an embodiment of the present disclosure;

[0016] Figure 2 A schematic diagram of the structure of a memory including a memory cell array and a peripheral circuit provided in an embodiment of the present disclosure;

[0017] Figure 3 A schematic diagram of a storage unit provided in an embodiment of the present disclosure Figure 1 ;

[0018] Figure 4 A schematic diagram of a storage unit provided in an embodiment of the present disclosure Figure 2 ;

[0019] Figure 5 A schematic diagram of pulses for performing a set operation and a reset operation on a phase change memory cell is shown;

[0020] Figure 6 A schematic diagram of the threshold voltage distribution of a memory cell in a memory provided by an embodiment of the present disclosure;

[0021] Figure 7 The relationship between the threshold voltage distribution and the applied voltage provided in the embodiment of the present disclosure is shown in FIG. Figure 1 ;

[0022] Figure 8 A schematic diagram of voltage application conditions of each storage unit provided in an embodiment of the present disclosure;

[0023] Fig. 9 The relationship between the threshold voltage distribution and the applied voltage provided in the embodiment of the present disclosure is shown in FIG. Figure 2 . DETAILED DESCRIPTION

[0024] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0025] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0026] In the drawings, like reference numerals refer to like elements throughout.

[0027] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0028] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0029] like Figure 1 As shown, an embodiment of the present disclosure shows an exemplary system 10, which may include a host 20 and a memory system 30. The exemplary system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory 34 therein; the host 20 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device. The memory system 30 includes a memory controller 32 and a memory 34 coupled to the memory controller 32.

[0030] Exemplarily, the memory controller 32 can communicate with an external host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, Firewire protocol, ONFI, DDR, LPDDR, etc.

[0031] The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the memory cell array may include a plurality of memory cells. The memory cell array may be integrated on the same die as the peripheral circuit, which allows a wider bus and a higher operating speed. In some embodiments, the memory cell array and the peripheral circuit may be formed in different regions on the same plane; or the memory cell array and the peripheral circuit may form a stacked structure, i.e., the two are formed on different planes.

[0032] Figure 2 FIG. 1 shows a schematic diagram of the structure of a memory including a memory cell array and a peripheral circuit. Figure 2 As shown, the memory 304 includes a memory cell array 401 and a peripheral circuit 402 coupled to the memory cell array 401. The memory cell array 401 may include a plurality of memory cells 4013 arranged in rows and columns. The plurality of memory cells 4013 arranged in rows are coupled to the same word line (WL) 4011, and the plurality of memory cells arranged in columns are coupled to the same bit line (BL) 4012.

[0033] In the embodiments of the present disclosure, the memory includes but is not limited to a variety of memory types such as phase change memory (PCM) and selector only memory (SOM). It should be understood that the present disclosure is not limited thereto. In some embodiments, the storage unit is a phase change memory unit, such as Figure 3As shown, the phase change memory cell 130 includes a gating element 110 and a phase change element 120 connected in series. In some embodiments, the memory cell is a select-only memory cell, such as Figure 4 As shown, only the selected memory cell 140 includes the gating element 110 .

[0034] The following is an explanation using a phase change memory as an example. The basic storage principle of phase change memory is to apply voltage or current pulse signals of different widths and heights to the phase change memory unit to change the physical phase of the phase change material in the phase change element of the phase change memory unit, for example, to achieve reversible mutual conversion between the crystalline state (low resistance state) and the amorphous state (high resistance state) of the phase change material, thereby realizing data storage. When the memory unit is in the crystalline state and the amorphous state, it has different threshold voltages, wherein the threshold voltage of the crystalline state (defined as 1) is lower, and the threshold voltage of the amorphous state (defined as 0) is higher. The operation that can complete the crystalline conversion of the memory unit is defined as a set operation, and the operation that can complete the amorphous conversion of the memory unit is defined as a reset operation.

[0035] In some embodiments, in order to realize the conversion of the phase change material in the phase change memory between the crystalline state and the amorphous state, different pulses (eg, light pulses, electrical pulses) may be used to control the heating of the phase change material. Figure 5 FIG. 4 shows a schematic diagram of pulses for performing a set operation and a reset operation on a phase change memory cell. Figure 5 As shown, the set operation includes: by applying a long and medium-intensity set pulse to raise the temperature of the phase change material of the phase change memory unit to below the melting temperature Tm and above the crystallization temperature Tx, and maintaining it for a period of time and promoting the growth of the crystal nucleus, the phase change material of the phase change memory unit can be transformed from the amorphous state (corresponding to the high resistance state) to the crystalline state (corresponding to the low resistance state). The reset operation includes: by applying a short and strong reset pulse to raise the temperature of the phase change material of the phase change memory unit to above the melting temperature Tm, and then rapidly cooling it, the phase change material of the phase change memory unit can be transformed from the crystalline state to the amorphous state. Among them, the set process and the reset process are mutually reversible processes, so that the phase change memory unit can use the crystalline state to represent the unit binary data "1", and use the amorphous state to represent the binary data "0".

[0036] Figure 6 A schematic diagram of the threshold voltage distribution of a storage unit in a memory provided by an embodiment of the present disclosure. Figure 6 As shown, a plurality of memory cells in the memory have a set state (crystalline state) and a reset state (amorphous state). The memory cells with the set state correspond to a first threshold voltage distribution, and the memory cells with the reset state correspond to a second threshold voltage distribution, wherein the minimum voltage of the second threshold voltage distribution is greater than the maximum voltage of the first threshold voltage distribution.

[0037] In order to implement the write operation, that is, to complete the above-mentioned set operation or reset operation, such as Figure 7 As shown, a maximum voltage higher than the threshold voltage distribution (second threshold voltage distribution) corresponding to the memory cell in the reset state needs to be applied to both ends of the target memory cell to ensure that the target memory cell is in the on state. The voltage Vwrite higher than the maximum voltage of the threshold voltage distribution corresponding to the memory cell in the reset state is generally higher.

[0038] In some embodiments, the higher Vwrite is applied to the selected word line or the selected bit line coupled to the target memory cell through a single-rail power supply. Non-target memory cells in the memory cell array that are in common with the selected word line or the selected bit line will also be subjected to a higher voltage, which will accelerate the threshold voltage drift of the storage data of the non-target memory cells, and may eventually cause errors in reading data from these non-target memory cells; in addition, the single-rail power supply solution requires the use of a high-voltage resistant process, and the power consumption is relatively large.

[0039] An embodiment of the present disclosure provides a memory, which includes a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes multiple bit lines, multiple word lines, and multiple memory cells located between the multiple bit lines and the multiple word lines; the peripheral circuit is configured to: in response to a write command, apply a first voltage to a selected word line, apply a second voltage to a selected bit line, apply a ground voltage to an unselected word line, and apply a power supply voltage to an unselected bit line, so that the target memory cell coupled to the selected word line and the selected bit line is in a conductive state, and the non-target memory cell coupled to the unselected word line and / or the unselected bit line is in a non-conductive state.

[0040] Figure 8 Schematic diagram of voltage application to each storage unit provided in the embodiment of the present disclosure. Figure 8 As shown, a first voltage (VH) is applied to a selected word line, a second voltage (VN) is applied to a selected bit line, a ground voltage (VSS) is applied to an unselected word line, and a power supply voltage (VDD) is applied to an unselected bit line. The target memory cell is cell0.

[0041] In the disclosed embodiment, a first voltage is applied to a selected word line and a second voltage is applied to a selected bit line so that the target memory cell is in a conducting state, and a ground voltage is applied to an unselected word line and a power supply voltage is applied to an unselected bit line so as to further make the non-target memory cell coupled to the unselected word line and / or the unselected bit line in a non-conducting state. In the scheme of the disclosed embodiment, in the first aspect, a dual-rail power supply is adopted to apply voltages to the selected word line and the selected bit line at the same time, so that the problems of the single-rail power supply scheme that a high-voltage resistant process is required, the power consumption is large, and the high voltage will accelerate the threshold voltage drift of the storage data of the non-target memory cell can be improved; in the second aspect, the first voltage and the second voltage are applied to the selected word line and the selected bit line coupled to the target memory cell respectively, so that the problems of the need to use a high-voltage resistant process and high power consumption caused by applying a higher voltage only to the selected word line or the selected bit line can be avoided; in the third aspect, a ground voltage is applied to the unselected word line and a power supply voltage is applied to the unselected bit line. A power supply voltage is applied to the neutral line to perform voltage compensation on the unselected word line and the unselected bit line, so that the non-target memory cell is in a non-conducting state, thereby avoiding the problem that the non-target memory cell is mistakenly opened and the data of the non-target memory cell is mistakenly rewritten; fourthly, the ground voltage applied to the unselected word line and the power supply voltage applied to the unselected bit line can be provided by the existing logic circuit power supply in the memory, and no additional voltage is added, thereby avoiding the problem of adding too many voltage sources in the memory due to the addition of additional voltage and the more complicated routing of the power supply in the memory cell array, which can save the area and cost of the memory.

[0042] In some embodiments, multiple memory cells in the memory cell array are configured to have a set state and a reset state; the set state corresponds to a first threshold voltage distribution, the reset state corresponds to a second threshold voltage distribution, the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution; the difference between the first voltage and the second voltage is greater than the maximum value of the second threshold voltage distribution.

[0043] In the disclosed embodiment, a first voltage is applied to a selected word line, and a second voltage is applied to a selected bit line, and the first voltage is greater than 0, and the second voltage is less than 0, that is, a positive voltage is applied to the selected word line, and a negative voltage is applied to the selected bit line. The voltage across the target memory cell is the difference between the first voltage and the second voltage, and the difference between the first voltage and the second voltage is greater than the maximum value of the second threshold voltage distribution, that is, the voltage across the target memory cell is greater than the maximum threshold voltage of the memory cell, so that no matter whether the target memory cell is in a set state or a reset state, or no matter whether the threshold voltage of the target memory cell is higher or lower, it can be ensured that the target memory cell is in a conducting state.

[0044] Fig. 9Schematic diagram of the relationship between the threshold voltage distribution and the applied voltage provided in the embodiment of the present disclosure. Figure 8 as well as Fig. 9 As shown, the non-target memory cells can be divided into three types according to the voltage across the non-target memory cells: the first type, non-target memory cell cell1, non-target memory cell cell1 is coupled to the selected word line and the unselected bit line, and the voltage across the non-target memory cell cell1 is (VH-VDD); the second type, non-target memory cell cell2, non-target memory cell cell2 is coupled to the unselected word line and the selected bit line, and the voltage across the non-target memory cell cell2 is (VSS-VN); the third type, non-target memory cell cell3, non-target memory cell cell3 is coupled to the unselected word line and the unselected bit line, and the voltage across the non-target memory cell cell3 is (VSS-VDD). In addition, the voltage across the target memory cell cell0 is (VH-VN), and (VH-VN) is equal to Vwrite.

[0045] In some embodiments, the first voltage is greater than 0, the second voltage is less than 0, and the first voltage is greater than an absolute value of the second voltage.

[0046] In the disclosed embodiment, the first voltage is greater than the absolute value of the second voltage, and an asymmetric voltage application method is adopted for the selected word line and the selected bit line, so that the voltage (VSS-VN) across the non-target storage cell cell2 can be less than Vwrite / 2. Figure 7 As shown, Vwrite / 2 here is greater than the minimum voltage of the first threshold voltage distribution and less than the maximum voltage of the first threshold voltage distribution.

[0047] In some embodiments, a difference between the first voltage and the power supply voltage is a first value, a difference between the ground voltage and the second voltage is a second value, and both the first value and the second value are smaller than a minimum value of the first threshold voltage distribution.

[0048] Here, the first value is (VH-VDD), and the second value is (VSS-VN). Both the first value and the second value are smaller than the minimum value of the first threshold voltage distribution, so that when the target memory cell cell0 is in the on state, the non-target memory cell cell1 and the non-target memory cell cell2 will not be mistakenly turned on.

[0049] In the disclosed embodiment, the voltage across the non-target memory cell cell3 is (VSS-VDD), and (VSS-VDD) is less than the minimum value of the first threshold voltage distribution. When the target memory cell cell0 is in the on state, the non-target memory cell cell3 will not be mistakenly turned on.

[0050] In some embodiments, an absolute value of a difference between the first value and the second value is less than or equal to 0.2V.

[0051] In the disclosed embodiment, the absolute value of the difference between the first value and the second value is small, that is, the first value is close to the second value, so that the voltages across different non-target memory cells are more balanced, and the bias drift phenomenon is greatly improved. The bias drift here can be understood as the phenomenon that the threshold voltage of the non-target memory cell coupled to the selected word line or the selected bit line is shifted by applying pressure to the selected word line and the selected bit line.

[0052] In some embodiments, the absolute value of the difference between the first value and the second value is equal to zero.

[0053] It can be understood that when the absolute value of the difference between the first value and the second value is equal to 0, the first value is equal to the second value. In this case, the voltages across different non-target memory cells can be more balanced, so that the bias drift phenomenon is improved to the greatest extent. In addition, when the absolute value of the difference between the first value and the second value is equal to 0, relative to the binary method (Vwrite / 2 is applied to the selected word line and -Vwrite / 2 is applied to the selected bit line), the above embodiment can reduce the voltage across the non-target memory cell cell1 and the non-target memory cell cell2 by VDD / 2.

[0054] In some embodiments, the first voltage ranges from 4V to 5V, the second voltage ranges from -4V to -3V, and the power supply voltage ranges from 1.1V to 1.2V.

[0055] It should be noted that the ranges of the first voltage, the second voltage, and the power supply voltage given in the above embodiments are only examples and are not used to limit the ranges of the first voltage, the second voltage, and the power supply voltage in the embodiments of the present disclosure. In some specific examples, corresponding adjustments can be made according to actual needs.

[0056] In some embodiments, the peripheral circuit is configured to:

[0057] Based on the target memory cell being in the on state, a set operation or a reset operation is performed on the target memory cell.

[0058] In the embodiment of the present disclosure, on the basis of making the target memory cell in a conducting state in response to the write command, a set operation or a reset operation is performed on the target memory cell, thereby realizing writing "0" or writing "1".

[0059] In some embodiments, the memory cell comprises a phase change memory cell; the phase change memory cell comprises a phase change element and a gating element connected in series with the phase change element.

[0060] In some specific examples, the phase change element may include a chalcogenide component, such as a binary compound such as GaSb, InSb, InSe, SbTe, and GeTe, a ternary compound such as GeSbTe, GaSeTe, InSbTe, SnSbTe, and InSbGe, and a quaternary compound such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and TeGeSbS. The gating element may include a material having an Ovonic Threshold Switch (OTS) property, and the material having the OTS property may include at least one element of oxygen, sulfur, selenium, tellurium, germanium, antimony, silicon, and arsenic, such as ZnxTey, GexTey, NbxOy, SixAsyTez, etc.

[0061] In the disclosed embodiment, the power supply voltage and ground voltage applied to the unselected word line and the unselected bit line are both voltages commonly used in the memory, and the VDD and VSS that can be provided by the existing general logic circuit power supply are used to reduce the pressure of the non-target memory cells coupled to the selected word line and / or the selected bit line, thereby eliminating the risk of the threshold voltage of the non-target memory cells coupled to the selected word line and / or the selected bit line being mistakenly turned on, and reducing the bias drift; in addition, since charging and discharging all the unselected bit lines requires a large power consumption, if an internal additional voltage source is used to charge the unselected bit lines, the required voltage source It has a larger load capacity, so a larger chip area is required, and the interconnection lines that power the memory cell array also need a larger current capacity, which requires a wider power path, which may further increase the area of ​​the memory cell array. Directly borrowing the existing logic power supply VDD and VSS effectively avoids these problems. The logic power supplies VDD and VSS are the most used voltages in the chip. Therefore, the power paths of VDD and VSS in the memory cell array are originally sufficient and can fully support the charging and discharging of unselected bit lines. Therefore, there is no need to add additional wiring or additional chip area.

[0062] Based on the above memory, an embodiment of the present disclosure further provides a memory system, which includes the memory described in any of the above embodiments and a memory controller coupled to the memory, and the memory controller is configured to control the memory.

[0063] Based on the above-mentioned memory, an embodiment of the present disclosure also provides a method for operating the memory, the operating method comprising: in response to a write command, applying a first voltage to a selected word line, applying a second voltage to a selected bit line, applying a ground voltage to an unselected word line, and applying a power supply voltage to an unselected bit line, so that the target memory cell coupled to the selected word line and the selected bit line is in a conductive state, and the non-target memory cell coupled to the unselected word line and / or the unselected bit line is in a non-conductive state.

[0064] In some embodiments, multiple memory cells in the memory cell array are configured to have a set state and a reset state; the set state corresponds to a first threshold voltage distribution, the reset state corresponds to a second threshold voltage distribution, the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution; the difference between the first voltage and the second voltage is greater than the maximum value of the second threshold voltage distribution.

[0065] In some embodiments, the first voltage is greater than 0, the second voltage is less than 0, and the first voltage is greater than an absolute value of the second voltage.

[0066] In some embodiments, a difference between the first voltage and the power supply voltage is a first value, a difference between the ground voltage and the second voltage is a second value, and both the first value and the second value are smaller than a minimum value of the first threshold voltage distribution.

[0067] In some embodiments, an absolute value of a difference between the first value and the second value is less than or equal to 0.2V.

[0068] In some embodiments, the absolute value of the difference between the first value and the second value is equal to 0.

[0069] In some embodiments, the first voltage ranges from 4V to 5V, the second voltage ranges from -4V to -3V, and the power supply voltage ranges from 1.1V to 1.2V.

[0070] In some embodiments, the operating method further includes: performing a set operation or a reset operation on the target memory cell based on the target memory cell being in a conductive state.

[0071] In some embodiments, the memory cell comprises a phase change memory cell; the phase change memory cell comprises a phase change element and a gating element connected in series with the phase change element.

[0072] The specific details of the operation method of the memory have been introduced in detail on the aforementioned memory side, and will not be repeated here for the sake of brevity.

[0073] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0074] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0075] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A memory, characterized in that: The memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines; the peripheral circuit is configured as follows: In response to a write command, a first voltage is applied to a selected word line, a second voltage is applied to a selected bit line, a ground voltage is applied to an unselected word line, and a power supply voltage is applied to an unselected bit line, so that the target memory cells coupled to the selected word line and the selected bit line are in a conductive state, and the non-target memory cells coupled to the unselected word line and / or the unselected bit line are in a non-conductive state.

2. The memory according to claim 1, characterized in that: The multiple memory cells in the memory cell array are configured to have a set state and a reset state; the set state corresponds to a first threshold voltage distribution, the reset state corresponds to a second threshold voltage distribution, the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution; the difference between the first voltage and the second voltage is greater than the maximum value of the second threshold voltage distribution.

3. The memory according to claim 2, characterized in that: The first voltage is greater than 0, the second voltage is less than 0, and the first voltage is greater than an absolute value of the second voltage.

4. The memory according to claim 2, characterized in that: A difference between the first voltage and the power supply voltage is a first value, a difference between the ground voltage and the second voltage is a second value, and both the first value and the second value are smaller than a minimum value of the first threshold voltage distribution.

5. The memory according to claim 4, characterized in that: An absolute value of a difference between the first value and the second value is less than or equal to 0.2V.

6. The memory according to claim 5, characterized in that: An absolute value of a difference between the first value and the second value is equal to 0.

7. The memory according to claim 1, characterized in that: The first voltage ranges from 4V to 5V, the second voltage ranges from -4V to -3V, and the power supply voltage ranges from 1.1V to 1.2V.

8. The memory according to claim 1, characterized in that: The peripheral circuit is configured as: Based on the target memory cell being in the on state, a set operation or a reset operation is performed on the target memory cell.

9. The memory according to claim 1, characterized in that: The memory cell comprises a phase change memory cell; the phase change memory cell comprises a phase change element and a gating element connected in series with the phase change element.

10. A method for operating a memory, characterized in that: The operation method comprises: In response to a write command, a first voltage is applied to a selected word line, a second voltage is applied to a selected bit line, a ground voltage is applied to an unselected word line, and a power supply voltage is applied to an unselected bit line, so that the target memory cells coupled to the selected word line and the selected bit line are in a conductive state, and the non-target memory cells coupled to the unselected word line and / or the unselected bit line are in a non-conductive state.

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