Pixel circuit, driving method thereof and display panel

Abstract

The invention discloses a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises a driving transistor which is an N-type transistor; the first end of the compensation module and the gate of the driving transistor are electrically connected to a first node, and the second end and the first pole of the driving transistor are electrically connected to a second node; a first end of the write-in module is electrically connected with a data voltage end, a second end is electrically connected with a first pole plate of the first capacitor, and a second pole plate of the first capacitor is electrically connected with a grid electrode of the driving transistor; the first end of the first light-emitting control module is electrically connected with the first power supply voltage end, and the second end is electrically connected with the second node; the first end of the second light-emitting control module and the second electrode of the driving transistor are electrically connected to a third node, and the second end and the light-emitting element are electrically connected to a fourth node; the first pole plate is electrically connected with the first node, and the second pole plate is electrically connected with the fourth node. By adopting the technical scheme, the problems of ghost shadow and splash screen caused by hysteresis of the driving transistor can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display panel. Background Art

[0002] Organic light-emitting display is the mainstream technology for displays in mobile phones, televisions, computers, etc. Compared with traditional liquid crystal displays, organic light-emitting display has the advantages of low energy consumption, low cost, self-luminescence, wide viewing angle and fast response speed.

[0003] Organic light-emitting displays are driven by current and require a stable driving current to control their light emission. The magnitude and stability of the driving current of organic light-emitting displays mainly depend on the magnitude and stability of the gate-source voltage and threshold voltage of the driving transistor in the pixel circuit.

[0004] However, due to the hysteresis effect of the driving transistor, the threshold voltage may drift, resulting in unstable driving current, which may easily cause afterimage or screen flickering. Summary of the invention

[0005] The present invention provides a pixel circuit and a driving method thereof, and a display panel, so as to improve the afterimage and screen flickering problems caused by the hysteresis of the driving transistor.

[0006] According to one aspect of the present invention, there is provided a pixel circuit, comprising: a driving transistor, a light emitting element, a compensation module, a writing module, a first light emitting control module, a second light emitting control module, a first capacitor and a second capacitor;

[0007] The first end of the compensation module is electrically connected to the gate of the driving transistor at a first node, and the second end of the compensation module is electrically connected to the first electrode of the driving transistor at a second node; the first end of the writing module is electrically connected to the data voltage end, the second end of the writing module is electrically connected to the first plate of the first capacitor, and the second plate of the first capacitor is electrically connected to the gate of the driving transistor;

[0008] A first end of the first light emitting control module is electrically connected to the first power supply voltage end, and a second end of the first light emitting control module is electrically connected to the second node;

[0009] The first end of the second light emitting control module and the second electrode of the driving transistor are electrically connected to a third node, and the second end of the second light emitting control module and the light emitting element are electrically connected to a fourth node;

[0010] The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the fourth node;

[0011] The driving transistor is an N-type transistor.

[0012] According to another aspect of the present invention, a driving method of a pixel circuit is provided, for driving the above-mentioned pixel circuit; the driving method comprises:

[0013] In the reset stage, the first power supply voltage terminal is connected to the second node, and the first node is connected to the second node;

[0014] In the compensation stage, the second node is conductively connected to the first node, the first power supply voltage terminal is conductively connected to the second node, or the third node is conductively connected to the fourth node;

[0015] In the writing stage, the data voltage terminal is connected to the first plate of the first capacitor;

[0016] In the light emitting stage, the first power supply voltage terminal is conductively connected to the second node, and the third node is conductively connected to the fourth node.

[0017] According to yet another aspect of the present invention, there is provided a display panel comprising: a plurality of the above pixel circuits arranged in an array.

[0018] The technical solution of the present invention, by setting the driving transistor as an N-type transistor, makes the carriers of the driving transistor electrons, the mobility is higher, the sensitivity of the threshold voltage is also lower, and the hysteresis and threshold voltage drift of the driving transistor can be improved; by setting the writing module to be coupled with the gate of the driving transistor, the compensation module is connected between the gate and the first pole of the driving transistor, the compensation stage and the writing stage can be separated, so that the threshold voltage compensation process has sufficient time, which is conducive to improving the charging rate in the threshold voltage compensation process, even if the pixel circuit is in a fixed gray scale for a long time or the refresh frequency is low, the threshold voltage is offset, the compensation module can also fully compensate the offset threshold voltage to the driving transistor, improve the luminous accuracy, improve the problem of residual image and low gray scale flicker. In addition, a first capacitor and a second capacitor are also set, and the first node and the third node can be coupled by the first capacitor and the second capacitor, so as to realize the precise control of the gate-source voltage of the driving transistor, which is conducive to the luminous accuracy; at the same time, the size of the driving current can also be adjusted by the first capacitor and the second capacitor, so as to realize the regulation of the range of the data signal, which is conducive to reducing the voltage drop of the gate of the driving transistor, further improving the hysteresis and threshold voltage drift of the driving transistor, and improving the display quality.

[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a circuit structure schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of a top view structure of a display panel provided by an embodiment of the present invention;

[0023] Figure 3 is a timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0024] Figure 4 is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0025] Figure 5 is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0026] Figure 6 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0027] Figure 7 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0028] Figure 8 is a schematic diagram of refreshing a pixel circuit provided by an embodiment of the present invention;

[0029] Fig. 9 is a timing diagram of a display panel provided by an embodiment of the present invention;

[0030] Fig.10 is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0031] Fig.11 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0032] Fig.12 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0033] Fig.13 is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0034] Fig.14is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0035] Fig.15 is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0036] Fig.16 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0037] Fig.17 is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0038] Fig.18 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0039] Fig.19 is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0040] Fig. 20 is a flow chart of a driving method of a pixel circuit provided by an embodiment of the present invention;

[0041] Fig.21 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0042] Fig. 22 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0045] The above is the core idea of ​​the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0046] Figure 1 is a circuit structure diagram of a pixel circuit provided by an embodiment of the present invention. Figure 1 The pixel circuit 10 includes a driving transistor M3, a light emitting element OLED, a compensation module 11, a writing module 12, a first light emitting control module 13, a second light emitting control module 14, a first capacitor C1 and a second capacitor C2, wherein the driving transistor M3 is an N-type transistor.

[0047] The first end of the compensation module 11 is electrically connected to the gate of the driving transistor M3 at the first node N1, and the second end of the compensation module 11 is electrically connected to the first electrode of the driving transistor M3 at the second node N2. The first end of the writing module 12 is electrically connected to the data voltage terminal, the second end of the writing module 12 is electrically connected to the first plate of the first capacitor C1, and the second plate of the first capacitor C1 is electrically connected to the gate of the driving transistor M3. The first end of the first light-emitting control module 13 is electrically connected to the first power supply voltage terminal, and the second end of the first light-emitting control module 13 is electrically connected to the second node N2. The first end of the second light-emitting control module 14 is electrically connected to the second electrode of the driving transistor M3 at the third node N3, and the second end of the second light-emitting control module 14 is electrically connected to the fourth node N4. The first plate of the second capacitor C2 is electrically connected to the first node N1, and the second plate of the second capacitor C2 is electrically connected to the fourth node N4.

[0048] Specifically, the first end of the writing module 12 can be electrically connected to the data voltage end through the data line Data_L to receive the data signal Data from the data voltage end; when the writing module 12 is turned on, the data signal Data can be transmitted to the first plate of the first capacitor C1 through the writing module 12. The first end of the first light emitting control module 13 can be electrically connected to the first power supply voltage end through the first power supply line PV1_L to receive the first power supply signal PV1 from the first power supply voltage end.

[0049] In addition, the control end of the writing module 12 can be electrically connected to the first scanning line SP_L to receive the first scanning signal SP; the level of the first scanning signal SP can control the on / off of the writing module 12. The control end of the compensation module 22 can be electrically connected to the second scanning line S2N_L to receive the second scanning signal S2N; the level of the second scanning signal S2N can control the on / off of the compensation module 11. The control end of the first light-emitting control module 13 can be electrically connected to the first light-emitting control line EM1_L to receive the first light-emitting control signal EM1; the level of the first light-emitting control signal EM1 can control the on / off of the first light-emitting control module 13. The control end of the second light-emitting control module 14 can be electrically connected to the second light-emitting control line EM2_L to receive the second light-emitting control signal EM2; the level of the second light-emitting control signal EM2 can control the on / off of the second light-emitting control module 14.

[0050] Exemplarily, the pixel circuit 10 may be applied to a display panel. Figure 2 is a schematic diagram of a top view structure of a display panel provided by an embodiment of the present invention. Figure 2 The display area AA of the display panel 01 may be provided with a plurality of pixel circuits 10 arranged in an array, a plurality of first scan lines SP_L, a plurality of second scan lines S2N_L, a plurality of first light emission control lines EM1_L, and a plurality of second light emission control lines EM2_L. The non-display area NA of the display panel 01 may be provided with a first driving circuit 20, and the first driving circuit 20 includes a first shift register VSR1, a second shift register VSR2, a third shift register VSR3, and a fourth shift register VSR4. The first shift register VSR1, the second shift register VSR2, the third shift register VSR3, and the fourth shift register VSR4 each include a plurality of cascaded shift register units.

[0051] refer to Figure 1 and Figure 2, the first shift register VSR1 can output the first scan signal SP that is shifted in sequence, and at least one shift register unit of the first shift register VSR1 can be electrically connected to a first scan line SP_L, and the first scan line SP_L can be electrically connected to the control end of the write module 12 of the pixel circuit 10. The second shift register VSR2 can output the second scan signal S2N that is shifted in sequence, and at least one shift register unit of the second shift register VSR2 can be electrically connected to a second scan line S2N_L, and the second scan line S2N_L can be electrically connected to the control end of the compensation module 11 of the pixel circuit 10. The third shift register VSR3 can output the first light-emitting control signal EM1 that is shifted in sequence, and at least one shift register unit of the third shift register VSR3 can be electrically connected to a first light-emitting control line EM1_L, and the first light-emitting control line EM1_L can be electrically connected to the control end of the first light-emitting control module 13 of the pixel circuit 10. The fourth shift register VSR4 can output a sequentially shifted second light control signal EM2. At least one shift register unit of the fourth shift register VSR4 can be electrically connected to a second light control line EM2_L. The second light control line EM2_L can be electrically connected to the control end of the second light control module 14 of the pixel circuit 10.

[0052] The display area AA of the display panel 01 may further be provided with a plurality of data lines Data_L, and the non-display area NA may further be provided with a second driving circuit 30. The second driving circuit 30 includes a plurality of data voltage terminals Do, and the data voltage terminal Do may be electrically connected to at least one data line Data_L, and the data line Data_L may be electrically connected to the first terminal of the writing module 12 of the pixel circuit 10.

[0053] In addition, the display area AA of the display panel 01 may further be provided with a plurality of first power lines PV1_L and a plurality of second power lines PV2_L ( Figure 2 The display panel 01 may further include a first power supply voltage terminal and a second power supply voltage terminal ( Figure 2 (not shown in the figure) The first power supply voltage terminal is used to provide a first power supply signal PV1 to a first power supply line PV1_L, and the first power supply line PV1_L can be electrically connected to a first end of a first light emitting control module 13 of the pixel circuit 10. The second power supply voltage terminal is used to provide a second power supply signal PV2 to a second power supply line PV2_L, and the second power supply line PV2_L can be electrically connected to the light emitting element OLED.

[0054] It should be noted that the figure only exemplarily shows that the shift register unit in the shift register is electrically connected to only one scan line or one light-emitting control line, and the data voltage terminal is electrically connected to only one data line. In other embodiments, at least part of the shift register units in the shift register may be electrically connected to multiple scan lines or multiple light-emitting control lines, and the data voltage terminal may be electrically connected to multiple data lines via a gate switch (not shown in the figure).

[0055] It should also be noted that the figure only shows that the first shift register, the second shift register, the third shift register and the fourth shift register are all located on both sides of the display area, and the embodiment of the present invention does not limit the setting position of the shift register. In an optional embodiment, at least part of the shift registers can be located only on one side of the display area. In another optional embodiment, at least part of the shift registers can be set in the display area.

[0056] The working principle of the pixel circuit provided in the embodiment of the present application is described below in conjunction with the timing.

[0057] For example, Figure 3 is a timing diagram of a pixel circuit provided by an embodiment of the present invention, Figure 3 Specific support Figure 1 As shown in the driving timing of the pixel circuit, in one embodiment, the second plate of the first capacitor C1 can be directly electrically connected to the gate of the driving transistor M3 at the first node N1, that is, no device or element is arranged between the second plate of the first capacitor C1 and the gate of the driving transistor M3, but they can be electrically connected through conductive structures such as metal wires, overlapping holes, and overlapping electrodes (not shown in the figure).

[0058] like Figure 3 As shown, the working period of the pixel circuit 10 includes a refresh phase tf, and each refresh phase tf includes a reset phase t1, a compensation phase t2, a write phase t3, and a light-emitting phase t4. For ease of understanding, this embodiment is described with a high level as an enable level and a low level as a non-enable level; in other implementations, each module can also have a low level as an enable level and a high level as a non-enable level. It should be noted that the enable level referred to here is the potential for controlling the conduction between the first end and the second end of each module, and the non-enable level is the potential for controlling the cutoff and disconnection between the first end and the second end of each module.

[0059] refer to Figure 1-Figure 3In the reset stage t1, the first light-emitting control signal EM1 is at the enable level, the second light-emitting control signal EM2 is at the disable level, the first scanning signal SP is at the disable level, and the second scanning signal S2N is at the enable level, so that the first light-emitting control module 13 and the compensation module 11 are turned on, the second light-emitting control module 14 and the writing module 12 are turned off, and the pixel circuit 10 stops providing the driving current to the light-emitting element OLED. The first power supply voltage terminal is connected with the second node N2, and the first power supply signal PV1 of the first power supply voltage terminal can be transmitted to the second node N2 through the first light-emitting control module 13; the first node N1 is connected with the second node N2, and the first power supply signal PV1 of the second node N2 can be transmitted to the first node N1, and the gate and the first electrode of the driving transistor M3 are reset, so that the voltage of the first node N1 and the voltage of the second node N2 are the same as the first power supply signal PV1, that is, VN1=VN2=PV1.

[0060] In the compensation stage t2, the first light-emitting control signal EM1 and the second scanning signal S2N continue to be at the enable level, and the second light-emitting control signal EM2 and the first scanning signal SP continue to be at the non-enable level. In the initial stage when the first light-emitting control signal EM1 and the second scanning signal S2N are both at the enable level, the first light-emitting control module 13 and the compensation module 11 can be in the on state at the same time, the signals of the first node N1 and the second node N2 are the same, and the difference between the voltage VN1 of the first node N1 and the voltage VN3 of the third node N3 is greater than the threshold voltage VTH of the driving transistor M3, that is, VN1=VN2>VN3+VTH, the gate-source voltage VGS of the driving transistor M3=VN1-VN3>VTH, and the driving transistor M3 conducts The first power signal PV1 of the second node N2 can be transmitted to the third node N3 through the driving transistor M3, and the gate-source voltage VGS of the driving transistor M3 is continuously reduced until VGS=VN1-VN3=VTH, the driving transistor M3 is in a transition state of on and off, the current in the driving transistor M3 is reduced to zero, the signal of the first node N1 is no longer transmitted to the third node N3, and the voltage of the third node N3 is stable. At this time, VN3=VN1-VTH=PV1-VTH, and the threshold voltage is compensated to the third node N3.

[0061] Among them, before the signal of the first node N1 is transmitted to the third node N3 through the compensation module 11 and the driving transistor M3, that is, before the reset stage t1, the first light control module 13, the driving transistor M3 and the second light control module 14 can be turned on at the same time, so that the pixel circuit 10 provides a driving current for the light emitting element OLED, and controls the light emitting element OLED to emit light. At this time, the driving transistor M3 is in a saturated state, and the on-state voltage drop VN2-VN3 of the driving transistor M3 is greater than VTH, so that the voltage VN3 of the third node N3 is less than VN2-VTH, that is, VN3 is less than PV1-VTH. Therefore, in the reset stage t1, VN1=VN2=PV1, VGS=VN1-VN3>VTH, and the driving transistor M3 can be turned on. In the threshold compensation stage t2, the first power signal PV1 of the second node N2 can be transmitted to the third node N3 through the driving transistor M3, and the gate-source voltage VGS of the driving transistor M3 is continuously reduced until VGS=VN1-VN3=VTH, so that the threshold voltage is compensated to the third node N3.

[0062] In the writing stage t3, the second light-emitting control signal EM2 continues to be at the non-enable level, and the first light-emitting control signal EM1 and the second scanning signal S2N jump to the non-enable level. The first light-emitting control module 13 can be cut off under the control of the first light-emitting control signal EM1, so that the first power supply voltage terminal and the second node N2 are cut off, and the first power supply signal PV1 at the first power supply voltage terminal stops transmitting to the second node N2. The compensation module 11 can be cut off under the control of the second scanning signal S2N, so that the first node N1 and the second node N2 are cut off, the first node N1 no longer receives the signal of the second node N2, and the voltage of the first node N1 can maintain the voltage at the previous moment.

[0063] After the first light-emitting control signal EM1 and the second scanning signal S2N both jump to the non-enable level, the first scanning signal SP on the first scanning line SP_L jumps to the enable level. The writing module 12 can be turned on under the control of the first scanning signal SP, so that the data voltage terminal Do is connected to the first plate of the first capacitor C1, and the data signal Data on the data line Data_L can be transmitted to the first plate of the first capacitor C1 through the writing module 12. The voltage of the first plate of the first capacitor C1 is Data, and the voltage change of the first plate of the first capacitor C1 is △C1=Data-Data', and Data' is the data signal Data written by the pixel circuit 10 in the previous working period. Through the first capacitor C1 and the second capacitor C2, the voltage change △C1 of the first plate of the first capacitor C1 can be partially coupled to the first node N1, the voltage change △N1 of the first node N1 = △C1*C1 / (C1+C2) = (Data-Data')*C1 / (C1+C2), and the voltage of the third node N3 remains unchanged. At this time, the voltage VN1 of the first node N1 = PV1+△N1 = PV1+(Data-Data')*C1 / (C1+C2), the voltage VN3 of the third node N3 = PV1-VTH, and the gate-source voltage VGS of the driving transistor M3 = VN1-VN3 = (Data-Data')*C1 / (C1+C2)+VTH.

[0064] In the light-emitting stage t4, the second scanning signal S2N continues to be at the non-enable level, and the first scanning signal SP jumps to the non-enable level. The writing module 12 can be cut off under the control of the first scanning signal SP, so that the data voltage terminal Do is cut off from the first node N1, the data signal Data on the data line Data_L stops being transmitted to the first plate of the first capacitor C1, the first plate of the first capacitor C1 stops receiving the data signal Data, the voltage of the first plate of the first capacitor C1 can maintain the voltage at the previous moment, and the voltage of the first node N1 can also maintain the voltage at the previous moment.

[0065] After the first scanning signal SP jumps to the non-enable level, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 both jump to the enable level. The first light-emitting control module 13 can be turned on under the control of the first light-emitting control signal EM1, and the second light-emitting control module 14 can be turned on under the control of the second light-emitting control signal EM2. When the first light-emitting control module 13, the driving transistor M3, and the second light-emitting control module 14 are turned on at the same time, a path can be formed between the first power supply voltage terminal and the second power supply voltage terminal, and the pixel circuit 10 can provide a driving current to the light-emitting element OLED. Since the second light emitting control module 14 is turned on, the third node N3 is connected to the fourth node N4, and the voltage of the third node N3 is equal to the voltage of the fourth node N4. The voltage change of the third node N3 can be coupled to the first node N1 through the fourth node N4 and the second capacitor C2, that is, the voltage of the first node N1 and the third node N3 can change by the same amount, and the gate-source voltage of the driving transistor M3 remains unchanged, which is still VGS=(Data-Data')*C1 / (C1+C2)+VTH, and the driving current Id=k*[(Data-Data')*C1 / (C1+C2)] 2 , the light emitting element OLED can display corresponding brightness according to the driving current Id. By controlling the brightness and light emitting duration of the light emitting element OLED, the display grayscale of the pixel circuit 10 can be controlled. Wherein, k is the current coefficient of the driving transistor M3, which is related to the material properties and size parameters of the driving transistor M3.

[0066] The pixel circuit provided by the embodiment of the present invention sets the driving transistor as an N-type transistor so that the carriers of the driving transistor are electrons, the mobility is higher, and the sensitivity of the threshold voltage is also lower, which can improve the hysteresis and threshold voltage drift of the driving transistor; by setting the writing module to be coupled with the gate of the driving transistor, and the compensation module to be connected between the gate and the first pole of the driving transistor, the compensation stage and the writing stage can be separated, so that the threshold voltage compensation process has sufficient time, which is conducive to improving the charging rate in the threshold voltage compensation process, even if the pixel circuit is in a fixed gray scale for a long time or the refresh frequency is low, the threshold voltage is offset, and the compensation module can fully compensate the offset threshold voltage to the driving transistor, improve the luminous accuracy, and improve the problem of residual image and low grayscale flicker. In addition, a first capacitor and a second capacitor are also set, and the first node and the third node can be coupled by the first capacitor and the second capacitor, so as to realize the precise control of the gate-source voltage of the driving transistor, which is conducive to the luminous accuracy; at the same time, the magnitude of the driving current can be adjusted by the first capacitor and the second capacitor, so as to realize the regulation of the range of the data signal, which is conducive to reducing the voltage drop of the gate of the driving transistor, further improving the hysteresis and threshold voltage drift of the driving transistor, and improving the display quality.

[0067] Optional, Figure 4 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention. Figure 4 The compensation module 11 includes a compensation transistor M4, the writing module 12 includes a writing transistor M5, the first light-emitting control module 13 includes a first light-emitting control transistor M1, and the second light-emitting control module 14 includes a second light-emitting control transistor M6; the compensation transistor M4, the writing transistor M5, the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are all N-type transistors.

[0068] Exemplarily, all transistors in the pixel circuit 10 are N-type transistors, and the active layers of all transistors in the pixel circuit 10 can be set on the same layer, reducing the preparation process and reducing the preparation cost; and the enable levels of the gates of all transistors are high levels, and when the pulse widths of the enable levels are the same, signal multiplexing between different transistors can also be performed.

[0069] In an optional embodiment, the active layer of the driving transistor M3 includes a metal oxide material.

[0070] The metal oxide material may include one or more oxide materials of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), titanium (Ti) and zinc (Zn). In this way, when preparing the active layer of the driving transistor M3, it is not necessary to crystallize to form a crystal structure, so that the defect density of the active layer is small, and the carrier mobility of the active layer is high and the temperature sensitivity is low, so that the voltage stability and switching characteristics of the driving transistor M3 are better, and the hysteresis effect and threshold voltage drift can be further reduced.

[0071] Exemplarily, the active layers of all transistors in the pixel circuit 10 may include one or more oxide materials of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), titanium (Ti) and zinc (Zn), for example, they may all include indium gallium zinc oxide (IGZO). In an optional embodiment, at least some transistors in the pixel circuit 10 may have a dual-gate structure, which is beneficial to improving the stability and mobility of the transistors.

[0072] Optional, continue to refer to Figure 4 The first electrode of the light emitting element OLED is electrically connected to the fourth node N4, the second electrode of the light emitting element OLED is electrically connected to the second power supply voltage terminal, and the voltage of the second power supply voltage terminal is lower than the voltage of the first power supply voltage terminal.

[0073] Specifically, the second electrode of the light emitting element OLED can be electrically connected to the second power supply voltage terminal through the second power supply line PV2_L. In an optional embodiment, the first power supply signal PV1 provided by the first power supply voltage terminal can be a DC high-level signal, for example, the voltage of the first power supply voltage terminal can be a power supply voltage VDD, and the power supply voltage VDD is generally a positive value. The second power supply signal PV2 provided by the second power supply voltage terminal can be a DC low-level signal, for example, the voltage of the second power supply voltage terminal can be a negative power supply voltage VEE, and the negative power supply voltage VEE is generally grounded or a negative value.

[0074] Exemplarily, the first electrode of the light-emitting element OLED is the anode of the light-emitting element OLED, and the second electrode of the light-emitting element OLED is the cathode of the light-emitting element OLED, and the light-emitting element OLED can be unidirectionally conductive. When the first light-emitting control module 13, the driving transistor M3, and the second light-emitting control module 14 are turned on at the same time, a path can be formed between the first power supply voltage terminal and the second power supply voltage terminal, and a current can be formed in the light-emitting element OLED. The current can first pass through the first light-emitting control module 13, the driving transistor M3, and the second light-emitting control module 14 in sequence, and then pass through the light-emitting element OLED.

[0075] Optional, continue to refer to Figure 4 , the second plate of the first capacitor C1 is directly electrically connected to the gate of the driving transistor M3.

[0076] There is no device or element between the second plate of the first capacitor C1 and the gate of the driving transistor M3, but a conductive structure such as a metal wire, a bridging hole, or a bridging electrode ( Figure 4 ) electrical connections.

[0077] Optional, Figure 5 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention. Figure 5 The second plate of the first capacitor C1 is electrically connected to the gate of the driving transistor M3 through the compensation module 11, and the second plate of the first capacitor C1 can be directly electrically connected to the second node N2.

[0078] The second plate of the first capacitor C1 and the gate of the driving transistor M3 can be electrically connected through devices and / or elements, for example, they can be electrically connected through the compensation module 11; no device or element is set between the second plate of the first capacitor C1 and the second node N2, but a conductive structure such as a metal wire, a bridging hole, a bridging electrode, etc. ( Figure 5 ) electrical connections.

[0079] For example, Figure 6 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Figure 6 Specific support Figure 5The driving timing of the pixel circuit shown in Figure 2 is shown in Figure 2. Figure 5 and Figure 6 , the pixel circuit 10 includes a refresh phase tf. Figure 6 Zhongyu Figure 3 The similarities will not be repeated here, and only the differences will be described.

[0080] In the writing phase t3 of the refresh phase tf, the first light emitting control signal EM1 and the second light emitting control signal EM2 are at the non-enable level, the second scanning signal S2N continues to be at the enable level, and the first scanning signal SP on the first scanning line SP_L jumps to the enable level. The first light-emitting control module 13 and the second light-emitting control module 14 are turned off, and the compensation module 11 and the writing module 12 are turned on, so that the data signal Data on the data line Data_L can be transmitted to the first plate of the first capacitor C1 through the writing module 12, and the voltage change of the first plate of the first capacitor C1 is △C1, which can be coupled to the second node N2, and the first node N1 is connected to the second node N2, and the signal of the second node N2 can be transmitted to the first node N1, so that △N1=△N2=△C1*C1 / (C1+C2)=(Data-Data')*C1 / (C1+C2), Data' is the data signal Data written by the pixel circuit 10 in the previous working period, and at this time, the voltage VN1 of the first node N1=PV1+△N1=PV1+(Data-Data')*C1 / (C1+C2).

[0081] Based on the above embodiments, Figure 7 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Figure 7 Specific support Figure 5 The driving timing of the pixel circuit shown in Figure 2 is shown in Figure 2. Figure 5 and Figure 7 The pixel circuit 10 includes a plurality of display periods DP, and the display period DP includes a refresh phase tf and a hold phase tk. Figure 7 Zhongyu Figure 6 The similarities are not repeated here, and only the differences are described. In the holding stage tk, the second node N2 is disconnected from the first node N1; and in a part of the holding stage tk, the first power supply voltage terminal is disconnected from the second node N2, and the data voltage terminal is connected to the first plate of the first capacitor C1.

[0082] Specifically, in the holding phase tk, the compensation module 11 is turned off; the writing module 12 can be turned on during the partial period when the pixel circuit 10 stops providing the driving current to the light emitting element OLED, and biases the driving transistor M3.

[0083] Exemplarily, in the holding stage tk, there is a partial time period when the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a non-enable level, and the first scanning signal SP is at an enable level, so that the first light-emitting control module 13 and the second light-emitting control module 4 are cut off, the writing module 12 is turned on, the pixel circuit 10 stops providing the driving current to the light-emitting element OLED, and the first plate of the first capacitor C1 receives the data signal Data at the data voltage end; at the same time, under the coupling action of the first capacitor C1, the voltage of the second node N2 changes, the gate voltage of the driving transistor M3 remains unchanged, the driving transistor M3 is turned on, and the voltage of the second node N2 can be transmitted to the third node N3 through the driving transistor M3, so that VN2=VN3, so as to bias the first and second electrodes of the driving transistor M3 and improve the problems of afterimage and low-frequency flicker.

[0084] The display period DP refers to the refresh period of the display grayscale of the pixel circuit 10. In the refresh phase tf of the display period DP, the pixel circuit 10 can write the data signal data, and the drive current Id can be adjusted by the data signal data to refresh the display grayscale; in the hold phase tk of the display period DP, the pixel circuit 10 can continue to write the data signal data, but the drive current Id remains unchanged, and the display grayscale is not refreshed. In other optional embodiments, the display period DP may also include only the refresh phase tf, but not the hold phase tk.

[0085] Exemplarily, the duration of the refresh phase tf and the hold phase tk may both be 1 / 120 s, and 120 refresh phases tf and / or hold phases tk may be included within 1 s. The display period DP of the pixel circuit 10 may include one refresh phase tf and 0, 1, 3 or 119 hold phases tk, so that the refresh frequency of the pixel circuit 10 may be 120 Hz, 60 Hz, 30 Hz or 1 Hz, as shown in FIG. Figure 8 When the pixel circuit 10 is in a fixed gray scale for a long time or the refresh frequency is low, the gate, the first electrode and the second electrode of the driving transistor M3 are in a fixed potential for a long time, and the driving transistor M3 may be delayed, resulting in a threshold voltage drift. The pixel circuit 10 provided by the embodiment of the present invention can compensate for the drifted threshold voltage in the compensation stage t2 of the refresh stage tf of the next display cycle DP to improve the problems of afterimage and low-frequency flicker.

[0086] It can be understood that when the duration of the refresh phase tf and the hold phase tk are both 1 / 120s, the refresh frequency of the pixel circuit 10 can also be 40Hz, 24Hz, 20Hz, 15Hz, 12Hz, 10Hz, 8Hz, 6Hz, 4Hz, 3Hz, 2Hz, etc., which are no longer shown one by one in the embodiments of the present invention.

[0087] It can also be understood that in other optional implementations, the duration of the refresh phase tf and the hold phase tk can also be other values. In this case, the refresh frequency of the pixel circuit 10 can also be other frequencies, which will not be described one by one in the embodiments of the present invention.

[0088] For example, it is assumed that the display period DP of all pixel circuits 10 in the display panel 01 includes a refresh phase tf and a hold phase tk, and the refresh frequencies of all pixel circuits 10 are the same. Fig. 9 is a timing diagram of a display panel provided by an embodiment of the present invention. Fig. 9 , the display panel 01 includes a first display mode, in which the display panel 01 includes a refresh frame DAf and a hold frame DAk. The display panel 01 may also include M rows of pixel circuits 10. In the refresh frame DAF, each row of pixel circuits 10 may be reset, threshold compensated, and data signals Data may be written, and the gate-source voltage of the driving transistor M3 may change according to the data Data, so that the display grayscale of each row of pixel circuits 10 is refreshed in sequence; in the hold frame DAk, each row of pixels 10 stops resetting and threshold compensation, but still writes the data signal data, but the data signal data does not change the gate-source voltage of the driving transistor M3, so that the display grayscale of each row of pixel circuits 10 is not refreshed, and the display grayscale of the previous frame may continue to be displayed, so as to achieve full-screen frequency reduction of the display panel 01.

[0089] In other embodiments, the display period DP of some pixel circuits 10 in the display panel 01 may include only the refresh phase tf, the display period DP of some pixel circuits 10 may include the refresh phase tf and the hold phase tk, and the refresh frequencies of the pixel circuits 10 in the same display panel 01 may be different. The display panel 01 may also include a second display mode. In the second display mode, the display panel 01 may include a refresh frame DAf and a frequency division frame ( Fig. 9 (not shown in the figure), in the frequency division frame, some rows of pixel circuits 10 can refresh the display grayscale, and some rows of pixel circuits 10 may not refresh the display grayscale, so as to realize the division and frequency division of the display panel 01.

[0090] Optional, Fig.10 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention, referring to Fig.10 The pixel circuit 10 further includes a first reset module 15, a first end of the first reset module 15 is electrically connected to the first reference voltage end, and a second end of the first reset module 15 is electrically connected to the fourth node N4.

[0091] The first reference voltage terminal may provide the pixel circuit 10 with a first reference signal VREF1 for resetting the fourth node N4. In an optional implementation, the first reference signal VREF1 at the first reference voltage terminal is less than zero.

[0092] Exemplarily, the first reset module 15 includes a first reset transistor M7, a first electrode of the first reset transistor M7 can be connected to the first reference voltage terminal through the first reference line VREF1_L to receive the first reference signal VREF1; a second electrode of the first reset transistor M7 is electrically connected to the fourth node N4; a gate of the first reset transistor M7 can be electrically connected to the shift register unit of the fifth shift register through the third scan line SPX_L to receive the third scan signal SPX( Figure 2 The first reset transistor M7 can be turned on and off under the control of the third scan signal SPX. When the first reset transistor M7 is turned on, the first reference signal VREF1 at the first reference voltage terminal can be transmitted to the fourth node N4 through the first reset transistor M7 to reset the fourth node N4.

[0093] In an optional embodiment, Fig.11 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Fig.11 Specific support Fig.10 The driving timing of the pixel circuit shown in Figure 2 is shown in Figure 2. Fig.10 and Fig.11 The pixel circuit 10 includes a refresh phase tf. In a reset phase t1 of the refresh phase tf, the fourth node N4 is conductively connected to the first reference voltage terminal.

[0094] Exemplarily, in the reset stage t1 of the refresh stage tf, the first light-emitting control signal EM1 is at an enable level, the second light-emitting control signal EM2 is at a non-enable level, the second scanning signal S2N is at an enable level, and the third scanning signal SPX is at an enable level, so that the first light-emitting control module 13, the compensation module 11 and the first reset module 15 are turned on, and the second light-emitting control module 14 is turned off. The pixel circuit 10 stops providing driving current to the light-emitting element OLED; the first power signal PV1 at the first power voltage end is transmitted to the second node N2 through the first light-emitting control module 13, the first power signal PV1 at the second node N2 is transmitted to the first node N1 through the compensation module 11, the driving transistor M3 is turned on, the first power signal PV1 at the second node N2 can also be transmitted to the third node N3, the first power signal PV1 can be used to reset the first node N1, the second node N2 and the third node N3, and the residual electrical signal in the previous working period is cleared; the first reference signal VREF1 at the first reference voltage end is transmitted to the fourth node N4 through the first reset module 15, the fourth node N4 can be reset, and the residual electrical signal in the previous working period is cleared.

[0095] In yet another optional embodiment, continue to refer to Fig.10 and Fig.11In the compensation phase t2 of the refresh phase tf, the first power supply voltage terminal and the second node N2 are cut off, the first node N1 and the second node N2 are connected, the third node N3 and the fourth node N4 are connected, and the fourth node N4 and the first reference voltage terminal are connected.

[0096] Specifically, in the compensation phase t2 of the refresh phase tf, the first light control module 13 is turned off, the compensation module 11, the second light control module 14 and the first reset module 15 are turned on, and the first reference signal VREF1 at the first reference voltage terminal is used to perform threshold compensation on the driving transistor M3.

[0097] Exemplarily, in the compensation phase t2 of the refresh phase tf, the first light-emitting control signal EM1 is at a non-enable level, and the second light-emitting control signal EM2, the second scanning signal S2N, and the third scanning signal SPX are all at an enable level, so that the first light-emitting control module 13 is turned off, and the second light-emitting control module 14, the compensation module 11, and the first reset module 15 are turned on. The pixel circuit 10 continues to stop providing the driving current to the light-emitting element OLED, and the first power signal PV1 at the first power voltage terminal stops being transmitted to the second node N2.

[0098] In the compensation stage t2, the first reference signal VREF1 of the first reference voltage terminal can be transmitted to the third node N3 through the first reset module 15 and the second light emitting control module 14, and the first reference signal VREF1 of the third node N3 can also be transmitted to the second node N2 through the driving transistor M3, and the signal of the second node N2 can be transmitted to the first node N1 through the compensation module 11, and the gate-source voltage VGS of the driving transistor M3 is continuously reduced until VGS=VN1-VN3=VTH, the driving transistor M3 is in a transition state of on and off, the current in the driving transistor M3 is reduced to zero, the first reference signal VREF1 of the third node N3 is no longer transmitted to the second node N2 and the first node N1, and the voltages of the first node N1 and the second node N2 are stable. At this time, VN1=VN2=VN3+VTH=VREF1+VTH, and the threshold voltage is compensated to the first node N1.

[0099] In the writing stage t3, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at the non-enable level, and the first scanning signal SP and the second scanning signal S2N are at the enable level. The first light-emitting control module 13 can be turned off under the control of the first light-emitting control signal EM1, the second light-emitting control module 14 can be turned off under the control of the second light-emitting control signal EM2, the first reset module 15 can be turned off under the control of the third scanning signal SPX, the compensation module 11 can be turned on under the control of the second scanning signal S2N, and the writing module 12 can be turned on under the control of the first scanning signal SP. The data signal Data on the data line Data_L can be transmitted to the first plate of the first capacitor C1 through the write module 12, the voltage of the first node N1 VN1 = VREF1 + VTH + △N1 = VREF1 + VTH + △C1 * C1 / (C1 + C2) = VREF1 + VTH + (Data - Data') * C1 / (C1 + C2), the gate-source voltage of the driving transistor M3 VGS = VN1 - VN3 = [VREF1 + VTH + (Data - Data') * C1 / (C1 + C2)] - VREF1 = (Data - Data') * C1 / (C1 + C2) + VTH.

[0100] In yet another optional embodiment, continue to refer to Fig.10 and Fig.11 The pixel circuit 10 includes a refresh phase tf. In a writing phase t3 of the refresh phase tf, the second plate of the first capacitor C1 is conductively connected to the gate of the driving transistor, and the first reference voltage terminal is conductively connected to the fourth node N4.

[0101] Specifically, in the writing stage t3 of the refresh stage tf, the compensation module 11 and the writing module 12 are turned on, and the first reset module 15 is also turned on, so that the fourth node N4 is a fixed potential, and the first capacitor C1 and the second capacitor C2 can be used to accurately control the gate voltage of the driving transistor M3, which is beneficial to accurately control the gate-source voltage and driving current of the driving transistor M3, thereby realizing accurate control of the display grayscale.

[0102] Exemplarily, in the write stage t3 of the refresh stage tf, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at the non-enable level, the first scan signal SP, the second scan signal S2N and the third scan signal SPX are at the enable level, the first light-emitting control module 13 and the second light-emitting control module 14 are turned off, the compensation module 11, the write module 12 and the first reset module 15 are turned on, so that the second plate of the first capacitor C1 is connected to the second node N2, the second node N2 is connected to the first node N1, and the first reference voltage terminal is connected to the fourth node N4.

[0103] When the data signal Data on the data line Data_L is transmitted to the first plate of the first capacitor C1 through the write module 12, the first reference signal VREF1 of the first reference voltage terminal can be transmitted to the second plate of the second capacitor C2 through the first reset module 15. When the voltage of the first plate of the first capacitor C1 changes, the voltage of the second plate of the second capacitor C2 can remain unchanged. Under the action of the first capacitor C1 and the second capacitor C2, the voltage change △C1 of the first plate of the first capacitor C1 can be partially coupled to the first node N1, so that the voltage change △N1 of the first node N1 = △C1*C1 / (C1+C2). By regulating the size of the first capacitor C1 and the second capacitor C2, the size of the driving current can be adjusted, thereby realizing the regulation of the range of the data signal Data, which is beneficial to reducing the voltage drop of the gate of the driving transistor M3, improving the hysteresis and threshold voltage drift of the driving transistor; it is also beneficial to low power consumption of the display panel.

[0104] In yet another optional embodiment, Fig.12 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Fig.12 Specific support Fig.10 The driving timing of the pixel circuit shown in Figure 2 is shown in Figure 2. Fig.10 and Fig.12 The pixel circuit 10 includes a plurality of display periods DP, and the display period DP includes a refresh phase tf and a hold phase tk. During a portion of the hold phase tk, the first reference voltage terminal is conductively connected to the fourth node N4.

[0105] Specifically, in the holding phase tk, the first reset module 15 can be turned on during a partial period when the pixel circuit 10 stops providing the driving current to the light emitting element OLED, so as to perform bias adjustment on the light emitting element OLED.

[0106] Exemplarily, in the holding stage tk, there is a partial period of time, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a non-enable level, and the third scanning signal SPX is at an enable level, so that the first light-emitting control module 13 and the second light-emitting control module 4 are turned off, the first reset module 15 is turned on, the pixel circuit 10 stops providing the driving current to the light-emitting element OLED, and the first reference signal VREF1 at the first reference voltage end is transmitted to the fourth node N4 through the first reset module 15, so that the light-emitting element OLED can be biased and adjusted; at the same time, the fourth node N4 can also be biased and adjusted through the second capacitor C2. The voltage change of the fourth node N4 is coupled to the first node N1, and the gate of the driving transistor M3 is biased and adjusted. When the pixel circuit 10 provides the driving current to the light-emitting element OLED, the fourth node N4 is changed back to the voltage when the pixel circuit 10 is working. Under the coupling effect of the second capacitor C2, the first node N1 can also be changed back to the voltage when the pixel circuit 10 is working. The driving current remains unchanged, and the light-emitting element OLED can continue to emit light in the holding stage tk. In the same display period DP, the light-emitting brightness of the light-emitting element OLED in the holding stage tk can be the same as the light-emitting brightness of the light-emitting element OLED in the refresh stage tf.

[0107] It can be understood that when the second electrode plate of the first capacitor C1 is electrically connected to the gate of the driving transistor M3 through the compensation module 11, the data voltage terminal and the first electrode plate of the first capacitor C1 can also be conductive during a partial period of the holding stage tk. During the holding stage tk, the conductive period between the first reference voltage terminal and the fourth node N4 and the conductive period between the data voltage terminal and the first electrode plate of the first capacitor C1 may overlap or not overlap, that is, during the holding stage tk, the conductive period of the first reset module 15 and the conductive period of the write module 12 may overlap or not overlap, which is not limited in the embodiment of the present invention.

[0108] Optional, Fig.13 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention, referring to Fig.13 The pixel circuit 10 further includes a second reset module 16, a first end of the second reset module 16 is electrically connected to the second reference voltage end, and a second end of the second reset module 16 is electrically connected to the first plate of the first capacitor C1 at a fifth node N5.

[0109] Among them, the second reference voltage terminal can provide the pixel circuit 10 with a second reference signal VREF2 for resetting the fifth node N5. The second reference signal VREF2 of the second reference voltage terminal can be zero, greater than zero, or less than zero. The embodiment of the present invention does not limit the second reference signal VREF2.

[0110] Exemplarily, the second reset module 16 includes a second reset transistor M2, a first electrode of the second reset transistor M2 can be connected to the second reference voltage terminal through the second reference line VREF2_L to receive the second reference signal VREF2; a second electrode of the second reset transistor M2 is electrically connected to the fifth node N5; a gate of the second reset transistor M2 can be electrically connected to the shift register unit of the sixth shift register through the fourth scan line SP*_L to receive the fourth scan signal SP*( Figure 2 The second reset transistor M2 can be turned on and off under the control of the fourth scan signal SP*. When the second reset transistor M2 is turned on, the second reference signal VREF2 at the second reference voltage end can be transmitted to the fifth node N5 through the second reset transistor M2 to reset the fifth node N5.

[0111] In an optional embodiment, Fig.14 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention, referring to Fig.14 , the second reference voltage terminal can be electrically connected to the first power supply voltage terminal.

[0112] Exemplarily, the first end of the first light emitting control module 13 and the first end of the second reset module 16 of the same pixel circuit 10 can be connected to the same signal line to receive the same signal; or, the first end of the first light emitting control module 13 and the first end of the second reset module 16 of the same pixel circuit 10 can also be connected to different signal lines, but electrically connected to the voltage end through different power lines ( Figure 2 Alternatively, the first end of the first light emitting control module 13 and the first end of the second reset module 16 of the same pixel circuit 10 can be connected to different signal lines, and electrically connected to different voltage ends through different signal lines, but different voltage ends can be electrically connected or receive the same signal ( Figure 2 This is beneficial to reducing signal lines and simplifying timing control.

[0113] In yet another optional embodiment, Fig.15 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention, referring to Fig.15 The pixel circuit 10 further includes a first reset module 15, a first end of the first reset module 15 is electrically connected to the first reference voltage end, and a second end of the first reset module 15 is electrically connected to the fourth node N4. The second reference voltage end can reuse the first reference voltage end, and a first end of the second reset module 16 is electrically connected to the fourth node N4, which is also conducive to reducing signal lines and simplifying timing control.

[0114] Exemplarily, the first reset module 15 includes a first reset transistor M7, and the second reset module 16 includes a second reset transistor M2. The first electrode of the first reset transistor M7 can be electrically connected to the first reference voltage terminal through the first reference line VREF1_L to receive the first reference signal VREF1, the second electrode of the first reset transistor M7 and the first electrode of the second reset transistor M2 are electrically connected to the fourth node N4, and the second electrode of the second reset transistor M2 is electrically connected to the fifth node N5; the gate of the first reset transistor M7 can be electrically connected to the third scan line SPX_L to receive the third scan signal SPX; the gate of the second reset transistor M2 is electrically connected to the fourth scan line SP*_L to receive the fourth scan signal SP*. In an optional embodiment, during the partial period when the pixel circuit 10 stops providing the driving current to the light-emitting element OLED, the enable level of the third scan line SPX_L overlaps with the enable level of the fourth scan signal SP*.

[0115] Based on the above embodiments, Fig.16 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Fig.16 Specific support Fig.15 The driving timing of the pixel circuit shown in Figure 2 is shown in Figure 2. Fig.15 and Fig.16 The pixel circuit 10 includes a refresh phase tf. In a compensation phase t2 of the refresh phase tf, the fifth node N5 is conductively connected to the second reference voltage terminal.

[0116] Exemplarily, in the compensation stage t2 of the refresh stage tf, the first light-emitting control signal EM1 is at a non-enable level, and the second light-emitting control signal EM2, the second scan signal S2N, the third scan signal SPX and the fourth scan signal SP* are all at enable levels, so that the first light-emitting control module 13 is turned off, and the second light-emitting control module 14, the compensation module 11, the first reset module 15 and the second reset module 16 are turned on. When the first light-emitting control module 13 is turned off, and the second light-emitting control module 14, the compensation module 11 and the first reset module 15 are turned on, the threshold voltage can be compensated to the first node N1. At this time, VN1=VN2=VN3+VTH=VREF1+VTH; at the end stage when the first light-emitting control module 13 is turned off, and the second light-emitting control module 14, the compensation module 11 and the first reset module 15 are turned on, the second reset module 16 is turned on. At this time, the voltages of the first node N1 and the second node N2 tend to be stable, and the first reference signal VREF1 of the fourth node N4 is transmitted to the fifth node N5 through the second reset module 16. The voltage of the fifth node N5 also tends to be stable, which can prevent the voltage change of the second node N2 from affecting the accurate reset of the fifth node N5.

[0117] In the writing stage t3, the first light-emitting control signal EM1, the second light-emitting control signal EM2 and the fourth scanning signal SP* are at the non-enabling level, and the first scanning signal SP, the second scanning signal S2N and the third scanning signal SPX are at the enabling level; the first light-emitting control module 13, the second light-emitting control module 14 and the second reset module 16 are turned off, and the compensation module 11, the writing module 12 and the first reset module 15 are turned on. When the data signal Data on the data line Data_L is transmitted to the first plate of the first capacitor C1 through the write module 12, the voltage change of the first plate of the first capacitor C1 is △C1=Data-VREF1, so that the voltage VN1 of the first node N1=VREF1+VTH+△N1=VREF1+VTH+△C1*C1 / (C1+C2)=VREF1+VTH+(Data-VREF1)*C1 / (C1+C2), and the gate-source voltage VGS of the driving transistor M3=VN1-VN3=[VREF1+VTH+(Data-VREF1)*C1 / (C1+C2)]-VREF1=(Data-VREF1)*C1 / (C1+C2)+VTH. In the light-emitting stage t4, the driving current Id=k*(VGS-VTH) 2 =k*[(Data-VREF1)*C1 / (C1+C2)] 2 .

[0118] Thus, by resetting the fifth node N5 in the compensation phase t2 of the refresh phase tf, the voltage variation of the first plate of the first capacitor C1 in the write phase can be controlled, thereby precisely controlling the gate-source voltage and driving current of the driving transistor M3 to achieve accurate display.

[0119] In an optional embodiment, the first shift register VSR1 includes M-stage shift register units, the fourth scan line SP*_L electrically connected to the same pixel circuit 10 can be electrically connected to the i-th stage shift register unit of the first shift register VSR1, the first scan line SP_L can be electrically connected to the j-th stage shift register unit of the first shift register VSR1, receive the i-th signal output by the first shift register VSR1 as the fourth scan signal SP*, and receive the j-th signal output by the first shift register VSR1 as the first scan signal SP, wherein 1≤i≤j≤M, and i and j are both integers; in other words, the fourth scan line SP*_L electrically connected to the j-th row pixel circuit 10 and the first scan line SP_L electrically connected to the i-th row pixel circuit 10 can be electrically connected and electrically connected to the output end of the same shift register unit of the first shift register VSR1, and the fourth scan line SP*_L and the first scan line SP_L electrically connected to the same row pixel circuit 10 can be electrically connected to different shift register units of the third shift register VSR3 ( Figure 2In this way, the fourth scanning signal SP* and the first scanning signal SP received by the pixel circuit 10 may both come from the first shift register VSR1, and the sixth shift register may not be provided, which is beneficial to the thinness of the display panel 01.

[0120] It can be understood that when the second plate of the first capacitor C1 is electrically connected to the gate of the driving transistor M3 through the compensation module 11, the data voltage terminal and the first plate of the first capacitor C1 can continue to be connected during a portion of the holding phase tk. The fourth scanning signal SP* and the first scanning signal SP received by the pixel circuit 10 are from the same shift register, and the fifth node and the second reference voltage terminal can also be connected during a portion of the holding phase tk.

[0121] It can also be understood that, during a partial period of the holding stage tk, when the first reference voltage terminal and the fourth node N4 are turned on, during the holding stage tk, the turn-on period between the first reference voltage terminal and the fourth node N4 and the turn-on period between the fifth node and the second reference voltage terminal may overlap or may not overlap, that is, during the holding stage tk, the turn-on period of the first reset module 15 and the turn-on period of the second reset module 16 may overlap or may not overlap, and the embodiment of the present invention does not limit this.

[0122] Optional, Fig.17 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention, referring to Fig.17 The pixel circuit 10 further includes a third reset module 17, a first end of the third reset module 17 is electrically connected to the first power supply voltage end, and a second end of the third reset module 17 is electrically connected to the first node N1.

[0123] Exemplarily, the third reset module 17 includes a third reset transistor M8, a first electrode of the third reset transistor M8 can be electrically connected to the first power supply voltage terminal through the first power line PV1_L, and receive the first power supply signal PV1; a second electrode of the third reset transistor M8 is electrically connected to the first node N1; a gate of the third reset transistor M8 can be electrically connected to the shift register unit of the seventh shift register through the fifth scan line S1N_L, and receive the fifth scan signal S1N( Figure 2 The third reset transistor M8 can be turned on and off under the control of the fifth scan signal S1N. When the third reset transistor M8 is turned on, the first power signal PV1 at the first power voltage terminal can be transmitted to the first node N1 through the third reset transistor M8 to reset the first node N1.

[0124] In an optional embodiment, Fig.18 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Fig.18 Specific support Fig.17 The driving timing of the pixel circuit shown in Figure 2 is shown in Figure 2. Fig.17 and Fig.18 The pixel circuit 10 includes a refresh phase tf. In a reset phase t1 and a compensation phase t2 of the refresh phase tf, the first power supply voltage terminal is conductively connected to the first node N1.

[0125] Exemplarily, in the reset stage t1, the fifth scan signal S1N is at an enable level, so that the third reset module 17 is turned on, and the first power signal PV1 at the first power voltage terminal can be transmitted to the first node N1 through the third reset module 17, and the first node N1 is reset. In the compensation stage t2, the fifth scan signal S1N and the second scan signal S2N are at an enable level, so that the third reset module 17 and the compensation module 11 are turned on, the first power signal PV1 can be transmitted to the second node N2 through the third reset module 17 and the compensation module 11, and the first power signal PV1 of the second node N2 is transmitted to the third node N3, and the threshold voltage can be compensated to the third node N3. At this time, VN3=VN1-VTH=PV1-VTH.

[0126] In an optional embodiment, the second shift register VSR2 includes M-stage shift register units, the fifth scan line S1N_L electrically connected to the same pixel circuit 10 can be electrically connected to the i-th stage shift register unit of the second shift register VSR2, the second scan line S2N_L can be electrically connected to the j-th stage shift register unit of the second shift register VSR2, and receives the i-th signal output by the second shift register VSR2 as the fifth scan signal S1N, and receives the j-th signal output by the second shift register VSR2 as The second scanning signal S2N, wherein 1≤i≤j≤M, and i and j are both integers; in other words, the fifth scanning line S1N_L electrically connected to the pixel circuit 10 of the j-th row and the second scanning line S2N_L electrically connected to the pixel circuit 10 of the i-th row can be electrically connected and electrically connected to the output end of the same shift register unit of the second shift register VSR2, and the fifth scanning line S1N_L and the second scanning line S2N_L electrically connected to the pixel circuit 10 of the same row can be electrically connected to different shift register units of the second shift register VSR2 ( Figure 2 In this way, the fifth scanning signal S1N and the second scanning signal S2N received by the pixel circuit 10 may both come from the second shift register VSR2, and the seventh shift register may not be provided, which is conducive to the thinness of the display panel 01.

[0127] In yet another optional embodiment, continue to refer to Fig.17 and Fig.18 , the conduction period between the fifth node N5 and the second reference voltage terminal overlaps with the conduction period between the first power supply voltage terminal and the first node N1, and / or the conduction period between the fifth node N5 and the second reference voltage terminal does not overlap with the conduction period between the second node N2 and the first node N1.

[0128] Specifically, the conduction period of the second reset module 16 overlaps with the conduction period of the third reset module 17, and / or the conduction period of the second reset module 16 does not overlap with the conduction period of the compensation module 11. In this way, when the second reset module 16 resets the fifth node N5, the first node N1 can receive the first power signal PV1 of the first power voltage terminal, and / or, when the second reset module 16 resets the fifth node N5, the first node N1 stops receiving the signal of the second node N2, so as to ensure that the voltage fluctuation of the fifth node N5 does not affect the voltage of the first node N1, which is conducive to accurately controlling the gate-source voltage and driving current of the driving transistor M3, and realizing accurate light emission.

[0129] In yet another optional embodiment, Fig.19 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention, referring to Fig.19 , the control end of the first light emitting control module 13 is electrically connected to the control end of the second light emitting control module.

[0130] Specifically, the first light emitting control module 13 is no longer required to reset the driving transistor M3 , and the first light emitting control module 13 and the second light emitting control module 14 of the same pixel circuit 10 can be turned on or off at the same time under the control of the same light emitting control signal.

[0131] Exemplarily, the control end of the first light emitting control module 13 and the control end of the second light emitting control module 14 of the same pixel circuit 10 can be directly electrically connected to the same control line, and receive the same signal as the first light emitting control signal EM1 and the second light emitting control signal EM2; or, the control end of the first light emitting control module 13 and the control end of the second light emitting control module 14 of the same pixel circuit 10 can also be electrically connected through a signal line, respectively connected to different light emitting control lines, but connected to the shift register unit ( Figure 2 ), receiving the same light emitting control signal as the first light emitting control signal EM1 and the second light emitting control signal EM2.

[0132] In this way, the first light-emitting control module 13 and the second light-emitting control module 14 of the same pixel circuit 10 can be turned on or off at the same time under the control of the same light-emitting control signal. When adjusting the light-emitting duration of the light-emitting element OLED of the pixel circuit 10, only one light-emitting control signal needs to be adjusted, which is beneficial to simplify the dimming process and dimming timing; in addition, it is also beneficial to reduce the number of shift registers in the display panel 01, thereby realizing the thinness of the display panel 01.

[0133] Based on the same inventive concept, an embodiment of the present invention further provides a driving method of a pixel circuit, which is used to drive the pixel circuit 10 provided by any embodiment of the present invention. Fig. 20 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present invention, with reference to Fig. 20 , the driving methods include:

[0134] S110, reset stage, the first power supply voltage terminal is connected to the second node, and the first node is connected to the second node.

[0135] S120, compensation stage, the second node is conductively connected to the first node, the first power supply voltage terminal is conductively connected to the second node, or the third node is conductively connected to the fourth node.

[0136] S130, writing stage, the data voltage terminal is connected to the first plate of the first capacitor.

[0137] S140, light emitting stage, the first power supply voltage terminal is connected to the second node, and the third node is connected to the fourth node.

[0138] The driving method of the pixel circuit provided by the embodiment of the present invention can, in the reset stage, control the first light-emitting control module to be turned on by the first light-emitting control signal, and the first power signal at the first power supply voltage end can be transmitted to the second node through the first light-emitting control module to reset the potential of the second node; and can also control the compensation module to be turned on by the second scanning signal, and the first power signal of the second node can be transmitted to the first node through the compensation module to reset the potential of the first node, and control the driving transistor to be in the on state. In the compensation stage, the first light-emitting control signal and the second scanning signal can be used to control the first light-emitting control module and the compensation module to continue to be turned on, and the threshold voltage of the driving transistor can be compensated to the driving transistor. In the writing stage, the writing module can be controlled to be turned on by the first scanning signal, and the data signal at the data voltage end can be transmitted to the first capacitor through the writing module, and coupled to the gate of the driving transistor through the first capacitor, and the second capacitor can store the gate-source voltage of the driving transistor. In the light-emitting stage, the first light-emitting control module and the second light-emitting control module can be controlled to be turned on by the first light-emitting control signal and the second light-emitting control signal, and the driving current of the pixel circuit can be provided to the light-emitting element, so that the light-emitting element emits light. When the pixel circuit is applied to a display panel, the problems of afterimage and low-frequency flicker of the display panel can be improved.

[0139] The driving method of the pixel circuit provided in the embodiment of the present invention is used to drive the pixel circuit provided in any embodiment of the present invention, and has the corresponding technical features and beneficial effects of the pixel circuit. For the contents not fully described in the embodiment of the driving method of the pixel circuit, refer to the above description of the pixel circuit, and will not be repeated here; similarly, the pixel circuit of the embodiment of the present invention also has the functional modules and beneficial effects that can execute the driving method of the pixel circuit provided in the embodiment of the present invention. For the contents not fully described in the embodiment of the pixel circuit, refer to the above description of the driving method of the pixel circuit, and will not be repeated here.

[0140] Based on the same inventive concept, an embodiment of the present invention further provides a display panel, Fig.21 is a schematic diagram of a display panel provided by an embodiment of the present invention, with reference to Fig.21 The display panel 01 includes a plurality of pixel circuits 10 arranged in an array. The pixel circuit 10 may be a pixel circuit 10 provided by any embodiment of the present invention.

[0141] Exemplarily, the display panel 01 further includes a plurality of first scan lines SP_L, a plurality of second scan lines S2N_L, a plurality of data lines Data_L, a plurality of first light emission control lines EM1_L, and a plurality of second light emission control lines EM2_L connected to the plurality of pixel circuits 10, and may further include a plurality of first power lines, a plurality of second power lines, etc. ( Fig.21 The first scan line SP_L can be connected to the control end of the writing module in the pixel circuit 10, the second scan line S2N_L can be connected to the control end of the compensation module in the pixel circuit 10, the first light-emitting control line EM1_L can be connected to the control end of the first light-emitting control module in the pixel circuit 10, and the second light-emitting control line EM2_L can be connected to the control end of the second light-emitting control module in the pixel circuit 10.

[0142] The display panel provided by an embodiment of the present invention includes a plurality of pixel circuits arranged in an array as provided by any embodiment of the present invention, and has the corresponding technical features and beneficial effects of the pixel circuit. For the contents not fully described in the embodiment of the display panel, refer to the above description of the pixel circuit and will not be repeated here.

[0143] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig. 22 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig. 22 As shown, the display device 02 includes a display panel 01 provided by any embodiment of the present invention. The display device 02 provided by the embodiment of the present invention can be Fig. 22The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0144] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that: include: A driving transistor, a light emitting element, a compensation module, a writing module, a first light emitting control module, a second light emitting control module, a first capacitor and a second capacitor; The first end of the compensation module is electrically connected to the gate of the driving transistor at a first node, and the second end of the compensation module is electrically connected to the first electrode of the driving transistor at a second node; the first end of the writing module is electrically connected to the data voltage end, the second end of the writing module is electrically connected to the first plate of the first capacitor, and the second plate of the first capacitor is electrically connected to the gate of the driving transistor; A first end of the first light emitting control module is electrically connected to a first power supply voltage end, and a second end of the first light emitting control module is electrically connected to the second node; The first end of the second light emitting control module and the second electrode of the driving transistor are electrically connected to a third node, and the second end of the second light emitting control module and the light emitting element are electrically connected to a fourth node; The first electrode plate of the second capacitor is electrically connected to the first node, and the second electrode plate of the second capacitor is electrically connected to the fourth node; The driving transistor is an N-type transistor.

2. The pixel circuit according to claim 1, characterized in that: The compensation module includes a compensation transistor, the writing module includes a writing transistor, the first light emission control module includes a first light emission control transistor, and the second light emission control module includes a second light emission control transistor; The compensation transistor, the write transistor, the first light emission control transistor, and the second light emission control transistor are all N-type transistors.

3. The pixel circuit according to claim 1, characterized in that: The first electrode of the light emitting element is electrically connected to the fourth node; the second electrode of the light emitting element is electrically connected to the second power supply voltage terminal; The voltage of the first power supply voltage terminal is greater than the voltage of the second power supply voltage terminal.

4. The pixel circuit according to claim 1, characterized in that: The second plate of the first capacitor is directly electrically connected to the gate of the driving transistor.

5. The pixel circuit according to claim 1, characterized in that: The second plate of the first capacitor is electrically connected to the gate of the driving transistor through the compensation module; The second plate of the first capacitor is directly electrically connected to the second node.

6. The pixel circuit according to claim 5, characterized in that: The pixel circuit includes a plurality of display cycles; the display cycle includes a refresh phase and a hold phase; In the holding phase, the second node is cut off from the first node; Furthermore, during a partial period of the holding phase, the first power supply voltage terminal is disconnected from the second node, and the data voltage terminal is connected to the first plate of the first capacitor.

7. The pixel circuit according to claim 1, characterized in that: Also includes: A first reset module; A first terminal of the first reset module is electrically connected to the first reference voltage terminal, and a second terminal of the first reset module is electrically connected to the fourth node.

8. The pixel circuit according to claim 7, characterized in that: The pixel circuit includes a refresh phase; In the compensation phase of the refresh phase, the first power supply voltage terminal and the second node are cut off, the first node and the second node are connected, the third node and the fourth node are connected, and the fourth node and the first reference voltage terminal are connected.

9. The pixel circuit according to claim 7, characterized in that: The pixel circuit includes a refresh phase; In the writing phase of the refresh phase, the second plate of the first capacitor is conductively connected to the gate of the driving transistor, and the first reference voltage terminal is conductively connected to the fourth node.

10. The pixel circuit according to claim 7, characterized in that: The pixel circuit includes a plurality of display cycles; the display cycle includes a refresh phase and a hold phase; During a partial period of the holding phase, the first reference voltage terminal is conductively connected to the fourth node.

11. The pixel circuit according to claim 1, characterized in that: Also includes: A second reset module; The first end of the second reset module is electrically connected to the second reference voltage end, and the second end of the second reset module is electrically connected to the first plate of the first capacitor at a fifth node.

12. The pixel circuit according to claim 11, characterized in that: The pixel circuit includes a refresh phase; During the compensation phase of the refresh phase, the fifth node is conductively connected to the second reference voltage terminal.

13. The pixel circuit according to claim 11, characterized in that: The second reference voltage terminal is electrically connected to the first power supply voltage terminal; Alternatively, the pixel circuit also includes a first reset module, a first end of the first reset module is electrically connected to the first reference voltage end, and a second end of the first reset module is electrically connected to the fourth node; the second reference voltage end reuses the first reference voltage end, and a first end of the second reset module is electrically connected to the fourth node.

14. The pixel circuit according to claim 1, characterized in that: Also includes a third reset module; A first terminal of the third reset module is electrically connected to the first power supply voltage terminal, and a second terminal of the third reset module is electrically connected to the first node.

15. The pixel circuit according to claim 14, characterized in that: The control end of the first light emitting control module is electrically connected to the control end of the second light emitting control module.

16. A method for driving a pixel circuit, characterized in that: Used to drive the pixel circuit according to any one of claims 1 to 15; the driving method comprises: In the reset stage, the first power supply voltage terminal is connected to the second node, and the first node is connected to the second node; In the compensation stage, the second node is conductively connected to the first node, the first power supply voltage terminal is conductively connected to the second node, or the third node is conductively connected to the fourth node; In the writing stage, the data voltage terminal is connected to the first plate of the first capacitor; In the light emitting stage, the first power supply voltage terminal is conductively connected to the second node, and the third node is conductively connected to the fourth node.

17. A display panel, characterized in that: include: A plurality of pixel circuits as described in any one of claims 1 to 15 are arranged in an array.

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