Through hole etching method of semiconductor device

Abstract

The invention provides a through hole etching method of a semiconductor device. The through hole etching method of the semiconductor device comprises the following steps that an etching stop layer, an interlayer dielectric layer, a hard mask layer, an anti-reflection layer and a photoresist layer are sequentially formed on a substrate in the direction away from the substrate, and the photoresist layer is provided with an etching pattern; first mixed gas is introduced to form a polymer protection layer on the surface of the side, away from the anti-reflection layer, of the photoresist layer, the anti-reflection layer and the hard mask layer are etched, and the first mixed gas comprises CF4, CHF3, O2 and N2; second mixed gas is introduced to etch the interlayer dielectric layer; and third mixed gas is introduced to etch the etching stop layer. According to the invention, the problem that the side wall of the through hole is easy to damage during the through hole etching of the semiconductor device in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a through-hole etching method for a semiconductor device. Background Art

[0002] With the rapid development of integrated circuits, the integration of semiconductor chips continues to increase, the line width continues to shrink, and the graphics become more dense. In order to solve the problems caused by the reduction of line width and increase the speed of semiconductor chips, copper interconnection processes have begun to be widely used in the back-end process of semiconductor chip manufacturing. In the copper interconnection process, the control of through-hole morphology is very important. In the traditional through-hole etching process, the low-frequency RF power used for etching has a high power, and it is easy to transfer the rough pattern on the top of the photoresist layer to the side wall of the through hole. If the side wall of the through hole is rough, it will affect the integrity of the subsequent electroplated copper filling, and as a defect, it is easy to cause electromigration, which in turn affects the reliability of the entire semiconductor chip.

[0003] That is to say, the via hole etching of the semiconductor device in the prior art has the problem of easily causing damage to the side wall of the via hole. Summary of the invention

[0004] The main purpose of the present invention is to provide a through-hole etching method for a semiconductor device, so as to solve the problem that the through-hole etching of the semiconductor device in the prior art easily causes damage to the side wall of the through-hole.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a through-hole etching method for a semiconductor device, comprising the following steps: forming an etch stop layer, an interlayer dielectric layer, a hard mask layer, an anti-reflection layer and a photoresist layer in sequence on a substrate in a direction away from the substrate, wherein the photoresist layer has an etching pattern; introducing a first mixed gas to form a polymer protective layer on a surface of the photoresist layer away from the anti-reflection layer, and etching the anti-reflection layer and the hard mask layer, wherein the first mixed gas comprises CF4, CHF3, O2 and N2; introducing a second mixed gas to etch the interlayer dielectric layer; introducing a third mixed gas to etch the etch stop layer.

[0006] Furthermore, in the step of introducing the first mixed gas to etch the anti-reflective layer and the hard mask layer, the flow rate of CF4 in the first mixed gas is controlled to be greater than the flow rates of the other three gases; and / or the flow rate of O2 in the first mixed gas is controlled to be less than the flow rates of the other three gases.

[0007] Furthermore, in the step of introducing the first mixed gas to etch the anti-reflective layer and the hard mask layer, the flow rates of CF4, O2 and N2 in the first mixed gas are controlled to satisfy: 2.2≤CF4 / (O2+N2)≤2.7; and / or the flow rates of CHF3, O2 and N2 in the first mixed gas are controlled to satisfy: 0.3≤CHF3 / (O2+N2)≤0.8.

[0008] Furthermore, in the step of introducing the first mixed gas to etch the anti-reflective layer and the hard mask layer, the flow rates of CF4, CHF3, O2 and N2 in the first mixed gas are controlled to satisfy: 1.9≤(CF4+CHF3) / (O2+N2)≤4.6.

[0009] Furthermore, in the step of introducing a second mixed gas to etch the interlayer dielectric layer, the second mixed gas includes C4F8, N2, and Ar.

[0010] Furthermore, in the step of introducing the second mixed gas to etch the interlayer dielectric layer, the flow ratio of C4F8 to Ar in the second mixed gas is controlled to be greater than or equal to 0.01 and less than or equal to 0.04; and / or the flow ratio of N2 to Ar in the second mixed gas is controlled to be greater than or equal to 0.4 and less than or equal to 0.7.

[0011] Furthermore, in the step of introducing the second mixed gas to etch the interlayer dielectric layer, the flow rate of C4F8 in the second mixed gas is controlled to be within the range of greater than or equal to 10 ml / min and less than or equal to 20 ml / min; and / or the flow rate of N2 in the second mixed gas is controlled to be within the range of greater than or equal to 350 ml / min and less than or equal to 400 ml / min; and / or the flow rate of Ar in the second mixed gas is controlled to be within the range of greater than or equal to 650 ml / min and less than or equal to 710 ml / min.

[0012] Further, in the step of introducing a third mixed gas to etch the etch stop layer, the third mixed gas includes C4F8, N2, and Ar.

[0013] Further, the flow rate of C4F8 in the third mixed gas is controlled within a range of greater than or equal to 10 ml / min and less than or equal to 20 ml / min; and / or the flow rate of N2 in the third mixed gas is controlled within a range of greater than or equal to 250 ml / min and less than or equal to 300 ml / min; and / or the flow rate of Ar in the third mixed gas is controlled within a range of greater than or equal to 650 ml / min and less than or equal to 710 ml / min.

[0014] Furthermore, in the step of introducing the first mixed gas to etch the anti-reflective layer and the hard mask layer, the etching pressure is controlled to be greater than or equal to 80mT and less than or equal to 100mT; and / or the high-frequency etching power is controlled to be greater than or equal to 600W and less than or equal to 800W, and the low-frequency etching power is controlled to be greater than or equal to 90W and less than 110W.

[0015] Furthermore, in the step of introducing the second mixed gas to etch the interlayer dielectric layer; and / or introducing the third mixed gas to etch the etch stop layer, the etching pressure is controlled to be greater than or equal to 25mT and less than or equal to 45mT; the high-frequency etching power is controlled to be greater than or equal to 430W and less than or equal to 450W, and the low-frequency etching power is controlled to be greater than or equal to 2000W and less than 2500W.

[0016] Furthermore, after the step of introducing the third mixed gas to etch the etch stop layer, the method further includes: introducing the fourth mixed gas to remove the remaining anti-reflection layer and the photoresist layer, and the fourth mixed gas includes CO and CO2.

[0017] By applying the technical solution of the present invention, in the process of etching a through hole, the present application first uses a photoresist layer with an etching pattern as a mask, adopts a first mixed gas composed of CF4, CHF3, O2 and N2 to form a polymer protective layer on the top surface of the photoresist layer, and simultaneously etches the anti-reflection layer and the hard mask layer, and adopts a step to etch the anti-reflection layer and the hard mask layer at the same time, which is conducive to ensuring the stability of the process, thereby transferring the etching pattern on the photoresist layer to the hard mask layer. By rationally planning the composition of the first mixed gas, it is conducive to the formation of the polymer protective layer, and by controlling the polymer deposition to form the polymer protective layer, it is ensured that the top surface of the photoresist layer is smooth, which can prevent the abnormal pattern on the photoresist layer from being transferred to the bottom of the through hole, causing the increase of the roughness of the side wall of the through hole, and can effectively avoid the generation of streaks or stripes on the side wall of the through hole, which is conducive to ensuring that the side wall of the through hole formed after etching is relatively smooth, and then it is conducive to ensuring the stability of the subsequent etching process of the interlayer dielectric layer and the etching stop layer, and ensuring the reliability of the use of the semiconductor device after etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0019] Figure 1 A schematic flow chart showing a through-hole etching method for a semiconductor device according to an optional embodiment of the present invention;

[0020] Figure 2 A schematic diagram of the structure of the semiconductor device of the present invention before etching is shown;

[0021] Figure 3 A schematic diagram showing the structure of the semiconductor device of the present invention after etching the anti-reflection layer and the hard mask layer;

[0022] Figure 4 A schematic diagram showing the structure of the semiconductor device of the present invention after etching the interlayer dielectric layer;

[0023] Figure 5 A schematic diagram showing the structure of the semiconductor device of the present invention after etching the etch stop layer;

[0024] Figure 6 The schematic diagram shows the structure of the semiconductor device of the present invention after the remaining anti-reflection layer and photoresist layer are removed.

[0025] The above drawings include the following reference numerals:

[0026] 10. substrate; 20. etch stop layer; 30. interlayer dielectric layer; 40. hard mask layer; 50. anti-reflective layer; 60. photoresist layer; 70. through hole. DETAILED DESCRIPTION

[0027] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0028] It should be noted that, unless otherwise specified, all technical and scientific terms used in this application have the same meanings as commonly understood by ordinary technicians in the technical field to which this application belongs.

[0029] In the present invention, unless otherwise specified, the directional words used, such as "up, down, top, bottom", usually refer to the directions shown in the drawings, or to the components themselves in the vertical, perpendicular or gravity directions; similarly, for ease of understanding and description, "inside and outside" refer to the inside and outside relative to the outline of each component itself, but the above-mentioned directional words are not used to limit the present invention.

[0030] In order to solve the problem in the prior art that through-hole etching of semiconductor devices easily causes damage to the sidewalls of the through-holes, the present invention provides a through-hole etching method for semiconductor devices.

[0031] like Figures 1 to 6 As shown, the through hole etching method of the semiconductor device comprises the following steps:

[0032] An etch stop layer 20, an interlayer dielectric layer 30, a hard mask layer 40, an anti-reflection layer 50 and a photoresist layer 60 are sequentially formed on the substrate 10 in a direction away from the substrate 10. The photoresist layer 60 has an etched pattern. Figure 2 As shown in , the etched pattern may be a through hole 70 in the photoresist layer 60 , or may be a cross-sectional shape of the through hole 70 along a direction parallel to the photoresist layer 60 .

[0033] like Figure 3As shown, a first mixed gas is introduced to form a polymer protective layer (not shown) on the surface of the photoresist layer 60 away from the anti-reflection layer 50, and the anti-reflection layer 50 and the hard mask layer 40 are etched to expose the portion of the interlayer dielectric layer 30 corresponding to the through hole 70 in the photoresist layer 60. The first mixed gas includes CF4, CHF3, O2 and N2. After the etching is completed in this step, a polymer protective layer is formed as shown in FIG. Figure 3 The structure shown.

[0034] like Figure 4 As shown, the second mixed gas is introduced to etch the interlayer dielectric layer 30, and the exposed portion of the interlayer dielectric layer 30 is further etched to expose the portion of the etch stop layer 20 corresponding to the through hole of the interlayer dielectric layer 30. Figure 4 The structure shown.

[0035] like Figure 5 As shown, the third mixed gas is introduced to etch the etch stop layer 20, specifically the exposed portion of the etch stop layer 20 is etched. Figure 5 The structure shown.

[0036] In the process of etching the through hole 70, the present application first uses the photoresist layer 60 with the etching pattern as a mask, adopts a first mixed gas composed of CF4, CHF3, O2 and N2 to form a polymer protective layer on the top surface of the photoresist layer 60, and synchronously etches the anti-reflection layer 50 and the hard mask layer 40. The two layers of the anti-reflection layer 50 and the hard mask layer 40 are etched simultaneously in one step, which is beneficial to ensure the stability of the process, thereby transferring the etching pattern on the photoresist layer 60 to the hard mask layer 40, thereby exposing the interlayer dielectric layer 30. By rationally planning the composition of the first mixed gas, it is beneficial to form a polymer protective layer. By controlling the method of forming the polymer protective layer by polymer deposition, the top surface of the photoresist layer 60 is ensured to be smooth, which can prevent the abnormal pattern on the photoresist layer 60 from being transferred to the bottom of the through hole 70 and causing the increase of the roughness of the side wall of the through hole 70. It can effectively avoid the generation of streaks or stripes on the side wall of the through hole 70, which is beneficial to ensure that the side wall of the through hole 70 formed after etching is relatively smooth, and further helps to ensure the stability of the subsequent etching process of the interlayer dielectric layer 30 and the etching stop layer 20, and ensure the reliability of the semiconductor device after the etching.

[0037] It should be noted that the above-mentioned etching stop layer 20 can be represented by NDC, in which a copper structure is provided. The interlayer dielectric layer 30 can be represented by BD. The hard mask layer 40 can be represented by TEOS. The anti-reflection layer 50 can be represented by BARC. The photoresist layer 60 can be represented by PR. The etching pattern of the photoresist layer 60 can be designed according to actual conditions and is not limited to the shape of the present application.

[0038] Specifically, in the step of introducing the first mixed gas to etch the anti-reflection layer 50 and the hard mask layer 40, the flow rate of CF4 in the first mixed gas is controlled to be greater than the flow rates of the other three gases; the flow rate of O2 in the first mixed gas is controlled to be less than the flow rates of the other three gases. By selecting the gas with the largest flow rate and the smallest flow rate, it is beneficial to ensure the stability of the polymer deposition, and then ensure the stability of the etching process of the through hole 70.

[0039] More specifically, in the step of introducing the first mixed gas to etch the anti-reflection layer 50 and the hard mask layer 40, the flow rates of CF4, O2 and N2 in the first mixed gas are controlled to satisfy: 2.2≤CF4 / (O2+N2)≤2.7; and the flow rates of CHF3, O2 and N2 in the first mixed gas are controlled to satisfy: 0.3≤CHF3 / (O2+N2)≤0.8. By rationally controlling the flow rate ratio of the more important gases in the first mixed gas, it is beneficial to increase the polymer concentration, making it easier to form the polymer protective layer, ensuring the reliability of the polymer protective layer, further reducing the damage to the side wall of the through hole 70 during the etching process, effectively improving the etching accuracy and verticality of the through hole 70, and improving the fidelity of the etched pattern.

[0040] Specifically, in the step of introducing the first mixed gas to etch the anti-reflection layer 50 and the hard mask layer 40, the flow rates of CF4, CHF3, O2 and N2 in the first mixed gas are controlled to satisfy: 1.9≤(CF4+CHF3) / (O2+N2)≤4.6. By reasonably constraining the range of the conditional formula, it is beneficial to control the gas concentration, to control the polymer concentration while ensuring the stability of the etching process and the etching accuracy, and to ensure the reliability of the formation of the polymer protective layer. Preferably, 2≤(CF4+CHF3) / (O2+N2)≤3.3.

[0041] In addition, the flow rate of CF4 in the first mixed gas needs to be controlled within a range of 350 ml / min to 410 ml / min, the flow rate of CHF3 needs to be controlled within a range of 80 ml / min to 110 ml / min, the flow rate of O2 needs to be controlled within a range of 5 ml / min to 15 ml / min, and the flow rate of N2 needs to be controlled within a range of 150 ml / min to 210 ml / min. By properly controlling the flow rate of each gas in the first mixed gas, the formation of the polymer is facilitated, the reliability of the polymer protective layer is ensured, and the generation of streaks and stripes on the side wall of the through hole 70 during the etching process is further reduced.

[0042] Specifically, in the step of introducing the first mixed gas to etch the anti-reflection layer 50 and the hard mask layer 40, the etching pressure is controlled to be greater than or equal to 80mT and less than or equal to 100mT; the high-frequency etching power is controlled to be greater than or equal to 600W and less than or equal to 800W, and the low-frequency etching power is controlled to be greater than or equal to 90W and less than 110W. In a specific embodiment of the present application, the low-frequency etching power is 100W. By reasonably constraining the etching pressure and etching power of the anti-reflection layer 50 and the hard mask layer 40, the controllability and selectivity of the etching process can be further improved, and etching defects can be reduced, which is suitable for the manufacture of semiconductor devices requiring high-precision etching.

[0043] It should be noted here that the high frequency may be 60 MHz and the low frequency may be 2 MHz.

[0044] like Figure 4 As shown, in the step of introducing the second mixed gas to etch the interlayer dielectric layer 30, the second mixed gas includes C4F8, N2, and Ar. In this process, the photoresist layer 60 with the etching pattern is used as a mask, and the interlayer dielectric layer 30 is etched by the second mixed gas composed of C4F8, N2, and Ar, and the etching is controlled to stop at the surface of the etching stop layer 20. By using the second mixed gas composed of C4F8, N2, and Ar to etch the interlayer dielectric layer 30, it is beneficial to ensure the accuracy and stability of the etching through hole 70, while maintaining a good etching rate and selectivity, and reducing damage to surrounding materials.

[0045] It should be noted that the material of the interlayer dielectric layer 30 of the present application is a material with a low dielectric constant. If only C4F8 and N2 are used for etching, although the side wall stripe phenomenon of the through hole 70 can be improved, it will cause more polymers at the side walls of the through hole 70, making the side walls of the through hole 70 finally formed inclined, with a side wall angle of about 70°, affecting the etching accuracy and verticality of the through hole 70. Therefore, the present application adds a high molecular weight gas Ar to enhance physical etching, reduce the accumulation of polymers on the side walls of the through hole 70, thereby ensuring the verticality of the through hole 70 and ensuring that the side wall angle of the through hole 70 is above 85°.

[0046] Specifically, in the step of introducing the second mixed gas to etch the interlayer dielectric layer 30, the flow ratio of C4F8 to Ar in the second mixed gas is controlled to be greater than or equal to 0.01 and less than or equal to 0.04, preferably greater than or equal to 0.02 and less than or equal to 0.03. The flow ratio of N2 to Ar in the second mixed gas is controlled to be greater than or equal to 0.4 and less than or equal to 0.7, preferably greater than or equal to 0.4 and less than or equal to 0.5. This arrangement is conducive to the reasonable regulation of the flow size and proportion of different gases, thereby ensuring the verticality of the etched through hole 70 while avoiding the generation of stripes and streaks on the side wall of the through hole 70, avoiding the processing situation where the side wall of the through hole 70 is inclined, optimizing the etching effect of the interlayer dielectric layer 30, and improving the accuracy of etching the through hole 70 and the reliability of the semiconductor device.

[0047] In addition, in the step of introducing the second mixed gas to etch the interlayer dielectric layer 30, the flow rate of C4F8 of the second mixed gas is controlled within the range of greater than or equal to 10 ml / min and less than or equal to 20 ml / min; the flow rate of N2 of the second mixed gas is controlled within the range of greater than or equal to 350 ml / min and less than or equal to 400 ml / min; the flow rate of Ar of the second mixed gas is controlled within the range of greater than or equal to 650 ml / min and less than or equal to 710 ml / min. Such a setting is conducive to ensuring accurate control of the flow range of each gas, and can achieve uniform etching of the interlayer dielectric layer 30, avoiding performance problems caused by uneven etching, and is suitable for the manufacture of high-performance computing chips and communication chips to ensure the stability of signal transmission and the accuracy of data processing.

[0048] Specifically, in the step of introducing the second mixed gas to etch the interlayer dielectric layer 30, the etching pressure is controlled to be greater than or equal to 25mT and less than or equal to 45mT; the high-frequency etching power is controlled to be greater than or equal to 430W and less than or equal to 450W, and the low-frequency etching power is controlled to be greater than or equal to 2000W and less than 2500W. In a specific embodiment of the present application, the etching pressure is 35mT, and the high-frequency etching power is 440W. Such etching conditions can effectively control the etching rate, reduce the etching damage of the interlayer dielectric layer 30, and ensure the stability of the etching process.

[0049] like Figure 5As shown, in the step of introducing the third mixed gas to etch the etch stop layer 20, the third mixed gas includes C4F8, N2, and Ar, and the second mixed gas and the third mixed gas have the same composition. In the process of etching the etch stop layer 20, the third mixed gas composed of C4F8, N2, and Ar is used to continue etching to ensure that the etch stop layer 20 forms a process window of sufficient size, the size including depth and width. By reasonably planning the composition of the third mixed gas and setting the composition of the third mixed gas to be the same as the composition of the second mixed gas, the etch stop layer 20 can continue to be etched after the interlayer dielectric layer 30 is etched, avoiding the change of the gas introduced, which is beneficial to improving the etching efficiency. At the same time, it is beneficial to ensure the effective etching of the etch stop layer 20, while protecting the substrate 10 below, and is suitable for manufacturing high-reliability semiconductor devices.

[0050] Specifically, the flow rate of C4F8 of the third mixed gas is controlled within a range of greater than or equal to 10 ml / min and less than or equal to 20 ml / min; the flow rate of N2 of the third mixed gas is controlled within a range of greater than or equal to 250 ml / min and less than or equal to 300 ml / min; the flow rate of Ar of the third mixed gas is controlled within a range of greater than or equal to 650 ml / min and less than or equal to 710 ml / min. By adjusting the gas flow rate, the etching effect of the etch stop layer 20 can be optimized, and the precise control of the etching depth can be ensured, which is suitable for the manufacture of micro-electromechanical systems (MEMS) and sensors that require precise control of the depth of the through hole 70.

[0051] Specifically, in the step of introducing the third mixed gas to etch the etch stop layer 20, the etching pressure is controlled to be greater than or equal to 25mT and less than or equal to 45mT; the high-frequency etching power is controlled to be greater than or equal to 430W and less than or equal to 450W, and the low-frequency etching power is controlled to be greater than or equal to 2000W and less than 2500W. In a specific embodiment of the present application, the etching pressure is 35mT, and the high-frequency etching power is 440W. This setting is conducive to accurately controlling the window size and depth of the etch stop layer 20, ensuring sufficient over-etching process window, and ensuring the accuracy of the etching process.

[0052] like Figure 6As shown, after the step of introducing the third mixed gas to etch the etch stop layer 20, it also includes: introducing the fourth mixed gas to etch and remove the remaining anti-reflection layer 50 and the photoresist layer 60, and the fourth mixed gas includes CO and CO2. At this time, the flow rate of CO in the fourth mixed gas is controlled to be greater than or equal to 850 ml / min and less than or equal to 900 ml / min, and the flow rate of CO2 in the fourth mixed gas is controlled to be greater than or equal to 1050 ml / min and less than or equal to 1500 ml / min. In the process of etching and removing the remaining anti-reflection layer 50 and the photoresist layer 60, the etching pressure is controlled to be 100mT, the high-frequency etching power is controlled to be 800W, and the low-frequency etching power is greater than or equal to 200W and less than 400W. By reasonably constraining the composition and proportion of the fourth mixed gas and controlling the etching parameters, it is beneficial to ensure the stability of clean etching, and the residual anti-reflection layer 50 and the photoresist layer 60 can be completely removed to avoid contamination in subsequent processes, which is suitable for semiconductor manufacturing processes requiring high cleanliness.

[0053] In summary, the through-hole etching method of the semiconductor device of the present application effectively improves the etching accuracy and verticality of the final through-hole 70 by accurately controlling the etching conditions of each layer, reduces the damage of the side wall of the through-hole 70, and forms a polymer protective layer on the surface of the photoresist layer 60, effectively preventing the abnormal pattern on the surface of the photoresist layer 60 in the subsequent etching process from being transmitted to the bottom of the through-hole 70 of the etching stop layer 20 so that the side wall of the through-hole 70 forms stripes or streaks, ensuring the smoothness of the side wall of the through-hole 70, and improving the manufacturing yield and performance of the semiconductor device. In addition, the method can flexibly respond to different materials and process requirements by adjusting the gas flow rate and etching power, and has a wide range of application prospects and industrial value. In practical applications, this method can not only improve the performance and reliability of semiconductor devices, but also reduce manufacturing costs and shorten production cycles, which is of great significance for promoting the development of the semiconductor industry. Especially in the context of the continuous advancement of current semiconductor technology to smaller size nodes, this high-precision, high-selectivity etching method will become an indispensable key technology in advanced processes, providing strong support for high-performance, high-density chip manufacturing.

[0054] Obviously, the above-described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0055] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0056] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A through-hole etching method for a semiconductor device, characterized in that: The steps include: An etching stop layer (20), an interlayer dielectric layer (30), a hard mask layer (40), an anti-reflection layer (50) and a photoresist layer (60) are sequentially formed on a substrate (10) in a direction away from the substrate (10), wherein the photoresist layer (60) has an etching pattern; Passing a first mixed gas to form a polymer protective layer on a surface of the photoresist layer (60) on a side away from the anti-reflection layer (50), and etching the anti-reflection layer (50) and the hard mask layer (40), wherein the first mixed gas includes CF4, CHF3, O2 and N2; Passing a second mixed gas to etch the interlayer dielectric layer (30); A third mixed gas is introduced to etch the etching stop layer (20).

2. The through hole etching method of a semiconductor device according to claim 1, characterized in that: In the step of introducing the first mixed gas to etch the anti-reflection layer (50) and the hard mask layer (40), Controlling the flow rate of CF4 in the first mixed gas to be greater than the flow rates of the other three gases; and / or The flow rate of O2 in the first mixed gas is controlled to be smaller than the flow rates of the other three gases.

3. The through hole etching method of a semiconductor device according to claim 1, characterized in that: In the step of introducing the first mixed gas to etch the anti-reflection layer (50) and the hard mask layer (40), Control the flow rates of CF4, O2 and N2 in the first mixed gas to satisfy: 2.2≤CF4 / (O2+N2)≤2.7; and / or The flow rates of CHF3, O2 and N2 in the first mixed gas are controlled as follows: 0.3≤CHF3 / (O2+N2)≤0.

8.

4. The through hole etching method of a semiconductor device according to claim 1, characterized in that: In the step of introducing the first mixed gas to etch the anti-reflection layer (50) and the hard mask layer (40), The flow rates of CF4, CHF3, O2 and N2 in the first mixed gas are controlled to satisfy: 1.9≤(CF4+CHF3) / (O2+N2)≤4.

6.

5. The through hole etching method of a semiconductor device according to claim 1, characterized in that: In the step of introducing the second mixed gas to etch the interlayer dielectric layer (30), The second mixed gas includes C4F8, N2, and Ar.

6. The through hole etching method of a semiconductor device according to claim 5, characterized in that: In the step of introducing the second mixed gas to etch the interlayer dielectric layer (30), Controlling the flow rate ratio of C4F8 to Ar in the second mixed gas to be greater than or equal to 0.01 and less than or equal to 0.04; and / or The flow rate ratio of N2 to Ar in the second mixed gas is controlled to be greater than or equal to 0.4 and less than or equal to 0.

7.

7. The through hole etching method of a semiconductor device according to claim 5, characterized in that: In the step of introducing the second mixed gas to etch the interlayer dielectric layer (30), Controlling the flow rate of C4F8 in the second mixed gas to be within a range of greater than or equal to 10 ml / min and less than or equal to 20 ml / min; and / or Controlling the flow rate of N2 in the second mixed gas to be within a range of greater than or equal to 350 ml / min and less than or equal to 400 ml / min; and / or The flow rate of Ar in the second mixed gas is controlled within a range of greater than or equal to 650 ml / min and less than or equal to 710 ml / min.

8. The through hole etching method of a semiconductor device according to claim 1, characterized in that: In the step of introducing the third mixed gas to etch the etching stop layer (20), The third mixed gas includes C4F8, N2, and Ar.

9. The through hole etching method of a semiconductor device according to claim 8, characterized in that: Controlling the flow rate of C4F8 in the third mixed gas to be within a range of greater than or equal to 10 ml / min and less than or equal to 20 ml / min; and / or Controlling the flow rate of N2 of the third mixed gas to be within a range of greater than or equal to 250 ml / min and less than or equal to 300 ml / min; and / or The flow rate of Ar in the third mixed gas is controlled within a range of greater than or equal to 650 ml / min and less than or equal to 710 ml / min.

10. The through hole etching method of a semiconductor device according to claim 1, characterized in that: In the step of introducing the first mixed gas to etch the anti-reflection layer (50) and the hard mask layer (40), Controlling the etching pressure to be greater than or equal to 80 mT and less than or equal to 100 mT; and / or The high-frequency etching power is controlled to be greater than or equal to 600W and less than or equal to 800W, and the low-frequency etching power is controlled to be greater than or equal to 90W and less than 110W.

11. The through hole etching method of a semiconductor device according to claim 1, characterized in that: In the step of introducing the second mixed gas to etch the interlayer dielectric layer (30); and / or introducing the third mixed gas to etch the etch stop layer (20), Control the etching pressure to be greater than or equal to 25mT and less than or equal to 45mT; The high-frequency etching power is controlled to be greater than or equal to 430W and less than or equal to 450W, and the low-frequency etching power is controlled to be greater than or equal to 2000W and less than 2500W.

12. The through hole etching method of a semiconductor device according to any one of claims 1 to 11, characterized in that: After the step of introducing the third mixed gas to etch the etching stop layer (20), the method further comprises: A fourth mixed gas is introduced to remove the remaining anti-reflection layer (50) and the photoresist layer (60), wherein the fourth mixed gas comprises CO and CO2.

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