Deep trench isolation structure, semiconductor device and isolation structure manufacturing method thereof

Abstract

The embodiment of the invention relates to a deep trench isolation structure, a semiconductor device and an isolation structure manufacturing method thereof. The semiconductor device includes: a substrate; the epitaxial layer is positioned on the substrate; the buried layer is positioned between at least one of the substrate and the epitaxial layer or between the substrate and the epitaxial layer; the first conductive channel extends into the buried layer from the surface of the epitaxial layer; the second conductive channel extends into the substrate from the surface of the epitaxial layer; the deep trench isolation is located between the first conductive channel and the second conductive channel, the deep trench isolation extends into the substrate from the surface of the epitaxial layer, the deep trench isolation comprises an insulating core part and an insulating liner surrounding the insulating core part, the deep trench isolation is arranged in a second trench, and the insulating liner is arranged between the first conductive channel and the second conductive channel. The second groove comprises a first part located in the epitaxial layer and the buried layer and a second part located in the substrate, and an air gap is formed in an insulating core part in the second part.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more specifically, to a deep trench isolation structure, a semiconductor device and a method for manufacturing the isolation structure. Background Art

[0002] Hybrid integration technology that integrates different types of transistors into the same semiconductor substrate or semiconductor layer has been widely used in integrated circuits. For example, integrated circuits using hybrid integration technology include: complementary metal oxide semiconductor (CMOS) integrated circuits composed of N-type MOS transistors and P-type MOS transistors, power integrated circuits composed of high-voltage transistors and low-voltage transistors, and hybrid integrated circuits composed of analog circuits and digital circuits.

[0003] In CMOS integrated circuits, different analog circuit functions, such as amplifiers, filters, oscillators, etc., are realized based on complementary N-type MOS transistors and P-type MOS transistors. Basic logic gate circuits can also be realized, thereby realizing various complex digital circuit functions. Since different types of transistors are used in CMOS integrated circuits, it is necessary to form an isolation structure to define the active area of ​​each transistor so that adjacent transistors are separated from each other and work independently without current leakage between each other. In addition, a buried layer may be formed under the well region in the semiconductor layer to improve the source-substrate breakdown voltage characteristics of the semiconductor device. When the isolation structure of the semiconductor device is reasonably designed, the CMOS integrated circuit has the characteristics of low power consumption, high precision, high speed and low noise.

[0004] The isolation structure of semiconductor devices may include trench isolations of different depths. For example, shallow trench isolation (abbreviated as STI) is used to separate the N-type MOS transistor and the P-type MOS transistor of the same circuit unit from each other, and deep trench isolation (abbreviated as DTI) is used to separate the conductive channels of the transistors from each other. However, deep trench isolation itself may damage the crystal structure of the semiconductor layer, and the insulating layer inside the deep trench will generate greater stress. Summary of the invention

[0005] The purpose of the present disclosure is to provide a deep trench isolation structure, a semiconductor device and a method for manufacturing the isolation structure, which can effectively solve the problems in the prior art.

[0006] According to one aspect of the present invention, there is provided a semiconductor device, comprising: a substrate; an epitaxial layer located on the substrate; a buried layer located between at least one or both of the substrate and the epitaxial layer; and a first conductive channel extending from the surface of the epitaxial layer into the buried layer; a second conductive channel extending from the surface of the epitaxial layer into the substrate; and a deep trench isolation located between the first conductive channel and the second conductive channel, the deep trench isolation extending from the surface of the epitaxial layer into the substrate, wherein the deep trench isolation comprises an insulating core and an insulating liner surrounding the insulating core, the deep trench isolation being arranged in a second trench, the second trench comprising a first portion located in the epitaxial layer and the buried layer and a second portion located in the substrate, the insulating core in the second portion having an air gap.

[0007] Optionally, an opening size of a first portion of the second groove is larger than an opening size of a second portion thereof.

[0008] Optionally, the insulating pad includes: a first insulating pad covering the side walls of a first portion of the second groove; and a second insulating pad covering the bottom and side walls of a second portion of the second groove; wherein, a first cavity is formed after the first portion of the second groove forms the first insulating pad, and a second cavity is formed after the second portion of the second groove forms the second insulating pad, and an opening size of the first cavity is smaller than an opening size of the second cavity; and the insulating core fills the first cavity and the second cavity.

[0009] Optionally, the first insulating pad includes a stacked first outermost insulating layer and a first intermediate insulating layer, the first outermost insulating layer is in contact with the epitaxial layer and the buried layer; the second insulating pad includes a single-layer insulating layer, the single-layer insulating layer is in contact with the substrate; wherein the thickness of the second insulating pad is less than the thickness of the first intermediate insulating layer.

[0010] Optionally, the insulating core in the first portion has an air gap therein.

[0011] Optionally, an opening size of the air gap in the first portion is smaller than an opening size of the air gap in the second portion.

[0012] Optionally, the first conductive channel includes a first conductive core and a second insulating pad surrounding the first conductive core, the second insulating pad has an opening at the bottom, and the first conductive core contacts the buried layer via the opening at the bottom of the second insulating pad.

[0013] Optionally, the second conductive channel includes a second conductive core and a third insulating pad surrounding the second conductive core, the second insulating pad has an opening at the bottom, and the second conductive core contacts the substrate via the opening at the bottom of the third insulating pad.

[0014] Optionally, the semiconductor device is a semiconductor device selected from any one of a power integrated circuit, a CMOS integrated circuit, and an analog-digital hybrid integrated circuit.

[0015] According to another aspect of the present invention, a deep trench isolation structure is provided, comprising: a substrate; an epitaxial layer located on the substrate; a buried layer located between at least one of the substrate and the epitaxial layer or both; the deep trench isolation extends from the surface of the epitaxial layer into the substrate, wherein the deep trench isolation comprises an insulating core and an insulating liner surrounding the insulating core, the deep trench isolation is arranged in a second trench, the second trench comprises a first portion located in the epitaxial layer and the buried layer and a second portion located in the substrate, the insulating core in the second portion has an air gap, and the insulating core in the first portion has an air gap.

[0016] Optionally, an opening size of a first portion of the second groove is larger than an opening size of a second portion thereof.

[0017] Optionally, the insulating pad includes: a first insulating pad covering the side walls of a first portion of the second groove; and a second insulating pad covering the bottom and side walls of a second portion of the second groove; wherein, a first cavity is formed after the first portion of the second groove forms the first insulating pad, and a second cavity is formed after the second portion of the second groove forms the second insulating pad, and an opening size of the first cavity is smaller than an opening size of the second cavity; and the insulating core fills the first cavity and the second cavity.

[0018] Optionally, the first insulating pad includes a stacked first outermost insulating layer and a first intermediate insulating layer, the first outermost insulating layer is in contact with the epitaxial layer and the buried layer; the second insulating pad includes a single-layer insulating layer, the single-layer insulating layer is in contact with the substrate; wherein the thickness of the second insulating pad is less than the thickness of the first intermediate insulating layer.

[0019] Optionally, an opening size of the air gap in the first portion is smaller than an opening size of the air gap in the second portion.

[0020] According to another aspect of the present invention, a method for manufacturing an isolation structure of a semiconductor device is provided, comprising: forming an epitaxial layer on a substrate; forming a buried layer between at least one or both of the substrate and the epitaxial layer; forming a first trench and a first portion of a second trench, wherein the first trench extends from a surface of the epitaxial layer into the buried layer, and the first portion of the second trench extends from the surface of the epitaxial layer to at least the bottom of the buried layer; forming a first conductive channel in the first trench, and forming a first outermost insulating layer and a dummy conductive core on the upper portion of the second trench; forming a third trench, a fourth trench, and a second trench; and the second part of the second trench, the third trench extends from the surface of the epitaxial layer to the substrate; the fourth trench is aligned with the second trench, extends in the dummy conductive core in the second trench, the fourth trench passes through the dummy conductive core of the second trench, and continues to extend downward into the substrate to form the second part of the second trench; a second conductive channel is formed in the third trench, and a deep trench isolation is formed in the second trench; wherein the deep trench isolation includes an insulating core and an insulating liner surrounding the insulating core, and the insulating core in the second part has an air gap.

[0021] Optionally, an opening size of a first portion of the second groove is larger than an opening size of a second portion thereof.

[0022] Optionally, the method for forming a second conductive channel in the third trench and forming deep trench isolation in the second trench includes: forming a second outermost insulating layer in the third trench, forming a first intermediate insulating layer in the first part of the second trench, and forming a second insulating pad in the second part of the second trench, the first outermost insulating layer in the first part of the second trench and the first intermediate insulating layer constituting a first insulating pad; forming a second intermediate insulating layer in the third trench and an insulating core in the second trench, the second intermediate insulating layer conformally covering the bottom and sidewalls of the third trench, and the second outermost insulating layer constituting a third insulating liner of the second conductive channel, the insulating core in the second trench filling the second trench; forming an opening penetrating the third insulating liner at the bottom of the third trench; and forming a second conductive core in the third trench, the second conductive core contacting the substrate.

[0023] Optionally, the first part of the second groove forms a first insulating pad before forming a first cavity, and the second part of the second groove forms a second insulating pad before forming a second cavity, and the opening size of the first cavity is smaller than the opening size of the second cavity; in the second groove, the insulating core preferentially closes the opening of the second cavity, forming an air gap in the insulating core in the second cavity.

[0024] Optionally, an air gap is formed in the insulating core in the first portion.

[0025] Optionally, an opening size of the air gap in the first portion is smaller than an opening size of the air gap in the second portion.

[0026] Optionally, the first trench and the first portion of the second trench are formed via a same step.

[0027] Optionally, the third trench, the fourth trench and the second portion of the second trench are formed through a same step.

[0028] According to the semiconductor device of the embodiment of the present disclosure, a deep trench isolation is provided in the peripheral region of the semiconductor device, and the deep trench isolation extends from the surface of the epitaxial layer to the substrate below the buried layer, separating the first conductive channel and the second conductive channel located in the peripheral region from each other. Not only can the breakdown voltage of the semiconductor device be improved due to the improved isolation performance of the deep trench isolation, but also the size of the semiconductor device can be reduced because the spacing between the first conductive channel and the second conductive channel is allowed to be reduced at the same breakdown voltage.

[0029] Furthermore, an air gap is provided in the insulating core located in the second part of the second trench, and the air gap is utilized to reduce the equivalent dielectric constant of the insulating core, thereby further reducing the parasitic capacitance of the semiconductor device introduced by the deep trench isolation, and further improving the performance of the semiconductor device; at the same time, the formation of the air gap greatly reduces the thickness of the insulating core, thereby greatly reducing the stress generated by the formation of the insulating core.

[0030] In a preferred embodiment, an air gap is provided in the insulating core located in the first portion of the second trench, thereby reducing the parasitic capacitance of the semiconductor device introduced by the deep trench isolation, and further improving the performance of the semiconductor device. Furthermore, the lateral size of the air gap in the first portion is greater than the lateral size of the air gap in the second portion, so as to further reduce the stress generated by the insulating core in the second portion.

[0031] In a preferred embodiment, the first deep trench isolation, the first conductive channel, and the second conductive channel are formed in the first trench, the second trench, and the third trench, respectively. In a preferred embodiment, by selecting the same opening width of the first conductive channel and the deep trench isolation, a common trench etching process can be used to simultaneously form the first trench extending into the buried layer and the second trench extending to the bottom of the buried layer. This can not only reduce the process steps and the number of masks for manufacturing the isolation structure, but also avoid the depth deviation of the first conductive channel and the first deep trench isolation caused by the independent etching steps, thereby reducing the manufacturing cost of the semiconductor device and improving the yield of the semiconductor device.

[0032] Furthermore, the insulating liner in the deep trench isolation is a stack of multiple insulating layers, the outermost insulating layer of the multiple insulating layers is located on the sidewall of the trench, and at least one intermediate insulating layer is located between the outermost insulating layer and the insulating core. The insulating liner uses a stack of multiple insulating layers to improve the isolation performance of the deep trench isolation, thereby improving the reliability of the semiconductor device.

[0033] In a preferred embodiment, after forming an outer insulating layer of an insulating pad in the second trench, sacrificial polysilicon is then filled in the second trench, and a fourth trench is formed by deep etching of the sacrificial polysilicon. Compared with forming a deep trench isolation directly in the fourth trench penetrating the epitaxial layer, the aspect ratio of the second trench is relatively reduced. Therefore, the etching time experienced by the epitaxial layer is shortened, which is beneficial to reducing damage to the epitaxial layer. The deep trench etching of the fourth trench is carried out in the sacrificial polysilicon and will not cause any damage to the epitaxial layer. Therefore, the crystal defects and / or dislocation defects at the silicon / silicon oxide interface can be significantly reduced, thereby suppressing the leakage current caused by the first deep trench isolation in the semiconductor device.

[0034] In a preferred embodiment, in the step of forming deep trench isolation, a deposition step common to the first conductive channel is used to form sacrificial polysilicon in the second trench, and a trench etching process common to the second conductive channel is used to form the fourth trench in the first portion of the second trench. This can ensure that the isolation structure of the semiconductor device disclosed in the present invention is compatible with the process of the existing isolation structure, and will not increase the number of process steps and masks of the isolation structure, so that while improving the isolation characteristics of the first deep trench isolation structure, the manufacturing cost of the semiconductor device will not be significantly increased.

[0035] In a preferred embodiment, by selecting the opening width of the fourth trench to be smaller than the opening width of the second conductive channel, a common trench etching process can be used to simultaneously form the third trench and the fourth trench, and the fourth trench is made to extend downward into the substrate to form the second portion of the second trench. This can not only reduce the number of process steps and masks for manufacturing the isolation structure, but also avoid the depth deviation of the second conductive channel and the deep trench isolation caused by the independent etching steps, thereby reducing the manufacturing cost of the semiconductor device and improving the yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other purposes, features and advantages of the embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown by way of example and not limitation, in which:

[0037] Figure 1a , Figure 1b and Figure 1cA schematic perspective view, a top view, and a cross-sectional view respectively illustrate a semiconductor device according to an embodiment of the present disclosure;

[0038] Figure 2a A schematic cross-sectional view showing a first conductive channel, a second conductive channel, and a deep trench isolation according to an embodiment of the present application;

[0039] Figure 2b Shows Figure 2a Schematic diagram of deep trench isolation in ;

[0040] Figures 3a to 3l Schematic cross-sectional views of a method for manufacturing an isolation structure of a semiconductor device according to an embodiment of the present disclosure at different stages are respectively shown. DETAILED DESCRIPTION

[0041] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0042] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects.

[0043] Furthermore, the terms "top", "bottom", "above", "below", "over", "below", etc., as used herein, are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that embodiments of the present disclosure are capable of operation in other orientations than described or illustrated herein.

[0044] In addition, the terms "shallow trench", "medium trench" and "deep trench" used in this article are used for descriptive purposes and are not necessarily used to define the absolute value of the trench depth. In the case of describing the "shallow trench", "medium trench" and "deep trench" in the same semiconductor device, they are only used to indicate the relative depth relationship between multiple trenches and other device structures of the semiconductor device, and are not necessarily used to describe the relative depth relationship between multiple trenches and other device structures of the semiconductor device. For example, when describing a "deep trench" in a semiconductor device, the trench mentioned may extend below the well region of the semiconductor device, or may further extend into the buried layer of the semiconductor device, or may further extend below the buried layer of the semiconductor device.

[0045] Embodiments of the present disclosure generally relate to semiconductor devices or integrated circuits (ICs). More specifically, some embodiments relate to semiconductor devices or CMOS integrated circuits having complementary N-type MOS transistors and P-type MOS transistors integrated on the same substrate. CMOS integrated circuits can be used for analog integrated circuits such as amplifiers, or digital integrated circuits such as logic circuits. The embodiments of the present disclosure form a plurality of trench structures of different depths while sharing existing trench process steps, and together with a buried layer (e.g., an N+ buried layer (NBL)), effectively isolate different device units in the same integrated circuit from each other.

[0046] Figure 1a , Figure 1b and Figure 1c A schematic perspective view, a top view and a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure are respectively shown, wherein Figure 1b The top view shown uses line AA to show the interception position of the cross-sectional view. Unless otherwise specified, the interception positions of the cross-sectional views in the drawings of the present disclosure are all along line AA.

[0047] In the present disclosure, the semiconductor device 100 may be any combination of different types of active devices. For example, in a CMOS integrated circuit, it is a combination of an N-type MOS transistor and a P-type MOS transistor, and in a power integrated circuit, it is a combination of a high-voltage transistor and a low-voltage transistor. The high-voltage transistor is, for example, a lateral double diffused metal oxide semiconductor (LDMOS) transistor, and the low-voltage transistor is, for example, a conventional planar MOS transistor. In the following, the present disclosure is described in detail only by taking a CMOS integrated circuit as an example.

[0048] The semiconductor device 100 includes a substrate 101, an epitaxial layer 102 and a buried layer 103. The epitaxial layer 102 is, for example, a semiconductor layer disposed above the substrate 101. The buried layer 103 is, for example, a doped region disposed in one of the substrate 101 and the epitaxial layer 102, or a semiconductor layer disposed between the substrate 101 and the epitaxial layer 102.

[0049] The substrate 101 and the epitaxial layer 102 have a first doping type, respectively, and the buried layer 103 has a second doping type opposite to the first doping type. For example, when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type. P-type dopants may include boron (B), aluminum (Al), indium (In) or a combination thereof, while N-type dopants may include phosphorus (P), arsenic (As), antimony (Sb) or a combination thereof. In one embodiment, the buried layer 103 may have a blanket structure having substantially the same horizontal extension as the substrate 101 and being laid flat on the substrate 101. In another embodiment, the buried layer 103 may have a patterned structure. The embodiments of the present disclosure are not strictly limited to this.

[0050] The semiconductor device 100 includes a plurality of device regions. Figure 1a , 1b The semiconductor device 100 shown in FIG. 1 c includes a core region 110 and a peripheral region 120 .

[0051] In the core region 110 of the semiconductor device 100, a well region 104 of a first transistor 111 and a well region 105 of a second transistor 112 are provided, which are doped regions in the epitaxial layer 102. The well region 104 of the first transistor 111 has a first doping type, a source region 106 and a drain region 107 of a second doping type are provided in the well region 104, and a gate stack is provided above the well region 104, the gate stack includes a gate dielectric 108 and a gate conductor 109 stacked in sequence, wherein the gate dielectric 108 is sandwiched between the gate conductor 109 and the epitaxial layer 102. For example, the gate dielectric 108 is composed of silicon oxide, and the gate conductor 109 is composed of doped polysilicon. For an N-type MOS transistor, the well region 104 of the first transistor 111 is doped to a P-type, and the source region 106 and the drain region 107 are doped to an N-type, respectively. For a P-type MOS transistor, the well region 104 of the first transistor 111 is doped to N-type, and the source region 106 and the drain region 107 are doped to P-type, respectively. The well region 104 of the first transistor 111 serves as the body region of the transistor. When a gate voltage is applied to the gate conductor 109, a channel is formed in the well region 104 of the first transistor 111, which is used to control the conductive path between the source region 106 and the drain region 107, thereby controlling the conduction state of the first transistor 111.

[0052] The first transistor 111 and the second transistor 112 are an N-type MOS transistor and a P-type MOS transistor that complement each other. The well region 105 of the second transistor 112 has a second doping type, and a source region and a drain region of a first doping type are arranged in the well region 105, and a gate stack is arranged above the well region. Since the device structure of the second transistor 112 is similar to that of the first transistor 111, the internal structure of the second transistor 112 will not be described in detail.

[0053] Furthermore, in the core region 110, a shallow trench isolation 121 is provided for isolating the first transistor 111 from the second transistor 112. In order to isolate the first transistor 111 from the second transistor 112, the shallow trench isolation 121 extends from the surface of the epitaxial layer 102 to the well region of the first transistor 111 and the second transistor 112 to a depth D1.

[0054] A first conductive via 10 and a second conductive via 20 are provided in the peripheral region 120 of the semiconductor device 100. The first conductive via 10 extends from the surface of the epitaxial layer 102 to the inside of the buried layer 103 to a depth D2, and is used to provide an electrical connection path from the buried layer 103 to the surface of the epitaxial layer 102. The second conductive via 20 extends from the surface of the epitaxial layer 102 to the bottom of the buried layer 103 until the inside of the substrate 101 reaches a depth D3, and is used to provide an electrical connection path from the substrate 101 to the surface of the epitaxial layer 102. The depth D2 is greater than the depth D1, and the depth D3 is greater than the depth D2.

[0055] The first conductive channel 10 is disposed in the first trench for electrically connecting the buried layer 103 to the surface of the epitaxial layer 102. In one embodiment, the first conductive channel 10 includes an insulating liner 11 and a conductive core 12. The insulating liner 11 is composed of an oxide, such as silicon oxide, and the conductive core 12 is composed of a conductive material, such as doped polysilicon. Other types of insulating liners 11 and conductive cores 12 are also feasible. The insulating liner 11 is formed on a portion of the sidewall and the bottom of the trench, and includes an opening formed at the bottom of the trench. The conductive core 12 fills the trench and the opening, extends from the surface of the epitaxial layer 102 to the bottom of the trench, and contacts the buried layer 103. The insulating liner 11 of the first conductive channel 10 isolates the conductive core 12 from the epitaxial layer 102.

[0056] With this arrangement, the first conductive channel 10 penetrates the epitaxial layer 102, and the conductive core 12 therein connects the buried layer 103 to the surface of the epitaxial layer 102. Therefore, in the working state of the semiconductor device 100, the buried layer 103 is biased to any desired potential via the first conductive channel 10. On the one hand, the bias voltage of the buried layer 103 can be used to improve the source-substrate breakdown voltage characteristics of the semiconductor device, and on the other hand, the shielding effect of the buried layer 103 can be used to suppress crosstalk between adjacent semiconductor devices. In this embodiment, the power supply voltage VDD is applied to the buried layer 103 via the first conductive channel 10 to obtain the desired bias voltage and shielding effect.

[0057] The second conductive channel 20 is disposed in the third trench for electrically connecting the substrate 101 to the surface of the epitaxial layer 102. In one embodiment, the second conductive channel 20 includes an insulating liner 21 and a conductive core 22. The insulating liner 21 is composed of an oxide, such as silicon oxide, and the conductive core 22 is composed of a conductive material, such as doped polysilicon. Other types of insulating liners 21 and conductive cores 22 are also feasible. The insulating liner 21 is formed on a portion of the sidewall and the bottom of the trench, and includes an opening formed at the bottom of the trench. The conductive core 22 fills the trench and the opening, that is, extends from the surface of the epitaxial layer 102 to the bottom of the trench, and contacts the substrate 101. The insulating liner 21 of the second conductive channel 20 isolates the conductive core 22 from the epitaxial layer 102 and the buried layer 103.

[0058] With this arrangement, the second conductive path 20 penetrates the epitaxial layer 102 and the buried layer 103, and the conductive core 22 therein connects the substrate 101 to the surface of the epitaxial layer 102. Therefore, in the working state of the semiconductor device 100, the substrate 101 is biased to any desired potential via the second conductive path 20. This can connect the substrate 101 to any desired potential on the one hand, thereby suppressing noise and interference, and on the other hand, can avoid latch-up problems. In this embodiment, the substrate 101 is grounded via the second conductive path 20 to obtain the desired anti-interference effect.

[0059] In this embodiment, the conductive core 12 of the first conductive channel 10 and the conductive core 22 of the second conductive channel 20 are both composed of doped polysilicon. The conductive core 12 of the first conductive channel 10 has the same doping type and a higher doping concentration as the buried layer 103 in contact with it, so a low resistance path of the buried layer 103 can be formed. The conductive core 22 of the second conductive channel 20 has the same doping type and a higher doping concentration as the substrate 101 in contact with it, so a low resistance path of the substrate 101 can be formed. In other embodiments, it is also feasible for the first conductive channel 10 and the second conductive channel 20 to use other types of conductive cores, as long as the semiconductor layer in contact with them can be electrically connected to the surface of the epitaxial layer 102.

[0060] Furthermore, in the peripheral region 120, a plurality of shallow trench isolations 122 and deep trench isolations 30 are provided around the core region 110. In order to isolate the first conductive channel 10 and the second conductive channel 20 from each other, the deep trench isolation 30 is provided between the first conductive channel 10 and the second conductive channel 20. The deep trench isolation 30 extends from the surface of the epitaxial layer 102 to below the buried layer 103 and reaches the inside of the substrate 101. The opening width and depth of the second conductive channel 20 are both greater than the deep trench isolation 30.

[0061] The deep trench isolation 30 is arranged in the second trench to isolate the first conductive channel 10 and the second conductive channel 20 from each other. In one embodiment, the deep trench isolation 30 includes an insulating liner 31 and an insulating core 32. The insulating liner 31 and the insulating core 32 are composed of oxide or nitride, such as silicon oxide or silicon nitride. Other types of insulating liner 31 and insulating core 32 are also feasible. In a preferred embodiment, the insulating liner 31 and the insulating core 32 are respectively composed of silicon oxide. The insulating liner 31 is formed on the sidewall and the bottom of the trench. The insulating core 32 fills the inner space of the trench. The insulating liner 31 and the insulating core 32 of the deep trench isolation 30 form a composite insulating layer to improve the isolation performance. Due to the improved isolation performance of the deep trench isolation 30, the breakdown voltage of the semiconductor device can be improved, and since the spacing between the first conductive channel and the second conductive channel is allowed to be reduced at the same breakdown voltage, the size of the semiconductor device can be reduced.

[0062] Figure 2a A schematic cross-sectional view of a first conductive channel, a second conductive channel, and a deep trench isolation according to an embodiment of the present application is shown. For the sake of clarity, Figure 2a Only the peripheral area of ​​the semiconductor device 300 is shown. Figure 2b Shows Figure 2a Schematic diagram of deep trench isolation in .

[0063] like Figure 2a and Figure 2b As shown, the first conductive channel 10 is arranged in the first trench, and is used to electrically connect the buried layer 103 to the surface of the epitaxial layer 102. The first conductive channel 10 includes an insulating liner 11 and a conductive core 12. The insulating liner 11 of the first conductive channel 10 is composed of a single-layer insulating layer, and the single-layer insulating liner 11 repairs the damage caused to the side wall of the trench when the epitaxial layer 102 is deeply etched to form the trench, and isolates the epitaxial layer 102 and the conductive core 12. The single-layer insulating layer also includes an opening formed at the bottom of the trench, and the conductive core 12 fills the inner space of the trench and the bottom opening of the trench to contact the buried layer 103.

[0064] Although not shown in the figure, it should be known that the first conductive channel 10 can also be a stack composed of multiple insulating layers. The outermost insulating layer of the multiple insulating layers is located on the sidewall of the groove, and at least one intermediate insulating layer is located between the outermost insulating layer and the conductive core 12. In one embodiment, the multiple insulating layers in the insulating liner 11 are composed of oxides or nitrides, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. The outermost insulating layer in the insulating liner 11 can repair the damage to the sidewall of the groove when the epitaxial layer 102 is deeply etched to form a groove, so as to facilitate the deposition of the intermediate insulating layer thereon. The intermediate insulating layer covers the surface of the existing insulating layer in the groove, and the thickness of the intermediate insulating layer is greater than the outermost insulating layer, which is used to enhance the isolation performance between the conductive core 12 and the epitaxial layer 102. The intermediate insulating layer also includes an opening formed at the bottom of the groove. The conductive core 12 fills the internal space of the groove and the bottom opening of the groove.

[0065] The second conductive channel 20 is disposed in the third trench for electrically connecting the substrate 101 to the surface of the epitaxial layer 102. The insulating liner 21 of the second conductive channel 20 is a stack composed of a plurality of insulating layers, wherein the outermost insulating layer of the plurality of insulating layers is located on the trench sidewall, and at least one intermediate insulating layer is located between the outermost insulating layer and the conductive core 22. The plurality of insulating layers in the insulating liner 21 are composed of oxides or nitrides, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. Figure 2a In the illustrated embodiment, the insulating liner 21 of the second conductive channel 20 includes an outermost insulating layer 2101 and an intermediate insulating layer 2102, wherein the outermost insulating layer 2101 is located on the sidewall of the groove, and the intermediate insulating layer 2102 is located between the outermost insulating layer 2101 and the conductive core 22. The outermost insulating layer 2101 and the intermediate insulating layer 2102 are, for example, oxide layers. The outermost insulating layer in the insulating liner 21 can repair the damage to the sidewall of the groove when the epitaxial layer 102 and the buried layer 103 are deeply etched to form the groove, so as to facilitate the deposition of the intermediate insulating layer thereon. The intermediate insulating layer covers the surface of the existing insulating layer in the groove, and is used to enhance the isolation performance between the conductive core 22 and the epitaxial layer 102 and the buried layer 103. The intermediate insulating layer is arranged inside the insulating liner 21 in the groove, and the intermediate insulating layer also includes an opening extending from the surface of the epitaxial layer 102 to the bottom of the groove. The conductive core 22 fills the inner space of the groove and the bottom opening of the groove.

[0066] The deep trench isolation 30 is arranged in the second trench to isolate the first conductive channel 10 and the second conductive channel 20 from each other. Further, the second trench includes a first portion and a second portion that are interconnected, and the opening size of the first portion of the second trench is larger than the opening size of the second portion. The first portion of the second trench extends from the surface of the epitaxial layer 102 to the surface of the buried layer 103 away from the epitaxial layer 102, and the second portion extends from the surface of the substrate 101 close to the buried layer 103 in a direction away from the buried layer 103. In other words, the first portion of the second trench is located in the epitaxial layer 102 and the buried layer 103, and the second portion of the second trench is located in the epitaxial layer 101.

[0067] The insulating pad 31 includes a first insulating pad 31a and a second insulating pad 31b, wherein the first insulating pad 31a covers the sidewall of the first part of the second groove, and the second insulating pad 31b covers the sidewall and the bottom of the second part of the second groove. Further, the thickness of the first insulating pad 31a is greater than the thickness of the second insulating pad 31b. After the first insulating pad 31a is formed, the first part of the second groove forms a first cavity, and after the second insulating pad 31b is formed, the second part of the second groove forms a second cavity, the opening size of the first cavity is smaller than the opening size of the second cavity, and the opening size of the connecting portion is smaller than the opening size of the first cavity.

[0068] In a preferred embodiment, the insulating liner 31 of the deep trench isolation 30 is a stack composed of multiple insulating layers, the outermost insulating layer of the multiple insulating layers is located on the trench sidewall, and at least one intermediate insulating layer is located between the outermost insulating layer and the insulating core 32. The multiple insulating layers in the insulating liner 31 are composed of oxides or nitrides, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible.

[0069] In a preferred embodiment, the first insulating liner 31a is a stack of multiple insulating layers, and the second insulating liner 31b includes a single insulating layer. In one embodiment, the first insulating liner 31a includes an outermost insulating layer 3101 and an intermediate insulating layer 3102, the outermost insulating layer 3101 is located on the side wall of the first part of the second trench, and the intermediate insulating layer 3102 is located between the outermost insulating layer 3101 and the insulating core 32. The outermost insulating layer 3101 can repair the damage to the trench side wall caused when the epitaxial layer 102 and the buried layer 103 are deeply etched to form the trench, so as to facilitate the deposition of the intermediate insulating layer 3102 thereon. The intermediate insulating layer 3102 covers the surface of the existing insulating layer in the first part of the second trench, and is used to enhance the isolation performance of the deep trench isolation 30. The second insulating liner 31b includes a single insulating layer.

[0070] Furthermore, the insulating core 32 fills the inner space of the second trench. There is an air gap 33b in the insulating core 32 located in the second portion of the second trench, and the air gap 33b is used to reduce the equivalent dielectric constant of the insulating core 32, thereby further reducing the parasitic capacitance introduced by the semiconductor device due to the deep trench isolation, and further improving the performance of the semiconductor device; at the same time, the formation of the air gap 33b greatly reduces the thickness of the insulating core 32, thereby greatly reducing the stress generated by the formation of the insulating core 32.

[0071] In a preferred embodiment, the insulating core 32 in the first portion of the second trench has an air gap 33a, and the lateral dimension of the air gap 33b is larger than that of the air gap 33a, so as to further reduce the stress generated by the insulating core in the second portion.

[0072] In the etching step for forming the first and second grooves, if the opening widths of the plurality of grooves are different, the etching depths reached by the plurality of grooves are different after the same etching time. The larger the opening width of the groove, the greater the etching depth of the groove. On the contrary, the smaller the opening width of the groove, the smaller the etching depth of the groove.

[0073] In this embodiment, the opening widths of the first trench of the first conductive channel 10 and the second trench of the deep trench isolation 30 are different. By controlling the opening sizes of the first trench and the second trench, different etching depths can be reached in the same etching step. That is, the trenches of the first conductive channel 10 and the deep trench isolation 30 can be formed simultaneously using a common etching step.

[0074] In the peripheral region 120 of the semiconductor device 100, the deep trench isolation 30 is used to form an insulating isolation ring between the first conductive channel 10 and the second conductive channel 20. The depth of the insulating isolation ring is greater than the depth of the shallow trench isolation 122, and is at least greater than the depth of the first conductive channel 10, thereby improving the isolation performance between the first conductive channel 10 and the second conductive channel 20.

[0075] Furthermore, it should be understood that although the isolation structure described above is used to isolate the CMOS

[0076] N-type MOS transistors and P-type MOS transistors in an integrated circuit. However, it should be understood that the above isolation structure can also be used to isolate device regions of other types of integrated circuits, and the embodiments of the present disclosure are not strictly limited to this.

[0077] Figures 3a to 3l Schematic cross-sectional views of a method for manufacturing an isolation structure of a semiconductor device according to an embodiment of the present disclosure at different stages are respectively shown. Figures 3a to 3l The manufacturing method shown can be used to manufacture Figures 1a to 2b The semiconductor device 100 shown in the figure. Figures 1a to 2b The description of the semiconductor device 100 may be incorporated herein.

[0078] like Figure 3a As shown, an initial semiconductor structure including a substrate 101, an epitaxial layer 102, and a buried layer 103 is provided. The epitaxial layer 102 is, for example, a semiconductor layer disposed above the substrate 101. The buried layer 103 is, for example, a doped region disposed in one of the substrate 101 and the epitaxial layer 102, or a semiconductor layer disposed between the substrate 101 and the epitaxial layer 102.

[0079] The substrate 101 and the epitaxial layer 102 have a first doping type, respectively, and the buried layer 103 has a second doping type opposite to the first doping type. For example, when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type. In one embodiment, an ion implantation process is used to implant a dopant of the second doping type into the substrate 101. By selecting a high dose of dopant, a portion of the substrate 101 is inverted to form a doped region of the second doping type, thereby forming a buried layer 103 of the second doping type in the substrate 101, and then, epitaxial growth is performed on the substrate 101 to form the epitaxial layer 102.

[0080] In one embodiment, by selecting the energy of ion implantation, the buried layer 103 extends downward from the surface of the substrate 101 by a predetermined distance, and further, the epitaxial layer 102 is formed by epitaxial growth on the surfaces of the substrate 101 and the buried layer 103. In another embodiment, by selecting the energy of ion implantation, the buried layer 103 is located below the surface of the substrate 101 and extends downward by a predetermined distance, and further, the epitaxial layer 102 is formed by epitaxial growth on the surface of the substrate 101. The embodiments of the present disclosure are not strictly limited to this. The epitaxial layer 102 can be used to form different device regions. The embodiments of the present disclosure are not strictly limited to this. The buried layer 103 can be a doped region disposed in one of the substrate 101 and the epitaxial layer 102.

[0081] In one embodiment, the buried layer 103 may have a blanket structure, which has substantially the same horizontal extension as the substrate 101 and is laid flat on the substrate 101. In another embodiment, the buried layer 103 may have a patterned structure. The embodiments of the present disclosure are not strictly limited to this. The epitaxial layer 102 may be used to form different device regions.

[0082] like Figure 3bAs shown, a first trench TR1 and a first portion TR2-1 of a second trench are formed by a trench etching process. The first trench TR1 extends downward from the surface of the epitaxial layer 102, and reaches the interior of the buried layer 103 after penetrating the epitaxial layer 102. The first portion TR2-1 of the second trench extends downward from the surface of the epitaxial layer 102, and reaches the bottom of the buried layer 103 after penetrating the epitaxial layer 102.

[0083] The trench etching process includes forming a hard mask HM1 by patterning, and removing exposed portions of the epitaxial layer 102 and the buried layer 103 by etching through openings in the hard mask HM1. The hard mask HM1 includes, for example, a protective stack composed of a plurality of oxide and / or nitride layers.

[0084] In one embodiment, the step of forming the hard mask HM1 includes: growing a first oxide layer HM11 on the surface of the epitaxial layer 102; depositing a nitride layer HM12 on the first oxide layer HM11; depositing a second oxide layer HM13 on the nitride layer HM12; and patterning the protective stack to form the hard mask HM1. In other embodiments, the hard mask HM1 may have other structures, which are not strictly limited by the embodiments of the present disclosure. In one embodiment, patterning the protective stack includes: forming a resist mask on the protective stack, patterning the resist mask for the first time using photolithography, etching and removing the exposed portion of the hard mask HM1 through the patterned resist mask for the second patterning, and then removing the resist mask by solvent dissolution or ashing. In other embodiments, the patterning of the hard mask HM1 may use other processes, which are not strictly limited by the embodiments of the present disclosure.

[0085] Next, anisotropic etching, for example, plasma etching, is used to remove the exposed portions of the epitaxial layer 102 and the buried layer 103 in a direction perpendicular to the substrate surface. The epitaxial layer 102 and the buried layer 103 are etched through the patterned hard mask HM1, and the patterns of the first trench TR1 and the first portion TR2-1 of the second trench are transferred from the hard mask HM1 to the epitaxial layer 102 and the buried layer 103. Since the depths of the first trench TR1 and the first portion TR2-1 of the second trench are relatively large, the plasma etching of the first trench TR1 and the first portion TR2-1 of the second trench requires a relatively large amount of energy and a relatively long time, which damages the trench sidewalls and may result in a large number of silicon lattice defects on the exposed surfaces of the epitaxial layer 102 and the buried layer 103 on the trench sidewalls.

[0086] In one embodiment, the opening width of the first trench TR1 is smaller than the opening width of the first portion TR2-1 of the second trench. In the same etching step, the etching depth reached by the first trench TR1 is also smaller than the etching depth reached by the first portion TR2-1 of the second trench. Therefore, the first trench TR1 and the first portion TR2-1 of the second trench are formed simultaneously using a common trench etching process. In one embodiment, the opening size of the first portion TR2-1 of the second trench is, for example, 1.0um~2.0um, preferably 1.4um~1.5um.

[0087] In other embodiments, the first portion TR2 - 1 of the second trench may also reach the inside of the substrate 101 after penetrating the epitaxial layer 102 and the buried layer 103 . In other words, the first portion TR2 - 1 of the second trench at least reaches the bottom of the buried layer 103 .

[0088] Although not shown in the figure, it should be known that the step of forming a sacrificial oxide layer may also be included. Specifically, for example, a thermal oxidation process is used to form a sacrificial oxide layer at the bottom and sidewall of the first trench TR1 and the first part TR2-1 of the second trench. The thickness of the sacrificial oxide layer is generally 100 angstroms to 300 angstroms. Then, a wet etching process is used to remove the sacrificial oxide layer. In one embodiment, the etchant for wet etching is, for example, diluted hydrofluoric acid (DHF). The above steps of forming a sacrificial oxide layer and etching the sacrificial oxide layer can repair the damage to the sidewalls of the trenches caused when the epitaxial layer 102 and the buried layer 103 are deeply etched to form the trenches, and at the same time, the opening size of the first trench TR1 and the first part TR2-1 of the second trench can be increased.

[0089] Further, see Figure 3c , an insulating liner 11 is formed in the first trench TR1 , an outermost insulating layer 3101 is formed in the first portion TR2 - 1 of the second trench, and an opening is formed at the bottom of the insulating liner 11 and the outermost insulating layer 3101 .

[0090] The above-mentioned insulating liner 11 and the outermost insulating layer 3101 are composed of oxide or nitride, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. In the present embodiment, the insulating liner 11 and the outermost insulating layer 3101 are composed of oxide, for example, an oxide layer is formed at the bottom and sidewall of the first trench TR1 and the first part TR2-1 of the second trench by a thermal oxidation process, and the oxide can further repair the damage to the sidewall of the trench caused when the epitaxial layer 102 and the buried layer 103 are deeply etched to form the trench. The thickness of the insulating liner 11 and the outermost insulating layer 3101 is generally 300 angstroms to 1000 angstroms. In one embodiment, the thickness of the insulating liner 11 and the outermost insulating layer 3101 is, for example, 500 angstroms.

[0091] Next, anisotropic etching, for example, plasma etching, is used, and the hard mask HM1 is still used for shielding to remove the exposed portions of the insulating liner 11 and the outermost insulating layer 3101 in a direction perpendicular to the substrate surface. The portions of the insulating liner 11 and the outermost insulating layer 3101 located on the sidewall and the bottom of the trench are etched at the same time. The portions of the insulating liner 11 and the outermost insulating layer 3101 located on the sidewall of the trench serve as an additional hard mask, together with the hard mask HM1, to define the pattern of the portions of the insulating liner 11 and the outermost insulating layer 3101 located at the bottom of the trench. By controlling the etching time, the exposed portions of the insulating liner 11 and the outermost insulating layer 3101 located at the bottom of the trench can be completely removed to form an opening. At this time, the portions of the outermost insulating liner 11 and the outermost insulating layer 3101 located on the sidewall of the trench are also etched back, but the portions located on the sidewall of the trench are still completely retained. During the etching process, the second oxide layer HM13 in the hard mask HM1 loses a certain thickness, but still has a certain thickness left.

[0092] See also Figure 3d , a conductive layer 1001 is deposited, and the conductive layer 1001 fills the inner space and the bottom opening of the first trench TR1 and the first portion TR2 - 1 of the second trench.

[0093] The conductive layer 1001 contacts the buried layer 103 via the opening at the bottom of the first trench TR1. The conductive layer 1001 has the same doping type as the buried layer 103 and a higher doping concentration. The conductive layer 1001 in the first trench TR1 forms a low resistance path of the buried layer 103. Inside the first trench TR1, the conductive layer 1001 is separated from the epitaxial layer 102 and the buried layer 103 by a liner 1101. Inside the first portion TR2-1 of the second trench, the conductive layer 1001 is separated from the epitaxial layer 102 and the buried layer 103 by an insulating layer 3101. Outside the first trench TR1 and the first portion TR2-1 of the second trench TR2, the conductive layer 1001 covers the surface of the hard mask HM1 and fills the opening of the hard mask HM1. In one embodiment, the conductive layer 1001 includes polysilicon with a second doping type. Other types of conductive layers 1001 are also feasible.

[0094] See also Figure 3e By removing the conductive layer 1001 on the surface of the hard mask HM1 and part of the conductive layer 1001 in the opening of the hard mask HM1, a conductive core 12 is formed in the first trench TR1, and a dummy conductive core 12a is formed in the first portion TR2-1 of the second trench.

[0095] In one embodiment, one or more protective layers in the hard mask HM1 are used as stop layers, and chemical mechanical polishing (CMP) is used to remove the portion of the conductive layer 1001 located on the surface of the hard mask HM1 to expose the surface of the hard mask HM1; after the above-mentioned chemical mechanical planarization, one or more protective layers in the hard mask HM1 are continued to be used as stop layers to etch back the conductive layer 1001 filling the opening of the hard mask HM1 to remove a portion of the conductive layer 1001 in the opening of the hard mask HM1, thereby forming a conductive core 12 in the first trench TR1 and forming a dummy conductive core 12a in the first portion TR2-1 of the second trench. In another embodiment, one or more protective layers in the hard mask HM1 are used as stop layers to etch the conductive layer 1001 and remove portions of the surface of the hard mask HM1 to expose the surface of the hard mask HM1; then, one or more protective layers in the hard mask HM1 are used as stop layers to etch back the conductive layer 1001 filling the opening of the hard mask HM1 to remove portions of the conductive layer 1001 in the opening of the hard mask HM1, thereby forming a conductive core 12 in the first trench TR1 and forming a dummy conductive core 12a in the first portion TR2-1 of the second trench.

[0096] Through the above steps, the tops of the conductive core 12 of the first trench TR1 and the dummy conductive core 12a in the first portion TR2-1 of the second trench are flush with the top of the nitride layer HM12 in the hard mask HM1, respectively.

[0097] See also Figure 3f By removing the second oxide layer HM13 in the hard mask HM1, the top of the remaining hard mask HM1 is flush with the top of the conductive core 12 of the first trench TR1 and the dummy conductive core 12a in the first portion TR2-1 of the second trench. The surface of the remaining hard mask HM1 is the nitride layer HM12.

[0098] In the above steps, for example, a wet etching process is used to remove the second oxide layer HM13 in the hard mask HM1 , and the etchant of the wet etching is, for example, diluted hydrofluoric acid (DHF) or buffered oxide etchant (BOE).

[0099] See also Figure 3g , an insulating layer HM14 is deposited, and the insulating layer HM14 covers the surface of the hard mask HM1 and the surfaces of the conductive core 12 and the dummy conductive core 12a. In the figure, the HM14 and the hard mask HM1 are integrally shown as a hard mask HM2.

[0100] The insulating layer HM14 is composed of oxide or nitride, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. In one embodiment, the insulating layer HM14 is, for example, a nitride layer with a thickness of, for example, 100 angstroms to 1000 angstroms.

[0101] See also Figure 3h , a third trench TR3, a fourth trench TR4 and a second portion TR2-2 of the second trench are formed by a trench etching process. The third trench TR3 extends downward from the surface of the epitaxial layer 102, and reaches the interior of the substrate 101 after penetrating the epitaxial layer 102 and the buried layer 103. The fourth trench TR4 is aligned with the second trench TR2, extends in the dummy conductive core 12a in the second trench TR2, and the fourth trench TR4 passes through the dummy conductive core 12a of the second trench TR2, and continues to extend downward into the substrate 101, forming the second portion TR2-2 of the second trench.

[0102] The above-mentioned trench etching process includes forming a patterned resist mask on the surface of the hard mask HM2, and the patterned resist mask includes patterns for forming the third trench TR3 and the fourth trench TR4; then, etching the hard mask HM2, the epitaxial layer 102, the buried layer 103 and the substrate 101 through the resist mask, transferring the pattern of the third trench TR3 to the epitaxial layer 102, the buried layer 103 and the substrate 101, and transferring the pattern of the fourth trench TR4 to the dummy conductive core 12a in the second trench TR2.

[0103] In one embodiment, the opening width of the third trench TR3 is greater than the opening width of the fourth trench TR4. In the same etching step, the etching depth reached by the third trench TR3 is greater than the etching depth reached by the fourth trench TR4, so the third trench TR3 and the fourth trench TR4 are formed simultaneously by a common trench etching process. Further, generally, the etching rate of the pseudo conductive core 12a (polysilicon) is greater than the etching rate of the epitaxial layer 102 (silicon), the buried layer 103 (silicon) and the substrate 101 (silicon), so that, although the fourth trench TR4 has a smaller opening width, the fourth trench TR4 can pass through the pseudo conductive core 12a of the second trench TR2 and continue to extend downward into the substrate 101 to form the second portion TR2-2 of the second trench connected to the first portion of the second trench TR2. That is, the fourth trench TR4 is located in the pseudo conductive core 12a, and the second portion TR2-2 of the second trench is located in the substrate 101. The first portion TR-1 of the second trench and the second portion TR2-2 of the second trench together constitute the second trench TR2.

[0104] In one embodiment, the opening width of the fourth trench TR4 is smaller than the opening width of the second trench TR2, and smaller than the width of the dummy conductive core 12a in the second trench TR2, so that the dummy conductive core 12a is retained on the sidewall of the fourth trench TR4. In one embodiment, the thickness of the remaining dummy conductive core 12a on the sidewall of the fourth trench TR4 is, for example, 2000 angstroms to 2500 angstroms. The second portion TR2-2 of the second trench has the same opening width as the fourth trench TR4, so the opening width of the second portion TR2-2 of the second trench is smaller than the opening width of the first portion TR2-1 of the second trench.

[0105] See also Figure 3i , an outermost insulating layer 2101 is formed in the third trench TR3, an intermediate insulating layer 3102 is formed in the first portion TR2-1 of the second trench, and an insulating liner 31b is formed in the second portion TR2-2 of the second trench.

[0106] In one embodiment, the outermost insulating layer 2101, the intermediate insulating layer 3102 and the insulating liner 31b are oxide layers formed by thermal oxidation, such as silicon oxide. In another embodiment, the outermost insulating layer 2101 is an oxide layer or a nitride layer formed by chemical vapor deposition, and the intermediate insulating layer 3102 and the insulating liner 31b are oxide layers formed by thermal oxidation. The outermost insulating layer 2101 in the third trench TR3 can repair the damage to the trench sidewall caused when the epitaxial layer 102, the buried layer 103 and the substrate 101 are deeply etched to form the trench, so as to facilitate the deposition of the intermediate insulating layer thereon. In the fourth trench TR4, all the dummy conductive cores 12a are oxidized and converted into the intermediate insulating layer 3102, so that it covers the outermost insulating layer 3101 in the first part TR2-1 of the second trench, and together with the outermost insulating layer 3101 in the first part TR2-1 of the second trench, it forms an insulating liner 31a to improve the isolation performance. In the second part TR2-2 of the second trench, the substrate 101 on its side wall is oxidized and converted into an insulating pad 31b, which covers the side wall and bottom of the second part TR2-2 of the second trench and can repair the damage to the side wall of the trench caused when the substrate 101 is deeply etched to form the trench.

[0107] Further, the oxidation rate of the pseudo conductive core 12a (polysilicon) of the fourth trench TR4 is higher than that of the substrate 101 (silicon) of the second portion TR2-2 of the second trench, so the thickness of the intermediate insulating layer 3102 is greater than that of the insulating liner 31b. In particular, at the junction of the fourth trench TR4 and the second portion TR2-2 of the second trench, the oxidation rate of the conductive core 12a (polysilicon) is higher, so that a thicker intermediate insulating layer 3102 is formed at the junction of the fourth trench TR4 and the second portion TR2-2 of the second trench. The thicker intermediate insulating layer 3102 formed at the junction of the fourth trench TR4 and the second portion TR2-2 of the second trench further limits the oxidation rate of the substrate 101 of the second portion TR2-2 of the second trench, and after the intermediate insulating layer 3102 and the insulating liner 31b are formed, the opening size of the fourth trench TR4 is smaller than the opening size of the second portion TR2-2 of the second trench.

[0108] See also Figure 3j , an insulating layer 1003 is deposited to cover the surface of the hard mask HM2. Since the opening widths of the third trench TR3 and the fourth trench TR4 are different, the insulating layer 1003 forms a conformal layer covering the sidewalls and bottom of the third trench TR3, and forms a filling layer filling the inner space of the third trench TR4.

[0109] The insulating layer 1003 is composed of an oxide or a nitride, such as silicon oxide or silicon nitride. Other types of insulating layers are also feasible. In a preferred embodiment, TEOS is used as a precursor source, and chemical vapor deposition is used to form a silicon oxide layer as the insulating layer 1003. By controlling the process parameters of the chemical vapor deposition, the desired insulating layer thickness can be obtained, so that the thickness of the insulating layer can just close the opening of the fourth trench TR4, but is not enough to close the opening of the third trench TR3.

[0110] In this step, due to the characteristics of chemical vapor deposition, the insulating layer 1003 will preferentially close the opening of the second portion TR-2 of the second trench, and an air gap 33b is formed in the insulating layer 1003 in the second portion TR-2 of the second trench. Since the dielectric constant of air is smaller than that of the dielectric material, the air gap 33b is used to reduce the equivalent dielectric constant of the insulating core 32, thereby further reducing the parasitic capacitance of the semiconductor device introduced by the deep trench isolation. At the same time, due to the formation of the air gap 33b, the stress generated by the insulating layer 1003 is reduced. Further, in the case where the opening of the fourth trench TR4 is closed, an air gap 33a may also be formed in the insulating layer 1003 in the fourth trench TR4.

[0111] See also Figure 3k, part of the insulating layer 1003 is removed, an insulating layer core 32 is formed in the first portion TR2-1 of the second trench and the second portion TR-2 of the second trench, and an intermediate insulating layer 2102 exposing the substrate 101 is formed in the third trench TR3.

[0112] Anisotropic etching, for example, plasma etching, is used, and the hard mask HM2 is still used for shielding, and the exposed portion of the insulating layer 1003 is removed in a direction perpendicular to the substrate surface. The anisotropic etching completely removes the portion of the insulating layer 1003 located on the hard mask HM2, so that the portion of the insulating layer 1003 located inside the second trench TR2 forms the insulating core 32, and the portion of the insulating layer 1003 located inside the third trench TR3 forms the intermediate insulating layer 2102 of the insulating liner. In the second trench TR2, a portion of the insulating core 32 is also etched. In the third trench TR3, a portion of the intermediate insulating layer 2102 of the insulating liner is also etched. The portion of the outermost insulating layer 2101 and the intermediate insulating layer 2102 of the liner 21 located on the sidewall of the third trench TR3 serves as an additional hard mask, and together with the hard mask HM2, is used to define the pattern of the portion of the outermost insulating layer 2101 and the intermediate insulating layer 2102 located at the bottom of the third trench TR3. By controlling the etching time, the exposed portions of the outermost insulating layer 2101 and the intermediate insulating layer 2102 at the bottom of the trench can be completely removed, thereby forming an opening exposing the substrate 101 in the third trench TR3.

[0113] Next, an additional resist mask is used, and the opening pattern of the resist mask exposes the region of the second trench TR2. Anisotropic etching, for example, plasma etching, is used, and the resist mask is used for masking, and the exposed portion of the mask HM2 is removed in a direction perpendicular to the substrate surface, thereby forming an opening in the second trench TR2 that exposes the insulating liner 31 and the insulating core 32 in the second trench TR2.

[0114] In a preferred embodiment, after forming an opening in the third trench TR3 to expose the substrate 101, ion implantation may be performed on the exposed portion of the substrate 101 through the opening, thereby forming a doping region 101a of the first doping type at the bottom of the third trench TR3. The doping type of the doping region 101a is the same as that of the substrate 101, and the doping concentration is higher than that of the substrate 101. In the final semiconductor device, the doping region is used as a contact region, and its function is to reduce the contact resistance between the conductive channel to be formed and the substrate 101.

[0115] Further, see Figure 3l , a conductive layer 1002 is deposited, and the conductive layer 1002 fills the inner space of the third trench TR3 and the top opening of the second trench TR2.

[0116] In this step, the conductive layer 1003 contacts the substrate 101 via the opening at the bottom of the third trench TR3. The conductive layer 1003 has the same doping type as the substrate 101 and a higher doping concentration, thereby forming a low resistance path of the substrate 101. Inside the third trench TR3, the conductive layer 1003 is separated from the epitaxial layer 102, the buried layer 102 and the substrate 101 by the outermost insulating layer 2101 and the intermediate insulating layer 2102. Outside the third trench TR3, the conductive layer 1002 covers the surface of the hard mask HM2. In one embodiment, the conductive layer 1002 includes polysilicon with a first doping type. Other types of conductive layers 1002 are also feasible.

[0117] Further, by removing a portion of the conductive layer 1002 located outside the third trench TR3 , a conductive core 22 is formed in the third trench TR3 .

[0118] In one embodiment, one or more protective layers in the hard mask HM2 are used as stop layers, and chemical mechanical polishing (CMP) is used to remove the portion of the conductive layer 1002 located outside the third trench TR3. In another embodiment, one or more protective layers in the hard mask HM2 are used as stop layers, and the conductive layer 1002 is etched to remove the portion of the conductive layer 1002 located outside the third trench TR3, and the portion of the conductive layer 1002 located inside the third trench TR3 and the portion at the top of the second trench TR2 are etched back. In yet another embodiment, after the above-mentioned chemical mechanical planarization, the portion of the conductive layer 1002 located inside the third trench TR3 and the portion at the top of the second trench TR2 are etched back. The portion of the conductive layer 1003 located in the third trench TR3 is retained to form the conductive core 22.

[0119] In a preferred embodiment, in the above-mentioned planarization step and etching back step, the portion of the conductive layer 1002 located in the top opening of the second trench TR2 is completely removed.

[0120] Next, the hard mask HM2 is removed by, for example, wet etching. In one embodiment, the etchant of the wet etching is, for example, a phosphoric acid (H 3 PO 4 ) solution.

[0121] Combination of the above Figure 3a to Figure 3l The invention describes a method for manufacturing an isolation structure of a semiconductor device, wherein the method comprises a first conductive channel 10 and a second conductive channel 20 in a peripheral region 120 of a semiconductor device 300, and a deep trench isolation 30, wherein the deep trench isolation 30 is located between the first conductive channel 10 and the second conductive channel 20.

[0122] The first conductive channel 10 extends from the surface of the epitaxial layer 102 to the interior of the buried layer 103. The first conductive channel 10 includes a conductive core 12 and an insulating liner 11 surrounding the conductive core 12. The first conductive channel 10 is used to provide an electrical connection path from the buried layer 103 to the surface of the epitaxial layer 102. The second conductive channel 20 extends from the surface of the epitaxial layer 102 to the bottom of the buried layer 103 and reaches the interior of the substrate 101. The second conductive channel 20 includes a conductive core 22 and an insulating liner 21 surrounding the conductive core 22. The second conductive channel provides an electrical connection path from the substrate 101 to the surface of the epitaxial layer 102. The deep trench isolation 30 includes an insulating core 32 and an insulating liner 31 surrounding the insulating core 32.

[0123] After the above-mentioned method for manufacturing the isolation structure of the semiconductor device, the active region structure of the transistor is formed in the core region of the semiconductor device according to known processes and steps, so as to obtain the complete structure of the final semiconductor device.

[0124] According to the method for manufacturing the isolation structure of the semiconductor device of the present embodiment, the insulating liner 31 in the deep trench isolation 30 is formed on the sidewall and a part of the bottom of the trench. The insulating core 32 fills the trench, that is, extends from the surface of the epitaxial layer 102 to the bottom of the trench. The insulating liner 31 and the insulating core 32 of the deep trench isolation 30 form a composite insulating layer to improve the isolation performance. Compared with the existing semiconductor device isolation structure, in the semiconductor device isolation structure disclosed in the present invention, the insulating liner 31 is used as a conformal layer in the trench, which can be used to repair the damage to the sidewall of the trench when the epitaxial layer 102 is deeply etched to form the trench, thereby reducing the crystal defects and / or dislocation defects at the silicon / silicon oxide interface. The insulating core 32 is used as a filling layer in the trench, which can reduce stress on the one hand, and on the other hand, it can reduce the parasitic capacitance introduced by the semiconductor device due to the deep trench isolation. Therefore, the semiconductor device disclosed in the present invention adopts the above-mentioned improved isolation structure process to block the vertical flow path of the leakage current between the well region and the buried layer of the transistor, thereby reducing the power consumption of the semiconductor device and improving the reliability of the semiconductor device.

[0125] Further, the first conductive channel 10, the deep trench isolation 30, and the second conductive channel 20 are formed in the first trench, the second trench, and the third trench, respectively. In a preferred embodiment, by selecting the same opening width of the first conductive channel 10 and the deep trench isolation 30, a common trench etching process can be used to simultaneously form the first trench extending into the buried layer 103 and the second trench extending to the bottom of the buried layer 103. This can not only reduce the process steps and the number of masks for manufacturing the isolation structure, but also avoid the depth deviation of the first conductive channel 10 and the first deep trench isolation 30 caused by the independent etching steps, thereby reducing the manufacturing cost of the semiconductor device and improving the yield of the semiconductor device.

[0126] Furthermore, the insulating liner in the deep trench isolation 30 is a stack of multiple insulating layers, the outermost insulating layer of the multiple insulating layers is located on the trench sidewall, and at least one intermediate insulating layer is located between the outermost insulating layer and the insulating core 32. The insulating liner uses a stack of multiple insulating layers to improve the isolation performance of the deep trench isolation 30, thereby improving the reliability of the semiconductor device.

[0127] In a preferred embodiment, after forming an outer insulating layer of an insulating pad in the second trench, sacrificial polysilicon is then filled in the second trench, and a fourth trench is formed by deep etching of the sacrificial polysilicon. Compared with forming a deep trench isolation directly in the fourth trench penetrating the epitaxial layer, the aspect ratio of the second trench is relatively reduced. Therefore, the etching time experienced by the epitaxial layer is shortened, which is beneficial to reducing damage to the epitaxial layer. The deep trench etching of the fourth trench is carried out in the sacrificial polysilicon and will not cause any damage to the epitaxial layer. Therefore, the crystal defects and / or dislocation defects at the silicon / silicon oxide interface can be significantly reduced, thereby suppressing the leakage current caused by the first deep trench isolation in the semiconductor device.

[0128] Furthermore, in the step of forming deep trench isolation, the sacrificial polysilicon in the second trench is formed by a deposition step shared with the first conductive channel, and the fourth trench in the second trench is formed by a trench etching process shared with the second conductive channel. This can ensure that the isolation structure of the semiconductor device disclosed in the present invention is compatible with the process of the existing isolation structure, and will not increase the number of process steps and masks of the isolation structure. Therefore, while improving the isolation characteristics of the first deep trench isolation structure, it will not significantly increase the manufacturing cost of the semiconductor device.

[0129] In a preferred embodiment, by selecting the opening width of the fourth trench to be smaller than the opening width of the second conductive channel, a common trench etching process can be used to simultaneously form the third trench and the fourth trench, and the fourth trench is made to extend downward into the substrate to form the second portion of the second trench. This can not only reduce the number of process steps and masks for manufacturing the isolation structure, but also avoid the depth deviation of the second conductive channel and the deep trench isolation caused by the independent etching steps, thereby reducing the manufacturing cost of the semiconductor device and improving the yield of the semiconductor device.

[0130] The embodiments of the present disclosure are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, according to the above description, many modifications and changes can be made, including but not limited to changes in the local structure of the circuit, and replacement of the type or model of components. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can make good use of the present disclosure and the modified use based on the present disclosure. The present disclosure is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, comprising: substrate; an epitaxial layer located on the substrate; a buried layer located between at least one or both of the substrate and the epitaxial layer; as well as a first conductive path extending from the surface of the epitaxial layer into the buried layer; a second conductive channel extending from the surface of the epitaxial layer into the substrate; as well as A deep trench isolation is located between the first conductive channel and the second conductive channel, and the deep trench isolation extends from the surface of the epitaxial layer into the substrate. The deep trench isolation includes an insulating core and an insulating liner surrounding the insulating core, the deep trench isolation is arranged in a second trench, the second trench includes a first part located in the epitaxial layer and the buried layer and a second part located in the substrate, and the insulating core in the second part has an air gap.

2. The semiconductor device according to claim 1, wherein The opening size of the first portion of the second groove is larger than the opening size of the second portion thereof.

3. The semiconductor device according to claim 2, wherein: The insulating pad comprises: a first insulating liner covering a sidewall of a first portion of the second trench; and a second insulating liner covering a bottom and sidewalls of a second portion of the second groove; The first portion of the second groove forms a first insulating pad and then forms a first cavity, the second portion of the second groove forms a second insulating pad and then forms a second cavity, and the opening size of the first cavity is smaller than the opening size of the second cavity; The insulating core fills the first cavity and the second cavity.

4. The semiconductor device according to claim 3, wherein: The first insulating liner comprises a first outermost insulating layer and a first intermediate insulating layer stacked, the first outermost insulating layer is in contact with the epitaxial layer and the buried layer; the second insulating liner comprises a single-layer insulating layer, the single-layer insulating layer is in contact with the substrate; Wherein, the thickness of the second insulating pad is smaller than the thickness of the first intermediate insulating layer.

5. The semiconductor device according to claim 1, wherein The insulating core in the first portion has an air gap therein.

6. The semiconductor device according to claim 5, wherein: An opening size of the air gap in the first portion is smaller than an opening size of the air gap in the second portion.

7. The semiconductor device according to claim 1, wherein The first conductive path includes a first conductive core and a second insulating pad surrounding the first conductive core, the second insulating pad has an opening at the bottom, and the first conductive core contacts the buried layer via the opening at the bottom of the second insulating pad.

8. The semiconductor device according to claim 1, wherein the second conductive channel comprises a second conductive core and a third insulating liner surrounding the second conductive core, the second insulating liner has an opening at the bottom, and the second conductive core contacts the substrate via the opening at the bottom of the third insulating liner.

9. The semiconductor device according to claim 1, wherein: The semiconductor device is a semiconductor device selected from any one of a power integrated circuit, a CMOS integrated circuit, and an analog-digital hybrid integrated circuit.

10. A deep trench isolation structure for a semiconductor device, the semiconductor device comprising: substrate; an epitaxial layer located on the substrate; a buried layer located between at least one or both of the substrate and the epitaxial layer; The deep trench isolation extends from the surface of the epitaxial layer into the substrate, Wherein, the deep trench isolation includes an insulating core and an insulating pad surrounding the insulating core, the deep trench isolation is arranged in a second trench, the second trench includes a first part located in the epitaxial layer and the buried layer and a second part located in the substrate, the insulating core in the second part has an air gap, and the insulating core in the first part has an air gap.

11. The deep trench isolation structure according to claim 10, wherein: The opening size of the first portion of the second groove is larger than the opening size of the second portion thereof.

12. The deep trench isolation structure according to claim 11, wherein: The insulating pad comprises: a first insulating liner covering a sidewall of a first portion of the second trench; and a second insulating liner covering a bottom and sidewalls of a second portion of the second groove; The first portion of the second groove forms a first insulating pad and then forms a first cavity, the second portion of the second groove forms a second insulating pad and then forms a second cavity, and the opening size of the first cavity is smaller than the opening size of the second cavity; The insulating core fills the first cavity and the second cavity.

13. The deep trench isolation structure according to claim 12, wherein: The first insulating liner comprises a first outermost insulating layer and a first intermediate insulating layer stacked, the first outermost insulating layer is in contact with the epitaxial layer and the buried layer; the second insulating liner comprises a single-layer insulating layer, the single-layer insulating layer is in contact with the substrate; Wherein, the thickness of the second insulating pad is smaller than the thickness of the first intermediate insulating layer.

14. The deep trench isolation structure according to claim 10, wherein: An opening size of the air gap in the first portion is smaller than an opening size of the air gap in the second portion.

15. A method for manufacturing an isolation structure of a semiconductor device, comprising: forming an epitaxial layer on a substrate; forming a buried layer between at least one or both of the substrate and the epitaxial layer; forming a first trench and a first portion of a second trench, wherein the first trench extends from a surface of the epitaxial layer into the buried layer, and the first portion of the second trench extends from the surface of the epitaxial layer to at least a bottom of the buried layer; forming a first conductive path in the first trench, and forming a first outermost insulating layer and a dummy conductive core on an upper portion of the second trench; forming a third trench, a fourth trench, and a second portion of the second trench, wherein the third trench extends from a surface of the epitaxial layer to the substrate; The fourth trench is aligned with the second trench and extends in the dummy conductive core in the second trench. The fourth trench passes through the dummy conductive core of the second trench and continues to extend downward into the substrate to form a second portion of the second trench. forming a second conductive channel in the third trench, and forming a deep trench isolation in the second trench; The deep trench isolation includes an insulating core and an insulating liner surrounding the insulating core, and an air gap is provided in the insulating core in the second portion.

16. The method according to claim 15, wherein: The opening size of the first portion of the second groove is larger than the opening size of the second portion thereof.

17. The method according to claim 16, wherein: The method of forming a second conductive channel in the third trench and forming a deep trench isolation in the second trench comprises: forming a second outermost insulating layer in the third trench, forming a first intermediate insulating layer in a first portion in the second trench, and forming a second insulating liner in a second portion of the second trench, the first outermost insulating layer in the first portion of the second trench and the first intermediate insulating layer constituting a first insulating liner; A second intermediate insulating layer is formed in the third trench, and an insulating core is formed in the second trench, wherein the second intermediate insulating layer conformally covers the bottom and sidewalls of the third trench and the second outermost insulating layer constitute a third insulating liner of the second conductive path, and the insulating core in the second trench fills the second trench; forming an opening penetrating the third insulating pad at the bottom of the third groove; as well as A second conductive core is formed in the third trench, the second conductive core contacting the substrate.

18. The method according to claim 17, wherein: A first cavity is formed after a first insulating pad is formed in the first portion of the second groove, and a second cavity is formed after a second insulating pad is formed in the second portion of the second groove, wherein an opening size of the first cavity is smaller than an opening size of the second cavity; In the second groove, the insulating core preferentially closes the opening of the second cavity, and an air gap is formed in the insulating core in the second cavity.

19. The method according to claim 18, wherein: An air gap is formed in the insulating core in the first portion.

20. The method according to claim 19, wherein: An opening size of the air gap in the first portion is smaller than an opening size of the air gap in the second portion.

21. The method according to claim 15, wherein: The first trench and the first portion of the second trench are formed through a same step.

22. The method according to claim 15, wherein: The third trench, the fourth trench, and the second portion of the second trench are formed through a same step.

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