Gallium nitride epitaxial wafer using buried layer type silicon substrate and preparation method thereof

Abstract

The invention discloses a gallium nitride epitaxial wafer using a buried layer type silicon substrate and a preparation method of the gallium nitride epitaxial wafer, and belongs to the technical field of semiconductor materials, the buried layer type silicon substrate sequentially comprises a surface layer, a buried layer and a base layer from top to bottom, the surface layer is made of silicon, and the thickness of the surface layer is 1-2000 nm; the buried layer is made of a silicon oxide insulating material, and the thickness of the buried layer is 1-50 microns; the base layer is made of silicon, the thickness of the base layer ranges from 50 micrometers to 1500 micrometers, and nitriding treatment is carried out on the surface layer before the aluminum nitride nucleating layer grows on the buried layer type silicon substrate. According to the invention, the problem that the operation loss of the silicon-based gallium nitride power device is obviously increased when the frequency is increased is avoided, the stress problem existing in the silicon-based gallium nitride heteroepitaxy process is improved, and the electric field voltage withstanding characteristic of the gallium nitride epitaxial structure is obviously improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor materials and relates to a gallium nitride epitaxial wafer using a buried silicon substrate and a preparation method thereof. Background Art

[0002] The third-generation semiconductor material gallium nitride has good electrical properties. In addition, its wide bandgap, high breakdown electric field, high thermal conductivity and strong radiation resistance make gallium nitride an ideal material for making high-frequency, high-power, high-temperature, high-voltage and radiation-resistant electronic and optoelectronic devices. However, the epitaxial growth of gallium nitride faces great limitations. This is mainly due to the immaturity of gallium nitride homoepitaxial technology, which leads to the growth of gallium nitride epitaxial layers mainly on heterogeneous substrates. At present, the main substrate materials include sapphire substrates, silicon carbide substrates and silicon substrate materials. Among them, silicon substrate materials have become one of the most popular substrate materials in gallium nitride epitaxial growth due to their low cost, large size, good electrical and thermal conductivity, process optimization and simple design methods.

[0003] However, there is a significant lattice mismatch between the silicon substrate and the gallium nitride material, which poses a severe challenge to device performance. To alleviate this adverse effect, researchers use insulating or high-resistance substrates and implement specific treatments on the silicon substrate to reduce interface switching losses. There are two main methods to effectively reduce the interface switching losses between the substrate and the epitaxial layer: (1) growing a silicon nitride layer on a silicon substrate; (2) improving the crystal quality of the nucleation layer (such as aluminum nitride). Although growing a silicon nitride layer on a silicon substrate can reduce losses by utilizing its insulating properties, the lattice difference between silicon nitride and the nucleation layer can easily lead to the formation of leakage paths, thereby affecting the reliability of the device. On the other hand, although increasing the thickness of the nucleation layer helps to reduce crystal defects and reduce the risk of leakage paths, it also increases the built-in electric field accordingly, which may lead to the formation of low-impedance channels, thereby causing an increase in losses. Therefore, how to effectively reduce losses while ensuring crystal quality remains a major technical problem that needs to be solved in the current research field of gallium nitride power devices. Summary of the invention

[0004] The purpose of the present invention is to overcome the crystal defects and stress problems caused by lattice mismatch between silicon substrate and gallium nitride material, and provide a gallium nitride epitaxial wafer using a buried silicon substrate and a preparation method thereof, which are used to reduce the interface switching loss between the substrate and the epitaxial layer.

[0005] In a first aspect, the present invention provides a gallium nitride epitaxial wafer, comprising a substrate and a gallium nitride epitaxial wafer arranged on the substrate, wherein the substrate comprises a surface layer, a buried layer and a base layer from top to bottom;

[0006] The gallium nitride epitaxial wafer is arranged on the surface layer;

[0007] The material of the surface layer is silicon;

[0008] The material of the buried layer is silicon oxide;

[0009] The material of the base layer is silicon.

[0010] Furthermore, in the substrate described in the present invention, the surface layer has a thickness of 1 to 2000 nm; the buried layer has a thickness of 1 to 50 μm; and the base layer has a thickness of 50 to 1500 μm.

[0011] Furthermore, in the substrate described in the present invention, the lattice arrangement direction of the silicon material of the surface layer is (111); the lattice arrangement direction of the silicon material of the base layer is any one of (001), (110), and (111).

[0012] In a second aspect, the present invention provides a method for preparing a gallium nitride epitaxial wafer, comprising the following steps: preparing a surface silicon substrate, preparing a buried silicon oxide on the surface of the surface silicon substrate by a wet oxidation method; bombarding the surface of the buried silicon oxide with hydrogen ions to form a hydrogen ion layer inside it; bonding the buried silicon oxide to a base silicon substrate by wafer bonding; breaking the hydrogen ion layer by heat treatment, grinding and polishing the cross section to obtain a substrate; and growing a gallium nitride epitaxial wafer after nitriding the surface of the substrate.

[0013] Furthermore, the reaction temperature of the wet oxidation method of the present invention is 800-1300° C., the reaction pressure is 0-50 bar, and the oxidant used in the reaction is a mixed gas of hydrogen and oxygen.

[0014] Furthermore, the hydrogen-oxygen ratio of the mixed gas of the present invention is 0.5 to 5:1.

[0015] Furthermore, the temperature of the heat treatment in the present invention is 400-800°C.

[0016] Furthermore, the nitridation treatment method of the present invention is a MOCVD method.

[0017] Furthermore, the MOCVD method of the present invention comprises: heating the substrate to 800-1400° C. and introducing nitrogen-containing gas for 1-600 seconds;

[0018] The nitrogen-containing gas is ammonia or nitrogen.

[0019] In a third aspect, the present invention provides the use of a gallium nitride epitaxial wafer in the preparation of a gallium nitride power device.

[0020] Compared with the prior art, the technical solution provided by the present invention has at least the following beneficial effects or advantages:

[0021] (1) The present invention absorbs and depletes the carriers in the surface layer through the oxygen atoms inside the silicon oxide buried layer, thereby reducing the leakage current phenomenon and providing a guarantee for the stable operation of the GaN power device. At the same time, the silicon oxide buried layer can suppress the warping problem that occurs during the growth process of the GaN heteroepitaxial structure. By appropriately increasing the thickness of the silicon oxide buried layer, the growth thickness of the GaN epitaxial layer can be increased accordingly, thereby enhancing the pressure resistance performance of the GaN epitaxial structure.

[0022] (2) The present invention controls the thickness of the buried layer to be between 1 μm and 50 μm, and the thickness of the surface layer is limited to the range of 1 nm to 2000 nm. The substrate-epitaxial interface carrier concentration is further reduced by nitriding the surface of the silicon substrate. At the same time, the reduction in the thickness of the surface layer also effectively reduces the intrinsic carriers generated by the silicon material in a high temperature environment, thereby further improving the leakage current problem and significantly improving the overall performance of the gallium nitride device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of the structure of a buried silicon substrate. top is the surface layer of the buried silicon substrate; buried is the buried layer of the buried silicon substrate; base It is the base layer of the buried silicon substrate.

[0024] Figure 2 The present invention is a flow chart for preparing a gallium nitride epitaxial wafer using a buried silicon substrate. DETAILED DESCRIPTION

[0025] The technical scheme of the present invention is described below in conjunction with the embodiments, but the present invention is not limited to the following embodiments. The experimental methods and detection methods described in each embodiment are conventional methods unless otherwise specified; the reagents and materials described are all commercially available unless otherwise specified.

[0026] Example 1

[0027] This embodiment provides a buried silicon substrate.

[0028] like Figure 1 As shown, the structure of the buried silicon substrate described in this embodiment is a surface layer, a buried layer and a base layer from top to bottom. The surface layer material is silicon with a thickness of 1nm to 2000nm; the buried layer material is silicon oxide insulating material with a thickness of 1μm to 50μm; the base layer material is silicon with a thickness of 50μm to 1500μm.

[0029] Example 2

[0030] This embodiment provides a method for preparing a buried silicon substrate.

[0031] The method for preparing the buried silicon substrate described in this embodiment is as follows Figure 2 shown.

[0032] S1: Place a silicon substrate (surface layer) with a lattice direction of (111) in a reaction chamber, raise the temperature of the reaction chamber to 800°C, set the pressure of the reaction chamber to 0 bar, introduce hydrogen and oxygen (hydrogen: oxygen = 0.5:1), and use a wet oxidation method to form a 1μm thick silicon oxide sheet, i.e., a silicon oxide insulating layer, on the surface of the silicon substrate.

[0033] S2: Bombard the surface of the silicon oxide wafer with hydrogen ions to form a hydrogen ion layer inside it.

[0034] S3: The silicon oxide wafer is bonded to a silicon substrate (base layer) having a lattice arrangement direction of (001) and a thickness of 50 μm by wafer bonding.

[0035] S4: Heat to 400°C to break the hydrogen ion layer and remove the excess part.

[0036] S5: Grind and polish the cross section to control the surface thickness to 1 nm, and obtain a buried silicon substrate for gallium nitride epitaxy.

[0037] Example 3

[0038] This embodiment provides a method for preparing a GaN epitaxial wafer on a buried silicon substrate.

[0039] S1: Place a silicon substrate (surface layer) with a lattice direction of (111) in a reaction chamber, raise the temperature of the reaction chamber to 1000°C, set the pressure of the reaction chamber to 10 bar, introduce hydrogen and oxygen (hydrogen: oxygen = 1:1), and use a wet oxidation method to form a 10μm thick silicon oxide sheet, i.e., a silicon oxide insulating layer, on the surface of the silicon substrate.

[0040] S2: Bombard the surface of the silicon oxide wafer with hydrogen ions to form a hydrogen ion layer inside it.

[0041] S3: The silicon oxide wafer is bonded to a silicon substrate (base layer) having a lattice arrangement direction of (110) and a thickness of 500 μm by wafer bonding.

[0042] S4: Heating to 600°C causes the hydrogen ion layer to break and remove the excess.

[0043] S5: Grind and polish the cross section to control the surface thickness to 1000 nm, and obtain a buried silicon substrate for gallium nitride epitaxy.

[0044] Example 4

[0045] This embodiment provides a method for preparing a GaN epitaxial wafer on a buried silicon substrate.

[0046] S1: Place a silicon substrate (surface layer) with a lattice direction of (111) in a reaction chamber, raise the temperature of the reaction chamber to 1300°C, set the pressure of the reaction chamber to 50 bar, introduce hydrogen and oxygen (hydrogen: oxygen = 5:1), and use a wet oxidation method to form a 50μm thick silicon oxide sheet, i.e., a silicon oxide insulating layer, on the surface of the silicon substrate.

[0047] S2: Bombard the surface of the silicon oxide wafer with hydrogen ions to form a hydrogen ion layer inside it.

[0048] S3: The silicon oxide wafer is bonded to a silicon substrate (base layer) having a lattice arrangement direction of (111) and a thickness of 1500 μm by wafer bonding.

[0049] S4: Heating to 800°C causes the hydrogen ion layer to break and remove the excess.

[0050] S5: Grind and polish the cross section to control the surface thickness to 2000 nm, and obtain a buried silicon substrate for gallium nitride epitaxy.

[0051] Example 5

[0052] This embodiment provides a method for preparing a gallium nitride epitaxial wafer using a buried silicon substrate.

[0053] Before the GaN epitaxial growth into the nucleation layer, the surface of the buried silicon substrate is nitrided by MOCVD (metal organic chemical vapor deposition), including: heating the buried silicon substrate to 800-1400°C, and then introducing nitrogen-containing gas for 1-600s, where the nitrogen-containing gas is ammonia or nitrogen, so that nitrogen atoms form bonds with the silicon on the surface, completing the surface nitridation and depleting the surface carriers.

[0054] After the surface nitridation treatment of the buried silicon substrate is completed, the gallium nitride epitaxial layer can be grown using methods such as MOCVD, HVPE (hydride vapor phase epitaxy) and MBE (molecular beam epitaxy).

[0055] The functions of the silicon oxide buried layer described in the present invention are as follows: (1) The silicon oxide buried layer can absorb and deplete the carriers in the surface layer by virtue of the oxygen atoms inside it, thereby reducing the leakage current phenomenon and providing a guarantee for the stable operation of the device. (2) The silicon oxide buried layer can suppress the warping problem that occurs during the growth process of the GaN heteroepitaxial structure. By appropriately increasing the thickness of the silicon oxide buried layer, the growth thickness of the GaN epitaxial layer can be increased accordingly, thereby enhancing the pressure resistance performance of the GaN epitaxial structure.

[0056] In addition, the present invention controls the thickness of the buried layer to be between 1μm and 50μm, and the thickness of the surface layer is limited to the range of 1nm to 2000nm. The substrate-epitaxial interface carrier concentration is further reduced by nitriding the surface of the silicon substrate. At the same time, the reduction in the thickness of the surface layer also effectively reduces the intrinsic carriers generated by the silicon material in a high temperature environment, thereby further improving the leakage current problem and significantly improving the overall performance of the gallium nitride device.

[0057] The embodiments described above are part of the embodiments of the present invention, but not all of them. The detailed description of the embodiments of the present invention is not intended to limit the scope of the invention claimed for protection, but only represents selected embodiments of the present invention. All other embodiments obtained without creative work and related deductions and substitutions made by ordinary technicians in the field under the conditions of the concept of the present invention belong to the scope of protection of the present invention.

Claims

1. A gallium nitride epitaxial wafer, comprising a substrate and a gallium nitride epitaxial wafer arranged on the substrate, characterized in that: The substrate comprises a surface layer, a buried layer and a base layer from top to bottom; The material of the surface layer is silicon; The material of the buried layer is silicon oxide; The material of the base layer is silicon.

2. The gallium nitride epitaxial wafer according to claim 1, characterized in that: The surface layer has a thickness of 1 to 2000 nm; the buried layer has a thickness of 1 to 50 μm; and the base layer has a thickness of 50 to 1500 μm.

3. The gallium nitride epitaxial wafer according to claim 1, characterized in that: The lattice arrangement direction of the silicon material of the surface layer is the (111) crystal plane; the lattice arrangement direction of the silicon material of the base layer is any one of the (001) crystal plane, the (110) crystal plane, and the (111) crystal plane.

4. A method for preparing a gallium nitride epitaxial wafer, characterized in that: The following steps are involved: A surface silicon substrate is prepared, and a buried silicon oxide layer is prepared on the surface of the surface silicon substrate by a wet oxidation method; hydrogen ions bombard the surface of the buried silicon oxide layer to form a hydrogen ion layer inside the buried silicon oxide layer; The buried silicon oxide layer is bonded to the base silicon substrate by wafer bonding; the hydrogen ion layer is broken by heat treatment, and the cross section is ground and polished to obtain the substrate; the surface of the substrate is nitrided and then a gallium nitride epitaxial wafer is grown.

5. The preparation method according to claim 4, characterized in that: The reaction temperature of the wet oxidation method is 800-1300° C., the reaction pressure is 0-50 bar, and the oxidant used in the reaction is a mixed gas of hydrogen and oxygen.

6. The preparation method according to claim 5, characterized in that: The hydrogen-oxygen ratio of the mixed gas is 0.5-5:

1.

7. The preparation method according to claim 4, characterized in that: The temperature of the heat treatment is 400-800°C.

8. The preparation method according to claim 4, characterized in that: The nitridation treatment method is a MOCVD method.

9. The preparation method according to claim 8, characterized in that: The MOCVD method comprises: heating the substrate to 800-1400° C. and introducing nitrogen-containing gas for 1-600 seconds; The nitrogen-containing gas is ammonia or nitrogen.

10. Use of the gallium nitride epitaxial wafer obtained by the preparation method according to any one of claims 4 to 9 in the preparation of gallium nitride power devices.

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