Chip packaging structure, manufacturing method thereof and semiconductor device

Abstract

The invention relates to a chip packaging structure, a manufacturing method thereof and a semiconductor device. The chip packaging structure comprises a packaging substrate and a chip. One side face of the packaging substrate is concaved inwards to form a concave part, and the inner side wall of the concave part is provided with a plurality of protruding parts which are sequentially arranged at intervals in the circumferential direction. The chip is placed in the concave part, the edge outline of the chip is arranged to be in a polygonal shape, and a plurality of side edges of the chip are correspondingly matched with the plurality of protruding parts in an abutting mode respectively. According to the chip packaging structure, the plurality of side edges of the chip placed in the concave part are correspondingly abutted against and matched with the plurality of protruding parts respectively, and the plurality of protruding parts play a role in limiting the chip, so that the chip is stably arranged in the concave part, the corner parts of the chip can be prevented from being in contact with the inner side wall of the concave part, and the chip packaging quality is improved. Therefore, damage or crack defects of the corners of the chip can be avoided, actual effects can be avoided in the chip placement process, the chip placement yield is improved, and the product yield of chip packaging products is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor structures, and in particular to a chip packaging structure and a manufacturing method thereof, and a semiconductor device. Background Art

[0002] In the related technology, chip packaging is the process of assembling integrated circuits into final chip products, that is, the integrated circuit dies produced by the wafer foundry, that is, the wafers from the wafer front-end process are cut into small chips through the dicing process, and placed on a substrate that plays a supporting role. Specifically, they are placed in the cavity of the substrate, and the pins are led out, so that the chip is isolated from the outside world, and the chip and the substrate are fixedly packaged as a whole. The packaged chip is easier to install and transport, and can prevent impurities in the air from corroding the chip circuit and causing a decrease in electrical performance. However, among the defective chip packaging products produced in batches, many chips have damage, cracks and other defects at the corners. Summary of the invention

[0003] Based on this, it is necessary to overcome the defects of the prior art and provide a chip packaging structure and its manufacturing method, and a semiconductor device, which can improve defects such as breakage and cracks at the corners of the chip, thereby improving the product yield of chip packaging products.

[0004] A chip packaging structure, the chip packaging structure comprising:

[0005] A packaging substrate, wherein one side surface of the packaging substrate is concave to form a concave portion, and an inner side wall of the concave portion is provided with a plurality of protrusions arranged in sequence and spaced apart in a circumferential direction; and

[0006] The chip is placed in the concave portion, the edge contour of the chip is set to be polygonal, and the multiple side edges of the chip are respectively abutted and matched with the multiple protrusions.

[0007] In one embodiment, the protrusion is made of the same material as the packaging substrate and is an integrated structure; or, the protrusion is configured as an adhesive and is bonded and cured on the packaging substrate.

[0008] In one embodiment, a distance W between a side surface of the protrusion away from the inner side wall of the recess and the inner side wall of the recess tends to increase in a direction approaching the bottom surface of the recess.

[0009] In one embodiment, the chip is configured as a rectangular chip, and the recess is configured as a rectangular recess; at least one protrusion is provided on the inner side wall of the recess at a position corresponding to each side edge of the chip.

[0010] In one embodiment, the chip is fixedly connected to the bottom surface of the recess through a DAF adhesive layer; or, the chip is solidified on the bottom surface of the recess by printing conductive glue and baking.

[0011] In one embodiment, the chip packaging structure also includes a filling layer, a wiring layer, a solder ball and a protective layer; the filling layer covers the outside of the chip and the top surface of the packaging substrate and fills the recess, the wiring layer is arranged on the filling layer, the protective layer is arranged on the wiring layer, the wiring layer is provided with a first electrical connection part and a second electrical connection part, the first electrical connection part passes through the filling layer and then is connected to the chip, and the second electrical connection part passes through the protective layer and is connected to the solder ball.

[0012] A method for manufacturing a chip packaging structure comprises the following steps:

[0013] Providing a substrate, processing the substrate to form a packaging substrate, wherein one side surface of the packaging substrate is concave to form a concave portion, and the inner side wall of the concave portion is provided with a plurality of protrusions arranged in sequence and spaced apart in a circumferential direction;

[0014] A chip is provided and placed in the concave portion. The edge contour of the chip is set to be polygonal, and multiple side edges of the chip are respectively abutted and matched with the multiple protrusions.

[0015] In one embodiment, the step of processing the substrate to form a packaging substrate includes:

[0016] Disposing a first photoresist layer on the substrate;

[0017] Performing exposure and development processing on the first photoresist layer to expose a first area on the substrate to be etched, wherein the first area includes a preset area on the concave portion other than the convex portion;

[0018] Etching a first region of the substrate to a first preset depth, wherein the first preset depth is less than a thickness of the substrate;

[0019] The substrate after etching is subjected to film stripping treatment to remove the first photoresist layer on the surface of the substrate.

[0020] In one embodiment, the step of processing the substrate to form a packaging substrate includes:

[0021] Disposing a second photoresist layer on the substrate;

[0022] Performing exposure and development processing on the second photoresist layer to expose a second area on the substrate to be etched, wherein the second area includes a preset area of ​​the concave portion;

[0023] Etching a second region of the substrate to a second preset depth, wherein the second preset depth is less than the thickness of the substrate;

[0024] Performing a film stripping treatment on the substrate after the etching treatment to remove the second photoresist layer on the surface of the substrate and obtain the concave portion on the substrate;

[0025] Disposing a protrusion material layer on the substrate;

[0026] The protruding portion material layer is exposed and developed, so that the protruding portion material layer remains on the substrate to have a plurality of solder resist portions, each of which corresponds to a preset area of ​​each protruding portion.

[0027] In one embodiment, after the step of placing the chip in the recess, the manufacturing method further comprises the steps of:

[0028] Filling the concave portion with a fourth solder resist layer, so that the filling layer covers the outside of the chip and the top surface of the packaging substrate and fills the concave portion;

[0029] After the fourth solder resist layer is solidified, a wiring layer is arranged on the fourth solder resist layer, wherein the wiring layer is provided with a first electrical connection portion and a second electrical connection portion, so that the first electrical connection portion penetrates the filling layer and is connected to the chip;

[0030] A protection layer is provided on the wiring layer, so that the second electrical connection portion penetrates through the protection layer and is connected to the solder ball.

[0031] The above-mentioned chip packaging structure and its manufacturing method, and semiconductor device, because the multiple side edges of the chip placed in the recess are respectively abutted against the multiple protrusions, the multiple protrusions play a limiting role on the chip, so that the chip is stably arranged in the recess, which can avoid the corners of the chip from contacting the inner wall of the recess, and can also avoid damage or crack defects at the corners of the chip, that is, it can avoid the occurrence of defects during the chip placement process, thereby improving the chip placement yield, thereby improving the product yield of the chip packaging product. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the structure in which a chip in the related art is placed in a cavity of a packaging substrate.

[0033] Figure 2 It is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.

[0034] Figure 3 It is a structural schematic diagram of a chip in a chip packaging structure according to an embodiment of the present application when the chip rotates.

[0035] Figure 4for Figure 2 The structure shown does not include the chip.

[0036] Figure 5 for Figure 4 Cross-sectional view of the structure at AA.

[0037] Figure 6 for Figure 5 The schematic diagram of the state of placing the chip on the basis of the structure shown.

[0038] Figure 7 It is a cross-sectional structural diagram of a chip packaging structure according to an embodiment of the present application.

[0039] Figure 8 This is a structural diagram of a first photoresist layer disposed on a substrate according to an embodiment of the present application.

[0040] Fig. 9 for Figure 8 Structural diagram of the structure shown after exposure and development.

[0041] Fig.10 for Fig. 9 Cross-sectional view of the structure at BB.

[0042] Fig.11 for Fig. 9 Structural diagram of the structure shown after etching.

[0043] Fig.12 for Fig.11 Cross-sectional structural diagram at CC.

[0044] Fig.13 for Fig.11 The structure shown is a diagram of the structure after leg membrane processing.

[0045] Fig.14 This is a structural diagram of a second photoresist layer disposed on a substrate according to an embodiment of the present application.

[0046] Fig.15 for Fig.14 Structural diagram of the structure shown after exposure and development.

[0047] Fig.16 for Fig.15 A top view of the structure shown.

[0048] Fig.17 for Fig.16 Structural diagram of the structure shown after etching.

[0049] Fig.18 for Fig.17 The structure shown is a leg membrane and a protruding material layer is arranged behind it.

[0050] Fig.19 for Fig.18 Structural diagram of the structure shown during exposure process.

[0051] Fig. 20 for Fig.19 Structural diagram of the structure shown after development processing.

[0052] 110, chip; 120, packaging substrate; 121, chamber;

[0053] 210, packaging substrate; 2101, base; 211, recess; 212, protrusion; 2121, oblique straight surface; 220, chip; 230, DAF bonding layer; 240, filling layer; 250, wiring layer; 251, first electrical connection part; 252, second electrical connection part; 260, solder ball; 270, protective layer; 281, first photoresist layer; 282, second photoresist layer; 283, protrusion material layer. DETAILED DESCRIPTION

[0054] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0055] As described in the background art, among the defective chip packaging products produced in batches in the related art, many chips have defects such as damage and cracks at the corners. The inventor has found that the reason for this problem is that, please refer to Figure 1 , Figure 1 A structural schematic diagram is shown in which a chip 110 in the related art is placed in a cavity 121 of a packaging substrate 120. During the process of placing the chip 110 in the cavity 121 of the packaging substrate 120, because the chip 110 itself is relatively fragile, especially when the corners of the chip 110 collide with the inner wall of the cavity 121, it is easy for the corners of the chip 110 to be damaged, cracked, and other defects to occur under the action of external forces.

[0056] Based on the above reasons, the present application provides a chip packaging structure and its manufacturing method, and a semiconductor device, which can improve defects such as breakage and cracks that occur at the corners of the chip, thereby improving the product yield of the chip packaging product.

[0057] See also Figure 2 , Figure 2A schematic structural diagram of a chip packaging structure of an embodiment of the present application is shown. An embodiment of the present application provides a chip packaging structure, and the chip packaging structure includes: a packaging substrate 210 and a chip 220. One side surface of the packaging substrate 210 is concave to form a recess 211, and the other side surface of the packaging substrate 210 is, for example, a flat surface, and a bottom film is provided. The inner side wall of the recess 211 is provided with a plurality of protrusions 212 arranged in sequence and spaced apart in the circumferential direction. The chip 220 is placed in the recess 211, and the edge contour of the chip 220 is set in a polygonal shape, and the multiple side edges of the chip 220 are respectively abutted and matched with the multiple protrusions 212.

[0058] In the above-mentioned chip packaging structure, since the multiple side edges of the chip 220 placed in the recess 211 are respectively abutted against the multiple protrusions 212, the multiple protrusions 212 limit the chip 220, so that the chip 220 is stably arranged in the recess 211, which can avoid the corners of the chip 220 from contacting the inner wall of the recess 211, and can also avoid damage or crack defects at the corners of the chip 220, that is, it can avoid the occurrence of defects during the placement of the chip 220, thereby improving the placement yield of the chip 220, thereby improving the product yield of the chip packaging product.

[0059] Also, see Figure 2 and Figure 3 , Figure 3 A schematic diagram of the structure of the chip 220 in the chip packaging structure of an embodiment of the present application is shown. When the chip 220 rotates, the protrusions 212 respectively abut against the side edges of the chip 220, thereby effectively preventing the corners of the chip 220 from contacting the inner wall of the recess 211.

[0060] The number of the recesses 211 on the package substrate 210 is not limited to one, and may be two, three, four or other numbers. The number of the chips 220 corresponds to the number of the recesses 211, and the number is not limited to one, and may be two, three, four or other numbers.

[0061] In some embodiments, the protrusion 212 and the package substrate 210 are made of the same material and are an integrated structure.

[0062] Of course, in some other embodiments, the material of the protrusion 212 may also be different from the material of the package substrate 210. Optionally, the protrusion 212 includes but is not limited to being set as an adhesive and bonded to the package substrate 210. The adhesive includes a thermosetting adhesive material or a thermoplastic adhesive material.

[0063] Among them, when the protrusion 212 is set as an adhesive, after the adhesive is initially solidified and shaped on the inner wall of the recess, the chip is placed in the recess, and the chip is positioned by having multiple side edges of the chip abut against the corresponding protrusions. Since the adhesive is elastic, the protrusion 212 can abut and fix the chip 220 located in the recess 211, and the chip 220 can also adaptively rotate within a certain angle range, thereby improving the performance of the chip packaging product.

[0064] See also Figure 2 , Figure 4 and Figure 5 , Figure 4 Shows Figure 2 The structure shown does not include the chip 220. Figure 5 Shows Figure 4 Cross-sectional structural diagram at AA. In some embodiments, the protrusion 212 is away from the side of the inner wall of the recess 211, that is, the abutting surface of the protrusion 212 that abuts against the side of the chip 220 is set to W with the inner wall of the recess 211, and W is set to 5μm-15μm, for example. In this way, on the one hand, the spacing W is large enough to form a gap between the side of the chip 220 and the inner wall of the recess 211, so that the chip 220 has enough space to rotate without contacting the inner wall of the recess 211; on the other hand, the spacing W is not too large, so that the spatial size of the recess 211 is small, thereby reducing the volume size of the chip packaging structure.

[0065] In some embodiments, W includes but is not limited to 5 μm, 8 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, etc. Of course, W can also be flexibly adjusted and set to any value less than 5 μm and greater than 15 μm according to actual needs.

[0066] See also Figure 5 In some embodiments, the distance W between the side of the protrusion 212 away from the inner side wall of the recess 211 and the inner side wall of the recess 211 is in the direction close to the bottom surface of the recess 211 (eg Figure 5 Thus, when placing the chip 220 into the recess 211, the side of the protrusion 212 away from the inner wall of the recess 211 guides the chip 220, so that the chip 220 moves smoothly into the recess 211.

[0067] See also Figure 5In some embodiments, the side of the protrusion 212 away from the inner wall of the recess 211 can be set as an inclined straight surface 2121, or can be set as an arc-shaped surface, or can be set as a combination of the inclined straight surface 2121 and the arc-shaped surface, or can be other regular shapes or irregular shapes, which can be flexibly adjusted and set according to actual needs.

[0068] See also Figure 5 Specifically, the side of the protrusion 212 away from the inner side wall of the recess 211 is set as an oblique straight surface 2121, and the oblique straight surface 2121 is set at an acute angle with the bottom surface of the recess 211. The angle between the oblique straight surface 2121 and the bottom surface of the recess 211 is set as a, and a is set to 70° to 90°, for example, 70°, 75°, 78°, 80°, 85° or 90°.

[0069] In some embodiments, the inner wall shape of the recess 211 is configured to conform to the edge contour shape of the chip 220, and the gap formed by the inner wall of the recess 211 and the edge contour of the chip 220 is uniform along the circumferential direction. In this way, the chip 220 is placed in the recess 211, and the structure volume is relatively compact, which can help reduce the product volume and size while stably placing the chip 220 in the recess 211.

[0070] It should be noted that the edge contour shape of the chip 220 includes, but is not limited to, various shapes such as a triangle, a quadrilateral, a pentagon, a hexagon, an octagon, and a dodecagon. The inner sidewall contour shape of the recess 211 is adapted to the edge contour shape of the chip 220, including but not limited to various shapes such as a triangle, a quadrilateral, a pentagon, a hexagon, an octagon, and a dodecagon. It can be set according to actual needs. In most cases, the edge contour shape of the chip 220 is designed to be a rectangle. In this embodiment, the chip 220 is specifically taken as a rectangular chip 220 as an example, but it is not limited to this.

[0071] See also Figure 2 In some embodiments, the chip 220 is configured as a rectangular chip 220, that is, the edge contour of the chip 220 is configured as a rectangle. The recess 211 is configured as a rectangular recess 211, that is, the inner sidewall of the recess 211 is configured as a rectangle. At least one protrusion 212 is provided on the inner sidewall of the recess 211 at a position corresponding to each side of the chip 220.

[0072] Specifically, the middle portion of each side of the chip 220 abuts against one, two or other number of protrusions 212 on the inner sidewall of the recess 211. The number of protrusions 212 abutted against each side of the chip 220 can be the same or different.

[0073] See also Figure 2In a specific embodiment, the middle part of each side of the chip 220 abuts against a protrusion 212 on the inner wall of the recess 211. In this way, the four corners of the chip 220 are provided with movable spaces with the inner wall of the recess 211, and can move freely without contacting the inner wall of the recess 211.

[0074] See also Figure 5 and Figure 6 , Figure 6 Shows Figure 5 Schematic diagram of the state of placing chip 220 on the basis of the structure shown. In some embodiments, the protrusion 212 extends from the edge of the recess 211 to the bottom surface of the recess 211. In this way, the contact area between the protrusion 212 and the side of the chip 220 is large, and the positioning effect of the chip 220 is stable and reliable.

[0075] See also Figure 2 , Figure 5 and Figure 6 , the distance from the top surface to the bottom surface of the protrusion 212 is set to h1, and the distance h1 can be the same as the depth of the concave portion 211, or can be greater than or less than the depth of the concave portion 211. The thickness of the chip 220 is set to h2. Among them, h1 is, for example, 0.7h2 to 1.3h2, and specifically, for example, 0.7h2, 0.8h2, 0.9h2, 1.1h2, 1.2h2 or 1.3h2. In this embodiment, Figure 2 After the chip 220 is placed in the recess 211, the top surface of the chip 220 is flush with the top surface of the package substrate 210, so that it is convenient to print and set the filling layer 240 on the top surface of the chip 220 and the top surface of the package substrate 210, which can not only improve the surface flatness, but also improve the structural stability. Of course, in some other embodiments, after the chip 220 is placed in the recess 211, the height position of the top surface of the chip 220 can be slightly lower or higher than the height position of the top surface of the package substrate 210.

[0076] See also Figure 2 and Figure 3 In some embodiments, the cross-sectional shape of the protrusion 212 in the direction perpendicular to the bottom surface of the recess 211 includes, but is not limited to, a square, a circle, a semicircle, an ellipse, a semi-ellipse or other regular and irregular shapes, which are not limited here. In this embodiment, the cross-sectional shape is specifically selected to be a square, so that the contact area of ​​the protrusion 212 and the chip 220 is in line contact or surface contact, so that the fixing effect of the chip 220 is stable and reliable.

[0077] See also Figure 6In some embodiments, the chip 220 is fixedly connected to the bottom surface of the recess 211 through a DAF (Die Attach film) bonding layer. Specifically, the DAF bonding layer includes but is not limited to being disposed between the chip 220 and the bottom surface of the recess 211 in the form of a silver adhesive patch, a sintered silver patch, a eutectic weld, or a hot melt weld, and is used to connect and fix the chip 220 to the bottom surface of the recess 211.

[0078] In some other embodiments, the chip 220 may also be provided with a conductive adhesive on the back side of the chip 220 , for example, by a screen printing process, and then baked and cured on the bottom surface of the recess 211 .

[0079] See also Figure 7 , Figure 7 The cross-sectional structure diagram of the chip packaging structure of an embodiment of the present application is shown. In some embodiments, the chip packaging structure further includes a filling layer 240, a wiring layer 250, a solder ball 260 and a protective layer 270. The filling layer 240 covers the outside of the chip 220 and the top surface of the packaging substrate 210 and fills the recess 211, the wiring layer 250 is arranged on the filling layer 240, the protective layer 270 is arranged on the wiring layer 250, and the wiring layer 250 is provided with a first electrical connection part 251 and a second electrical connection part 252. The first electrical connection part 251 penetrates the filling layer 240 and is connected to the chip 220, and the second electrical connection part 252 penetrates the protective layer 270 and is connected to the solder ball 260. Under the action of the filling layer 240, the chip 220 can be stably arranged in the recess 211.

[0080] It should be noted that the first electrical connection portion 251 and the second electrical connection portion 252 are each set to one, two, three or other numbers, for example, and can be flexibly adjusted and set according to actual needs, and are not limited here.

[0081] In one embodiment, the filling layer 240 is configured to include but is not limited to an adhesive, specifically, for example, one of polyimide and epoxy resin, or a composite layer thereof.

[0082] In one embodiment, the protective layer 270 includes, but is not limited to, printing ink.

[0083] See also Figure 2 In one embodiment, a semiconductor device includes the chip packaging structure of any of the above embodiments.

[0084] In the above-mentioned semiconductor device, since the multiple side edges of the chip 220 placed in the recess 211 are respectively abutted against the multiple protrusions 212, the multiple protrusions 212 play a limiting role on the chip 220, so that the chip 220 is stably arranged in the recess 211, which can avoid the corners of the chip 220 from contacting the inner wall of the recess 211, and can also avoid damage or crack defects at the corners of the chip 220, that is, it can avoid the occurrence of defects during the placement of the chip 220, thereby improving the placement yield of the chip 220, thereby improving the product yield of the chip packaging product.

[0085] See also Figure 2 and Figures 7 to 20 In one embodiment, a method for manufacturing a chip packaging structure includes the following steps:

[0086] Step S100, providing a substrate 2101, processing the substrate 2101 to form a packaging substrate 210, wherein one side surface of the packaging substrate 210 is concave to form a concave portion 211, and the inner side wall of the concave portion 211 is provided with a plurality of protrusions 212 sequentially arranged at intervals along the circumferential direction;

[0087] Step S200 , providing a chip 220 , placing the chip 220 in the recess 211 , the edge profile of the chip 220 is set to be polygonal, and the multiple side edges of the chip 220 are respectively in contact with the multiple protrusions 212 .

[0088] In the manufacturing method of the chip packaging structure described above, since the multiple side edges of the chip 220 placed in the recess 211 are respectively abutted against the multiple protrusions 212, the multiple protrusions 212 play a limiting role on the chip 220, so that the chip 220 is stably arranged in the recess 211, which can avoid the corners of the chip 220 from contacting the inner wall of the recess 211, and can also avoid damage or crack defects at the corners of the chip 220, that is, it can avoid the occurrence of defects during the placement of the chip 220, thereby improving the placement yield of the chip 220, thereby improving the product yield of the chip packaging product.

[0089] In some embodiments, the substrate 2101 may include a semiconductor substrate. For example, the semiconductor substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V substrates or II / VI substrates. Alternatively, for example, the substrate 2101 may include a semiconductor substrate such as a Si / SiGe substrate, a Si / SiC substrate, a silicon on insulator (SOI) substrate, or a silicon germanium on insulator substrate. Therefore, the type of semiconductor substrate should not limit the scope of protection of the present application.

[0090] In one embodiment, the step of processing the substrate 2101 to form the package substrate 210 includes:

[0091] Step S210, disposing a first photoresist layer 281 on the substrate 2101;

[0092] See also Figure 8 , Figure 8 The structure diagram shows a first photoresist layer 281 disposed on a substrate 2101. Specifically, the first photoresist layer 281 is disposed on the surface of the substrate 2101 by, for example, a screen printing process, and its thickness can be flexibly adjusted and set according to actual needs.

[0093] Step S220, performing exposure and development processing on the first photoresist layer 281 to expose a first area on the substrate 2101 that needs to be etched, wherein the first area includes a preset area on the concave portion 211 other than the convex portion 212;

[0094] See also Fig. 9 and Fig.10 , Fig. 9 Shows Figure 8 The structure shown in the figure is exposed and developed. Fig.10 Shows Fig. 9 Cross-sectional view of the structure at BB. Fig.10 The blank area shown in the figure corresponds to the area where the first photoresist layer 281 is exposed and developed, and this area is also the first area. Fig.10 The area outside the blank area shown in the figure is covered by the first photoresist layer 281, which protects the substrate 2101 thereunder from being etched.

[0095] Step S230, etching the first region of the substrate 2101 to a first preset depth, wherein the first preset depth is less than the thickness of the substrate 2101;

[0096] See also Fig.11 and Fig.12 , Fig.11 Shows Fig. 9 Structural diagram of the structure shown after etching. Fig.12 Shows Fig.11 Cross-sectional structural diagram at CC. Fig.11 and Fig.12 It can be seen that the material in the first area on the substrate 2101 is etched away to form the concave portion 211 because it is not covered by the first photoresist layer 281, and the portion of the substrate 2101 covered by the first photoresist layer 281 is not etched, thereby forming a plurality of protrusions 212 located on the inner sidewall of the concave portion 211. In addition, the first preset depth corresponds to the depth of the concave portion 211.

[0097] Step S240 , performing a stripping treatment on the substrate 2101 after the etching treatment to remove the first photoresist layer 281 on the surface of the substrate 2101 .

[0098] See also Figures 11 to 13 , Fig.13 Shows Fig.11 The structure shown is a diagram of the structure after leg membrane processing.

[0099] See also Figure 5 and Fig.13 In one embodiment, the step of processing the base 2101 to form the package substrate 210 further includes: step S250, etching the side of each protrusion 212 away from the inner side wall of the recess 211, so that the distance W between the side of the protrusion 212 away from the inner side wall of the recess 211 and the inner side wall of the recess 211 is in the direction close to the bottom surface of the recess 211 (such as Figure 5 Thus, the distance W between the side of the protrusion 212 away from the inner side wall of the recess 211 and the inner side wall of the recess 211 increases in the direction close to the bottom surface of the recess 211 (as shown by the arrow S in FIG. 1 ). Figure 5 In the process of placing the chip 220 into the concave portion 211, the side of the protrusion 212 away from the inner wall of the concave portion 211 guides the chip 220, so that the chip 220 moves smoothly into the concave portion 211.

[0100] Of course, in some optional solutions, the side surface of each protrusion 212 away from the inner wall of the recess 211 can be processed by various methods such as cutting and grinding to obtain a desired side surface shape.

[0101] See also Figures 14 to 20 In another embodiment, the step of processing the substrate 2101 to form the package substrate 210 includes:

[0102] Step S310, disposing a second photoresist layer 282 on the substrate 2101;

[0103] See also Fig.14 , Fig.14 The structure diagram shows a second photoresist layer 282 disposed on the substrate 2101. Specifically, the second photoresist layer 282 is disposed on the surface of the substrate 2101 by, for example, a screen printing process, and its thickness can be flexibly adjusted and set according to actual needs.

[0104] Step S320, performing exposure and development processing on the second photoresist layer 282 to expose the second area to be etched on the substrate 2101. The second area includes a preset area of ​​the concave portion 211;

[0105] See also Fig.15 and Fig.16 , Fig.15 Shows Fig.14 Structural diagram of the structure shown after exposure and development. Fig.16 Shows Fig.15 The portion of the second photoresist layer 282 corresponding to the second region will be developed. Fig.15 As shown, a notch is formed in the middle portion of the second photoresist layer 282 , and the solder resist layer on the second photoresist layer 282 corresponding to the area outside the second area is retained on the substrate 2101 .

[0106] Step S330, etching the second region of the substrate 2101 to a second preset depth, wherein the second preset depth is less than the thickness of the substrate 2101;

[0107] See also Fig.17 , Fig.17 Shows Fig.16 The structure diagram after etching. Fig.17 In the embodiment, the material of the second region of the substrate 2101 is all etched away, thereby forming the concave portion 211. The second preset depth is also the depth of the concave portion 211.

[0108] Step S340, performing a stripping process on the etched substrate 2101 to remove the second photoresist layer 282 on the surface of the substrate 2101;

[0109] See also Fig.18 , Fig.18 Shows Fig.17 The structure shown is a diagram of a structure in which a protruding material layer 283 is arranged behind the structure leg membrane.

[0110] Step S350, please continue to refer to Fig.18 , a protrusion material layer 283 is provided on the substrate 2101;

[0111] As an example, the protrusion material layer 283 completely covers the top surface of the substrate 2101 and the bottom surface of the recess 211 .

[0112] Step S360 , exposing and developing the protrusion material layer 283 , so that the protrusion material layer 283 has a plurality of solder resists remaining on the substrate 2101 after development, and each solder resist corresponds to a preset area of ​​each protrusion 212 .

[0113] See also Fig.19 and Fig. 20 , Fig.19 Shows Fig.18 Structural diagram of the structure shown during exposure process. Fig. 20 Shows Fig.19Structural diagram of the structure shown after development processing.

[0114] Specifically, the solder resist is baked so that the solder resist is solidified on the inner wall of the recess 211 , thereby obtaining the protrusion 212 .

[0115] See also Figure 5 , Fig.19 and Fig. 20 In one embodiment, when the protruding portion material layer 283 is subjected to exposure and development processing, the distance W between the side of the solder resist portion (i.e., the protruding portion 212) away from the inner side wall of the recess 211 and the inner side wall of the recess 211 is also made to be closer to the bottom surface of the recess 211 (e.g., Figure 5 In this way, the distance W between the side of the protrusion 212 away from the inner side wall of the concave portion 211 and the inner side wall of the concave portion 211 can be increased along the direction close to the bottom surface of the concave portion 211 (as shown by the arrow S in the figure). Figure 5 In the process of placing the chip 220 into the recess 211, the side of the protrusion 212 away from the inner wall of the recess 211 guides the chip 220, so that the chip 220 moves smoothly into the recess 211. In addition, since the shape of the side of the solder resist away from the inner wall of the recess 211 meets the requirements during the exposure and development process of the protrusion material layer 283, there is no need to wait until the solder resist is solidified to be processed by cutting and grinding, etc., so that the work efficiency is higher and the process cost is reduced.

[0116] Specifically, in the exposure and development processing steps, at least one of the conditions, such as the exposure energy, exposure position, exposure time, and the etching ability of the developer solution, is flexibly adjusted and controlled to achieve a side of the solder resist portion away from the inner wall of the recess 211 in the form of an oblique straight surface 2121, an arcuate surface, or a combination of an oblique straight surface 2121 and an arcuate surface.

[0117] Of course, in some optional schemes, it is also possible to set the side of the solder resist portion away from the inner wall of the recess 211 to a required shape without having to perform the exposure and development processing steps. For example, after the solder resist portion is solidified, the desired side shape can be obtained by various processing methods such as cutting and grinding.

[0118] See also Figure 7 In one embodiment, after the step of placing the chip 220 in the recess 211, the manufacturing method further comprises the steps of:

[0119] Step S300, filling the concave portion 211 with a fourth solder resist layer, so that the filling layer 240 covers the outside of the chip 220 and the top surface of the package substrate 210 and fills the concave portion 211;

[0120] Among them, the fourth solder resist layer is also as shown Figure 7 The filling layer 240 is shown in FIG.

[0121] Step S400, after the fourth solder resist layer is cured, a wiring layer 250 is disposed on the fourth solder resist layer, wherein the wiring layer 250 is provided with a first electrical connection portion 251 and a second electrical connection portion 252, so that the first electrical connection portion 251 penetrates the filling layer 240 and is connected to the chip 220;

[0122] Step S500 , disposing a protection layer 270 on the wiring layer 250 , so that the second electrical connection portion 252 penetrates the protection layer 270 and is connected to the solder ball 260 .

[0123] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0124] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.

[0125] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises: A packaging substrate, wherein one side surface of the packaging substrate is concave to form a concave portion, and an inner side wall of the concave portion is provided with a plurality of protrusions arranged in sequence and spaced apart in a circumferential direction; and The chip is placed in the concave portion, the edge contour of the chip is set to be polygonal, and the multiple side edges of the chip are respectively abutted and matched with the multiple protrusions.

2. The chip packaging structure according to claim 1, characterized in that: The protrusion is made of the same material as the packaging substrate and is an integrated structure; or, the protrusion is made of an adhesive and is bonded and cured on the packaging substrate.

3. The chip packaging structure according to claim 1, characterized in that: A distance W between the side surface of the protrusion away from the inner side wall of the recess and the inner side wall of the recess tends to increase in a direction approaching the bottom surface of the recess.

4. The chip packaging structure according to claim 1, characterized in that: The chip is configured as a rectangular chip, and the recess is configured as a rectangular recess; at least one protrusion is respectively arranged on the inner side wall of the recess at a position corresponding to each side edge of the chip.

5. The chip packaging structure according to claim 1, characterized in that: The chip is fixedly connected to the bottom surface of the concave portion through a DAF adhesive layer; or, the chip is solidified on the bottom surface of the concave portion by printing conductive glue and baking.

6. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure also includes a filling layer, a wiring layer, solder balls and a protective layer; the filling layer covers the outside of the chip and the top surface of the packaging substrate and fills the recess, the wiring layer is arranged on the filling layer, the protective layer is arranged on the wiring layer, the wiring layer is provided with a first electrical connection part and a second electrical connection part, the first electrical connection part passes through the filling layer and then is connected to the chip, and the second electrical connection part passes through the protective layer and is connected to the solder ball.

7. A method for manufacturing a chip packaging structure, characterized in that: The steps include: Providing a substrate, processing the substrate to form a packaging substrate, wherein one side surface of the packaging substrate is concave to form a concave portion, and the inner side wall of the concave portion is provided with a plurality of protrusions arranged in sequence and spaced apart in a circumferential direction; A chip is provided and placed in the concave portion. The edge contour of the chip is set to be polygonal, and multiple side edges of the chip are respectively abutted and matched with the multiple protrusions.

8. The manufacturing method according to claim 7, characterized in that: The step of processing the substrate to form a packaging substrate comprises: Disposing a first photoresist layer on the substrate; Performing exposure and development processing on the first photoresist layer to expose a first area on the substrate to be etched, wherein the first area includes a preset area on the concave portion other than the convex portion; Etching a first region of the substrate to a first preset depth, wherein the first preset depth is less than a thickness of the substrate; The substrate after etching is subjected to film stripping treatment to remove the first photoresist layer on the surface of the substrate.

9. The manufacturing method according to claim 7, characterized in that: The step of processing the substrate to form a packaging substrate comprises: Disposing a second photoresist layer on the substrate; Performing exposure and development processing on the second photoresist layer to expose a second area on the substrate to be etched, wherein the second area includes a preset area of ​​the concave portion; Etching a second region of the substrate to a second preset depth, wherein the second preset depth is less than the thickness of the substrate; Performing a film stripping treatment on the substrate after the etching treatment to remove the second photoresist layer on the surface of the substrate and obtain the concave portion on the substrate; Disposing a protrusion material layer on the substrate; The protruding portion material layer is exposed and developed, so that the protruding portion material layer remains on the substrate to have a plurality of solder resist portions, each of which corresponds to a preset area of ​​each protruding portion.

10. The manufacturing method according to claim 7, characterized in that: After the step of placing the chip in the recess, the manufacturing method further comprises the steps of: Filling the concave portion with a fourth solder resist layer, so that the filling layer covers the outside of the chip and the top surface of the packaging substrate and fills the concave portion; After the fourth solder resist layer is solidified, a wiring layer is arranged on the fourth solder resist layer, wherein the wiring layer is provided with a first electrical connection portion and a second electrical connection portion, so that the first electrical connection portion penetrates the filling layer and is connected to the chip; A protection layer is provided on the wiring layer, so that the second electrical connection portion penetrates through the protection layer and is connected to the solder ball.

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