Package, integrated circuit and packaging method

Abstract

The embodiment of the invention discloses a packaging piece, an integrated circuit and a packaging method, relates to the technical field of semiconductors, and is convenient for optimizing the heat dissipation performance by improving the internal structure of the packaging piece. A package includes: a redistribution layer; the cache crystal grain is positioned on the rewiring layer and is interconnected with the rewiring layer; and the core crystal grain is arranged above the cache crystal grain, is positioned on the top layer of the internal structure of the packaging piece, and is interconnected with the cache crystal grain. The core crystal grain is arranged on the top layer in the stacked structure form in the packaging piece, so that a large amount of heat generated by the central processing unit can be directly dissipated upwards from the top of the packaging piece, and the heat dissipation performance can be improved. The method is suitable for chip structure design and packaging.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a package, an integrated circuit and a packaging method. Background Art

[0002] In the high-performance computing and semiconductor industries, 3D integrated circuit (3DIC) stacking technology has become an important means to improve device performance and reduce chip size. Traditional 2D chip structures are gradually approaching physical limits in terms of size and performance improvement, while 3D stacking achieves higher computing density and energy efficiency by integrating multiple layers of chips in the vertical direction. Current 3D stacking solutions mostly use through silicon via (TSV) technology to achieve signal transmission between different chip layers, and cooperate with hybrid bonding technology to improve interconnection density and signal integrity.

[0003] In some related technologies, a cache die layer is stacked vertically on top of the processor's core die (also called CPU die) layer. This 3D stacking structure expands the cache capacity without increasing the processor area, thereby significantly improving system performance in specific application scenarios. However, due to the high power consumption of the processor's core die, the heat generated is conducted to the chip surface through the upper cache die layer and the silicon carrier (Si carrier), resulting in higher requirements for heat dissipation efficiency for this 3D stacking structure, and the increase in operating frequency is limited by the heat dissipation bottleneck. For example, in some multi-layer stacking structures, in order to reduce the impact of heat on frequency, certain restrictions are usually placed on the operating frequency. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a package, an integrated circuit and a packaging method, which improves the internal structure of the package to optimize its heat dissipation performance.

[0005] In order to achieve the above-mentioned invention object, the following technical scheme is adopted: According to a first aspect of an embodiment of the present invention, there is provided a package, comprising: a redistribution layer; A cache die is located on the redistribution layer and interconnected with the redistribution layer; The core die is arranged above the cache die, is located at the top layer of the internal structure of the package, and is interconnected with the cache die.

[0006] According to a specific implementation of the embodiment of the present application, a first conductive path is longitudinally arranged in the cache grain, the front side of the core grain faces the cache grain, and the core grain is bonded and interconnected with the cache grain at an exposed surface of the first conductive path.

[0007] According to a specific implementation method of an embodiment of the present application, the package also includes: a virtual grain, which is arranged above the redistribution layer and located on the side of the cache grain, and a second conductive path is longitudinally arranged inside the virtual grain, the upper end of the second conductive path is interconnected with the core grain, and the lower end of the second conductive path is connected to the redistribution layer.

[0008] According to a specific implementation manner of the embodiment of the present application, the front side of the core die faces the virtual die, and is bonded and interconnected with the virtual die at an exposed surface of the second conductive path.

[0009] According to a specific implementation method of an embodiment of the present application, the package also includes: a virtual grain, which is arranged above the redistribution layer and located on the side of the cache grain, and a second conductive path is longitudinally arranged inside the virtual grain, the upper end of the second conductive path is interconnected with the core grain, and the lower end of the second conductive path is connected to the redistribution layer, and the diameter of the second conductive path is greater than the diameter of the first conductive path.

[0010] According to a specific implementation manner of the embodiment of the present application, a metal layer is grown on the front side of the cache grain, the front side of the cache grain faces downward, and is connected to the redistribution layer through the metal layer.

[0011] According to a specific implementation of the embodiment of the present application, the core chip is integrated into a system-level chip.

[0012] According to a second aspect of an embodiment of the present invention, there is provided an integrated circuit, comprising: a substrate; a redistribution layer located on the substrate and interconnected with the substrate; a cache grain located on the redistribution layer and interconnected with the redistribution layer; a core grain disposed above the cache grain and located on the top layer of the internal structure of the package and interconnected with the cache grain.

[0013] According to a third aspect of an embodiment of the present invention, a packaging method is provided, comprising: providing cache grains and core grains; vertically stacking and interconnecting at least one of the cache grains with at least one core grain to form a 3D stacking structure; wherein the front side of the cache grain is interconnected to a redistribution layer; and mounting the 3D stacking structure upside down on a substrate so that at least one of the core grains is located on the top layer of the internal structure of the formed package.

[0014] According to a specific implementation method of an embodiment of the present application, before or after vertically stacking and interconnecting at least one cache grain with at least one core grain to form a 3D stacking structure, the method further includes: forming a plurality of metal layers on the front side of at least one cache grain; forming a redistribution layer on the top metal layer, and interconnecting the top metal layer with the redistribution layer to interconnect the cache grain with the redistribution layer; and forming conductive bumps on the lower surface of the redistribution layer for interconnection with the substrate.

[0015] According to a specific implementation method of an embodiment of the present application, providing a cache grain includes: fixing at least one of the cache grains with its front side facing downward on a temporary semiconductor carrier; forming at least one first silicon via that penetrates longitudinally on the cache grain using a photolithography mask; and filling the first silicon via with metal to form a first conductive path.

[0016] According to a specific implementation method of an embodiment of the present application, after fixing at least one of the cache grains with its front side facing down on a temporary semiconductor carrier, it also includes: attaching virtual grains around the cache grains, and filling with oxide until the gap between the cache grains and the virtual grains is completely filled; chemically mechanically polishing the oxide and stopping on silicon; performing silicon chemical mechanical polishing to thin the cache grains and the virtual core grains to a target thickness; using a photolithography mask to form at least one second silicon through-hole extending longitudinally through the virtual grain; and filling the second silicon through-hole with metal to form a second conductive path.

[0017] According to a specific implementation method of an embodiment of the present application, at least one cache grain is stacked and interconnected with at least one core grain in a vertical direction to form a 3D stacking structure, including: hybrid bonding and interconnecting the front side of at least one core grain facing downward with at least one cache grain at an exposed surface of a first conductive path.

[0018] According to a specific implementation method of an embodiment of the present application, before or after vertically stacking and interconnecting at least one of the cache grains with at least one core grain, it also includes: facing the front side of at least one core grain toward the virtual grain, hybrid bonding and interconnecting with the virtual grain on the exposed surface of the second conductive path, and connecting to the redistribution layer through the second conductive path.

[0019] The package, integrated circuit and packaging method provided in the embodiments of the present application improve the internal structure of the package and place the core die (CPU die or Core die) at the top layer of the stacked structure inside the package. In this way, a large amount of heat generated by the CPU (central processing unit, generally referred to as the CPU after the core die is packaged) can be directly dissipated upward from the top, thereby helping to improve the heat dissipation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic diagram of a packaging structure provided by an embodiment of the present invention; Figure 2 A schematic diagram of a packaging structure provided by yet another embodiment of the present invention; Figure 3 A schematic diagram of the structure of an integrated circuit provided in yet another embodiment of the present invention; Figure 4 A schematic diagram of a packaging method flow chart provided by an embodiment of the present invention; Figures 5 to 17 A schematic cross-sectional view of the structure during the process of forming a package provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0023] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] In order to realize the different features of the provided subject matter, the present invention provides many different embodiments or examples. The following describes specific examples of components and arrangements to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first and second components are formed in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact.

[0025] In some 3D stacked chip packaging technologies, the top of the central processing unit die (CPU die, or core die) is connected to the cache die and dummy die layers, and the bottom is connected to the substrate. Since the power consumption of the central processing unit die is much greater than that of the cache die, a large amount of heat needs to be transferred from the top of the 3D stacked structure through the cache die and the silicon carrier. This type of 3D stacked structure has extremely high requirements for heat dissipation efficiency. Specifically: since the CPU die is at the bottom of the stacked structure, the heat transfer path upward is long and the heat dissipation efficiency is low; the heat emitted by the CPU die is transferred upward to the cache die, making the cache die temperature very high, affecting the performance of the cache die, such as affecting the frequency, and may even cause the cache die to overheat and burn. In some solutions, in order to reduce heat accumulation, the operating frequency of the processor will be appropriately lowered, however, this will affect the operating frequency.

[0026] In view of the problem of low heat dissipation efficiency in the existing 3D stacked packaging structure, an embodiment of the present invention provides a package suitable for chip structure design and packaging. By improving the internal stacking structure of the package, the Core die (i.e., CPU die) in the heat-generating core area is placed on the top layer of the stacking structure, so that the heat generated by the core grains can be dissipated upward without obstruction, and the heat transfer path is shortened, which is beneficial to improving the heat dissipation performance, thereby increasing the heat dissipation efficiency.

[0027] Figure 1 The structure of a package according to an embodiment of the present invention is shown. In some embodiments, the package 100 includes: a redistribution layer (RDL) 102, which can be formed by a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process to provide an electrical connection path. The materials used include copper, aluminum or other conductive materials to ensure the reliability of the electrical connection.

[0028] The cache die 104 is located on the redistribution layer 102 and is interconnected with the redistribution layer 102. When interconnecting with the redistribution layer 102, bonding technology, such as hybrid bonding, can be used to achieve high-density connection and reduce parasitic resistance and capacitance, thereby improving performance.

[0029] The core die 106 is disposed above the cache die 104 and is located at the top layer of the internal structure of the package 100, and is interconnected with the cache die 104. By improving the layout of the 3D stacking structure, the core die 106 is disposed at the top layer of the internal structure of the package 100, so that the heat generated by the core die can be dissipated upward without shielding, reducing the heat transfer path and significantly improving the heat dissipation performance.

[0030] Therefore, the 3D stacked chip package provided in the embodiment of the present invention improves the internal structure of the chip package and places the core crystal grains on the top layer of the stacked structure inside the package. In this way, a large amount of heat generated by the CPU (central processing unit, generally referred to as the CPU after the core crystal grains are packaged) can be directly dissipated upward from the top, thereby helping to improve the heat dissipation performance.

[0031] In the 3D stacked packaging structure introduced above, TSV is set on the CPU die, so the CPU die needs to be thinned first, and finally, in order to balance the overall stress, it is necessary to bond the silicon carrier (bonding Si Carrier die) to form a three-layer stack of Si Carrierdie / Cache die / CPU die.

[0032] Figure 2 The structure of a package according to an embodiment of the present invention is shown. In some embodiments, a first conductive path 108 is vertically arranged in the cache die 104. The first conductive path 108 can be a through-silicon via (TSV) for achieving electrical connection between the die in different layers.

[0033] The core die 106 faces the cache die 104, and the core die 106 and the cache die 104 are interconnected by bonding at the exposed surface of the first conductive path 108. Specifically, the core die 106 is electrically interconnected with the exposed surface of the first conductive path 108 on the cache die 104 by metal-to-metal bonding or hybrid bonding.

[0034] In this embodiment, since the first conductive path 108 is formed in the cache die 104, the core die 106 does not need to be thinned, and the overall stress can be balanced directly by the thickness of the core die 106. Therefore, in some embodiments, the final form only includes a two-layer structure of the core die and the cache die, and the overall heat dissipation path is shorter and the heat dissipation performance is relatively better.

[0035] It is understandable that in 3D stacking packaging technology, in order to improve computing performance and integration, multiple functional chips are usually stacked together, such as cache chips and core computing chips. However, as the number of stacking layers increases, the distance between the core die and the substrate also increases, which may cause problems with signal integrity (SI) and power integrity (PI). Specifically, the signal may be attenuated and interfered by noise in a longer transmission path, resulting in a decrease in system performance; and the power distribution network may also cause power instability due to voltage fluctuations, affecting the reliability of computing.

[0036] Continue to view Figure 1 In some embodiments, the package further includes a dummy die 110 . The dummy die 110 is disposed on the redistribution layer 102 and is located on the side of the cache die 104 .

[0037] A second conductive path 112 is longitudinally disposed inside the virtual die 110. The second conductive path 112 is a large-sized through silicon via (TSV) for optimizing the transmission of signal integrity and power integrity. The upper end of the second conductive path 112 is interconnected with the core die 106, and the lower end is connected to the redistribution layer 102.

[0038] In this embodiment, by setting a conductive path inside the virtual die, the core die can establish an effective electrical connection with the redistribution layer and finally connect to the substrate, and the path can also assist in heat dissipation. This not only improves the electrical performance of the overall package, but also enhances its thermal management capability, and improves the reliability and stability of the 3D stacked package.

[0039] In some embodiments, the front side of the core die 106 is also arranged toward the virtual die 110 so as to form an effective connection with the virtual die 110 in terms of spatial structure, and is bonded and interconnected with the virtual die 110 at the exposed surface of the second conductive path 112. Specifically, the core die 106 and the virtual die 110 are hybrid bonded and interconnected through the exposed surface of the upper end of the second conductive path 112, and the conductive path 112 is located inside the virtual die 110 and extends in the longitudinal direction, providing a stable electrical connection and a heat conduction path for the interconnection between the core die and the substrate.

[0040] In some embodiments, to ensure the reliability and conduction performance of the connection, the second conductive path 112 can be made of a material with excellent conductive properties, such as copper or tungsten. The surface of the conductive path is processed by electroplating or chemical vapor deposition (CVD) process to enhance the conductive properties and improve the interconnection quality with the core die 106. The upper end of the conductive path is cleaned and patterned to form an exposed surface to ensure good bonding contact.

[0041] In addition, during the preparation process of the virtual grain 110, insulating materials such as silicon dioxide or silicon nitride can be deposited to achieve electrical insulation between the conductive path 112 and the virtual grain body, which not only improves the electrical connection stability of the package, but also effectively manages heat conduction within the chip and improves the overall heat dissipation performance.

[0042] See also Figure 5As shown, in other embodiments, the package 100 further includes a dummy die 110, which is located on the redistribution layer 102 and is located on the side of the cache die 104 in terms of spatial layout. A second conductive path 112 is longitudinally arranged inside the dummy die 110, and the upper end of the second conductive path 112 is interconnected with the core die 106, and the lower end is connected to the redistribution layer 102 to achieve electrical interconnection.

[0043] In some embodiments, the diameter of the second conductive path 112 is designed to be larger to meet the requirements of electrical conduction and heat transfer. The diameter of this path is larger than the diameter of the first conductive path in the cache die 104, aiming to optimize the current capacity and signal transmission performance. The second conductive path 112 can be processed by deep silicon etching technology and filled with conductive materials such as copper or tungsten to enhance conductivity.

[0044] In the manufacturing process, the main body material of the virtual die 110 can be selected from the same semiconductor material as the cache die to ensure matching thermal expansion coefficients and reduce the impact of thermal stress on the package.

[0045] In this embodiment, optimization is performed by making a large-sized second conductive path within the virtual crystal grain, which plays the role of thermal management and electrical transmission at the same time, thereby achieving a shorter signal path and reducing signal transmission delay. At the same time, an effective heat dissipation channel is provided in terms of heat dissipation performance, thereby optimizing the overall performance of the package.

[0046] Continue to view Figure 1 As shown, in some embodiments, a metal layer 120 is grown on the front side of the cache grain 104. The metal layer 120 can be formed by electroplating or physical vapor deposition (PVD) process, and is usually made of highly conductive materials such as copper, aluminum or gold, and is mainly used to provide a transmission path for electrical signals to ensure reliable electrical connection with the redistribution layer 102.

[0047] The front side of the cache die 104 faces downward and is connected to the redistribution layer 102 through the metal layer 120. By optimizing the electrical interconnection between the cache die 104 and the redistribution layer 102, the electrical conductivity and signal transmission stability are significantly improved.

[0048] In addition, the thickness and growth process of the metal layer 120 can be adjusted according to specific needs to balance electrical performance and structural strength.

[0049] See also Figure 2 As shown, in other embodiments, the core die 106 is integrated into a system-on-chip (SoC) 10. The system-on-chip 10, as the main processing unit of the package, may include multiple functional modules, such as a central processing unit (i.e., the core die 106), a graphics processing unit (GPU), etc., to achieve multifunctional system-level integration.

[0050] In this embodiment, the core die 106 is integrated into the SoC through advanced manufacturing processes, such as wafer-level packaging technology, allowing the core die 106 to share the redistribution layer 102 and electrical interconnection paths of the package with other functional modules, thereby achieving higher I / O density and shorter signal transmission paths.

[0051] In addition, the integration of the core die 106 also allows the package to achieve a more compact structure, thereby reducing chip size and manufacturing costs.

[0052] Therefore, the 3D stacked chip package provided in the embodiment of the present invention improves the internal structure of the chip package and places the core grains on the top layer of the stacked structure inside the package. In this way, a large amount of heat generated by the CPU can be directly dissipated upward from the top, which is beneficial to improving the heat dissipation performance.

[0053] Embodiment 2 See also Figure 3 As shown, the present invention also provides an integrated circuit in an embodiment, including: a substrate 200, a redistribution layer (RDL) 102, a cache die 104, and a core die 106. The substrate 200 can be a multi-layer printed circuit board (PCB) or other conductive substrate, which has high conductivity and mechanical support functions, and is used to carry a package and realize electrical connection with an external circuit.

[0054] The redistribution layer 102 is located on the substrate 200 and is formed by microfabrication technology. The material can be selected from metals with good conductivity such as copper and aluminum. The redistribution layer 102 provides an electrical connection path to electrically interconnect the cache die 104 and the substrate 200 to achieve efficient transmission of signals and power.

[0055] The cache die 104 is disposed on the redistribution layer 102 and interconnected with the redistribution layer 102. The cache die may be a high-performance cache module, and the electrical connection between the cache die and the redistribution layer 102 is achieved through conductive bumps or solder balls, providing stable electrical interconnection.

[0056] The core die 106 is arranged above the cache die 104 and is located at the top layer of the internal structure of the package, forming the top layer structure of the package. The core die 106 and the cache die 104 are interconnected through interlayers to achieve data transmission and electrical connection between different layers.

[0057] In this embodiment, a stacking structure can be implemented through wafer-level packaging technology, flip-chip packaging technology, etc., to ensure efficient thermal management and electrical performance.

[0058] In this embodiment, the core die 106 in the package is designed to be located at the top layer of the package structure so that the heat generated by the core die 106 can be quickly transferred to the outside, thereby improving the heat dissipation performance and thus the heat dissipation efficiency.

[0059] It should be noted that the scheme of this embodiment has corresponding specific technical features as the first embodiment, and its specific technical scheme and technical effects are similar. The difference lies in that the integrated circuit of the embodiment of the present invention and the package in the first embodiment have different positions in the industrial chain. Generally, after the chip packaging in the first embodiment is completed, the back-end substrate packaging process will be carried out to form an integrated circuit.

[0060] For each embodiment provided by the present invention, the technical solutions and technical effects are basically the same, and the relevant parts can be referenced to each other.

[0061] Figure 4 The schematic diagram of the process of an embodiment of the packaging method of the present invention is shown, which can be used in advanced packaging technologies including 2.5D, 3D or other forms to realize chip packaging. A packaging method includes: S210, providing a cache die and a core die. Figures 5 and 6 As shown in FIG. 1 , cache die can be prepared from a wafer to the top copper metal layer, then cut into individual cache dies and thinned to a specific thickness, such as 10 microns, according to process requirements. Fig.12 As shown, the core die is prepared to its ALPA Pad (specific pad or connection point for system-level packaging) using Wafer, completes its required 2D related processes, and completes the bonding pad via and bonding pad preparation of the SOC wafer by using a photomask, as shown in FIG. Fig.13 As shown, it is prepared for the subsequent wafer-level packaging process.

[0062] S220, stacking and interconnecting at least one cache die and at least one core die in a vertical direction to form a 3D stacking structure.

[0063] Wherein, the front side of the cache die is interconnected to the redistribution layer. Figures 14 to 16 As shown, specifically, the cache die and the core die are stacked vertically and can be interconnected by a hybrid bonding process. The hybrid bonding process specifically uses metal-to-metal or direct surface bonding. Fig.14 As shown in the red dotted box, a strong electrical connection is achieved through proper heat treatment and pressure, ensuring low resistivity and high reliability of the electrical connection.

[0064] S230, mounting the 3D stacked structure upside down on a substrate so that at least one of the core chips is located on a top layer of an internal structure of the formed package.

[0065] In this embodiment, Fig.17 As shown, the formed 3D stacked structure is mounted upside down on the substrate so that the core die is located at the top layer of the package, ensuring that its heat can be dissipated upward without hindrance, effectively shortening the heat transfer path, thereby improving the heat dissipation performance.

[0066] Specifically, the process of interconnecting the front side of the cache die to the redistribution layer can be performed after the cache die and the core die are stacked and interconnected. Fig.14 In some embodiments, before or after vertically stacking and interconnecting at least one cache die with at least one core die to form a 3D stacked structure, the method further includes: forming a plurality of metal layers on the front side of at least one cache die, such as Figure 5 As shown; forming a redistribution layer on the top metal layer, and interconnecting the top metal layer with the redistribution layer to achieve interconnection between the cache grains and the redistribution layer, such as Fig.15 As shown, the redistribution layer formation process is performed after the 3D stacking structure is formed; Fig.16 As shown, conductive bumps are formed on the lower surface of the redistribution layer for interconnection with the substrate.

[0067] The metal layer can be formed by sputtering, physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes. The metal materials include conductive materials such as copper and aluminum to ensure good conductivity and adhesion. Each layer of metal is patterned to achieve the best conductive layout.

[0068] On the top metal layer, a redistribution layer is formed by photolithography and etching processes. The redistribution layer uses a highly conductive material, such as copper or aluminum, and is interconnected with the top metal layer to achieve a stable electrical connection between the cache die and the redistribution layer. Next, conductive bumps are formed on the lower surface of the redistribution layer and filled with metal materials such as tin, lead or indium using electroplating or evaporation technology so that the package can be stably electrically interconnected with the substrate.

[0069] Figures 9 to 11 The process of forming the first conductive path and the second circuit path is shown. The providing of the cache grain comprises: Fix at least one of the cache grains face down on a temporary semiconductor carrier; form at least one first through silicon via (TSV) vertically penetrating the cache grain using a photolithography mask; and fill the first through silicon via with metal to form a first conductive path.

[0070] Specifically, at least one cache die is cut from the wafer and fixed face down on a temporary semiconductor carrier. The carrier can be made of silicon and has stability and thermal matching performance to provide sufficient support in subsequent processes. Then, a close connection between the cache die and the carrier is achieved through a chemical oxide bonding process to ensure stability and alignment accuracy throughout the process.

[0071] After the cache die is fixed, it is patterned using photolithography mask technology. The photolithography mask defines the position and shape of the first silicon through-hole that runs vertically through the die through the steps of coating photoresist, exposure and development. After that, dry etching technology, such as reactive ion etching (RIE), can be used to etch through holes (VIA) at these locations, so that they penetrate the full thickness of the cache die.

[0072] After etching is completed, the metal filling step of the through hole is carried out. Electroplating or chemical vapor deposition (CVD) technology can be used to fill the conductive material such as copper or tungsten. It is necessary to ensure that the metal completely fills the through hole and forms a highly conductive first conductive path. Subsequently, chemical mechanical polishing (CMP) is used to remove excess metal to ensure that the through hole surface is flat and flush with the top layer of the cache grain, such as Fig.10 , a cross-sectional view of a cache die after filling and CMP is completed is shown, showing the structure of the first conductive path running through the cache die.

[0073] Figures 9 and 10 Detailed steps of attaching dummy die around cache die and filling oxide are shown. In some embodiments, after fixing at least one cache die with its front side facing downward on a temporary semiconductor carrier, the process further includes: attaching dummy die around cache die and filling with oxide until the gap between cache die and dummy die is completely filled; chemical mechanical polishing of oxide is performed and stopped on silicon; chemical mechanical polishing of silicon is performed to thin cache die and dummy die to target thickness; at least one second silicon through hole is formed longitudinally on the dummy die using a photolithography mask; and metal is filled into the second silicon through hole to form a second conductive path. The specific process of forming the second conductive path is similar to the process of forming the first conductive path, and the two can be performed in the same step or separately.

[0074] Specifically, after the cache die is fixed face-down on the temporary semiconductor carrier, the virtual die can also be arranged and the second conductive path formation process can be performed. Specifically, virtual die of suitable size and material are selected and arranged around the cache die. The arrangement of the virtual die is intended to provide optimization of thermal and electrical performance and form a stable electrical interconnection structure in subsequent steps.

[0075] Subsequently, silicon dioxide oxide is filled in the gaps between the cache grains and the dummy grains using chemical vapor deposition (CVD) or spin coating techniques, ensuring that it completely fills all gaps. The deposition of the oxide helps stabilize the structure between the grains and provides electrical insulation properties.

[0076] After the oxide filling is completed, chemical mechanical polishing (CMP) is performed to stop at the silicon layer to flatten the oxide surface and provide a smooth base for subsequent steps. Fig.11 As shown, the cache die and the dummy die are thinned to a target thickness, such as about 10 microns, by CMP of silicon to meet the TSV process requirements.

[0077] The process of forming the second through silicon via on the virtual die using a photolithography mask can refer to the process of forming the first through silicon via, and will not be described in detail. At this point, the wafer level reconstruction of the cache die and the virtual die is completed; wherein, Fig.11 The formation process of the second conductive path in the virtual die and its arrangement with the surrounding structures are demonstrated.

[0078] Fig.14 The process of stacking and hybrid bonding interconnection of cache grains and core grains according to the embodiment is shown. The cache grains have completed the aforementioned wafer-level reconstruction steps, such as the formation of conductive paths, temporary carrier fixation, oxide filling, etc., and the provided core grains already have their predefined functional structures and metal connection layers. The stacking and interconnecting of at least one cache grain with at least one core grain in the vertical direction to form a 3D stacking structure includes: hybrid bonding interconnection of at least one core grain facing downward with at least one cache grain at the exposed surface of the first conductive path.

[0079] like Fig.14 Specifically, at the beginning of the stacking step, ensure that the cache die is facing up and ready to be interconnected with the core die. The core die, after the front-end manufacturing process, faces down and is placed face to face with the cache die, ready for hybrid bonding. The key to this process is the precise alignment of the two to ensure reliable electrical connection between the exposed surface of the first conductive path and the interconnection point of the core die.

[0080] In some embodiments, hybrid bonding can be achieved by a solid phase diffusion process combining pressure and temperature, supplemented by interface cleaning and surface flattening, to ensure high bonding strength and low contact resistance at the bonding interface. To enhance the bonding effect, a thin layer of metal material (such as copper or nickel) can be pre-coated at the contact interface between the cache grain and the core grain to promote self-alignment and diffusion reaction of the interconnection point.

[0081] In actual process operation, the core die is placed face down on top of the cache die, so that the connection point on the core die is aligned with the pre-exposed first conductive path on the cache die. Under certain temperature and pressure conditions, the core die and the conductive path of the cache die are hybrid bonded to form a stable electrical and mechanical connection. Fig.15 A cross-section of the stacked structure is shown, showing the precise interconnection of the core die and the cache die on the conductive paths.

[0082] See also Fig.16 , after hybrid bonding of the conductive paths of the core die and the cache die, and after the arrangement of the redistribution layer is completed, the conductive bumps of the 3DIC wafer are prepared to complete the wafer-level packaging.

[0083] According to the requirements, the 3DIC SOC wafer can also be thinned and cut into individual chips. Then the subsequent substrate packaging process is completed, such as Fig.17 As shown, at this point, the 3D structure packaging process of the present invention is completed.

[0084] In some embodiments, the hybrid bonding process can also be further optimized by adjusting the temperature, pressure and time parameters so that the bonding interface can achieve a void-free and microcrack-free bonding at the microscopic level, which not only ensures the reliable electrical performance of the 3D package, but also improves its overall mechanical stability and thermal stability.

[0085] In this embodiment, through the above process, the core grain is placed at the top layer of the internal structure of the package, which is beneficial to improving its thermal management effect, and solves the SI / PI transmission problem that may be caused by the core grain being far away from the substrate, thereby improving signal transmission efficiency.

[0086] In summary, the package and packaging method provided in the embodiments of the present invention improve the internal structure of the chip package and place the core die on the top layer of the stacked structure inside the package. In this way, a large amount of heat generated by the CPU can be directly dissipated upward from the top, which is beneficial to improving the heat dissipation performance.

[0087] In addition, by making the SI / PI transmission channel of the core grain inside the virtual grain, the heat dissipation performance of the CPU on the outside of the 3D structure is improved while meeting the SI / PI requirements, effectively improving the overall performance of the 3D stacked chip packaging structure.

[0088] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0089] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0090] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A package, characterized in that: include: Rewiring layer; A cache die is located on the redistribution layer and interconnected with the redistribution layer; The core die is arranged above the cache die, is located at the top layer of the internal structure of the package, and is interconnected with the cache die.

2. The package according to claim 1, characterized in that A first conductive path is longitudinally arranged in the cache grain, and the front side of the core grain faces the cache grain, and the core grain is bonded and interconnected with the cache grain at an exposed surface of the first conductive path.

3. The package according to claim 1, characterized in that The package also includes: a virtual grain, which is arranged on the redistribution layer and located on the side of the cache grain. A second conductive path is longitudinally arranged inside the virtual grain, the upper end of the second conductive path is interconnected with the core grain, and the lower end of the second conductive path is connected to the redistribution layer.

4. The package according to claim 3, characterized in that The front surface of the core die faces the dummy die, and the core die is bonded and interconnected with the dummy die at an exposed surface of the second conductive path.

5. The package according to claim 2, characterized in that: The package also includes: a virtual grain, which is arranged above the redistribution layer and located on the side of the cache grain. A second conductive path is longitudinally arranged inside the virtual grain. The upper end of the second conductive path is interconnected with the core grain, and the lower end of the second conductive path is connected to the redistribution layer. The diameter of the second conductive path is greater than the diameter of the first conductive path.

6. The package according to claim 1, characterized in that A metal layer is grown on the front side of the cache die. The front side of the cache die faces downward and is connected to the redistribution layer through the metal layer.

7. The package according to claim 1, characterized in that The core die is integrated into a system-on-chip.

8. An integrated circuit, characterized in that: include: substrate; A redistribution layer, located on the substrate and interconnected with the substrate; A cache die is located on the redistribution layer and interconnected with the redistribution layer; The core die is arranged above the cache die, is located at the top layer of the internal structure of the package, and is interconnected with the cache die.

9. A packaging method, characterized in that: include: Provide cache grains and core grains; At least one of the cache die is stacked and interconnected with at least one core die in a vertical direction to form a 3D stacking structure; wherein the front side of the cache die is interconnected to the redistribution layer; The 3D stacked structure is flip-mounted onto a substrate so that at least one of the core die is located on a top layer of an internal structure of a formed package.

10. The packaging method according to claim 9, characterized in that: Before or after vertically stacking and interconnecting at least one of the cache grains with at least one core grain to form a 3D stacked structure, the method further includes: forming a plurality of metal layers on the front side of at least one cache grain; Forming a redistribution layer on the top metal layer, and interconnecting the top metal layer with the redistribution layer to achieve interconnection between the cache grain and the redistribution layer; Conductive bumps are formed on the lower surface of the redistribution layer for interconnection with the substrate.

11. The packaging method according to claim 9, characterized in that: Providing the cache die comprises: fixing at least one of the cache die with its front side facing downward on a temporary semiconductor carrier; Using a photolithography mask, forming at least one first through silicon via that vertically penetrates the cache die; Filling the first through silicon via with metal to form a first conductive path.

12. The packaging method according to claim 9, characterized in that: After fixing at least one of the cache die with the front side facing downward on a temporary semiconductor carrier, the method further comprises: A dummy grain is attached around the cache grain, and oxide filling is performed until the gap between the cache grain and the dummy grain is completely filled; performing chemical mechanical polishing on the oxide and stopping on silicon; Perform silicon chemical mechanical polishing to thin the cache grains and dummy cores to a target thickness; Using a photolithography mask, forming at least one second through silicon via that penetrates vertically on the dummy die; Filling the second through silicon via with metal to form a second conductive path.

13. The packaging method according to claim 9, characterized in that: The method of stacking and interconnecting at least one cache grain and at least one core grain in a vertical direction to form a 3D stacking structure includes: interconnecting the front side of at least one core grain facing downward with at least one cache grain by hybrid bonding at an exposed surface of a first conductive path.

14. The packaging method according to claim 12, characterized in that: Before or after vertically stacking and interconnecting at least one of the cache grains with at least one core grain, the method further includes: facing the front side of at least one core grain toward the virtual grain, hybrid bonding and interconnecting the virtual grain with the exposed surface of the second conductive path, and connecting to the redistribution layer through the second conductive path.

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