LVDS format data receiving system based on FPGA

Abstract

The invention relates to the technical field of electronics, in particular to an LVDS (Low Voltage Differential Signaling) format data receiving system based on an FPGA (Field Programmable Gate Array). Firstly, a receiving system is integrated on an FPGA, so that a high-speed clock is provided for LVDS data transmission, in addition, the receiving system comprises an LVDS data conversion module, an interface delay module, a serial-parallel conversion module and a data combination module, data positive lines and data negative lines of LVDS are independently collected through the high-speed clock, then the data are combined, LVDS data receiving is achieved, and the LVDS data transmission efficiency is improved. And a level conversion process is avoided, and higher-speed data transmission can be adapted.

Description

Technical Field

[0001] The invention belongs to the technical field of electronics, and in particular relates to an LVDS format data receiving system based on FPGA. Background Art

[0002] LVDS (Low-Voltage Differential Signaling) format data can transmit high-speed data in serial mode and is one of the main data transmission formats of image sensors. LVDS format data has two physical data lines, the positive line and the negative line. The voltage difference between the two lines is used to realize the high-level and low-level coding transmission of data, and finally complete the data transmission.

[0003] The transmission and reception of LVDS format data requires converting parallel multi-bit width data into sequential serial mode for transmission. The receiving end needs to restore the serial data to parallel data after receiving it. Since LVDS data usually has a high transmission rate, it usually needs to go through data training and alignment to ensure the correctness of data transmission. This places high demands on the robustness and accuracy of the receiving system.

[0004] The existing LVDS data training and alignment process usually pre-parses the high and low levels of the LVDS positive and negative lines, converts them to single-line levels, and then uses a high-speed clock to simultaneously collect the data bits at each moment on the single-line level. Since the level conversion process from two lines to a single line is added after the data, the inherent delay of the system is increased on top of the delay adjustment function, resulting in a limited upper limit for system data reception, which is not conducive to future high-speed data reception. At the same time, the corresponding IP (intellectual property) cores provided by existing manufacturers' devices need to be cascaded to achieve specific data bit width collection, such as 10-bit bit width data. Although the cascade method can solve the problem of receiving data with a specific bit width, it cannot be quickly modified to adapt to another bit width method. When the bit width needs to be modified, reconstructing the system program will bring additional workload, which is not conducive to the agile development of the system. Summary of the invention

[0005] In view of this, the present invention aims to provide an LVDS format data receiving system based on FPGA, with an LVDS data conversion module integrated on the FPGA, to independently collect the serial data of the LVDS positive line and the negative line respectively, and after signal delay and serial-to-parallel conversion, through a data combination module, to synthesize the final parallel data format, thereby realizing high-speed reception of LVDS data, eliminating the LVDS data rate upper limit bottleneck of the original method, and improving the system portability and reusability.

[0006] To achieve the above object, the technical solution created by the present invention is implemented as follows: A LVDS format data receiving system based on FPGA comprises an LVDS data conversion module, an interface delay module, a serial-to-parallel conversion module and a data combination module integrated on the FPGA; wherein the LVDS data conversion module collects the level of an external two-wire serial signal and converts it into the level of a two-wire serial signal inside the FPGA; the interface delay module receives the two-wire output signal of the LVDS data conversion module and provides independent transmission delay superposition for the two-wire input signal; the serial-to-parallel conversion module receives the two-wire output signal of the interface delay module and converts the two-wire serial input signal into a two-wire parallel output signal; the data combination module performs data combination on the two-wire parallel output signal of the serial-to-parallel conversion module to obtain final LVDS parallel data.

[0007] Furthermore, the external two-wire serial signal includes a serial LVDS positive line P signal and a serial LVDS negative line N signal; the LVDS data conversion module converts the two-wire signal into a LVDS positive line P signal and a LVDS negative line N signal respectively, and the levels of the LVDS positive line P signal and the LVDS negative line N signal are the levels of the two-wire serial signal inside the FPGA.

[0008] Furthermore, the interface delay module includes a P signal delay submodule and an N signal delay submodule; wherein the P signal delay submodule provides transmission delay superposition for the LVDS positive line P signal; and the N signal delay submodule provides transmission delay superposition for the LVDS negative line N signal.

[0009] Furthermore, the serial-to-parallel conversion module includes a P signal conversion submodule and an N signal conversion submodule; wherein the P signal conversion submodule converts the signal output by the P signal delay submodule into a parallel LVDS positive line P signal; and the N signal conversion submodule converts the signal output by the N signal delay submodule into a parallel LVDS negative line N signal.

[0010] Furthermore, the P signal conversion submodule and the N signal conversion submodule are configured in an SDR data rate mode.

[0011] Furthermore, the serial-to-parallel conversion range of the P signal conversion submodule and the N signal conversion submodule is 2-8 bits.

[0012] Furthermore, the data combination module receives and combines the parallel LVDS positive line P signal and the parallel LVDS negative line N signal to obtain final LVDS parallel data.

[0013] Furthermore, the data combination module combines the parallel LVDS positive line P signal and the parallel LVDS negative line N signal in a signal crossing or signal splicing manner.

[0014] Compared with the prior art, the invention can achieve the following beneficial effects: (1) In the FPGA-based LVDS format data receiving system created by the present invention, the LVDS data conversion module, the interface delay module, the serial-to-parallel conversion module and the data combination module are all integrated on the FPGA, thereby providing a high-speed clock for LVDS data transmission; based on this, the present invention uses a high-speed clock to independently collect the LVDS data positive line and negative line, and then combines the data to realize LVDS data reception, thereby avoiding the level conversion process of two lines to a single line, and can adapt to higher-speed data transmission; (2) In the FPGA-based LVDS format data receiving system created by the present invention, by adopting the positive line and negative line independent sampling method, it is more adaptable to LVDS data of different bit widths, more flexible and more portable. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings: Figure 1 The present invention is a schematic diagram of the structure of an FPGA-based LVDS format data receiving system described in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the invention more clear, the invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the invention and do not constitute a limitation of the invention.

[0017] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0018] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0019] In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0020] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0021] like Figure 1 As shown, the FPGA-based LVDS format data receiving system described in the embodiment of the present invention includes an LVDS data conversion module, an interface delay module, a serial-to-parallel conversion module and a data combination module integrated on the FPGA. In the process of LVDS data reception, a high-speed clock is required to parse the LVDS data. The high-speed clock is usually generated by an external input or an internal phase-locked loop of the FPGA, and is usually above 200Mbps. Each module in the embodiment of the present invention is implemented based on a mature IP module provided by an FPGA device manufacturer. The calling module in the embodiment of the present invention includes but is not limited to ISERDESLVDS of AMD Xilinx.

[0022] The external two-wire serial signal is transmitted to the FPGA chip through a physical connection, wherein the external two-wire serial signal includes a serial LVDS positive line P signal and a serial LVDS negative line N signal. Since the FPGA device usually does not accept the direct connection between the delay module and the I / O (input / output) pin of the FPGA, it is necessary to rely on other cache modules for bridging, so it is necessary to perform level conversion on the input LVDS signal. The conventional signal receiving and conversion method is to use an LVDS to TTL (transistor-transistor logic level) level conversion module to convert the two-wire serial signal into a single-wire signal to achieve the preliminary level conversion of the LVDS data. In an embodiment of the present invention, the LVDS data conversion module converts the level of the two-wire serial signal into the level of the two-wire serial signal inside the FPGA while retaining the two-wire serial signal. Specifically, the LVDS data conversion module converts the two-wire serial signal into an LVDS positive line P signal and an LVDS negative line N signal respectively, and the levels of the LVDS positive line P signal and the LVDS negative line N signal are the levels inside the FPGA.

[0023] The interface delay module receives the two-line output signal of the LVDS data conversion module, and provides transmission delay superposition for the input two-line signal, which can adjust the forward and backward displacement of the single-line signal in the time dimension. Among them, the interface delay module includes a P signal delay submodule and an N signal delay submodule. The P signal delay submodule provides transmission delay superposition for the LVDS positive line P signal, and the N signal delay submodule provides transmission delay superposition for the LVDS negative line N signal.

[0024] The serial-to-parallel conversion module receives the two-line output signal of the interface delay module and converts the serial input signal into a parallel two-line output signal. Among them, the serial-to-parallel conversion module includes a P signal conversion submodule and an N signal conversion submodule. The P signal conversion submodule converts the signal output by the P signal delay submodule into a parallel LVDS positive line P signal, and the N signal conversion submodule converts the signal output by the N signal delay submodule into a parallel LVDS negative line N signal. The P signal conversion submodule and the N signal conversion submodule are configured in the SDR data rate mode, which is different from the DDR data rate mode in the traditional serial-to-parallel conversion module. The SDR data rate mode belongs to single clock edge sampling, which has low requirements for the input clock frequency and can effectively improve the stability of the system. The serial-to-parallel conversion range of the two submodules is 2-8bit, that is, a single-line serial signal input can achieve parallel output of 2bit to 8bit bit width data.

[0025] The data combination module combines the two-line output signals of the serial-to-parallel conversion module to obtain the final LVDS parallel data. The data combination module receives and combines the parallel LVDS positive line P signal and the parallel LVDS negative line N signal by signal crossing or signal splicing. For example, when the parallel LVDS positive line P signal and the parallel LVDS negative line N signal are combined by signal crossing, the final LVDS parallel data is PNPNPNPN... (where P represents one signal in the parallel LVDS positive line P signal, and N represents one signal in the parallel LVDS negative line N signal); when the parallel LVDS positive line P signal and the parallel LVDS negative line N signal are combined by signal splicing, the final LVDS parallel data is PPPPNNNN... This type of data integration uses different integration methods according to specific needs.

[0026] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An LVDS format data receiving system based on FPGA, characterized in that: It includes an LVDS data conversion module, an interface delay module, a serial-to-parallel conversion module and a data combination module integrated on the FPGA; wherein the LVDS data conversion module collects the level of an external two-wire serial signal and converts it into the level of a two-wire serial signal inside the FPGA; the interface delay module receives the two-wire output signal of the LVDS data conversion module and provides independent transmission delay superposition for the two-wire input signal; the serial-to-parallel conversion module receives the two-wire output signal of the interface delay module and converts the two-wire serial input signal into a two-wire parallel output signal; the data combination module performs data combination on the two-wire parallel output signal of the serial-to-parallel conversion module to obtain final LVDS parallel data.

2. The FPGA-based LVDS format data receiving system according to claim 1, characterized in that: The external two-wire serial signal includes a serial LVDS positive line P signal and a serial LVDS negative line N signal; the LVDS data conversion module converts the two-wire signal into a LVDS positive line P signal and a LVDS negative line N signal respectively, and the levels of the LVDS positive line P signal and the LVDS negative line N signal are the levels of the two-wire serial signal inside the FPGA.

3. The FPGA-based LVDS format data receiving system according to claim 2, characterized in that: The interface delay module includes a P signal delay submodule and an N signal delay submodule; wherein the P signal delay submodule provides transmission delay superposition for the LVDS positive line P signal; and the N signal delay submodule provides transmission delay superposition for the LVDS negative line N signal.

4. The FPGA-based LVDS format data receiving system according to claim 3, characterized in that: The serial-to-parallel conversion module includes a P signal conversion submodule and an N signal conversion submodule; wherein the P signal conversion submodule converts the signal output by the P signal delay submodule into a parallel LVDS positive line P signal; and the N signal conversion submodule converts the signal output by the N signal delay submodule into a parallel LVDS negative line N signal.

5. The FPGA-based LVDS format data receiving system according to claim 4, characterized in that: The P signal conversion submodule and the N signal conversion submodule are configured in an SDR data rate mode.

6. The FPGA-based LVDS format data receiving system according to claim 4, characterized in that: The serial-to-parallel conversion range of the P signal conversion submodule and the N signal conversion submodule is 2-8 bits.

7. The FPGA-based LVDS format data receiving system according to claim 4, characterized in that: The data combination module receives and combines the parallel LVDS positive line P signal and the parallel LVDS negative line N signal to obtain final LVDS parallel data.

8. The FPGA-based LVDS format data receiving system according to claim 7, characterized in that: The data combination module combines the parallel LVDS positive line P signal and the parallel LVDS negative line N signal by signal crossing or signal splicing.

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