Formation method of semiconductor structure, semiconductor structure, device and apparatus

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure forming method, a semiconductor structure, a device and a device. The method comprises: providing an initial semiconductor structure; forming a side wall structure positioned on the side wall of the control gate structure, at least one tunneling oxide layer positioned in the erasing gate region and a gate oxide layer positioned in the logic region; the gate oxide layer comprises a first type of gate oxide layer and a second type of gate oxide layer, and the gate oxide layer, the side wall structure and the tunneling oxide layer are synchronously formed; and forming a target gap oxide layer based on the side wall structure, forming a target first-type gate oxide layer based on the first-type gate oxide layer, forming a target tunneling oxide layer based on the tunneling oxide layer, and forming a target second-type gate oxide layer based on the second-type gate oxide layer to obtain a target semiconductor structure. The gap oxide layer is prepared on the basis of the stacked side walls, accurate control over the thickness of the gap oxide layer can be achieved, and therefore the uniformity of the gap oxide layer is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] With the rapid development and popularization of embedded devices, various embedded devices have been designed and developed. Flash memory has become an important data storage medium for various embedded devices due to its advantages such as high performance, low power consumption and non-volatility. Flash memory usually includes structures such as word line (WL) and floating gate (FG). In order for flash memory to achieve efficient memory performance, the gap oxide structure between the word line and the floating gate is crucial.

[0003] At present, the preparation process of flash memory is relatively complex, usually including logic process and flash memory process. The gap oxide layer between the word line and the floating gate is not only affected by the flash memory process, but also by the logic process. Since the two processes have different requirements, a balance needs to be made between the two processes during the preparation process, which makes it difficult to control the consistency of the gap oxide layer in the flash memory, which will cause the device performance to decline and lead to poor yield. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a method for forming a semiconductor structure, a semiconductor structure, a device and an apparatus.

[0005] In a first aspect, an embodiment of the present application discloses a method for forming a semiconductor structure, the method comprising:

[0006] Providing an initial semiconductor structure; the initial semiconductor structure includes a flash memory area and a logic area; the flash memory area includes a control gate area and an erase gate area, and a control gate structure is formed on the surface of the control gate area; the logic area includes a first type of logic gate area and a second type of logic gate area;

[0007] Forming a sidewall structure located on the sidewall of the control gate structure, at least one tunneling oxide layer located in the erase gate region, and a gate oxide layer located in the logic region; the gate oxide layer includes at least one first-type gate oxide layer located in the first-type logic gate region and at least one second-type gate oxide layer located in the second-type logic gate region, and the gate oxide layer is formed synchronously with the sidewall structure and the tunneling oxide layer;

[0008] A target gap oxide layer is formed based on the sidewall structure, a target first-type gate oxide layer is formed based on the first-type gate oxide layer, a target tunneling oxide layer is formed based on the tunneling oxide layer, and a target second-type gate oxide layer is formed based on the second-type gate oxide layer to obtain a target semiconductor structure.

[0009] In a second aspect, an embodiment of the present application discloses a semiconductor structure, including: a logic area and a flash memory area;

[0010] A logic area and a flash memory area; the logic area includes a first type of logic gate area and a second type of logic gate area; the flash memory area includes a control gate area and an erase gate area;

[0011] A target first-type gate oxide layer located on the surface of the first-type logic gate region; the target first-type gate oxide layer is obtained based on at least one first-type gate oxide layer;

[0012] A target second type gate oxide layer located on the surface of the second type logic gate region; the target second type gate oxide layer is obtained based on at least one layer of the second type gate oxide layer;

[0013] A control gate structure is located on the surface of the control gate region, and a target gap oxide layer is formed on the sidewall of the control gate structure; the target gap oxide layer is obtained based on the sidewall structure sequentially formed on the sidewall of the control gate structure;

[0014] A target tunneling oxide layer is formed on the surface of the erase gate region; the target tunneling oxide layer is obtained based on at least one tunneling oxide layer.

[0015] In a third aspect, an embodiment of the present application discloses a memory device, which includes the semiconductor structure as described above.

[0016] In a fourth aspect, an embodiment of the present application discloses an electronic device, which includes the storage device described above.

[0017] The technical solution has the following technical effects:

[0018] The semiconductor structure formation method, semiconductor structure, device and apparatus described in the embodiments of the present application are formed by forming a sidewall structure located on the sidewall of the control gate structure, at least one tunneling oxide layer located in the erase gate region and a gate oxide layer located in the logic region. The gate oxide layer includes at least one first-type gate oxide layer located in the first-type logic gate region and at least one second-type gate oxide layer located in the second-type logic gate region. The gate oxide layer is formed synchronously with the sidewall structure and the tunneling oxide layer, and a target gap oxide layer is formed based on the sidewall structure, and a target first-type gate oxide layer is formed based on the first-type gate oxide layer, and a target tunneling oxide layer is formed based on the tunneling oxide layer, and a target second-type gate oxide layer is formed based on the second-type gate oxide layer to obtain a target semiconductor structure. This solution can combine the flash memory process and the logic process, and can simultaneously realize the preparation of the gap oxide layer, the first-type gate oxide layer, the tunneling oxide layer and the second-type gate oxide layer, thereby improving the preparation efficiency of flash memory devices. At the same time, when preparing the oxide layers in the erase gate area, the first type of logic gate area and the second type of logic gate area, multiple stacked side walls can be obtained on the side walls of the control gate structure. The gap oxide layer is prepared based on these side walls, and the thickness of the gap oxide layer can be precisely controlled, thereby improving the uniformity of the gap oxide layer, thereby improving the performance of the flash device, and improving the preparation yield of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 is a schematic diagram of the structure of a flash memory device;

[0021] Figure 2 It is a schematic diagram of scanning the microstructure of oxide layers with different gaps in a flash memory device;

[0022] Figure 3 is a schematic diagram of test results of a flash memory device;

[0023] Figure 4 is a schematic flow chart of a method for forming a semiconductor structure provided in an embodiment of the present application;

[0024] Figure 5 to Figure 15 is a structural schematic diagram of a semiconductor structure formation process provided by an embodiment of the present application;

[0025] Fig.16 is a schematic diagram of test results of another flash memory device provided in an embodiment of the present application;

[0026] Fig.17 It is a structural schematic diagram of a semiconductor structure provided in an embodiment of the present application.

[0027] The following is a supplementary description of the attached drawings:

[0028] 11-floating gate; 12-word line; 13-control gate; 14-gap oxide layer; 15-erase gate; 16-high voltage logic gate region; 17-medium voltage logic gate region; 18-low voltage logic gate region; 1-substrate; 100-flash memory region; 101-first oxide layer; 102-second oxide layer; 103-third oxide layer; 104-fourth oxide layer; 105-fifth oxide layer; 110-erase gate region; 111-target tunneling oxide layer; 112-erase gate; 120-control gate region; 121-floating gate oxide layer; 122-floating gate; 123-dielectric layer; 124-control gate; 1200-target gap oxide layer; 1201-first oxide layer; 1202-second oxide layer; 1203-third oxide layer; 1204-fourth oxide layer; 1205-fifth oxide layer; 110-erase gate region; 111-target tunneling oxide layer; 112-erase gate; 120-control gate region; 121-floating gate oxide layer; 122-floating gate; 123-dielectric layer; 124-control gate; 1200-target gap oxide layer; 1201-third oxide layer; 1202-third oxide layer; 1203-third oxide layer; 1204-third oxide layer; 1205-fifth oxide layer; 110-flash memory region; 111-target tunneling oxide layer; 112-flash memory region; 112-flash memory region; 113-flash memory region; 114-flash memory region; 115-flash memory region; 116-flash memory region; 117-flash memory region; 118-f A side wall; 1202-a second side wall; 1203-a third side wall; 1204-a fourth side wall; 1205-a fifth side wall; 131-a first sacrificial layer; 132-a second sacrificial layer; 133-a third sacrificial layer; 134-a fourth sacrificial layer; 140-a word line region; 141-a word line; 200-a logic region; 210-a logic gate region; 211-a target first gate oxide layer; 212-a target second gate oxide layer; 213-a target third gate oxide layer 213; 221-a first logic gate; 222-a second logic gate; 223-a third logic gate; 231-a first logic gate region; 232-a second logic gate region; 233-a third logic gate region. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0030] It should be noted that the "one embodiment" or "embodiment" referred to in the specification of the embodiment of the present application refers to a specific feature, structure or characteristic that can be included in at least one implementation of the present application. It should be understood that in the specification and claims of the embodiment of the present application and the above-mentioned drawings, the orientation or position relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, in the description of the present embodiment, unless otherwise specified, "plurality" means two or more. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system or product including a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] In order to make the purpose, technical solution and advantages disclosed in the embodiments of the present application more clear, the embodiments of the present application are further described in detail in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present application and are not used to limit the embodiments of the present application.

[0032] See also Figure 1 , Figure 1 is a schematic diagram of the structure of a flash memory device, such as Figure 1 As shown, the flash memory device includes a flash memory area and a logic area. A word line 12, a floating gate 11, a control gate (CG) 13 and an erasing gate (EG) 15 are formed in the flash memory area. A tunneling oxide layer is formed under the erasing gate. A gap oxide layer 14 ( Figure 1The oxide layer structure can affect the erase current (IR1) of the flash memory device, thereby affecting the performance of the flash memory device. The logic area includes a high voltage (High voltage, HV) logic gate area 16, a middle voltage (Middle voltage, MV) logic gate area 17, and a low voltage (Low voltage, LV) logic gate area 18. Different voltage logic areas have gate oxide layers of different thicknesses. Therefore, the thickness of the gap oxide layer between the word line 12 and the floating gate 11 is not only affected by the preparation process of the flash memory area, but also by the preparation process of the gate oxide layer in the high, middle and low areas of the logic area, making it difficult to control the uniformity of the thickness of the gap oxide layer between the word line 12 and the floating gate 11.

[0033] The non-uniformity of the gap oxide layer thickness is not only reflected between different gap oxide layers in the same flash memory device, but also reflected between different flash memory devices fabricated on the same wafer. Figure 2 It is a schematic diagram of the microstructure scanning of different gap oxide layers in a flash memory device, such as Figure 2 As shown, the average thickness of the gap oxide layer on the left side (gap OX THK avg) is 378 angstroms, and the thickness of the gap oxide layer on the right side is 346 angstroms. The erase current corresponding to the gap oxide layer on the left side is 18 μA, and the erase current corresponding to the gap oxide layer on the right side is 13 μA. Figure 3 is a schematic diagram of the test results of a flash memory device, such as Figure 3 As shown, by performing a current test on the storage cells of the flash memory devices in a test group (Group: 1), it can be found that the interfaces (I / O) of the storage cells of some flash memory devices in the test group have a low erase current (IR1), that is, the erase current consistency is poor. The poor consistency of the erase current will directly affect the yield of the flash memory device. According to statistics, the yield of the above flash memory devices is about 60%. Therefore, how to form an excellent gap oxide layer and balance the process contradictions caused by the structural differences between the flash memory area and the logic area is an urgent problem to be solved.

[0034] In view of this, an embodiment of the present application provides a method for forming a semiconductor structure. Figure 4 is a schematic flow chart of a method for forming a semiconductor structure provided in an embodiment of the present application, such as Figure 4 As shown, the method includes:

[0035] S101: providing an initial semiconductor structure; the initial semiconductor structure comprises a flash memory region and a logic region; the flash memory region comprises a control gate region and an erase gate region, a control gate structure is formed on the surface of the control gate region; the logic region comprises a first type of logic gate region and a second type of logic gate region.

[0036] In the embodiment of the present application, the initial semiconductor structure refers to a semiconductor structure obtained by completing the preparation of a part of the device structure during the preparation process of the flash memory device. Figure 5 is a schematic diagram of an initial semiconductor structure provided in an embodiment of the present application, such as Figure 5 As shown, the initial semiconductor structure includes a substrate 1. Optionally, the substrate 1 may be one of semiconductor substrates such as a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, and a silicon germanium substrate. As an example, the substrate 1 in the initial semiconductor structure may be a single crystal silicon substrate. When preparing a flash memory device, the substrate 1 may be divided into a flash memory area 100 and a logic area 200, wherein a flash memory cell structure may be prepared on the flash memory area 100, and a logic gate structure may be prepared on the logic area 200. Optionally, a shallow trench may be formed on the surface of the substrate 1 by a shallow trench process, thereby dividing the substrate 1 into a flash memory area 100 and a logic area 200.

[0037] like Figure 5 As shown, at least one control gate region 120 is formed on the surface of the flash memory region 100 in the substrate 1, and a control gate structure (not marked) is formed on each control gate region 120. In the flash memory region 100, the number of control gate structures can be one, or two or more. Generally speaking, there can be two control gate structures in a flash memory device. For any control gate structure, it can include a floating gate oxide layer 121 formed on the surface of the substrate 1, a floating gate 122 formed on the surface of the floating gate oxide layer 121, a dielectric layer 123 formed on the floating gate 122, and a control gate 124 formed on the dielectric layer 123. In some embodiments, an oxide layer and a silicon nitride layer located on the oxide layer can also be formed on the control gate 124. The area adjacent to the control gate structure in the flash memory region 100 is an erase gate region 110. Optionally, the erase gate region 110 is formed between two adjacent control gate structures.

[0038] like Figure 5 As shown, at least one logic gate region 210 is formed in the logic region 200 in the substrate 1. These logic gate regions 210 can be divided into a first type of logic gate region and a second type of logic gate region according to the thickness of the gate oxide layer to be formed thereon. Among them, the first type of logic gate region refers to the gate oxide layer to be formed thereon with a thickness greater than the thickness of the tunnel oxide layer, and the second type of logic gate region refers to the gate oxide layer to be formed thereon with a thickness less than the thickness of the tunnel oxide layer. Optionally, the first type of logic gate region includes at least one logic gate region 210, and the second type of logic gate region includes at least one logic gate region 210. As an example, Figure 5As shown, three logic gate regions 210 are formed in the logic region 200, wherein the first logic gate region 231 is a first type of logic gate region, and the second logic gate region 232 and the third logic gate region 233 are second type of logic gate regions. In some embodiments, the first logic gate region 231 may be a high voltage logic gate region, the second logic gate region 232 may be a medium voltage logic gate region, and the third logic gate region 233 may be a low voltage logic gate region. Among them, high voltage, medium voltage and low voltage refer to the turn-on voltage of the logic gate. For example, the turn-on voltage of the logic gate formed on the high voltage logic gate region may be 5V, the turn-on voltage of the logic gate formed on the medium voltage logic gate region may be 3.3V, and the turn-on voltage of the logic gate formed on the low voltage logic gate region may be 1.5V. It should be noted that, generally speaking, the higher the turn-on voltage of the logic gate, the thicker the gate oxide layer needs to be formed in the corresponding logic gate region 210.

[0039] S103: forming a sidewall structure located on the sidewall of the control gate structure, at least one tunneling oxide layer located in the erase gate region, and a gate oxide layer located in the logic region; the gate oxide layer includes at least one first-type gate oxide layer located in the first-type logic gate region and at least one second-type gate oxide layer located in the second-type logic gate region, and the gate oxide layer is formed synchronously with the sidewall structure and the tunneling oxide layer.

[0040] In the embodiment of the present application, after obtaining the initial semiconductor structure, the target semiconductor structure can be prepared based on the initial semiconductor structure. Optionally, the target semiconductor structure refers to the semiconductor structure after the target gap oxide layer 1200, the tunneling oxide layer, the first type of gate oxide layer and the second type of gate oxide layer are prepared in the process of preparing the flash memory device. The target semiconductor structure can also be the semiconductor structure obtained after the flash memory device is prepared. When preparing the target semiconductor structure, the target gap oxide layer 1200, the tunneling oxide layer, the first type of gate oxide layer and the second type of gate oxide layer can be prepared simultaneously by combining the flash memory process and the logic process. Specifically, according to the design of the flash memory device structure size, the preparation scheme of the target gap oxide layer 1200, the tunneling oxide layer, the first type of gate oxide layer and the second type of gate oxide layer can be designed to be deposited through several oxide layers to achieve the corresponding thicknesses. Optionally, the materials of the target gap oxide layer 1200, the tunneling oxide layer, the first type of gate oxide layer and the second type of gate oxide layer are all silicon oxide.

[0041] In the embodiment of the present application, when the target gap oxide layer 1200, the tunnel oxide layer, the first type of gate oxide layer and the second type of gate oxide layer are prepared at the same time, since the thickness of the target gap oxide layer 1200 is usually thicker, the first oxide layer 101 can be first deposited on the sidewall of the control gate structure to form a first sidewall 1201 on the sidewall of the control gate structure, and the first sidewall 1201 is used to make the target gap oxide layer structure (not marked). Optionally, the thickness of the first oxide layer 101 is 250 angstroms to 280 angstroms. For example, 250 angstroms, 255 angstroms, 260 angstroms, 265 angstroms, 270 angstroms, 275 angstroms, 280 angstroms, etc.

[0042] In the embodiment of the present application, when the first oxide layer 101 is deposited on the sidewall of the control gate structure, an optional implementation is to shield the erase gate region 110, the first type logic gate region and the second type logic gate region by making a mask, exposing only the control gate region 120, and then depositing the first oxide layer 101 on the surface of the control gate region 120. Due to the shielding of the mask, the first oxide layer 101 can only be deposited in the control gate region 120, so that the first sidewall 1201 composed of the first oxide layer 101 can be formed only on the sidewall of the control gate structure.

[0043] In the embodiment of the present application, in order to reduce the complexity of the process, improve the preparation efficiency and improve the process control accuracy, when the first sidewall spacer 1201 is formed on the sidewall of the control gate structure, another optional implementation is to deposit the first oxide layer 101 on the entire surface of the initial semiconductor structure. Specifically, the first oxide layer 101 is deposited on the surface of the control gate region 120, the erase gate region 110, the first type of logic gate region and the second type of logic gate region, so as to form the first sidewall spacer 1201 on the sidewall of the control gate structure. Optionally, the process of depositing the first oxide layer 101 can be a high temperature oxidation deposition (HTO) process, a chemical vapor deposition tetraethoxysilane (TEOS) process, an in-situ steam generation (ISSG) process, etc. In some embodiments, the process of depositing the first oxide layer 101 can also be a chemical vapor deposition process or a physical vapor deposition process, etc.

[0044] In the embodiment of the present application, after the first oxide layer 101 is deposited on the surface of the initial semiconductor structure, a first semiconductor structure can be obtained. Figure 6 is a schematic structural diagram of a first semiconductor structure provided in an embodiment of the present application, such as Figure 6As shown, the surface of the first semiconductor is covered by the first oxide layer 101, and the sidewall of the control gate structure forms a first sidewall 1201. After the deposition of the first oxide layer 101 is completed, the surface of the initial semiconductor structure except the control gate region 120 can also be etched by an etching process to remove the first oxide layer 101 deposited in other regions. Optionally, the etching process can be dry etching. Since the principle of dry etching is to bombard the surface of the etched object with plasma, dry etching is used to remove the first oxide layer 101, and the first sidewall 1201 formed on the sidewall of the control gate structure will not be damaged. In some embodiments, in order to avoid damage to the substrate 1 in the initial semiconductor structure, when the first oxide layer 101 is removed by dry etching, part of the first oxide layer 101 can be left to protect the substrate 1.

[0045] It should be noted that it is not necessary to etch the first oxide layer 101 deposited in other regions, because in the subsequent preparation of the tunneling oxide layer, the first type of gate oxide layer and the second type of gate oxide layer, in order to control the thickness of the oxide layer in different regions, the oxide layer previously deposited in each region will be removed. However, the use of dry etching to remove the first oxide layer 101 in other regions can improve the efficiency of subsequent removal of the oxide layer in each region. Therefore, whether to use dry etching to remove the first oxide layer 101 in other regions can be independently selected according to actual process needs, and this process does not require creative labor.

[0046] In the embodiment of the present application, after forming the first sidewall spacer 1201 on the sidewall of the control gate structure, a first type of gate oxide layer with a first preset thickness can be formed on the first type of logic gate region, and a second sidewall spacer 1202 can be formed on the sidewall of the first sidewall spacer 1201. Specifically, by depositing the second oxide layer 102 on the surface of the first semiconductor structure, the second sidewall spacer 1202 is formed on the sidewall of the first sidewall spacer 1201, and at the same time, the first type of gate oxide layer with a first preset thickness is formed in the first type of logic gate region. The first preset thickness is the same as the thickness of the second oxide layer 102, and the first sidewall spacer 1201 and the second sidewall spacer 1202 are used to make the target gap oxide layer 1200. Optionally, the thickness of the second oxide layer 102 is 40 angstroms to 70 angstroms. For example, 40 angstroms, 45 angstroms, 50 angstroms, 55 angstroms, 60 angstroms, 65 angstroms, 70 angstroms, etc.

[0047] In the embodiment of the present application, when forming the first type gate oxide layer, if the first oxide layer 101 is not deposited in the first type logic gate region, the second oxide layer 102 can be directly deposited on the control gate region 120, the erase gate region 110, the first type logic gate region and the second type logic gate region, so as to form the second spacer 1202 on the sidewall of the first spacer 1201, and simultaneously form the first type gate oxide layer of partial thickness in the first type logic gate region. If the first oxide layer 101 is deposited in the first type logic gate region, in order to achieve precise control of the thickness of the first type gate oxide layer, the first oxide layer 101 on the surface of the first type logic gate region can be removed first, and then the second oxide layer 102 can be deposited on the control gate region 120, the erase gate region 110, the first type logic gate region and the second type logic gate region, so that the second spacer 1202 can be formed on the sidewall of the first spacer 1201, and the first type gate oxide layer of partial thickness can be formed in the first type logic gate region. In another embodiment, if a first oxide layer 101 is deposited in the first type of logic gate region, after depositing the second oxide layer 102, a portion of the thickness of the second oxide layer 102 in the first type of logic gate region may be removed, or the second oxide layer 102 and a portion of the thickness of the first oxide layer 101 in the first type of logic gate region may be removed, so that the thickness of the first type of gate oxide layer in the first type of logic gate region is the same as the thickness of the second oxide layer 102.

[0048] Specifically, taking the first type of logic gate region including the first logic gate region 231 as an example, if a first oxide layer 101 is deposited in the first logic gate region 231, the first sacrificial layer 131 can be covered on the surface of the first semiconductor structure and the first logic gate region 231 can be exposed, thereby removing the first oxide layer 101 in the first logic gate region 231. Figure 7 is a schematic diagram of a structure after a first sacrificial layer is covered on the surface of a first semiconductor structure provided by an embodiment of the present application, such as Figure 7 As shown, the first sacrificial layer 131 covers the control gate region 120, the erase gate region 110 and the second type of logic gate region, and only the first logic gate region 231 is exposed, and then the first oxide layer 101 in the first logic gate region 231 is removed by an etching process. Optionally, the first sacrificial layer 131 can be made of photoresist (PR). When etching the first oxide layer 101 in the first logic gate region 231, a combination of dry etching and wet etching can be used to completely remove the first oxide layer 101 in the first logic gate region 231. In some embodiments, the first oxide layer 101 in the first logic gate region 231 can also be completely removed by only wet etching.

[0049] Figure 8 is a schematic diagram of a structure after a second oxide layer is deposited on the surface of a first semiconductor structure provided by an embodiment of the present application, such as Figure 8As shown, after the first oxide layer 101 in the first logic gate region 231 is completely removed, the first sacrificial layer 131 can be removed. Then, the second oxide layer 102 is deposited on the surface of the first semiconductor structure, so that the second spacer 1202 can be formed outside the first spacer 1201, and at the same time, a first gate oxide layer of a partial thickness is formed in the first logic gate region 231. Optionally, the process of depositing the second oxide layer 102 includes but is not limited to a high temperature oxidation deposition process, an in-situ water vapor generation process, a chemical vapor deposition process, a physical vapor deposition process, etc.

[0050] It should be noted that when the first type of logic gate region includes multiple logic gate regions 210, the above process of depositing the second oxide layer 102 can be divided into multiple repeated preparation processes. For example, the first type of logic gate region includes a first sub-logic gate region and a second sub-logic gate region, and the thickness of the corresponding first sub-gate oxide layer in the first sub-logic gate region is greater than the thickness of the corresponding second sub-gate oxide layer in the second sub-logic gate region. Then, the first oxide layer 101 in the first sub-logic gate region can be removed first, and then a second oxide layer 102 is deposited on the surface of the first semiconductor structure. Then, the first oxide layer 101 and the second oxide layer 102 in the second sub-logic gate region are removed, and then a second oxide layer 102 is deposited on the surface of the first semiconductor structure.

[0051] In the embodiment of the present application, after the second oxide layer 102 is deposited on the surface of the first semiconductor structure, a second semiconductor structure can be obtained. In the second semiconductor structure, a first sidewall 1201 and a second sidewall 1202 are formed on the sidewall of the control gate structure, and a first type of gate oxide layer with a first preset thickness is formed in the first type of logic gate region. Then, a third oxide layer 103 can be deposited on the surface of the second semiconductor structure to form a third sidewall 1203 outside the second sidewall 1202, and to form a first type of gate oxide layer with a second preset thickness. At the same time, a tunneling oxide layer with a third preset thickness can also be formed in the erase gate region 110 at the same time. Among them, the first sidewall 1201, the second sidewall 1202 and the third sidewall 1203 are used to make the target gap oxide layer 1200. The second preset thickness and the third preset thickness are both the same as the thickness of the third oxide layer 103. Optionally, the thickness of the third oxide layer 103 is 100 angstroms-140 angstroms. For example, 100 angstroms, 105 angstroms, 110 angstroms, 115 angstroms, 120 angstroms, 125 angstroms, 130 angstroms, 135 angstroms, 140 angstroms, etc.

[0052] In the embodiment of the present application, when a tunneling oxide layer of a partial thickness is formed in the erase gate region 110, if the first oxide layer 101 is not deposited in the erase gate region 110, only the second oxide layer 102 deposited in the erase gate region 110 is removed. If the first oxide layer 101 is deposited in the erase gate region 110, it is necessary to remove the first oxide layer 101 and the second oxide layer 102 deposited in the erase gate region 110. Specifically, taking the removal of the first oxide layer 101 and the second oxide layer 102 deposited in the erase gate region 110 as an example, the second sacrificial layer 132 can be covered on the surface of the second semiconductor structure, and the erase gate region 110 is exposed, so as to remove the first oxide layer 101 and the second oxide layer 102 in the erase gate region 110. Fig. 9 is a schematic diagram of a structure after a second sacrificial layer is covered on the surface of a second semiconductor structure provided by an embodiment of the present application, such as Fig. 9 As shown, the second sacrificial layer 132 covers the control gate region 120, the first type logic gate region and the second type logic gate region, and only exposes the erase gate region 110, and then the first oxide layer 101 and the second oxide layer 102 in the erase gate region 110 are removed by an etching process. Optionally, the second sacrificial layer 132 can be made of photoresist. When etching the first oxide layer 101 and the second oxide layer 102 in the erase gate region 110, a combination of dry etching and wet etching can be used to completely remove the first oxide layer 101 and the second oxide layer 102 in the erase gate region 110. In some embodiments, the first oxide layer 101 and the second oxide layer 102 in the erase gate region 110 can also be completely removed by only wet etching.

[0053] In the embodiment of the present application, Fig.10 is a schematic diagram of a structure after a third oxide layer is deposited on the surface of a second semiconductor structure provided in an embodiment of the present application, such as Fig.10 As shown, after the oxide layer in the erase gate region 110 is completely removed, the second sacrificial layer 132 can be removed. Then, a third oxide layer 103 is deposited on the surface of the second semiconductor structure, so that the third spacer 1203 can be formed outside the second spacer 1202, and at the same time, a first type of gate oxide layer with a partial thickness is formed in the first type of logic gate region, and a tunnel oxide layer with a partial thickness is formed in the erase gate region 110. Optionally, the process of depositing the third oxide layer 103 includes but is not limited to a high temperature oxidation deposition process, an in-situ water vapor generation process, a chemical vapor deposition process, a physical vapor deposition process, etc.

[0054] In the embodiment of the present application, after the third oxide layer 103 is deposited on the surface of the second semiconductor structure, a third semiconductor structure can be obtained. In the third semiconductor structure, a stacked first sidewall 1201, a second sidewall 1202 and a third sidewall 1203 are formed on the sidewall of the control gate structure, a first gate oxide layer with a partial thickness is formed in the first type of logic gate region, and a tunnel oxide layer with a partial thickness is formed in the erase gate region 110. Then, a fourth oxide layer 104 can be deposited on the surface of the third semiconductor structure to form a fourth sidewall 1204 outside the third sidewall 1203, and to form a first gate oxide layer and a tunnel oxide layer with a partial thickness. At the same time, a second gate oxide layer with a partial thickness can also be formed in the second type of logic gate region.

[0055] In the embodiment of the present application, when a second type of gate oxide layer of partial thickness is formed in the second type of logic gate region, if the first oxide layer 101 is not deposited in the second type of logic gate region, the second oxide layer 102 and the third oxide layer 103 deposited in the second type of logic gate region are removed. If the first oxide layer 101 is deposited in the second type of logic gate region, the first oxide layer 101, the second oxide layer 102 and the third oxide layer 103 deposited in the second type of logic gate region need to be removed. The second type of logic gate region may include one or more logic gate regions 210. When multiple logic gate regions 210 are included, the oxide layer in the logic gate region 210 corresponding to the thicker gate oxide layer thickness may be removed first.

[0056] In an embodiment of the present application, after the oxide layer deposited in the second-type logic gate region is removed, a fourth oxide layer 104 is deposited on the surface of the third semiconductor to form a fourth side wall 1204 outside the third side wall 1203, and at the same time, a first-type gate oxide layer of partial thickness is formed in the first-type logic gate region, a tunneling oxide layer of partial thickness is formed in the erase gate region 110, and a second-type gate oxide layer of partial thickness is formed in the second-type logic gate region.

[0057] In the embodiment of the present application, when the second type of logic gate region includes a plurality of logic gate regions 210, for example, the second type of logic gate region includes a second logic gate region 232 and a third logic gate region 233. When the fourth oxide layer 104 is deposited on the surface of the third semiconductor structure, the first oxide layer 101, the second oxide layer 102 and the third oxide layer 103 on the surface of the second logic gate region 232 may be removed first. Then, the fourth oxide layer 104 is deposited on the control gate region 120, the erase gate region 110, the first type of logic gate region and the second type of logic gate region to form a first type of gate oxide layer with a fourth preset thickness in the first type of logic gate region, a tunnel oxide layer with a fifth preset thickness in the erase gate region 110, a second gate oxide layer with a sixth preset thickness in the second logic gate region 232, and a fourth spacer 1204 on the sidewall of the third spacer 1203. Then, the first oxide layer 101, the second oxide layer 102, the third oxide layer 103 and the fourth oxide layer 104 on the surface of the third logic gate region 233 are removed. Finally, a fifth oxide layer 105 is deposited in the control gate region 120, the erase gate region 110, the first type of logic gate region and the second type of logic gate region to form a first type of gate oxide layer with a seventh preset thickness in the first type of logic gate region, a tunneling oxide layer with an eighth preset thickness in the erase gate region 110, a second gate oxide layer with a ninth preset thickness in the second logic gate region 232, a third type of gate oxide layer with a tenth preset thickness in the third logic gate region 233, and a fifth sidewall 1205 on the sidewall of the fourth sidewall 1204, to obtain a target semiconductor structure.

[0058] As an optional implementation, the thickness of the second gate oxide layer corresponding to the second logic gate region 232 is greater than the thickness of the third gate oxide layer corresponding to the third logic gate region 233. When removing the oxide layer in the second type of logic gate region, the oxide layer in the second logic gate region 232 may be removed first. Specifically, the third sacrificial layer 133 is covered on the surface of the third semiconductor structure, and the second logic gate region 232 is exposed, thereby removing the oxide layer in the second logic gate region 232. Fig.11 is a schematic diagram of a structure after a third sacrificial layer is covered on the surface of a third semiconductor structure provided by an embodiment of the present application, such as Fig.11As shown, the third sacrificial layer 133 covers the control gate region 120, the erase gate region 110, the first type logic gate region and the third logic gate region 233, and only the second logic gate region 232 is exposed, and then the oxide layer in the second logic gate region 232 is removed by an etching process. Optionally, the third sacrificial layer 133 can be made of photoresist. When etching the oxide layer in the second logic gate region 232, a combination of dry etching and wet etching can be used to completely remove the oxide layer in the second logic gate region 232. In some embodiments, the oxide layer in the second logic gate region 232 can also be completely removed by wet etching alone. Then, a fourth oxide layer 104 is deposited on the control gate region 120, the erase gate region 110, the first type logic gate region and the second type logic gate region to form a fourth sidewall 1204 on the sidewall of the third sidewall 1203.

[0059] Fig.12 is a schematic diagram of a structure after a fourth oxide layer is deposited on the surface of a third semiconductor structure provided in an embodiment of the present application, such as Fig.12 As shown, after the oxide layer in the second logic gate region 232 is completely removed, the third sacrificial layer 133 can be removed, and then the fourth oxide layer 104 can be deposited on the surface of the third semiconductor structure, so that the fourth sidewall 1204 can be formed on the outside of the third sidewall 1203, and at the same time, a first type gate oxide layer of a fourth preset thickness is formed in the first type logic gate region, a tunneling oxide layer of a fifth preset thickness is formed in the erase gate region 110, and a second gate oxide layer of a sixth preset thickness is formed in the second logic gate region 232. Wherein, the first sidewall 1201, the second sidewall 1202, the third sidewall 1203 and the fourth sidewall 1204 are used to make the target gap oxide layer 1200. Optionally, the process of depositing the fourth oxide layer 104 includes but is not limited to a high temperature oxidation deposition process, an in-situ water vapor generation process, a chemical vapor deposition process, a physical vapor deposition process, etc. Optionally, the fourth preset thickness and the fifth preset thickness can be 0, or can be the same as the thickness of the fourth oxide layer 104. The sixth preset thickness is the same as the thickness of the fourth oxide layer 104. Optionally, the thickness of the fourth oxide layer 104 is 40 angstroms to 80 angstroms, and specifically, may be 55 angstroms to 60 angstroms, such as 55 angstroms, 55.5 angstroms, 56 angstroms, 56.5 angstroms, 57 angstroms, 57.5 angstroms, 58 angstroms, 58.5 angstroms, 59 angstroms, 59.5 angstroms, 60 angstroms, and the like.

[0060] In a flash memory device, the second logic gate region 232 is usually formed between the first logic gate region 231 and the third logic gate region 233, and the gate oxide integrity (Gate Oxide Integrity, GOI) of the second gate oxide layer finally formed thereon may be affected by the first logic region and the second logic region. Therefore, in order to ensure the gate oxide integrity of the second gate oxide layer, a high-quality oxide deposition process can be used to make the second gate oxide layer, such as using an in-situ water vapor generation process to deposit the fourth oxide layer 104, so that a high-quality second gate oxide layer can be formed in the second logic gate region 232. Specifically, when the fourth oxide layer 104 is deposited in the control gate region 120, the erase gate region 110, the first type of logic gate region and the second type of logic gate region, the fourth oxide layer 104 can be deposited in the control gate region 120, the erase gate region 110, the first type of logic gate region and the second type of logic gate region based on the in-situ water vapor generation process to form a fourth sidewall 1204 on the sidewall of the third sidewall 1203. Since the in-situ water vapor generation process is based on the reaction between silicon and oxygen to generate an oxide layer, and the control gate region 120, the erase gate region 110, the first type of logic gate region and the third logic gate region 233 are all covered with an oxide layer, only the surface of the silicon substrate 1 in the second logic gate region 232 is exposed. Therefore, when the fourth oxide layer 104 is deposited using the in-situ water vapor generation process, the fourth oxide layer 104 will only be formed in the second logic gate region 232.

[0061] Next, after the fourth oxide layer 104 is deposited on the surface of the third semiconductor structure, the fourth semiconductor structure can be obtained. In the fourth semiconductor structure, the first sidewall 1201, the second sidewall 1202, the third sidewall 1203 and the fourth sidewall 1204 are formed on the sidewall of the control gate structure, the first type of gate oxide layer with a partial thickness is formed in the first type of logic gate area, the tunnel oxide layer with a partial thickness is formed in the erase gate area 110, and the second gate oxide layer with a partial thickness is formed in the second logic gate area 232. Then, the fifth oxide layer 105 can be deposited on the surface of the fourth semiconductor structure to form the fifth sidewall 1205 outside the fourth sidewall 1204, and to form the first type of gate oxide layer with a seventh preset thickness, the tunnel oxide layer with an eighth preset thickness and the second gate oxide layer with a ninth preset thickness. At the same time, the third gate oxide layer with a tenth preset thickness can also be formed in the third logic gate area 233 at the same time. Among them, the first sidewall spacer 1201, the second sidewall spacer 1202, the third sidewall spacer 1203, the fourth sidewall spacer 1204 and the fifth sidewall spacer 1205 are used to make the target gap oxide layer 1200. The seventh preset thickness, the eighth preset thickness, the ninth preset thickness and the tenth preset thickness are all the same as the thickness of the fifth oxide layer 105. Optionally, the thickness of the fifth oxide layer 105 is 5 angstroms to 40 angstroms. For example, 5 angstroms, 10 angstroms, 15 angstroms, 20 angstroms, 25 angstroms, 30 angstroms, 35 angstroms, 40 angstroms, etc.

[0062] Before forming the third gate oxide layer in the third logic gate region 233, it is necessary to remove the oxide layer in the third logic gate region 233. In addition, since the third logic gate region 233 is the last region where the oxide layer needs to be prepared, when removing the oxide layer in the third logic gate region 233, the oxide layer in the dual gate (DG) region in the fourth semiconductor structure can also be removed at the same time. Specifically, the flash memory region 100 also includes a word line region 140, the word line region 140 is adjacent to the control gate region 120, and the control gate region 120 is formed between the word line region 140 and the erase gate region 110. The dual gate region refers to the word line region 140 and a portion of the control gate region 120 adjacent to the word line region 140. A fourth sacrificial layer 134 is covered on the surface of the fourth semiconductor structure, and the dual gate region and the third logic gate region 233 are exposed, thereby removing the oxide layer in the dual gate region and the third logic gate region 233. Fig.13 is a schematic diagram of a structure after a fourth sacrificial layer is covered on the surface of a fourth semiconductor structure provided by an embodiment of the present application, such as Fig.13 As shown, the fourth sacrificial layer 134 is covered on the erase gate region 110 and the part of the control gate region 120 adjacent to the erase gate region 110, the first type logic gate region and the second logic gate region 232 in the fourth semiconductor structure. The word line region 140, the part of the control gate region 120 adjacent to the word line region 140 and the third logic gate region 233 are exposed, and then the oxide layer in the word line region 140, the part of the control gate region 120 adjacent to the word line region 140 and the third logic gate region 233 is removed by an etching process. Optionally, the fourth sacrificial layer 134 can be made of photoresist. When etching the oxide layer in the word line region 140, the part of the control gate region 120 adjacent to the word line region 140 and the third logic gate region 233, a combination of dry etching and wet etching can be used to achieve the removal of the oxide layer in the word line region 140, the part of the control gate region 120 adjacent to the word line region 140 and the third logic gate region 233. In some embodiments, a combination of dry etching and wet etching may be used to remove the oxide layer in the word line region 140, a portion of the control gate region 120 adjacent to the word line region 140, and the third logic gate region 233. In other embodiments, only wet etching may be used to remove the oxide layer in the word line region 140, a portion of the control gate region 120 adjacent to the word line region 140, and the third logic gate region 233.

[0063] It should be noted that when wet etching is used to remove the oxide layer in the dual-gate region, since the wet etching will perform side etching on the first sidewall spacer 1201, the second sidewall spacer 1202, the third sidewall spacer 1203 and the fourth sidewall spacer 1204 formed on the sidewall of the control gate structure, it is necessary to control the time of the wet etching to ensure that the target gap oxide layer 1200 produced subsequently can reach the target thickness. In some embodiments, in order not to affect the subsequent production of the target gap oxide layer 1200, the fourth sacrificial layer 134 may also cover the word line region 140 and the control gate region 120.

[0064] Fig.14 is a schematic diagram of a structure after a fifth oxide layer is deposited on the surface of a fourth semiconductor structure provided in an embodiment of the present application, such as Fig.14 As shown, after removing the oxide layers in the dual-gate region and the third logic gate region 233, the fourth sacrificial layer 134 can be removed, and then the fifth oxide layer 105 can be deposited on the surface of the fourth semiconductor structure, so that the fifth spacer 1205 can be formed on the outside of the fourth spacer 1204, and at the same time, the first type of gate oxide layer with a remaining thickness is formed in the first type of logic gate region, a tunneling oxide layer with an eighth preset thickness is formed in the erase gate region 110, a second gate oxide layer with a ninth preset thickness is formed in the second logic gate region 232, and a third gate oxide layer with a tenth preset thickness is formed in the third logic gate region 233. Optionally, the process of depositing the fifth oxide layer 105 includes but is not limited to a high temperature oxidation deposition process, a chemical vapor deposition process, a physical vapor deposition process, and the like.

[0065] S105: forming a target gap oxide layer based on the sidewall structure, forming a target first-type gate oxide layer based on the first-type gate oxide layer, forming a target tunneling oxide layer based on the tunneling oxide layer, and forming a target second-type gate oxide layer based on the second-type gate oxide layer to obtain a target semiconductor structure.

[0066] In the embodiment of the present application, after the first oxide layer 101, the second oxide layer 102, the third oxide layer 103, the fourth oxide layer 104 and the fifth oxide layer 105 are deposited in the initial semiconductor structure, the first sidewall 1201, the second sidewall 1202, the third sidewall 1203, the fourth sidewall 1204 and the fifth sidewall 1205 are sequentially formed on the sidewall of the control gate structure, and the sidewall structure formed by these five sidewalls constitutes an initial gap oxide layer. By removing the initial gap oxide layer of the target thickness, a target gap oxide layer 1200 of a preset thickness is obtained, thereby obtaining a target semiconductor structure. Optionally, the target thickness can be 200 angstroms-240 angstroms, such as 200 angstroms, 205 angstroms, 210 angstroms, 215 angstroms, 220 angstroms, 225 angstroms, 230 angstroms, 235 angstroms, 240 angstroms, etc.

[0067] It should be noted that after the preparation of the first sidewall 1201, the second sidewall 1202, the third sidewall 1203, the fourth sidewall 1204 and the fifth sidewall 1205 is completed, it is not necessary to remove the initial gap oxide layer of the target thickness. Removal of the initial gap oxide layer of the target thickness can also be achieved before forming the fifth sidewall 1205. When the oxide layer in the dual-gate region and the third logic gate region 233 is removed before, wet etching will perform side etching on the sidewall structure formed by the first sidewall 1201, the second sidewall 1202, the third sidewall 1203 and the fourth sidewall 1204. At this time, by controlling the wet etching time, the sidewall structure of the target thickness can be removed, so that after the fifth sidewall 1205 is formed, it is no longer necessary to remove the initial gap oxide layer of the target thickness, thereby simplifying the process flow and improving the efficiency of semiconductor structure preparation.

[0068] In the embodiment of the present application, for the oxide layer deposited in the first type of logic gate region, the first type of gate oxide layer of the first preset thickness, the first type of gate oxide layer of the second preset thickness, the first type of gate oxide layer of the fourth preset thickness, and the first type of gate oxide layer of the seventh preset thickness are combined together to form a target first type of gate oxide layer. Taking the first type of logic gate region including the first logic gate region 231 as an example, a first gate oxide layer of the first preset thickness, a first gate oxide layer of the second preset thickness, a first gate oxide layer of the fourth preset thickness, and a first gate oxide layer of the seventh preset thickness are formed in the first logic gate region 231, and these first gate oxide layers are stacked together to form a target first gate oxide layer 211 that meets the thickness requirements.

[0069] Similarly, for the oxide layer deposited in the erase gate area 110, a tunnel oxide layer of a third preset thickness, a tunnel oxide layer of a fifth preset thickness, and a tunnel oxide layer of an eighth preset thickness are stacked together and combined with the subsequently formed tunnel oxide layer of an eighth preset thickness to form a target tunnel oxide layer 111 that meets the thickness requirements.

[0070] In addition, for the oxide layer deposited in the second type of logic gate region, the second type of gate oxide layer of the sixth preset thickness forms the target second type of gate oxide layer. In the case where the second type of logic gate region includes multiple logic gate regions, taking the second type of logic gate region including the second logic gate region 232 and the third logic gate region 233 as an example, a second gate oxide layer of the sixth preset thickness and a second gate oxide layer of the ninth preset thickness are formed in the second logic gate region 232, and these second gate oxide layers are stacked together to form a target second gate oxide layer 212 that meets the thickness requirement. A third type of gate oxide layer of the tenth preset thickness is formed in the third logic gate region 233, and the third gate oxide layer forms a target third gate oxide layer 213 that meets the thickness requirement.

[0071] In an embodiment of the present application, after removing the initial gap oxide layer of the target thickness to obtain the target gap oxide layer 1200, electrode materials can also be deposited in the word line area 140, the erase gate area 110, the first type of logic gate area and the second type of logic gate area to obtain the target semiconductor structure. Depositing electrode material in the word line area 140 can form a word line 141. Depositing electrode material in the erase gate area 110 can form an erase gate 112, and depositing electrode material in the first type of logic gate area can form a first type of logic gate. Depositing electrode material in the second type of logic gate area can form a second type of logic gate. Optionally, the electrode material is polysilicon. As an optional embodiment, Fig.15 is a schematic diagram of a target semiconductor structure provided in an embodiment of the present application, such as Fig.15 As shown, the first type of logic gate region includes a first logic gate region 231, and an electrode material is deposited in the first logic gate region 231 to form a first logic gate 221. The second type of logic gate region includes a second logic gate region 232 and a third logic gate region 233, and an electrode material is deposited in the second logic gate region 232 to form a second logic gate 222, and an electrode material is deposited in the third logic gate region 233 to form a third logic gate 223.

[0072] Through the above method, the flash memory process and the logic process can be combined, and the preparation of the gap oxide layer, the first type of gate oxide layer, the tunnel oxide layer and the second type of gate oxide layer can be realized at the same time, so that the oxide layer preparation process of each area is unified, thereby simplifying the oxide layer preparation process and improving the preparation efficiency of the semiconductor structure. Moreover, since the gap oxide layer finally prepared is obtained by compounding the oxide layers prepared multiple times, and since the oxide layers in other areas have been prepared at the same time, the thickness of the gap oxide layer is no longer affected by the logic area process and the flash memory area process, and the precise control of the thickness of the gap oxide layer is achieved, thereby improving the uniformity of the gap oxide layer, and then improving the performance of the flash device. In addition, in practical applications, this method can realize the simultaneous preparation of the gap oxide layers in different flash memory devices in a whole wafer, so that the gap oxide layers in different flash memory devices in the whole wafer maintain uniformity, thereby improving the preparation yield of the flash memory device.

[0073] Fig.16 is a schematic diagram of test results of another flash memory device provided in an embodiment of the present application, such as Fig.16As shown, a group of flash memory devices including a target semiconductor structure is arbitrarily selected as a test group, and the target semiconductor structure is prepared based on the formation method of the above semiconductor structure. By performing a current test on the interface (I / O) of the storage unit of the group of flash memory devices, it can be found that the erase current (IR1) corresponding to the storage unit of these flash memory devices has a high degree of consistency. According to statistics, based on the formation method of the above semiconductor structure, the yield of the obtained flash memory device is above 97%. It can be seen that this method greatly improves the yield of the flash memory device.

[0074] The present application embodiment provides a semiconductor structure, Fig.17 is a schematic diagram of a semiconductor structure provided in an embodiment of the present application, such as Fig.17 As shown, the semiconductor structure may include a flash memory region 100 and a logic region 200 .

[0075] In the embodiment of the present application, the flash memory area 100 includes a control gate area 120 and an erase gate area 110. A control gate structure is formed on the surface of the control gate area 120, and a target gap oxide layer structure is formed on the sidewall of the control gate structure. The target gap oxide layer structure is obtained based on the first sidewall 1201, the second sidewall 1202, the third sidewall 1203 and the fourth sidewall 1204 formed on the sidewall of the control gate structure in sequence. The first sidewall 1201 is obtained based on the first oxide layer 101, and optionally, the thickness of the first sidewall 1201 is 250 angstroms to 280 angstroms. For example, 250 angstroms, 255 angstroms, 260 angstroms, 265 angstroms, 270 angstroms, 275 angstroms, 280 angstroms, etc. The second sidewall 1202 is obtained based on the second oxide layer 102, and optionally, the thickness of the second sidewall 1202 is 40 angstroms to 70 angstroms. For example, 40 angstroms, 45 angstroms, 50 angstroms, 55 angstroms, 60 angstroms, 65 angstroms, 70 angstroms, etc. The third sidewall spacer 1203 is obtained based on the third oxide layer 103. Optionally, the thickness of the third sidewall spacer 1203 is 100 angstroms-140 angstroms. For example, 100 angstroms, 105 angstroms, 110 angstroms, 115 angstroms, 120 angstroms, 125 angstroms, 130 angstroms, 135 angstroms, 140 angstroms, etc. The fourth sidewall spacer 1204 is obtained based on the fourth oxide layer 104. Optionally, the thickness of the fourth sidewall spacer 1204 is 0 angstroms-80 angstroms. For example, 0 angstroms or 40 angstroms-80 angstroms. Optionally, the thickness of the target gap oxide layer 1200 is 220 angstroms-260 angstroms, such as 220 angstroms, 225 angstroms, 230 angstroms, 235 angstroms, 240 angstroms, 245 angstroms, 250 angstroms, 255 angstroms, 260 angstroms, etc.

[0076] In the embodiment of the present application, a target tunneling oxide layer 111 is formed on the surface of the erase gate region 110, and the target tunneling oxide layer 111 is obtained based on a tunneling oxide layer of a third preset thickness and a tunneling oxide layer of a fifth preset thickness. The tunneling oxide layer of the third preset thickness is obtained based on the third oxide layer 103 formed in the erase gate region 110, and the tunneling oxide layer of the fifth preset thickness is obtained based on the fourth oxide layer 104 formed in the erase gate region 110. Optionally, the thickness of the tunneling oxide layer is 120 angstroms to 160 angstroms. For example, 120 angstroms, 125 angstroms, 130 angstroms, 135 angstroms, 140 angstroms, 145 angstroms, 150 angstroms, 155 angstroms, 160 angstroms, etc.

[0077] In the embodiment of the present application, the logic region 200 includes a first type of logic gate region and a second type of logic gate region. A target first type of gate oxide layer is formed on the surface of the first type of logic gate region, and the target first type of gate oxide layer is obtained based on a first type of gate oxide layer of a first preset thickness, a first type of gate oxide layer of a second preset thickness, and a first type of gate oxide layer of a fourth preset thickness. The first type of gate oxide layer of the first preset thickness is obtained based on a second oxide layer 102 formed in the first type of logic gate region, the first type of gate oxide layer of the second preset thickness is based on a third oxide layer 103 formed in the first type of logic gate region, and the first type of gate oxide layer of the fourth preset thickness is obtained based on a fourth oxide layer 104 formed in the first type of logic gate region. In an optional embodiment, the target first type of gate oxide layer includes a target first gate oxide layer 211. Optionally, the thickness of the target first gate oxide layer 211 is 170 angstroms to 220 angstroms. For example, 170 angstroms, 175 angstroms, 180 angstroms, 185 angstroms, 190 angstroms, 195 angstroms, 200 angstroms, 205 angstroms, 210 angstroms, 215 angstroms, 220 angstroms, etc. A target second-class gate oxide layer is formed on the surface of the second-class logic gate region, and the target second-class gate oxide layer is obtained based on the second-class gate oxide layer of the sixth preset thickness. The target second-class gate oxide layer includes a target second gate oxide layer 212 and a target third gate oxide layer 213. Optionally, the thickness of the second gate oxide layer is 60 angstroms-100 angstroms. Specifically, it can be 75 angstroms-80 angstroms, for example, 75.5 angstroms, 76 angstroms, 76.5 angstroms, 77 angstroms, 77.5 angstroms, 78 angstroms, 78.5 angstroms, 79 angstroms, 79.5 angstroms, 80 angstroms, etc. Optionally, the thickness of the third gate oxide layer is 5 angstroms-35 angstroms. For example, 5 angstroms, 10 angstroms, 15 angstroms, 20 angstroms, 25 angstroms, 30 angstroms, 35 angstroms, etc.

[0078] The semiconductor structure described in the embodiment of the present application can be formed based on the formation method of the semiconductor structure described above. In the semiconductor junction, the gap oxide layer between the word line 141 and the floating gate 122 has high consistency, so it has excellent storage performance, and the preparation efficiency of the semiconductor structure is high and the preparation cost is low, so it can be widely promoted and applied.

[0079] An embodiment of the present application further provides a memory device, which includes the semiconductor structure as described above.

[0080] The memory device described in the embodiment of the present application may be a flash memory device, which can be used in embedded devices. The memory device includes the above-mentioned semiconductor structure, in which the gap oxide layer between the word line and the floating gate has a high consistency, thereby having excellent storage performance, and the preparation efficiency is higher and the preparation cost is reduced. Therefore, the memory device also has similar advantages.

[0081] An embodiment of the present application provides an electronic device, which includes the storage device described above.

[0082] The electronic device described in the embodiments of the present application may be any electronic product or device such as a smart phone, a desktop computer, a tablet computer, a laptop computer, a digital assistant, an augmented reality (AR) / virtual reality (VR) device, an intelligent voice interaction device, a smart home appliance, a smart wearable device, a vehicle-mounted terminal device, or any intermediate product including the above-mentioned storage device.

[0083] The electronic device described in the embodiment of the present application includes the access device, and the storage device includes the semiconductor structure. In the semiconductor structure, the gap oxide layer between the word line and the floating gate has a high consistency, so it has excellent storage performance, and the manufacturing efficiency is higher and the manufacturing cost is reduced. Therefore, the electronic device also has similar advantages.

[0084] It should be noted that the above-mentioned sequence of the embodiments of the present application is for description only and does not represent the advantages and disadvantages of the embodiments. The above-mentioned specific embodiments of this specification are described. Other embodiments are within the scope of the attached claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0085] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0086] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0087] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that: The method comprises: Providing an initial semiconductor structure; the initial semiconductor structure includes a flash memory area and a logic area; the flash memory area includes a control gate area and an erase gate area, and a control gate structure is formed on the surface of the control gate area; the logic area includes a first type of logic gate area and a second type of logic gate area; Forming a sidewall structure located on the sidewall of the control gate structure, at least one tunneling oxide layer located in the erase gate region, and a gate oxide layer located in the logic region; the gate oxide layer includes at least one first-type gate oxide layer located in the first-type logic gate region and at least one second-type gate oxide layer located in the second-type logic gate region, and the gate oxide layer is formed synchronously with the sidewall structure and the tunneling oxide layer; A target gap oxide layer is formed based on the sidewall structure, a target first-type gate oxide layer is formed based on the first-type gate oxide layer, a target tunneling oxide layer is formed based on the tunneling oxide layer, and a target second-type gate oxide layer is formed based on the second-type gate oxide layer to obtain a target semiconductor structure.

2. The method according to claim 1, characterized in that The sidewall structure includes: a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; the sidewall structure formed on the sidewall of the control gate structure, at least one tunneling oxide layer located in the erase gate region and the gate oxide layer located in the logic region include: forming a first spacer on a sidewall of the control gate structure; Forming a first type of gate oxide layer with a first preset thickness in the first type of logic gate region, and forming a second sidewall spacer on the sidewall of the first sidewall spacer; Forming a first type gate oxide layer of a second preset thickness in the first type logic gate region, forming a tunnel oxide layer of a third preset thickness in the erase gate region, and forming a third sidewall spacer on the sidewall of the second sidewall spacer; A first gate oxide layer with a fourth preset thickness is formed in the first logic gate region, a tunnel oxide layer with a fifth preset thickness is formed in the erase gate region, a second gate oxide layer with a sixth preset thickness is formed in the second logic gate region, and a fourth sidewall is formed on the sidewall of the third sidewall.

3. The method according to claim 2, characterized in that The forming of a first spacer on the sidewall of the control gate structure comprises: A first oxide layer is deposited to form a first sidewall spacer covering the sidewall of the control gate structure.

4. The method according to claim 2, characterized in that: The first type of logic gate region includes a first logic gate region; the first type of gate oxide layer with a first preset thickness is formed in the first type of logic gate region, and a second sidewall spacer is formed on the sidewall of the first sidewall spacer, including: A second oxide layer is deposited to form a first type gate oxide layer with a first preset thickness in the first type logic gate region, and a second sidewall spacer is formed on the sidewall of the first sidewall spacer.

5. The method according to claim 2, characterized in that: Forming a first type gate oxide layer of a second preset thickness in the first type logic gate region, forming a tunnel oxide layer of a third preset thickness in the erase gate region, and forming a third sidewall spacer on the sidewall of the second sidewall spacer, comprising: A third oxide layer is deposited to form a first gate oxide layer of a second preset thickness in the first logic gate region, a tunnel oxide layer of a third preset thickness is formed in the erase gate region, and a third sidewall is formed on the sidewall of the second sidewall.

6. The method according to claim 2, characterized in that The second type of logic gate region includes a second logic gate region; the first type of gate oxide layer with a fourth preset thickness is formed in the first type of logic gate region, a tunnel oxide layer with a fifth preset thickness is formed in the erase gate region, a second type of gate oxide layer with a sixth preset thickness is formed in the second type of logic gate region, and a fourth sidewall is formed on the sidewall of the third sidewall, including: A fourth oxide layer is deposited, a first gate oxide layer of a fourth preset thickness is formed in the first logic gate region, a tunnel oxide layer of a fifth preset thickness is formed in the erase gate region, a second gate oxide layer of a sixth preset thickness is formed in the second logic gate region, and a fourth sidewall is formed on the sidewall of the third sidewall.

7. The method according to claim 6, characterized in that The depositing of the fourth oxide layer, forming a first type gate oxide layer of a fourth preset thickness in the first type logic gate region, forming a tunneling oxide layer of a fifth preset thickness in the erase gate region, forming a second gate oxide layer of a sixth preset thickness in the second logic gate region, and forming a fourth sidewall spacer on the sidewall of the third sidewall spacer, comprises: A fourth oxide layer is deposited based on an in-situ water vapor generation process, a first gate oxide layer with a fourth preset thickness is formed in the first logic gate region, a tunnel oxide layer with a fifth preset thickness is formed in the erase gate region, a second gate oxide layer with a sixth preset thickness is formed in the second logic gate region, and a fourth sidewall is formed on the sidewall of the third sidewall.

8. The method according to claim 6, characterized in that The second type of logic gate region further includes a third logic gate region; the spacer structure further includes a fifth spacer, and the method for forming the semiconductor structure further includes: A fifth oxide layer is deposited, a first gate oxide layer with a seventh preset thickness is formed in the first logic gate region, a tunnel oxide layer with an eighth preset thickness is formed in the erase gate region, a second gate oxide layer with a ninth preset thickness is formed in the second logic gate region, a third gate oxide layer with a tenth preset thickness is formed in the third logic gate region, and a fifth sidewall is formed on the sidewall of the fourth sidewall.

9. The method according to claim 8, characterized in that The target second-type gate oxide layer includes a target second gate oxide layer and a target third gate oxide layer; the target gap oxide layer is formed based on the sidewall structure, the target first-type gate oxide layer is formed based on the first-type gate oxide layer, the target tunneling oxide layer is formed based on the tunneling oxide layer, and the target second-type gate oxide layer is formed based on the second-type gate oxide layer, to obtain a target semiconductor structure, including: Forming an initial gap oxide layer based on the first spacer, the second spacer, the third spacer, the fourth spacer and the fifth spacer; Removing the initial gap oxide layer of target thickness to obtain the target gap oxide layer; Forming a target first-type gate oxide layer based on the first-type gate oxide layer of the first preset thickness, the first-type gate oxide layer of the second preset thickness, the first-type gate oxide layer of the fourth preset thickness, and the first-type gate oxide layer of the seventh preset thickness; forming a target tunneling oxide layer based on the tunneling oxide layer of the third preset thickness, the tunneling oxide layer of the fifth preset thickness, and the tunneling oxide layer of the eighth preset thickness; Forming a target second gate oxide layer based on the second gate oxide layer of the sixth preset thickness and the second gate oxide layer of the ninth preset thickness; A target third gate oxide layer is formed based on the third type gate oxide layer with the tenth preset thickness to obtain a target semiconductor structure.

10. The method according to claim 1, characterized in that The flash memory area also includes a word line region, and the control gate region is formed between the word line region and the erase gate region; The target gap oxide layer is formed based on the sidewall structure, the target first-type gate oxide layer is formed based on the first-type gate oxide layer, the target tunneling oxide layer is formed based on the tunneling oxide layer, and the target second-type gate oxide layer is formed based on the second-type gate oxide layer to obtain a target semiconductor structure, including: Based on the sidewall structure, a target gap oxide layer is formed; Based on the first type of gate oxide layer, forming a target first type of gate oxide layer; Based on the tunneling oxide layer, forming a target tunneling oxide layer; Based on the second type of gate oxide layer, forming a target second type of gate oxide layer; Electrode materials are deposited on the word line region, the erase gate region, the first type of logic gate region, and the second type of logic gate region to obtain the target semiconductor structure.

11. A semiconductor structure, characterized in that: include: A logic area and a flash memory area; the logic area includes a first type of logic gate area and a second type of logic gate area; the flash memory area includes a control gate area and an erase gate area; A target first-type gate oxide layer located on the surface of the first-type logic gate region; the target first-type gate oxide layer is obtained based on at least one first-type gate oxide layer; a target second type gate oxide layer located on a surface of the second type logic gate region; The target second type gate oxide layer is obtained based on at least one layer of second type gate oxide layer; A control gate structure located on the surface of the control gate region, wherein a target gap oxide layer is formed on the sidewall of the control gate structure; the target gap oxide layer is obtained based on a sidewall structure sequentially formed on the sidewall of the control gate structure; A target tunneling oxide layer is formed on the surface of the erase gate region; The target tunneling oxide layer is obtained based on at least one tunneling oxide layer.

12. The semiconductor structure according to claim 11, characterized in that: The sidewall structure includes: a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; the thickness of the first sidewall is 250 angstroms to 280 angstroms; the thickness of the second sidewall is 40 angstroms to 70 angstroms; the thickness of the third sidewall is 100 angstroms to 140 angstroms; the thickness of the fourth sidewall is 0-80 angstroms.

13. The semiconductor structure according to claim 11 or 12, characterized in that: The target gap oxide layer has a thickness of 220 angstroms to 260 angstroms; the tunnel oxide layer has a thickness of 120 angstroms to 160 angstroms.

14. The semiconductor structure according to claim 11 or 12, characterized in that: The target first type gate oxide layer includes a target first gate oxide layer; the thickness of the target first gate oxide layer is 170 angstroms to 220 angstroms.

15. The semiconductor structure according to claim 14, characterized in that: The target second type gate oxide layer includes a target second gate oxide layer and a target third gate oxide layer: the target second gate oxide layer has a thickness of 60 angstroms to 100 angstroms; the target third gate oxide layer has a thickness of 5 angstroms to 35 angstroms.

16. A storage device, characterized in that: The memory device comprises the semiconductor structure according to any one of claims 11 to 15.

17. An electronic device, characterized in that: The electronic device includes the memory device according to claim 16.

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