Semiconductor device, preparation method of semiconductor device and memory system

Abstract

The invention provides a semiconductor device and a preparation method thereof, and a memory system, and the semiconductor device comprises a first semiconductor structure which comprises a first grid line; the second semiconductor structure comprises a second grid line; and a third semiconductor structure; the first semiconductor structure and the second semiconductor structure are respectively bonded with the third semiconductor structure; the first semiconductor structure and the second semiconductor structure are adjacently arranged on the same side of the third semiconductor structure, the first grid line extends along a first direction, and the second grid line extends along a second direction intersected with the first direction. According to the semiconductor device, the preparation method thereof and the memory system provided by the invention, the warping of the carrier plate can be reduced, so that the stress of the carrier plate is matched with that of the bonding wafer.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device, a method for preparing a semiconductor device, and a memory system. Background Art

[0002] 3D NAND flash memory has the advantage of large capacity, while ferroelectric memory has the advantage of high operating speed. The combination of the two can make up for their respective shortcomings, especially in the future fields of artificial intelligence, storage and computing integration, etc., multi-memory integrated products will play a stronger role. The industry's multi-chip integration often has problems such as wafer warping and stress mismatch between the carrier and the bonded wafer. Summary of the invention

[0003] In view of this, the present application provides a semiconductor device, a method for preparing a semiconductor device, and a memory system that can solve the above-mentioned technical problems.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] The present application provides a semiconductor device, comprising: a first semiconductor structure, comprising a first gate line; a second semiconductor structure, comprising a second gate line; and a third semiconductor structure; the first semiconductor structure and the second semiconductor structure are bonded to the third semiconductor structure, respectively; wherein the first semiconductor structure and the second semiconductor structure are adjacently arranged on the same side of the third semiconductor structure, the first gate line extends along a first direction, and the second gate line extends along a second direction intersecting with the first direction.

[0006] In some embodiments, the first semiconductor structure includes a first core region and a first connection region arranged adjacent to the first core region in the first direction; wherein a memory cell array is provided in the first core region.

[0007] In some embodiments, the first semiconductor structure also includes a second core region, and the first connection region is located between the first core region and the second core region; the first gate line includes a first sub-gate line and a second sub-gate line, the first sub-gate line is located in the first core region, and the second sub-gate line is located in the second core region, and the first sub-gate line and the second sub-gate line both extend along the first direction and are separated by the first connection region; wherein a storage cell array is provided in the second core region.

[0008] In some embodiments, the second semiconductor structure includes a third storage area and a second connection area arranged adjacent to the third storage area in the second direction; wherein the third storage area has a memory cell array.

[0009] In some embodiments, the second semiconductor structure also includes a fourth storage area, and the second connection area is located between the third storage area and the fourth storage area; the second gate line includes a third sub-gate line and a fourth sub-gate line, the third sub-gate line is located in the third storage area, and the fourth sub-gate line is located in the fourth storage area, and the third sub-gate line and the fourth sub-gate line both extend along the second direction and are separated by the second connection area; wherein the fourth storage area has a storage cell array.

[0010] In some embodiments, the semiconductor device includes a first semiconductor structure row and a second semiconductor structure row, the first semiconductor structure row includes at least one first semiconductor structure, and the second semiconductor structure row includes at least one second semiconductor structure; the first semiconductor structure row and the second semiconductor structure row are adjacent to each other in the second direction.

[0011] In some embodiments, the number of the first semiconductor structure rows and the second semiconductor structure rows is multiple; two adjacent first semiconductor structure rows are located on opposite sides of a second semiconductor structure row in the second direction; and two adjacent second semiconductor structure rows are located on opposite sides of a first semiconductor structure row in the second direction.

[0012] In some embodiments, the first direction is perpendicular to the second direction.

[0013] The present application also provides a method for preparing a semiconductor device, comprising: dividing a first initial semiconductor structure into a plurality of first semiconductor structures including a first gate line, and dividing a second initial semiconductor structure into a plurality of second semiconductor structures including a second gate line; transferring and fixing the first semiconductor structure and the second semiconductor structure on the same side of a carrier respectively, and making the first semiconductor structure and the second semiconductor structure adjacent to each other and making the first gate line extend along a first direction, and making the second gate line extend along a second direction intersecting with the first direction; transferring the carrier with the first semiconductor structure and the second semiconductor structure as a whole to a third initial semiconductor structure and making the first semiconductor structure and the second semiconductor structure bonded to the third initial semiconductor structure; and removing the carrier and dividing the third initial semiconductor structure bonded with the first semiconductor structure and the second semiconductor structure into a plurality of semiconductor devices.

[0014] In some embodiments, the steps of transferring and fixing the first semiconductor structure and the second semiconductor structure on the same side of a carrier include: transferring and fixing the first semiconductor structure and the second semiconductor structure on the same side of a carrier by a transfer component with a protective layer; and removing the transfer component and leaving the protective layer on the first semiconductor structure and the second semiconductor structure.

[0015] In some embodiments, the first semiconductor structure includes a first bonding layer, the second semiconductor structure includes a second bonding layer, and the protective layer is respectively located on the first bonding layer and the second bonding layer; after the step of removing the transfer component and leaving the protective layer on the first semiconductor structure and the second semiconductor structure, it also includes: removing the protective layer to expose the first bonding layer and the second bonding layer; in the step of transferring the carrier with the first semiconductor structure and the second semiconductor structure as a whole to a third initial semiconductor structure and bonding the first semiconductor structure and the second semiconductor structure to the third initial semiconductor structure, the first bonding layer and the second bonding layer are respectively bonded to the third initial semiconductor structure.

[0016] In some embodiments, the first semiconductor structure and the second semiconductor structure are both fixed to the carrier via an adhesive layer; after the step of removing the carrier, the step further includes: removing the adhesive layer.

[0017] In some embodiments, in the step of transferring and fixing the first semiconductor structure and the second semiconductor structure on the same side of a carrier, a plurality of the first semiconductor structures and a plurality of the second semiconductor structures are arranged along a first direction.

[0018] In some embodiments, in the steps of respectively transferring and fixing the first semiconductor structure and the second semiconductor structure on the same side of a carrier, the distance in the second direction between adjacent first semiconductor structures and second semiconductor structures located in the same semiconductor device is smaller than the distance between two adjacent semiconductor devices in the second direction.

[0019] In some embodiments, in respectively transferring and fixing the first semiconductor structure and the second semiconductor structure on the same side of a carrier, the first direction is perpendicular to the second direction.

[0020] The present application also provides a memory system, comprising: at least one semiconductor device as described above; and a controller configured to control the semiconductor device.

[0021] The semiconductor device, the method for preparing the semiconductor device and the memory system provided in the present application adjust the arrangement of the first semiconductor structure and the second semiconductor structure on the third semiconductor structure, and make the extension direction of the first gate line of the first semiconductor structure and the second gate line of the second semiconductor structure intersect (perpendicular) so that the stress between the first semiconductor structure and the second semiconductor structure is relatively balanced, thereby reducing the warping of the carrier and matching the stress of the carrier and the bonded wafer (the first semiconductor structure and the second semiconductor structure). BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A flow chart of a method for preparing a semiconductor device provided for some embodiments of the present application.

[0024] Figure 2 A cross-sectional view of a first semiconductor structure array provided in some embodiments of the present application.

[0025] Figure 3 for Figure 2 A top view of a first semiconductor structure in the first semiconductor structure array is shown.

[0026] Figure 4 A cross-sectional view of a second semiconductor structure array provided in some embodiments of the present application.

[0027] Figure 5 for Figure 4 A top view of a second semiconductor structure in the second semiconductor structure array is shown.

[0028] Figure 6 For the general Figure 2 The first semiconductor structure and Figure 4 The second semiconductor structure shown is transferred and fixed on the same side of a carrier according to a preset arrangement to obtain a first bonding intermediate.

[0029] Figure 7 for Figure 6 A cross-sectional view of the first bonding intermediate is shown.

[0030] Figure 8 Some embodiments of the present application provide Figure 7 The arrangement of the first semiconductor structure and the second semiconductor structure on the carrier is shown.

[0031] Fig. 9 Some other embodiments of the present application provide an arrangement of the first semiconductor structure and the second semiconductor structure on a carrier.

[0032] Fig.10 To remove Figure 7 The protective layers on the first semiconductor structure and the second semiconductor structure are shown as a cross-sectional view after obtaining a second bonding intermediate.

[0033] Fig.11 For the general Fig.10 The second bonding intermediate is transferred as a whole and bonded to the third initial semiconductor structure to obtain a cross-sectional view of the third bonding intermediate.

[0034] Fig.12 To remove Fig.11 The carrier in the figure shows a cross-sectional view after obtaining the fourth bonding intermediate.

[0035] Fig.13 To remove Fig.12 Cross-sectional view after the bonding layer.

[0036] Fig.14 For the general Fig.13 The fourth bonding intermediate is shown as a cross-sectional view after being divided into a plurality of semiconductor devices.

[0037] Fig.15 for Fig.14 A top view of a semiconductor device is shown.

[0038] Fig.16 for Fig.14 FIG. 1 is a top view of another semiconductor device shown in FIG.

[0039] Fig.17 Cross-sectional views of semiconductor devices provided for some other embodiments of the present application.

[0040] Fig.18 for Fig.17 A top view of the semiconductor device shown.

[0041] Fig.19 for Fig.17 A top view of another semiconductor device is shown.

[0042] Fig. 20 A module diagram of a memory system provided for some embodiments of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0044] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0045] In the description of the present application, it is to be understood that the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range that is less than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnects and / or via contacts are formed), and one or more dielectric sublayers.

[0046] The present application may repeat reference numerals and / or reference letters in different implementations. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0047] The present application addresses the technical problems of carrier warping and stress mismatch between the carrier and the bonded wafer. The arrangement of the first semiconductor structure and the second semiconductor structure on the third semiconductor structure is adjusted, and the extension directions of the first gate line of the first semiconductor structure and the second gate line of the second semiconductor structure are made to intersect (be perpendicular) with each other, so that the stress between the first semiconductor structure and the second semiconductor structure is relatively balanced, thereby reducing the carrier warping and matching the stress between the carrier and the bonded wafer (the first semiconductor structure and the second semiconductor structure).

[0048] See also Figures 1 to 19 Some embodiments of the present application provide a method for preparing a semiconductor device, comprising:

[0049] Step S1: Please refer to Figures 1 to 5 , dividing the first initial semiconductor structure (not shown) into a plurality of first semiconductor structures 10 including first gate lines 11 , and dividing the second initial semiconductor structure (not shown) into a plurality of second semiconductor structures 20 including second gate lines 21 .

[0050] The first semiconductor structure 10 includes a first bonding layer 12 , and a plurality of the first semiconductor structures 10 constitute a first semiconductor structure array 110 . The first semiconductor structure array 110 also includes a first substrate 13 . The plurality of the first semiconductor structures 10 are located on the first substrate 13 , and the first bonding layer 12 is away from the first substrate 13 .

[0051] The second semiconductor structure 20 includes a second bonding layer 22 , and a plurality of the second semiconductor structures 20 constitute a second semiconductor structure array 120 . The second semiconductor structure array 120 also includes a second substrate 23 . The plurality of the second semiconductor structures 20 are located on the second substrate 23 , and the second bonding layer 22 is away from the second substrate 23 .

[0052] In some embodiments, the first semiconductor structure 10 includes a first core region 14 and a first connection region 15 arranged adjacent to the first core region 14 in a first direction X, wherein a memory cell array is provided in the first core region 14. The signal of the first gate line 11 can be led out or connected from the first connection region 15. The first connection region 15 can release the stress of the first gate line 11 in the extension direction of the first gate line 11.

[0053] In some embodiments, the first semiconductor structure 10 also includes a second core area 16, and the first connection area 15 is located between the first core area 14 and the second core area 16; the first gate line 11 includes a first sub-gate line 111 and a second sub-gate line 112, the first sub-gate line 111 is located in the first core area 14, the second sub-gate line 112 is located in the second core area 16, and the first sub-gate line 111 and the second sub-gate line 112 are separated by the first connection area 15; wherein, the second core area 16 also has a storage cell array.

[0054] Among them, at least one of one of the first core regions 14 and one of the second core regions 16 and one of the first connection regions 15 form a first storage region 101. In some embodiments, one of the first semiconductor structures 10 includes at least one of the first storage regions 101, that is, the first semiconductor structure 10 includes a plurality of the first core regions 14, a plurality of second storage regions 16, and a plurality of the first connection regions 15. In this embodiment, one of the first semiconductor structures 10 includes four of the first storage regions 101, and the four first storage regions 101 are distributed in a "field" shape, and the extending directions of the first gate lines 11 in the plurality of first storage regions 101 are the same. Among them, the extending direction includes the positive direction and the reverse direction of a certain direction.

[0055] In some embodiments, the second semiconductor structure 20 includes a third storage region 24 and a second connection region 25 arranged adjacent to the third storage region 24, and a memory cell array is also provided in the third storage region 24. The signal of the second gate line 21 can be led out or accessed from the second connection region 25.

[0056] In some embodiments, the second semiconductor structure 20 further includes a fourth storage region 26, and the second connection region 25 is located between the third storage region 24 and the fourth storage region 26; the second gate line 21 includes a third sub-gate line 211 and a fourth sub-gate line 212, the third sub-gate line 211 is located in the third storage region 24, the fourth sub-gate line 212 is located in the fourth storage region 26, and the third sub-gate line 211 and the fourth sub-gate line 212 are separated by the second connection region 25; among them, a memory cell array is also provided in the fourth storage region 26.

[0057] Among them, at least one of one of the third storage regions 24 and one of the fourth storage regions 26 and one of the second connection regions 25 form a second storage region 201. In some embodiments, one of the second semiconductor structures 20 includes at least one of the second storage regions 201, that is, the second semiconductor structure 20 includes a plurality of the third storage regions 24, a plurality of the fourth storage regions 26, and a plurality of the second connection regions 25. In this embodiment, one of the second semiconductor structures 20 includes four of the second storage regions 201, and the four second storage regions 201 are distributed in a "field" shape, and the extending directions of the second gate lines 21 in the plurality of second storage regions 201 are the same.

[0058] Among them, the second connection region 25 can release the stress of the second gate line 21 in the extending direction of the second gate line 21.

[0059] Step S2: Please refer to Figures 6 to 9The first semiconductor structure 10 and the second semiconductor structure 20 are transferred and fixed on the same side of a carrier 30 respectively, and the first semiconductor structure 10 is arranged adjacent to the second semiconductor structure 20 and the first gate line 11 extends along the first direction X, and the second gate line 21 extends along the second direction Y intersecting with the first direction X.

[0060] By adjusting the arrangement of the first semiconductor structure 10 and the second semiconductor structure 20 on the carrier 30, and making the extension directions of the first gate line 11 of the first semiconductor structure 10 and the second gate line 21 of the second semiconductor structure 20 intersect (be perpendicular), the stress between the first semiconductor structure 10 and the second semiconductor structure 20 is relatively balanced, thereby reducing the warping of the carrier 30 and matching the stress of the carrier 30 and the bonded wafer (i.e., the first semiconductor structure 10 and the second semiconductor structure 20).

[0061] Among them, the first connection area 15 can release the stress of the first gate line 11 in the extension direction of the first gate line 11. The second connection area 25 can release the stress of the second gate line 21 in the extension direction of the second gate line 21. In this way, when the first gate line 11 of the first semiconductor structure 10 is arranged in an arrangement manner that the extension direction of the second gate line 21 of the second semiconductor structure 20 intersects (is perpendicular to), the stress of the first semiconductor structure 10 in the extension direction of the first gate line 11 (the first direction X) is released, and the stress of the first semiconductor structure 10 is mainly concentrated in the second direction Y; the stress of the second semiconductor structure 20 in the extension direction of the second gate line 21 (the second direction Y) is released, and the stress of the second semiconductor structure 20 is mainly concentrated in the first direction X; in general, the semiconductor device 100 has a good structure in the first direction. The stress in the direction X is generated by the first semiconductor structure 10, and the stress in the second direction Y is generated by the second semiconductor structure 20. Since the structures of the first semiconductor structure 10 and the second semiconductor structure 20 are generally arranged as symmetrical structures, the stress of the semiconductor device 100 in the first direction X is balanced, and the stress of the semiconductor device 100 in the second direction Y is also balanced. Therefore, the stress between the first semiconductor structure and the second semiconductor structure can be kept relatively balanced, thereby reducing the warping of the carrier and matching the stress of the carrier and the bonded wafer (the first semiconductor structure and the second semiconductor structure).

[0062] Specifically, step S2 includes: transferring and fixing the first semiconductor structure 10 and the second semiconductor structure 20 on the same side of the carrier 30 respectively through a transfer component 33 with a protective layer 31; and removing the transfer component 33 and leaving the protective layer 31 on the first semiconductor structure 10 and the second semiconductor structure 20.

[0063] In some embodiments, the first direction X is perpendicular to the second direction Y.

[0064] After step S2, a first bonding intermediate 130 is obtained. The first bonding intermediate 130 includes the first semiconductor structure 10, the second semiconductor structure 20 and the carrier 30, the first semiconductor structure 10 and the second semiconductor structure 20 are located on the carrier 30, the first bonding layer 12 is located on a side of the first semiconductor structure 10 away from the carrier 30, and the second bonding layer 22 is located on a side of the second semiconductor structure 20 away from the carrier 30.

[0065] In some embodiments, the first bonding intermediate 130 further includes a protection layer 31 , and the protection layer 31 is located between the first bonding layer 12 and the first semiconductor structure 10 , and between the second bonding layer 22 and the second semiconductor structure 20 .

[0066] In some embodiments, an adhesive layer 32 is further formed on the carrier 30 , and the first semiconductor structure 10 and the second semiconductor structure 20 are fixed on the carrier 30 via the adhesive layer 32 .

[0067] In some embodiments, the first semiconductor structures 10 constitute a first semiconductor structure row 102, and the second semiconductor structures 20 constitute a second semiconductor structure row 103. That is, the first semiconductor structure row 102 includes at least one first semiconductor structure 10, and the second semiconductor structure row 103 includes at least one second semiconductor structure 20; the first semiconductor structure row 102 and the second semiconductor structure row 103 are adjacently arranged in the second direction Y.

[0068] Specifically, please refer to Figure 8 The first semiconductor structure row 102 includes one first semiconductor structure 10 , and the second semiconductor structure row 103 includes two second semiconductor structures 20 , and the two second semiconductor structures 20 are arranged along the first direction X.

[0069] Specifically, please refer to Fig. 9The first semiconductor structure row 102 includes two first semiconductor structures 10 , and the second semiconductor structure row 103 includes four second semiconductor structures 20 . The two first semiconductor structures 10 and the four second semiconductor structures 20 are arranged along the first direction X.

[0070] In other embodiments, the number of the first semiconductor structures 10 in the first semiconductor structure row 102 may be a plurality greater than two, and the number of the second semiconductor structures 20 in the second semiconductor structure row 103 may be one or a plurality greater than two, and the number of the first semiconductor structures 10 and the second semiconductor structures 20 may be set according to specific circumstances.

[0071] In this embodiment, the first semiconductor structure 10 is a 3D NAND chip structure, and the second semiconductor structure 20 is a Fe RAM chip structure. Of course, in other embodiments, the first semiconductor structure 10 and the second semiconductor structure 20 are not limited to the 3D NAND chip structure and the Fe RAM chip structure, and can also be other chip structures, which can be specifically set according to actual conditions.

[0072] For details, please continue to refer to Figure 8 and Fig. 9 The number of the first semiconductor structure 10 and the second semiconductor structure 20 is multiple, two adjacent rows of the first semiconductor structure 102 are located on opposite sides of a row of the second semiconductor structure 103 in the second direction Y, and two adjacent rows of the second semiconductor structure 103 are located on opposite sides of a row of the first semiconductor structure 102 in the second direction Y.

[0073] In some embodiments, a vertical distance H1 between adjacent first semiconductor structures 10 and second semiconductor structures 20 in the same semiconductor device in the second direction Y is smaller than a vertical distance H2 between two adjacent semiconductor devices 100 in the second direction Y. The gap between two adjacent semiconductor devices 100 in the second direction Y is a cutting position, and in subsequent steps, the cutting position has a cutting line L1.

[0074] Step S3: Please refer to Fig.10 , removing the protective layer 31 to obtain a second bonding intermediate 140.

[0075] The second bonding intermediate 140 includes the carrier 30 , the first semiconductor structure 10 , and the second semiconductor structure 20 .

[0076] Step S4: Please refer to Fig.11, the carrier 30 (i.e., the second bonding intermediate 140 ) carrying the first semiconductor structure 10 and the second semiconductor structure 20 is transferred as a whole to the third initial semiconductor structure 40 and the first semiconductor structure 10 and the second semiconductor structure 20 are bonded to the third initial semiconductor structure 40 .

[0077] In step S4 , a third bonding intermediate 150 is finally obtained. The third bonding intermediate 150 includes the second bonding intermediate 140 and the third initial semiconductor structure 40 .

[0078] Step S5: Please refer to Figure 12 to Figure 14 , removing the carrier 30 and dividing the third initial semiconductor structure 40 bonded with the first semiconductor structure 10 and the second semiconductor structure 20 into a plurality of semiconductor devices 100 .

[0079] In step S5 , after removing the carrier 30 , a fourth bonding intermediate 160 is obtained. The fourth bonding intermediate 160 includes the first semiconductor structure 10 , the second semiconductor structure 20 and the third initial semiconductor structure 40 .

[0080] In step S5 , after removing the carrier 30 and before dividing the third initial semiconductor structure 40 bonded with the first semiconductor structure 10 and the second semiconductor structure 20 into a plurality of semiconductor devices 100 , the method further includes removing the bonding layer 32 .

[0081] See also Figures 14 to 20 The present application also provides a semiconductor device 100, which includes a first semiconductor structure 10, a second semiconductor structure 20 and a third semiconductor structure 50, wherein the first semiconductor structure 10 and the second semiconductor structure 20 are located on the same side of the third semiconductor structure 50 and are bonded to the third semiconductor structure 50 respectively.

[0082] The first semiconductor structure 10 includes a first gate line 11 , and the second semiconductor structure 20 includes a second gate line 21 . The first gate line 11 extends along a first direction X, and the second gate line 21 extends along a second direction Y intersecting the first direction X.

[0083] In some embodiments, the first direction X is perpendicular to the second direction Y.

[0084] The semiconductor device 100 includes at least one first semiconductor structure 10 , at least one second semiconductor structure 20 and one third semiconductor structure 50 .

[0085] See also Fig.14 and Fig.15 In some embodiments, the semiconductor device 100 includes one first semiconductor structure 10, two second semiconductor structures 20, and one third semiconductor structure 50.

[0086] Among them, the first semiconductor structure 10 includes a first bonding layer 12, the second semiconductor structure 20 includes a second bonding layer 22, and the first bonding layer 12 and the second bonding layer 22 are respectively bonded to the third semiconductor structure 50.

[0087] In some embodiments, the first semiconductor structure 10 includes a first core region 14 and a first connection region 15 arranged adjacent to the first core region 14 in a first direction X. A memory cell array is provided in the first core region 14. Signals of the first gate line 11 can be led out from or accessed through the first connection region 15.

[0088] In some embodiments, the first semiconductor structure 10 further includes a second core region 16. The first connection region 15 is located between the first core region 14 and the second core region 16. The first gate line 11 includes a first sub-gate line 111 and a second sub-gate line 112. The first sub-gate line 111 is located in the first core region 14, the second sub-gate line 112 is located in the second core region 16, the first sub-gate line 111 and the second sub-gate line 112 are separated by the first connection region 15, and the first sub-gate line 111 and the second sub-gate line 112 respectively extend along the first direction X. Among them, a memory cell array is also provided in the second core region 16.

[0089] Among them, at least one of one first core region 14 and one second core region 16 and one first connection region 15 constitute a first storage region 101. In some embodiments, one first semiconductor structure 10 includes at least one first storage region 101, that is, the first semiconductor structure 10 includes a plurality of first core regions 14, a plurality of second storage regions 16, and a plurality of first connection regions 15. In this embodiment, one first semiconductor structure 10 includes four first storage regions 101. The four first storage regions 101 are distributed in a "field" shape, and the extending directions of the first gate lines 11 in the plurality of first storage regions 101 are the same.

[0090] In some embodiments, the second semiconductor structure 20 includes a third storage region 24 and a second connection region 25 arranged adjacent to the third storage region 24. A memory cell array is also provided in the third storage region 24. Signals of the second gate line 21 can be led out from or accessed through the second connection region 25.

[0091] In some embodiments, the second semiconductor structure 20 further includes a fourth storage region 26, and the second connection region 25 is located between the third storage region 24 and the fourth storage region 26; the second gate line 21 includes a third sub-gate line 211 and a fourth sub-gate line 212, the third sub-gate line 211 is located in the third storage region 24, the fourth sub-gate line 212 is located in the fourth storage region 26, the third sub-gate line 211 and the fourth sub-gate line 212 are separated by the second connection region 25, and the third sub-gate line 211 and the fourth sub-gate line 212 respectively extend along the second direction Y; wherein, a memory cell array is also provided in the fourth storage region 26.

[0092] Wherein, at least one of one of the third storage regions 24 and one of the fourth storage regions 26 and one of the second connection regions 25 form a second storage region 201. In some embodiments, one second semiconductor structure 20 includes at least one of the second storage regions 201, that is, the second semiconductor structure 20 includes a plurality of the third storage regions 24, a plurality of the fourth storage regions 26, and a plurality of the second connection regions 25. In this embodiment, one second semiconductor structure 20 includes four of the second storage regions 201, and the four second storage regions 201 are distributed in a "field" shape, and the extending directions of the second gate lines 21 in the plurality of second storage regions 201 are the same.

[0093] In some embodiments, the first semiconductor structure 10 forms a first semiconductor structure row 102, and the second semiconductor structure 20 forms a second semiconductor structure row 103. That is, the first semiconductor structure row 102 includes at least one of the first semiconductor structures 10, and the second semiconductor structure row 103 includes at least one of the second semiconductor structures 20; the first semiconductor structure row 102 and the second semiconductor structure row 103 are arranged adjacent to each other in the second direction Y.

[0094] Specifically, please refer to Fig.15 and Fig.18 , the first semiconductor structure row 102 includes one of the first semiconductor structures 10, the second semiconductor structure row 103 includes two of the second semiconductor structures 20, and the two second semiconductor structures 20 are arranged along the first direction X.

[0095] Specifically, please refer to Fig.16 and Fig.19 , the first semiconductor structure row 102 includes two of the first semiconductor structures 10, the second semiconductor structure row 103 includes four of the second semiconductor structures 20, and the two first semiconductor structures 10 and the four second semiconductor structures 20 are all arranged along the first direction X.

[0096] In other embodiments, the number of the first semiconductor structures 10 in the first semiconductor structure row 102 may be a plurality greater than two, and the number of the second semiconductor structures 20 in the second semiconductor structure row 103 may be one or a plurality greater than two, and the number of the first semiconductor structures 10 and the second semiconductor structures 20 may be set according to specific circumstances.

[0097] In this embodiment, the first semiconductor structure 10 is a 3D NAND chip structure, and the second semiconductor structure 20 is a Fe RAM chip structure. Of course, in other embodiments, the first semiconductor structure 10 and the second semiconductor structure 20 are not limited to the 3D NAND chip structure and the Fe RAM chip structure, and can also be other chip structures, which can be specifically set according to actual conditions.

[0098] For details, please continue to refer to Fig.18 and Fig.19 The number of the first semiconductor structure rows 102 and the second semiconductor structure rows 103 is multiple, two adjacent first semiconductor structure rows 102 are located on opposite sides of a second semiconductor structure row 103 in the second direction Y, and two adjacent second semiconductor structure rows 103 are located on opposite sides of a first semiconductor structure row 102 in the second direction Y.

[0099] Among them, the first connection area 15 can release the stress of the first gate line 11 in the extension direction of the first gate line 11. The second connection area 25 can release the stress of the second gate line 21 in the extension direction of the second gate line 21. In this way, when the first gate line 11 of the first semiconductor structure 10 is arranged in an arrangement manner that the extension direction of the second gate line 21 of the second semiconductor structure 20 intersects (is perpendicular to), the stress of the first semiconductor structure 10 in the extension direction of the first gate line 11 (the first direction X) is released, and the stress of the first semiconductor structure 10 is mainly concentrated in the second direction Y; the stress of the second semiconductor structure 20 in the extension direction of the second gate line 21 (the second direction Y) is released, and the stress of the second semiconductor structure 20 is mainly concentrated in the first direction X; in general, the semiconductor device 100 has a good structure in the first direction. The stress in the direction X is generated by the first semiconductor structure 10, and the stress in the second direction Y is generated by the second semiconductor structure 20. Since the structures of the first semiconductor structure 10 and the second semiconductor structure 20 are generally arranged as symmetrical structures, the stress of the semiconductor device 100 in the first direction X is balanced, and the stress of the semiconductor device 100 in the second direction Y is also balanced. Therefore, the stress between the first semiconductor structure and the second semiconductor structure can be kept relatively balanced, thereby reducing the warping of the carrier and matching the stress of the carrier and the bonded wafer (the first semiconductor structure and the second semiconductor structure).

[0100] See also Fig. 20 The present application also provides a memory system 1000 , which includes one or more semiconductor devices 100 as described above and a controller 200 , wherein the controller 200 is connected to the semiconductor device 100 , and the controller 200 is configured to control the semiconductor device 100 .

[0101] The memory system 1000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. The controller may be configured to control operations of the semiconductor device, such as read, erase, and program operations.

[0102] In some embodiments, the controller is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0103] In some embodiments, the controller is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0104] The semiconductor device, the method for preparing the semiconductor device and the memory system provided by the present application adjust the arrangement of the first semiconductor structure and the second semiconductor structure on the third semiconductor structure, and make the extension direction of the first gate line of the first semiconductor structure intersect (perpendicular) with the extension direction of the second gate line of the second semiconductor structure, so that the stress between the first semiconductor structure and the second semiconductor structure is relatively balanced, thereby reducing the warping of the carrier and matching the stress of the carrier and the bonded wafer.

[0105] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A semiconductor device, characterized in that: include: A first semiconductor structure including a first gate line; A second semiconductor structure includes a second gate line; and a third semiconductor structure; the first semiconductor structure and the second semiconductor structure are respectively bonded to the third semiconductor structure; The first semiconductor structure and the second semiconductor structure are adjacently arranged on the same side of the third semiconductor structure, the first gate line extends along a first direction, and the second gate line extends along a second direction intersecting the first direction.

2. The semiconductor device according to claim 1, wherein The first semiconductor structure includes a first core region and a first connection region arranged adjacent to the first core region in the first direction; Wherein, the first core area has a storage unit array.

3. The semiconductor device according to claim 2, wherein: The first semiconductor structure further includes a second core region, and the first connection region is located between the first core region and the second core region; The first gate line includes a first sub-gate line and a second sub-gate line, the first sub-gate line is located in the first core area, the second sub-gate line is located in the second core area, the first sub-gate line and the second sub-gate line both extend along the first direction and are separated by the first connection area; Wherein, the second core area has a storage unit array.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The second semiconductor structure includes a third storage area and a second connection area arranged adjacent to the third storage area in the second direction; Wherein, the third storage area has a storage cell array.

5. The semiconductor device according to claim 4, wherein: The second semiconductor structure further includes a fourth storage region, and the second connection region is located between the third storage region and the fourth storage region; The second gate line includes a third sub-gate line and a fourth sub-gate line, the third sub-gate line is located in the third storage area, the fourth sub-gate line is located in the fourth storage area, the third sub-gate line and the fourth sub-gate line both extend along the second direction and are separated by the second connection area; Wherein, the fourth storage area has a storage cell array.

6. The semiconductor device according to claim 1, wherein: The semiconductor device includes a first semiconductor structure row and a second semiconductor structure row. The first semiconductor structure row includes at least one first semiconductor structure, and the second semiconductor structure row includes at least one second semiconductor structure. The first semiconductor structure row and the second semiconductor structure row are adjacently arranged in the second direction.

7. The semiconductor device according to claim 6, wherein: The number of the first semiconductor structure row and the number of the second semiconductor structure row are multiple; Two adjacent rows of the first semiconductor structures are located on opposite sides of one row of the second semiconductor structure in the second direction; Two adjacent rows of the second semiconductor structures are located on two opposite sides of one row of the first semiconductor structures in the second direction.

8. The semiconductor device according to claim 1, wherein The first direction is perpendicular to the second direction.

9. A method for preparing a semiconductor device, characterized in that: include: Dividing the first initial semiconductor structure into a plurality of first semiconductor structures including first gate lines, and dividing the second initial semiconductor structure into a plurality of second semiconductor structures including second gate lines; The first semiconductor structure and the second semiconductor structure are transferred and fixed to the same side of a carrier respectively, and the first semiconductor structure is arranged adjacent to the second semiconductor structure and the first gate line extends along a first direction, and the second gate line extends along a second direction intersecting the first direction; Transferring the carrier with the first semiconductor structure and the second semiconductor structure as a whole onto a third initial semiconductor structure and bonding the first semiconductor structure and the second semiconductor structure to the third initial semiconductor structure; and The carrier is removed and the third initial semiconductor structure bonded with the first semiconductor structure and the second semiconductor structure is divided into a plurality of semiconductor devices.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The steps of transferring and fixing the first semiconductor structure and the second semiconductor structure on the same side of a carrier include: Transferring and fixing the first semiconductor structure and the second semiconductor structure to the same side of a carrier respectively by a transfer assembly with a protective layer; and The transfer component is removed and the protective layer is left on the first semiconductor structure and the second semiconductor structure.

11. The method for preparing a semiconductor device according to claim 10, wherein: The first semiconductor structure includes a first bonding layer, the second semiconductor structure includes a second bonding layer, and the protection layer is respectively located on the first bonding layer and the second bonding layer; After the step of removing the transfer component and leaving the protective layer on the first semiconductor structure and the second semiconductor structure, the method further includes: removing the protective layer to expose the first bonding layer and the second bonding layer; In the step of transferring the carrier with the first semiconductor structure and the second semiconductor structure as a whole to a third initial semiconductor structure and bonding the first semiconductor structure and the second semiconductor structure to the third initial semiconductor structure, the first bonding layer and the second bonding layer are respectively bonded to the third initial semiconductor structure.

12. The method for preparing a semiconductor device according to claim 9, wherein: The first semiconductor structure and the second semiconductor structure are both fixed to the carrier through an adhesive layer; after the step of removing the carrier, the method further includes: The adhesive layer is removed.

13. The method for preparing a semiconductor device according to claim 9, wherein: In the step of transferring and fixing the first semiconductor structure and the second semiconductor structure on the same side of a carrier, a plurality of the first semiconductor structures and a plurality of the second semiconductor structures are arranged along a first direction.

14. The method for preparing a semiconductor device according to claim 9, wherein: In the steps of transferring and fixing the first semiconductor structure and the second semiconductor structure on the same side of a carrier, the distance in the second direction between adjacent first semiconductor structures and second semiconductor structures located in the same semiconductor device is smaller than the distance between two adjacent semiconductor devices in the second direction.

15. The method for preparing a semiconductor device according to claim 9, wherein: In the process of transferring and fixing the first semiconductor structure and the second semiconductor structure on the same side of a carrier, the first direction is perpendicular to the second direction.

16. A memory system, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 8; and A controller is configured to control the semiconductor device.

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