Array substrate, preparation method thereof and display panel

Abstract

The embodiment of the invention provides an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate; the first semiconductor layer is positioned on one side of the substrate and comprises a first active part; the first insulating layer is located on the side, away from the substrate, of the first semiconductor layer; the second semiconductor layer is located on the side, away from the first semiconductor layer, of the first insulating layer, and the second semiconductor layer comprises a second active part; the first grid electrode is located on the side, away from the first insulating layer, of the first semiconductor layer, and the orthographic projection of the first grid electrode on the substrate and the orthographic projection of the first active part on the substrate are at least partially overlapped; the second grid electrode is located on the side, away from the first insulating layer, of the second semiconductor layer, and the orthographic projection of the second grid electrode on the substrate and the orthographic projection of the second active part on the substrate are at least partially overlapped; wherein the carrier mobility of one of the first active part and the second active part is greater than the carrier mobility of the other one of the first active part and the second active part. The processing performance of the array substrate can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to an array substrate and a method for preparing the same, and a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the process performance of current OLED display products needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a method for manufacturing the same, and a display panel, aiming to improve the process performance of the array substrate.

[0005] An embodiment of the first aspect of the present application provides an array substrate, which includes: a substrate; a first semiconductor layer, located on one side of the substrate and including a first active portion; a first insulating layer, located on a side of the first semiconductor layer facing away from the substrate; a second semiconductor layer, located on a side of the first insulating layer facing away from the substrate, the second semiconductor layer including a second active portion; a first gate, located on a side of the first semiconductor layer facing away from the substrate, an orthographic projection of the first gate on the substrate and an orthographic projection of the first active portion on the substrate at least partially overlap; a second gate, located on a side of the second semiconductor layer facing away from the substrate, an orthographic projection of the second gate on the substrate and an orthographic projection of the second active portion on the substrate at least partially overlap; wherein, of the first active portion and the second active portion, the carrier mobility of one is greater than the carrier mobility of the other.

[0006] According to an implementation of the first aspect of the present application, the thickness of the first insulating layer is 10 nm to 200 nm.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the thickness of the first insulating layer is 50 nm to 100 nm.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, the carrier mobility of the first active portion is less than the carrier mobility of the second active portion, and the material of the first active portion and / or the second active portion includes metal oxide.

[0009] According to any of the aforementioned embodiments of the first aspect of the present application, the material of the first active part includes at least one of indium oxide, gallium oxide, zinc oxide, tin oxide, indium gallium zinc oxide, and indium gallium oxide, the number of indium atoms accounts for 30% to 70% of the total number of metal atoms in the first active part, the number of gallium atoms accounts for 0 to 70% of the total number of metal atoms in the first active part, and the number of zinc atoms accounts for 0 to 70% of the total number of metal atoms in the first active part.

[0010] According to any of the aforementioned embodiments of the first aspect of the present application, the thickness of the first active portion ranges from 3 nm to 100 nm.

[0011] According to any of the aforementioned embodiments of the first aspect of the present application, the material of the second active part includes at least one of indium oxide, gallium oxide, zinc oxide, tin oxide, indium gallium zinc oxide, and indium gallium oxide, the number of indium atoms accounts for 50% to 100% of the total number of metal atoms in the second active part, the number of gallium atoms accounts for 0-50% of the total number of metal atoms in the second active part, and the number of zinc atoms accounts for 0-50% of the total number of metal atoms in the second active part.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, the thickness of the second active portion is in the range of 3 nm to 100 nm.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the proportion of metal atoms of indium in the first active portion is smaller than the proportion of metal atoms of indium in the second active portion.

[0014] According to any of the aforementioned embodiments of the first aspect of the present application, the carrier mobility of the first active portion is greater than the carrier mobility of the second active portion, and the material of the first active portion and / or the second active portion includes metal oxide.

[0015] According to any of the aforementioned embodiments of the first aspect of the present application, the material of the second active part includes at least one of indium oxide, gallium oxide, zinc oxide, tin oxide, indium gallium zinc oxide, and indium gallium oxide, the number of indium atoms accounts for 30% to 70% of the total number of metal atoms in the first active part, the number of gallium atoms accounts for 0 to 70% of the total number of metal atoms in the first active part, and the number of zinc atoms accounts for 0 to 70% of the total number of metal atoms in the first active part.

[0016] According to any of the aforementioned embodiments of the first aspect of the present application, the thickness of the second active portion is in the range of 3 nm to 100 nm.

[0017] According to any of the aforementioned embodiments of the first aspect of the present application, the material of the first active part includes at least one of indium oxide, gallium oxide, zinc oxide, tin oxide, indium gallium zinc oxide, and indium gallium oxide, the number of indium atoms accounts for 50% to 100% of the total number of metal atoms in the second active part, the number of gallium atoms accounts for 0-50% of the total number of metal atoms in the second active part, and the number of zinc atoms accounts for 0-50% of the total number of metal atoms in the second active part.

[0018] According to any of the aforementioned embodiments of the first aspect of the present application, the thickness of the first active portion ranges from 3 nm to 100 nm.

[0019] According to any of the aforementioned embodiments of the first aspect of the present application, the proportion of metal atoms of indium in the first active portion is greater than the proportion of metal atoms of indium in the second active portion.

[0020] According to any of the aforementioned embodiments of the first aspect of the present application, it also includes a second insulating layer located on a side of the second semiconductor layer facing away from the substrate, and the second gate is located on a side of the second insulating layer facing away from the substrate.

[0021] According to any of the aforementioned embodiments of the first aspect of the present application, the first insulating layer and / or the second insulating layer are arranged as a whole layer.

[0022] According to any of the aforementioned embodiments of the first aspect of the present application, the first insulating layer is in contact with the first active portion and the second active portion.

[0023] According to any of the aforementioned embodiments of the first aspect of the present application, the second insulating layer is in contact with the second active portion.

[0024] According to any of the aforementioned embodiments of the first aspect of the present application, the first gate is located on a side of the second insulating layer facing away from the substrate.

[0025] According to any of the aforementioned embodiments of the first aspect of the present application, the first gate and the second gate are arranged in the same layer.

[0026] According to any of the aforementioned embodiments of the first aspect of the present application, the second insulating layer includes a first section located on the side of the first gate facing the substrate and a second section located on the side of the second gate facing the substrate, and the first section and the second section are spaced apart.

[0027] According to any of the aforementioned embodiments of the first aspect of the present application, an orthographic projection of the first section on the substrate overlaps with an orthographic projection of the first gate on the substrate.

[0028] According to any of the aforementioned embodiments of the first aspect of the present application, an orthographic projection of the second section on the substrate overlaps with an orthographic projection of the second gate on the substrate.

[0029] According to any of the aforementioned embodiments of the first aspect of the present application, the first insulating layer includes a third section located on the side of the first section facing the substrate and a fourth section located on the side of the second active section facing the substrate, and the third section and the fourth section are spaced apart.

[0030] According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of the third section on the substrate overlaps with the orthographic projection of the first section on the substrate.

[0031] According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of the fourth portion on the substrate overlaps with the orthographic projection of the second active portion on the substrate.

[0032] According to any of the aforementioned embodiments of the first aspect of the present application, the first active portion is a single-layer arrangement, or the first active portion includes a plurality of stacked first sublayers, and the carrier mobility of each first sublayer is greater than or less than the carrier mobility of the second active portion.

[0033] According to any of the aforementioned implementations of the first aspect of the present application, the first active portion includes two first sublayers, and the two first sublayers have different carrier mobilities;

[0034] Alternatively, the first active portion includes three first sub-layers, and the carrier mobility of the first sub-layer located in the middle is greater than the carrier mobility of the other first sub-layers.

[0035] According to any of the aforementioned embodiments of the first aspect of the present application, the second active portion is a single-layer arrangement, or the second active portion includes a plurality of stacked second sublayers, and the carrier mobility of each second sublayer is greater than or less than the carrier mobility of the first active portion.

[0036] According to any of the aforementioned implementations of the first aspect of the present application, the second active portion includes two second sublayers, and the two second sublayers have different carrier mobilities;

[0037] Alternatively, the second active portion includes three second sub-layers, and the carrier mobility of the second sub-layer located in the middle is greater than the carrier mobility of the other second sub-layers.

[0038] According to any of the aforementioned embodiments of the first aspect of the present application, the first source and the first drain are further included, the first active portion includes a first source region and a first drain region, the first source and the first source region are electrically connected, the first drain and the first drain region are electrically connected, and the first source, the first drain, the first gate and the first active portion are combined to form a first transistor;

[0039] The second active portion includes a second source and a second drain, the second source and the second source region are electrically connected, the second drain and the second drain region are electrically connected, and the second source, the second drain, the second gate and the second active portion are combined to form a second transistor;

[0040] The absolute value of the difference between the threshold voltages of the first transistor and the second transistor is less than or equal to 0.4V.

[0041] According to any of the aforementioned embodiments of the first aspect of the present application, the carrier mobility of the first active portion is less than the carrier mobility of the second active portion, the first transistor is a pixel circuit driving transistor, and the second transistor is a gate driving circuit transistor or a pixel circuit switching transistor;

[0042] Alternatively, the carrier mobility of the first active portion is greater than the carrier mobility of the second active portion, the first transistor is a gate drive circuit transistor or a pixel circuit switch transistor, and the second transistor is a pixel circuit drive transistor.

[0043] According to any of the aforementioned implementations of the first aspect of the present application, it also includes: a third gate located on a side of the first active portion facing the substrate.

[0044] According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of the first gate on the substrate is located within the orthographic projection of the third gate on the substrate.

[0045] According to any of the aforementioned implementations of the first aspect of the present application, it also includes a fourth gate located on a side of the second active portion facing the substrate.

[0046] According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of the second gate on the substrate is located within the orthographic projection of the fourth gate on the substrate.

[0047] According to any of the aforementioned embodiments of the first aspect of the present application, it also includes a light-shielding layer, and the light-shielding layer is multiplexed as the third gate and / or the fourth gate.

[0048] An embodiment of the first aspect of the present application provides an array substrate, which includes: a substrate; a first semiconductor layer, located on one side of the substrate and including a first active portion; a first insulating layer, located on a side of the first semiconductor layer facing away from the substrate; a second semiconductor layer, located on a side of the first insulating layer facing away from the substrate, the second semiconductor layer including a second active portion; a first gate, located on a side of the first semiconductor layer facing away from the substrate, an orthographic projection of the first gate on the substrate and an orthographic projection of the first active portion on the substrate at least partially overlap; a second gate, located on a side of the second semiconductor layer facing away from the substrate, an orthographic projection of the second gate on the substrate and an orthographic projection of the second active portion on the substrate at least partially overlap; wherein materials of the first active portion and the second active portion both include indium, and the indium content of one is greater than that of the other.

[0049] According to an implementation of the first aspect of the present application, the first active portion is a single-layer arrangement, or the first active portion includes a plurality of stacked first sub-layers, and the indium content of each first sub-layer is greater than or less than the indium content of the second active portion.

[0050] According to any of the aforementioned implementations of the first aspect of the present application, the first active portion includes two first sub-layers, and the two first sub-layers have different indium contents;

[0051] Alternatively, the first active portion includes three first sub-layers, and the indium content of the first sub-layer located in the middle is greater than the indium content of the other first sub-layers.

[0052] According to any of the aforementioned embodiments of the first aspect of the present application, the second active portion is a single-layer arrangement, or the second active portion includes a plurality of stacked second sub-layers, and the indium content of each second sub-layer is greater than or less than the indium content of the first active portion.

[0053] According to any of the aforementioned implementations of the first aspect of the present application, the second active portion includes two second sub-layers, and the two second sub-layers have different indium contents;

[0054] Alternatively, the second active portion includes three second sub-layers, and the indium content of the second sub-layer located in the middle is greater than that of the other second sub-layers.

[0055] The second aspect of the present application also provides a method for preparing an array substrate, including:

[0056] A first active material layer is disposed on one side of the substrate, and the first active material layer is patterned to form a first semiconductor layer having a first active portion;

[0057] Disposing a first insulating layer on a side of the first semiconductor layer facing away from the substrate;

[0058] Disposing a second active material layer on a side of the first insulating layer facing away from the substrate, and patterning the second active material layer to form a second semiconductor layer having a second active portion;

[0059] A first gate and a second gate are formed on a side of the second semiconductor layer facing away from the substrate, wherein an orthographic projection of the first gate on the substrate and an orthographic projection of the first active portion on the substrate at least partially overlap, and an orthographic projection of the second gate on the substrate and an orthographic projection of the second active portion on the substrate at least partially overlap;

[0060] Among them, the carrier mobility of one of the first active portion and the second active portion is greater than the carrier mobility of the other.

[0061] According to an implementation of the second aspect of the present application, before the step of preparing the first gate and the second gate on the side of the second semiconductor layer facing away from the substrate, the step further includes:

[0062] forming a second insulating layer on a side of the second semiconductor layer facing away from the substrate;

[0063] In the step of forming the first gate and the second gate on the side of the second semiconductor layer facing away from the substrate, the first gate and the second gate are formed on the side of the second insulating layer facing away from the substrate.

[0064] According to any of the aforementioned implementations of the second aspect of the present application, further comprising:

[0065] The second insulating layer is patterned using the first gate and the second gate as masks, so that the second insulating layer includes a first section located on the side of the first gate facing the substrate and a second section located on the side of the second gate facing the substrate, and the first section and the second section are spaced apart.

[0066] According to any of the aforementioned embodiments of the second aspect of the present application, in the step of patterning the second insulating layer using the first gate and the second gate as mask plates, the first insulating layer is also patterned so that the first insulating layer includes a third section located on the side of the first section facing the substrate and a fourth section located on the side of the second active section facing the substrate, and the third section and the fourth section are arranged at intervals.

[0067] According to any of the aforementioned embodiments of the second aspect of the present application, before the step of providing a first active material layer on one side of the substrate and patterning the first active material layer to form a first semiconductor layer having a first active portion, the step further includes:

[0068] A gate material layer is provided on one side of the substrate, and the gate material layer is patterned to form a third gate;

[0069] In the step of arranging a first active material layer on one side of the substrate and patterning the first active material layer to form a first semiconductor layer having a first active portion: the first active portion is located on a side of the third gate away from the substrate;

[0070] And / or, before the step of disposing a second active material layer on a side of the first insulating layer facing away from the substrate and patterning the second active material layer to form a second semiconductor layer having a second active portion, the method further includes:

[0071] A gate material layer is provided on one side of the substrate, and the gate material layer is patterned to form a fourth gate;

[0072] In the step of disposing a second active material layer on a side of the first insulating layer away from the substrate and patterning the second active material layer to form a second semiconductor layer having a second active portion: the second active portion is located on a side of the fourth gate away from the substrate.

[0073] According to any of the aforementioned embodiments of the second aspect of the present application, before the step of providing a first active material layer on one side of the substrate and patterning the first active material layer to form a first semiconductor layer having a first active portion, the step further includes:

[0074] A gate material layer is disposed on one side of the substrate, and the gate material layer is patterned to form a third gate and a fourth gate.

[0075] A third aspect of the present application further provides a display panel, comprising an array substrate according to any of the above-mentioned first aspect embodiments, or an array substrate prepared by any of the above-mentioned second aspect preparation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features.

[0077] Figure 1 is a structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0078] Figure 2 In one embodiment of the present application Figure 1 Sectional view at AA in the middle;

[0079] Figure 3 In another embodiment of the present application Figure 1 Sectional view at AA in the middle;

[0080] Figure 4 In another embodiment of the present application Figure 1 Sectional view at AA in the middle;

[0081] Figure 5 In another embodiment of the present application Figure 1 Sectional view at AA in the middle;

[0082] Figure 6 In another embodiment of the present application Figure 1 Sectional view at AA in the middle;

[0083] Figure 7 is a structural diagram of a pixel circuit of an array substrate provided in an embodiment of the present application;

[0084] Figure 8 It is a schematic flow chart of a method for preparing an array substrate provided in an embodiment of the present application;

[0085] Figures 9 to 12 It is a schematic diagram of the process structure of a method for preparing an array substrate provided in an embodiment of the present application;

[0086] Fig.13 is a schematic flow chart of a method for preparing an array substrate provided in another embodiment of the present application;

[0087] Fig.14 and Fig.15 It is a schematic diagram of the process structure of a method for preparing an array substrate provided in another embodiment of the present application.

[0088] Description of reference numerals:

[0089] 100, substrate;

[0090] 20a, first semiconductor layer; 210, first active portion; 211, first sublayer; 211a, first outer edge sublayer; 211b, first inner edge sublayer; 211c, first intermediate position layer; 212, first source region; 213, first drain region; 214, first channel region; 20b, second semiconductor layer; 220, second active portion; 221, second sublayer; 221a, second outer edge sublayer; 221b, second inner edge sublayer; 221c, second intermediate position layer; 222, second source region; 223, second drain region; 224, second channel region;

[0091] 310, first insulating layer; 311, third subsection; 312, fourth subsection; 320, second insulating layer; 321, first subsection; 322, second subsection; 330, third insulating layer; 340, fourth insulating layer;

[0092] 410, first grid; 420, second grid; 430, third grid; 440, fourth grid;

[0093] 510, first source; 520, first drain; 530, second source; 540, second drain;

[0094] T1, first transistor; T2, second transistor. DETAILED DESCRIPTION

[0095] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0096] In the description of the present application, it should be noted that, unless otherwise specified, "multiple" means more than two; the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0097] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0098] Please also read Figure 1 and Figure 2 , Figure 1 A partial cross-sectional view of an array substrate provided in an embodiment of the present application, Figure 2 In one example Figure 1 Cross-sectional view at AA in the middle.

[0099] like Figure 1 and Figure 2 As shown, an embodiment of the first aspect of the present application provides an array substrate, the array substrate comprising: a substrate 100; a first semiconductor layer 20a, located on one side of the substrate 100 and comprising a first active portion 210; a first insulating layer 310, located on a side of the first semiconductor layer 20a away from the substrate 100; a second semiconductor layer 20b, located on a side of the first insulating layer 310 away from the substrate 100, the second semiconductor layer 20b comprising a second active portion 220; a first gate 410, located on the back of the first semiconductor layer 20a On the side away from the substrate 100, the orthographic projection of the first gate 410 on the substrate 100 and the orthographic projection of the first active portion 210 on the substrate 100 at least partially overlap; the second gate 420 is located on the side of the second semiconductor layer 20b away from the substrate 100, and the orthographic projection of the second gate 420 on the substrate 100 and the orthographic projection of the second active portion 220 on the substrate 100 at least partially overlap; wherein, the carrier mobility of one of the first active portion 210 and the second active portion 220 is greater than the carrier mobility of the other.

[0100] In the array substrate provided in the embodiment of the present application, the array substrate includes a substrate 100, a first semiconductor layer 20a, a first insulating layer 310, a second semiconductor layer 20b, a first gate 410 and a second gate 420. The orthographic projection of the first gate 410 on the substrate 100 and the orthographic projection of the first active portion 210 of the first semiconductor layer 20a on the substrate 100 at least partially overlap, and the first gate 410 and the first active portion 210 are correspondingly arranged to turn on the first active portion 210. Similarly, the second gate 420 and the second active portion 220 are correspondingly arranged to turn on the second active portion 220. Among the first active part 210 and the second active part 220, the carrier mobility of one is greater than the carrier mobility of the other, that is, the carrier mobility of the first active part 210 and the second active part 220 are different. A first insulating layer 310 is arranged between the first semiconductor layer 20a where the first active part 210 is located and the second semiconductor layer 20b where the second active part 220 is located, so that the carrier concentration in the first active part 210 can be adjusted through the first insulating layer 310, so as to achieve process compatibility between the first active part 210 and the second active part 220, and improve the process performance of the array substrate.

[0101] Optionally, the array substrate includes a first transistor T1 and a second transistor T2, wherein the first transistor T1 includes a first source 510, a first drain 520, the first active portion 210, and a first gate 410, and the second transistor T2 includes a second source 530, a second drain 540, the second active portion 220, and a second gate 420. That is, the first source 510, the first drain 520, the first gate 410, and the first active portion 210 are combined to form the first transistor T1. The second drain 540, the second gate 420, and the second active portion 220 are combined to form the second transistor T2.

[0102] Optionally, the first active portion 210 includes a first source region 212, a first drain region 213, and a first channel region 214 located between the first source region 212 and the first drain region 213. The first source electrode 510 is electrically connected to the first source region 212, the first drain region 213 is electrically connected to the first drain electrode 520, and the orthographic projection of the first gate electrode 410 on the substrate 100 and the orthographic projection of the first channel region 214 on the substrate 100 at least partially overlap. The first gate electrode 410 is used to control whether the first channel region 214 is turned on. When the first channel region 214 is turned on, the first source electrode 510 and the first drain electrode 520 are connected to each other through the first active portion 210, and when the first channel region 214 is disconnected, the first source electrode 510 and the first drain electrode 520 are disconnected from each other.

[0103] Optionally, the second active portion 220 includes a second source region 222, a second drain region 223, and a second channel region 224 located between the second source region 222 and the second drain region 223. The second source 530 is electrically connected to the second source region 222, the second drain region 223 is electrically connected to the second drain 540, and the orthographic projection of the second gate 420 on the substrate 100 and the orthographic projection of the second channel region 224 on the substrate 100 at least partially overlap. The second gate 420 is used to control whether the second channel region 224 is turned on. When the second channel region 224 is turned on, the second source 530 and the second drain 540 are connected to each other through the second active portion 220, and when the second channel region 224 is disconnected, the second source 530 and the second drain 540 are disconnected from each other.

[0104] Optionally, the first transistor T1 and the second transistor T2 are transistors with different mobilities. When the first insulating layer 310 is not provided between the first active portion 210 and the second active portion 220, under the same process conditions, the difference in threshold voltages between the first transistor T1 and the second transistor T2 will be too large. When the threshold voltage requirement of the low-mobility transistor is met, the high-mobility transistor will be severely negatively biased and will not meet the circuit requirement. Alternatively, when the threshold voltage requirement of the high-mobility transistor is met, the stability of the low-mobility transistor will be affected.

[0105] In the embodiment of the present application, since the first insulating layer 310 is arranged between the first active portion 210 and the second active portion 220, the carriers in the semiconductor layer located on the side facing the substrate 100 can be adjusted through the first insulating layer 310, so that the difference in threshold voltage between the first transistor T1 and the second transistor T2 is within a reasonable range, thereby achieving process compatibility between the first transistor T1 and the second transistor T2.

[0106] In some optional embodiments, the thickness of the first insulating layer 310 is 10 nm to 200 nm, so as to improve the problem that the first insulating layer 310 is too thin and the carriers in the first active portion 210 cannot be well adjusted, and the problem that the first insulating layer 310 is too thick and causes material waste can also be improved, thereby avoiding increasing the overall thickness of the array substrate.

[0107] Optionally, the thickness of the first insulating layer 310 may be 10 nm, 23 nm, 58 nm, 69 nm, 140 nm, 185 nm, 200 nm, etc.

[0108] For example, the thickness of the first insulating layer 310 may be 50 nm to 100 nm, so as to ensure that the first insulating layer 310 has sufficient thickness to adjust the carriers in the first active portion 210 and improve the material waste caused by the excessive thickness of the first insulating layer 310 .

[0109] Optionally, the thickness of the first insulating layer 310 may be 50 nm, 53 nm, 58 nm, 69 nm, 80 nm, 85 nm, 100 nm, etc.

[0110] There are many ways to set the material of the first insulating layer 310. For example, the material of the first insulating layer 310 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The hydrogen content and oxygen content of the first insulating layer 310 can be adjusted to adjust the carriers in the first active portion 210, thereby adjusting the threshold voltage of the first transistor T1.

[0111] In some optional embodiments, the carrier mobility of the first active portion 210 is less than the carrier mobility of the second active portion 220, and the materials of the first active portion 210 and the second active portion 220 include metal oxide. Then the first transistor T1 can be a low-transition transistor, and the second transistor T2 can be a high-transition transistor.

[0112] Optionally, the metal oxide includes indium oxide (In Oxide), indium zinc oxide (In-Zn Oxide), indium tin oxide (In-Sn Oxide), indium titanium oxide (In-Ti Oxide), indium gallium oxide (In-Ga Oxide), indium gallium aluminum oxide (In-Ga-Al Oxide), indium gallium tin oxide (In-Ga-Sn Oxide, also written as IGTO), gallium zinc oxide (Ga-Zn Oxide, also written as GZO), aluminum zinc oxide (Al-Zn Oxide, also written as AZO), indium aluminum zinc oxide (In-Al-Zn Oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn Oxide, also written as ITZO), indium titanium zinc oxide (In-Ti-Zn Oxide), indium gallium zinc oxide (In-Ga-Zn Oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn Oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn Oxide, also written as IGAZO, IGZAO or IAGZO), gallium tin oxide (Ga-SnOxide), aluminum tin oxide (Al-Sn Oxide), etc.

[0113] Optionally, when the carrier mobility of the first active portion 210 is less than the carrier mobility of the second active portion 220, the material of the first active portion 210 may include at least one of indium oxide, gallium oxide, zinc oxide, tin oxide, indium gallium zinc oxide, and indium gallium oxide, the number of indium atoms accounting for 30% to 70% of the total number of metal atoms in the first active portion 210, the number of gallium atoms accounting for 0 to 70% of the total number of metal atoms in the first active portion 210, and the number of zinc atoms accounting for 0 to 70% of the total number of metal atoms in the first active portion 210.

[0114] In these optional embodiments, the number of indium atoms in the first active portion 210 accounts for 30% to 70% of the total number of metal atoms in the first active portion 210 . The proportion of indium in the first active portion 210 is small, so that the first active portion 210 has a smaller carrier mobility.

[0115] As an optional embodiment, the atomic ratios of indium, gallium and zinc in the first active portion 210 may be 30%, 0 and 70%, respectively, or the atomic ratios of indium, gallium and zinc in the first active portion 210 may be 30%, 70% and 0%, respectively, or the atomic ratios of indium, gallium and zinc in the first active portion 210 may be 30%, 35% and 35%, respectively, or the atomic ratios of indium, gallium and zinc in the first active portion 210 may be 35%, 5% and 60%, respectively, or the atomic ratios of indium, gallium and zinc in the first active portion 210 may be 70%, 25%, 5%, etc., as long as the sum of the atomic ratios of indium, gallium and zinc in the first active portion 210 is less than or equal to 100%.

[0116] Optionally, the thickness range of the first active portion 210 is 3nm to 100nm, so as to improve the problem that the thickness of the first active portion 210 is too small, affecting the movement of carriers in the first active portion 210, and can also improve the problem that the thickness of the first active portion 210 is too large, resulting in material waste and the first transistor T1 cannot meet the usage requirements.

[0117] For example, the thickness of the first active portion 210 may be 3 nm, 5 nm, 18 nm, 55 nm, 70 nm, 90 nm, 100 nm, or the like.

[0118] Optionally, when the carrier mobility of the first active portion 210 is less than the carrier mobility of the second active portion 220, the material of the second active portion 220 includes at least one of indium oxide, gallium oxide, zinc oxide, tin oxide, indium gallium zinc oxide, and indium gallium oxide, the number of indium atoms accounts for 50% to 100% of the total number of metal atoms in the second active portion 220, the number of gallium atoms accounts for 0-50% of the total number of metal atoms in the second active portion 220, and the number of zinc atoms accounts for 0-50% of the total number of metal atoms in the second active portion 220.

[0119] In these optional embodiments, the number of indium atoms in the second active portion 220 accounts for a relatively high proportion, so that the second active portion 220 has a relatively high carrier mobility.

[0120] As an optional embodiment, the atomic ratios of indium, gallium and zinc in the second active portion 220 may be 100%, 0 and 0, respectively, or the atomic ratios of indium, gallium and zinc in the second active portion 220 may be 90%, 10% and 0, respectively, or the atomic ratios of indium, gallium and zinc in the second active portion 220 may be 90%, 0% and 10%, respectively, or the atomic ratios of indium, gallium and zinc in the second active portion 220 may be 80%, 10% and 10%, respectively, or the atomic ratios of indium, gallium and zinc in the second active portion 220 may be 50%, 35%, 15% and the like, as long as the sum of the atomic ratios of indium, gallium and zinc in the second active portion 220 is less than or equal to 100%.

[0121] Optionally, the thickness of the second active portion 220 ranges from 3nm to 100nm to improve the problem that the thickness of the second active portion 220 is too small, affecting the movement of carriers in the second active portion 220, and can also improve the problem that the thickness of the second active portion 220 is too large, resulting in material waste and the second transistor T2 cannot meet usage requirements.

[0122] For example, the thickness of the second active portion 220 may be 3 nm, 5 nm, 18 nm, 55 nm, 70 nm, 90 nm, 100 nm, or the like.

[0123] Optionally, when the carrier mobility of the first active portion 210 is less than the carrier mobility of the second active portion 220, the proportion of metal atoms of indium in the first active portion 210 is less than the proportion of metal atoms of indium in the second active portion 220, so that the carrier mobility of the first active portion 210 is less than the carrier mobility of the second active portion 220. For example, when the number of indium atoms in the second active portion 220 accounts for 50% of the total number of metal atoms in the second active portion 220, the number of indium atoms in the first active portion 210 accounts for 49%, 40%, etc. of the total number of metal atoms in the first active portion 210; when the number of indium atoms in the second active portion 220 accounts for 80% of the total number of metal atoms in the second active portion 220, the number of indium atoms in the first active portion 210 accounts for 79%, 40%, etc. of the total number of metal atoms in the first active portion 210, as long as the proportion of indium atoms in the first active portion 210 is less than the proportion of indium atoms in the second active portion 220, it will be sufficient.

[0124] In some other optional embodiments, the mobility of the first active portion 210 may be greater than the mobility of the second active portion 220, and the material of the first active portion 210 and / or the second active portion 220 includes metal oxide. Then the first transistor T1 may be a high mobility transistor, and the second transistor T2 may be a low mobility transistor.

[0125] Optionally, the metal oxide includes indium oxide (In Oxide), indium zinc oxide (In-Zn Oxide), indium tin oxide (In-Sn Oxide), indium titanium oxide (In-Ti Oxide), indium gallium oxide (In-Ga Oxide), indium gallium aluminum oxide (In-Ga-Al Oxide), indium gallium tin oxide (In-Ga-Sn Oxide, also written as IGTO), gallium zinc oxide (Ga-Zn Oxide, also written as GZO), aluminum zinc oxide (Al-Zn Oxide, also written as AZO), indium aluminum zinc oxide (In-Al-Zn Oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn Oxide, also written as ITZO), indium titanium zinc oxide (In-Ti-Zn Oxide), indium gallium zinc oxide (In-Ga-Zn Oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn Oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn Oxide, also written as IGAZO, IGZAO or IAGZO), gallium tin oxide (Ga-SnOxide), aluminum tin oxide (Al-Sn Oxide), etc.

[0126] Optionally, when the carrier mobility of the first active portion 210 is greater than the carrier mobility of the second active portion 220, the material of the second active portion 220 may include at least one of indium oxide, gallium oxide, zinc oxide, tin oxide, indium gallium zinc oxide, and indium gallium oxide, the number of indium atoms accounting for 30% to 70% of the total number of metal atoms in the second active portion 220, the number of gallium atoms accounting for 0 to 70% of the total number of metal atoms in the second active portion 220, and the number of zinc atoms accounting for 0 to 70% of the total number of metal atoms in the first active portion 210.

[0127] In these optional embodiments, the number of indium atoms in the second active portion 220 accounts for 30% to 70% of the total number of metal atoms in the first active portion 210. The smaller the proportion of indium in the second active portion 220, the smaller the carrier mobility of the first active portion 210.

[0128] As an optional embodiment, the atomic ratios of indium, gallium and zinc in the second active portion 220 may be 30%, 0 and 70%, respectively, or the atomic ratios of indium, gallium and zinc in the second active portion 220 may be 30%, 70% and 0%, respectively, or the atomic ratios of indium, gallium and zinc in the second active portion 220 may be 30%, 35% and 35%, respectively, or the atomic ratios of indium, gallium and zinc in the second active portion 220 may be 35%, 5% and 60%, respectively, or the atomic ratios of indium, gallium and zinc in the second active portion 220 may be 70%, 25%, 5%, etc., as long as the sum of the atomic ratios of indium, gallium and zinc in the second active portion 220 is less than or equal to 100%.

[0129] Optionally, the thickness of the first active portion 210 and the second active portion 220 is set as described above and will not be repeated here.

[0130] Optionally, when the carrier mobility of the first active portion 210 is greater than the carrier mobility of the second active portion 220, the material of the first active portion 210 includes at least one of indium oxide, gallium oxide, zinc oxide, tin oxide, indium gallium zinc oxide, and indium gallium oxide, the number of indium atoms accounts for 50% to 100% of the total number of metal atoms in the first active portion 210, the number of gallium atoms accounts for 0-50% of the total number of metal atoms in the first active portion 210, and the number of zinc atoms accounts for 0-50% of the total number of metal atoms in the first active portion 210.

[0131] In these optional embodiments, the proportion of metal atoms of indium in the first active portion 210 is relatively high, so that the first active portion 210 has a relatively high carrier mobility.

[0132] As an optional embodiment, the atomic proportions of indium, gallium, and zinc in the first active portion 210 may be 100%, 0, and 0, respectively, or the atomic proportions of indium, gallium, and zinc in the first active portion 210 may be 90%, 10%, and 0, respectively, or the atomic proportions of indium, gallium, and zinc in the first active portion 210 may be 90%, 0%, and 10%, respectively, or the atomic proportions of indium, gallium, and zinc in the first active portion 210 may be 80%, 10%, and 10%, respectively, or the atomic proportions of indium, gallium, and zinc in the first active portion 210 may be 50%, 35%, 15%, etc., as long as the sum of the atomic proportions of indium, gallium, and zinc in the first active portion 210 is less than or equal to 100%.

[0133] Optionally, when the carrier mobility of the first active portion 210 is greater than the carrier mobility of the second active portion 220, the proportion of metal atoms of indium in the first active portion 210 is greater than the proportion of metal atoms of indium in the second active portion 220, so that the carrier mobility of the first active portion 210 is greater than the carrier mobility of the second active portion 220.

[0134] In some optional embodiments, please continue to refer to Figure 1 and Figure 2 The array substrate further includes a second insulating layer 320, which is located on a side of the second semiconductor layer 20b away from the substrate 100, and a second gate 420 is located on a side of the second insulating layer 320 away from the substrate 100. The second insulating layer 320 is provided to achieve mutual insulation between the second gate 420 and the second semiconductor layer 20b.

[0135] There are many ways to set the material of the second insulating layer 320. For example, the material of the second insulating layer 320 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The hydrogen content and oxygen content of the second insulating layer 320 can be adjusted to adjust the carriers in the second active portion 220, thereby adjusting the threshold voltage of the second transistor T2.

[0136] There are many ways to set the first insulating layer 310 and / or the second insulating layer 320, such as Figure 2 and Figure 3 As shown, the first insulating layer 310 can be arranged as a whole layer, that is, the first insulating layer 310 is laid as a whole layer on the side of the first semiconductor layer 20a facing away from the substrate 100, and the first insulating layer 310 is not patterned except that necessary holes are punched in the first insulating layer 310 to achieve electrical connection between the first source 510, the first drain 520 and the first active part 210. Optionally, the second insulating layer 320 can also be arranged as a whole layer.

[0137] Optionally, the first insulating layer 310 is in contact with the first active portion 210 and the second active portion 220, that is, the first insulating layer 310 is located between the first semiconductor layer 20a and the second semiconductor layer 20b, and no other layer structure is arranged between the first semiconductor layer 20a and the second semiconductor layer 20b, so that the first insulating layer 310 is in contact with the first active portion 210 and the second active portion 220.

[0138] Optionally, the second insulating layer 320 contacts the second active part 220. That is, in the manufacturing process, after the second active part 220 is provided, the second insulating layer 320 is immediately formed on the second active part 220, so that the second insulating layer 320 and the second active part 220 can be directly contacted and connected.

[0139] In some other optional embodiments, such as Figure 4 As shown, the first insulating layer 310 and / or the second insulating layer 320 may be disposed in a non-entire layer. For example, the second insulating layer 320 includes a first sub-portion 321 located on the side of the first gate 410 facing the substrate 100 and a second sub-portion 322 located on the side of the second gate 420 facing the substrate 100, and the first sub-portion 321 and the second sub-portion 322 are disposed at intervals.

[0140] In these optional embodiments, the second insulating layer 320 is patterned into a first section 321 and a second section 322, so that the second insulating layer 320 can not only play an insulating role, but also reduce the overall distribution area of ​​the second insulating layer 320, simplify the structure of the array substrate, and reduce the thickness of part of the array substrate, which can further facilitate bending.

[0141] Optionally, the orthographic projection of the first sub-portion 321 on the substrate 100 overlaps with the orthographic projection of the first gate 410 on the substrate 100. In the process of preparing the array substrate, the first gate 410 can be used as a mask to pattern the second insulating layer 320 to form the first sub-portion 321, without adding a new mask, which can simplify the preparation process.

[0142] Optionally, the orthographic projection of the second sub-portion 322 on the substrate 100 overlaps with the orthographic projection of the second gate 420 on the substrate 100. In the process of preparing the array substrate, the second gate 420 can be used as a mask to pattern the second insulating layer 320 to form the second sub-portion 322, without adding a new mask, which can simplify the preparation process.

[0143] Optionally, when the second insulating layer 320 includes a first section 321 and a second section 322, as Figure 5 As shown, the first insulating layer 310 may be arranged as a whole layer, or, as shown in Figure 5 As shown, the first insulating layer 310 may also be arranged as a non-entire layer.

[0144] In some optional embodiments, such as Figure 5 As shown, the first insulating layer 310 includes a third section 311 located on the side of the first section 321 facing the substrate 100 and a fourth section 312 located on the side of the second active portion 220 facing the substrate 100 , and the third section 311 and the fourth section 312 are arranged at intervals.

[0145] In these optional embodiments, the first insulating layer 310 is patterned into a third section 311 and a fourth section 312, so that the first insulating layer 310 can not only play an insulating role, but also reduce the overall distribution area of ​​the first insulating layer 310 and simplify the structure of the array substrate.

[0146] Optionally, the orthographic projection of the third subdivision 311 on the substrate 100 overlaps with the orthographic projection of the first subdivision 321 on the substrate 100. In the process of preparing the array substrate, the first gate 410 can be used as a mask plate to pattern the second insulating layer 320 to form the first subdivision 321, and the first insulating layer 310 can be patterned to form the third subdivision 311, without adding a new mask plate, which can simplify the preparation process. In addition, the third subdivision 311 and the first subdivision 321 can be prepared and formed in the same process step, which can simplify the preparation process of the array substrate.

[0147] Preferably, the orthographic projection of the fourth sub-portion 312 on the substrate 100 overlaps with the orthographic projection of the second active portion 220 on the substrate 100. In the process of preparing the array substrate, the second active portion 220 can be used as a mask plate to pattern the first insulating layer 310 to form the fourth sub-portion 312, without adding a new mask plate, which can simplify the preparation process.

[0148] During the preparation process of the first insulating layer 310 and the second insulating layer 320, after the first gate 410 and the second gate 420 are prepared, the first gate 410 and the second gate 420 can be used as mask plates to pattern the first insulating layer 310 and the second insulating layer 320 to form a first division 321, a second division 322 and a third division 311, and due to the shielding of the second active portion 220, a fourth division 312 is formed.

[0149] There are many ways to configure the first active portion 210, such as Figures 1 to 5 As shown, the first active portion 210 may be a single layer or a stacked layer. When the first active portion 210 is a single layer, the carrier mobility of the first active portion 210 is greater than or less than the carrier mobility of the second active portion 220 .

[0150] Or, if Figure 6 As shown, when the first active portion 210 is a stacked layer and includes a plurality of stacked first sub-layers 211 , the carrier mobility of each of the first sub-layers 211 is greater than or less than the carrier mobility of the second active portion 220 .

[0151] Optionally, the first sub-layers 211 are stacked to form the first source region 212 , the first drain region 213 and the first channel region 214 .

[0152] There are many ways to set the number of first sublayers 211. The number of first sublayers 211 can be two, and the carrier mobility of the two first sublayers 211 can be different to adjust the overall carrier mobility of the first active portion 210 to an appropriate range.

[0153] Alternatively, the number of the first sublayers 211 may be three, and the carrier mobility of the first sublayer 211 located in the middle is greater than the carrier mobility of the other first sublayers 211. The first sublayer 211 in the middle has the largest mobility, which can improve the migration efficiency of the carriers and ensure the performance of the first active portion 210.

[0154] Optionally, when the number of first sublayers 211 is three or more, the multiple first sublayers 211 may include a first outer edge sublayer 211a, a first inner edge sublayer 211b and a first middle position layer 211c, the first outer edge sublayer 211a is located on the side of the first middle position layer 211c facing away from the substrate 100, the first inner edge sublayer 211b is located on the side of the first middle position layer 211c facing the substrate 100, and the carrier mobility of the first outer edge sublayer 211a and the first inner edge sublayer 211b are both less than the carrier mobility of the first middle position layer 211c.

[0155] In some optional embodiments, the number of first sublayers 211 can be more than four, and the more than four first sublayers 211 include the above-mentioned first outer edge sublayer 211a, the first inner edge sublayer 211b and the first middle position layer 211c, and any first sublayer 211 located between the first outer edge sublayer 211a and the first inner edge sublayer 211b can be the first middle position layer 211c.

[0156] There are many ways to configure the second active portion 220, such as Figures 1 to 5 As shown, the second active portion 220 may be a single layer or a stacked layer. When the second active portion 220 is a single layer, the carrier mobility of the second active portion 220 is greater than or less than the carrier mobility of the second active portion 220.

[0157] Or, if Figure 6 As shown, when the second active portion 220 is a stacked layer and includes a plurality of stacked second sub-layers 221 , the carrier mobility of each of the second sub-layers 221 is greater than or less than the carrier mobility of the second active portion 220 .

[0158] There are many ways to set the number of the second sublayers 221. The number of the second sublayers 221 can be two, and the carrier mobility of the two second sublayers 221 can be different to adjust the overall carrier mobility of the second active portion 220 to an appropriate range.

[0159] Alternatively, the number of the second sublayers 221 may be three, and the carrier mobility of the second sublayer 221 located in the middle is greater than the carrier mobility of the other second sublayers 221. The second sublayer 221 in the middle has the largest mobility, which can improve the migration efficiency of the carriers and ensure the performance of the second active portion 220.

[0160] Optionally, when the number of second sublayers 221 is three or more, the multiple second sublayers 221 may include a second outer edge sublayer 221a, a second inner edge sublayer 221b and a second intermediate position layer 221c, the second outer edge sublayer 221a is located on the side of the second intermediate position layer 221c facing away from the substrate 100, the second inner edge sublayer 221b is located on the side of the second intermediate position layer 221c facing the substrate 100, and the carrier mobility of the second outer edge sublayer 221a and the second inner edge sublayer 221b are both less than the carrier mobility of the second intermediate position layer 221c.

[0161] In some optional embodiments, the number of second sublayers 221 can also be more than four, and the more than four second sublayers 221 include the above-mentioned second outer edge sublayer 221a, the second inner edge sublayer 221b and the second middle position layer 221c, and any second sublayer 221 located between the second outer edge sublayer 221a and the second inner edge sublayer 221b can be the second middle position layer 221c.

[0162] Optionally, when the array substrate includes the first transistor T1 and the second transistor T2, the absolute value of the difference in threshold voltage between the first transistor T1 and the second transistor T2 is less than or equal to 0.4V, so that the threshold voltages of the first transistor T1 and the second transistor T2 are close to each other, and the first transistor T1 and the second transistor T2 can be compatible. For example, the absolute value of the difference in threshold voltage between the first transistor T1 and the second transistor T2 is 0.35V, 0.30V, 0.28V, 0.22V, 0.15V, etc.

[0163] like Figure 7 As shown, the array substrate may include a pixel circuit, and the pixel circuit may include a switching transistor (S-TFT), a driving transistor (D-TFT), and a capacitor (C). The driving transistor (D-TFT) is connected between the power signal line (VDD) and the light emitting element (EL), the gate of the switching transistor (S-TFT) is connected to the scanning signal line (Scan), one of the source and the drain of the switching transistor (S-TFT) is connected to the data signal line (Data), and the other of the source and the drain of the switching transistor (S-TFT) is connected to the gate of the driving transistor (D-TFT). When there are driving signals on both the scanning signal line (Scan) and the data signal line (Data), the source and the drain of the switching transistor (S-TFT) are turned on, the gate of the driving transistor (D-TFT) controls the source and the drain of the driving transistor (D-TFT) to turn on, and the power signal line (VDD) and the light emitting element (EL) are turned on to drive the light emitting element (EL) to emit light.

[0164] Optionally, when the carrier mobility of the first active portion 210 is less than the carrier mobility of the second active portion 220, that is, the first transistor T1 is a low-mobility transistor and the second transistor T2 is a high-mobility transistor, optionally, the first transistor T1 is a driving transistor (D-TFT) of the pixel circuit, and the second transistor T2 is a gate driving circuit transistor or a switching transistor (S-TFT) of the pixel circuit to meet the use requirements of the array substrate.

[0165] Alternatively, optionally, when the carrier mobility of the first active portion 210 is greater than the carrier mobility of the second active portion 220, that is, the second transistor T2 is a low-mobility transistor and the first transistor T1 is a high-mobility transistor, optionally, the second transistor T2 is a driving transistor (D-TFT) of the pixel circuit, and the first transistor T1 is a gate driving circuit transistor or a switching transistor (S-TFT) of the pixel circuit to meet the use requirements of the array substrate.

[0166] Optionally, in the above embodiment, the first transistor T1 and the second transistor T2 can both be top-gate transistors, that is, the first gate 410 of the first transistor T1 is located on the side of the first active portion 210 away from the substrate 100, and the second gate 420 of the second transistor T2 is located on the side of the second active portion 220 away from the substrate 100.

[0167] In some further optional embodiments, at least one of the first transistor T1 and the second transistor T2 may also be a dual-gate transistor.

[0168] For example, Figure 3 As shown, the array substrate further includes a third gate 430, which is located on the side of the first active portion 210 facing the substrate 100. The third gate 430 and the first gate 410 can serve as two gates of the first transistor T1, so that the first transistor T1 can become a dual-gate transistor. The third gate 430 can not only assist in controlling the on and off of the first active portion 210, but also play a light shielding role, improving the light incident on the first active portion 210 from the side of the first active portion 210 facing the substrate 100 and affecting its performance.

[0169] Optionally, when the first transistor T1 includes the third gate 430, the orthographic projection of the first gate 410 on the substrate 100 is located within the orthographic projection of the third gate 430 on the substrate 100. That is, the distribution area of ​​the first gate 410 may be smaller than the distribution area of ​​the third gate 430, and the first gate 410 may better assist in controlling the on and off of the first active portion 210, and is more conducive to light shielding, so as to improve the performance of the first transistor T1.

[0170] In some other embodiments, the array substrate further includes a fourth gate 440, which is located on the side of the second active portion 220 facing the substrate 100. The fourth gate 440 and the second gate 420 can serve as two gates of the second transistor T2, so that the second transistor T2 can become a dual-gate transistor. The fourth gate 440 can not only assist in controlling the on and off of the second active portion 220, but also play a light shielding role, improving the light incident on the second active portion 220 from the side of the second active portion 220 facing the substrate 100 and affecting its performance.

[0171] Optionally, when the second transistor T2 includes the fourth gate 440, the orthographic projection of the second gate 420 on the substrate 100 is located within the orthographic projection of the fourth gate 440 on the substrate 100. That is, the distribution area of ​​the second gate 420 may be smaller than the distribution area of ​​the fourth gate 440, and the second gate 420 may better assist in controlling the on and off of the second active portion 220, and is more conducive to light shielding, so as to improve the performance of the second transistor T2.

[0172] Optionally, the third gate 430 and the fourth gate 440 may be provided in the same layer and with the same material, so that the third gate 430 and the fourth gate 440 may be manufactured and formed in the same process step, so as to simplify the manufacturing process of the array substrate.

[0173] Optionally, the array substrate may include a light shielding layer, which may be reused as the third gate 430 and / or the fourth gate 440, so that the third gate 430 and / or the fourth gate 440 can not only serve as the gate of the dual-gate transistor but also have a light shielding effect.

[0174] Optionally, the array substrate also includes a third insulating layer 330, which is located on the side of the first gate 410 and the second gate 420 away from the substrate 100, and the first source 510, the first drain 520, the second source 530 and the second drain 540 can be located on the side of the third insulating layer 330 away from the substrate 100 to improve the short circuit problem between different conductive layers.

[0175] Optionally, the first source electrode 510 , the first drain electrode 520 , the second source electrode 530 , and the second drain electrode 540 may be disposed in the same layer to simplify the structure and preparation process of the array substrate.

[0176] Optionally, the array substrate further includes a fourth insulating layer 340 , and the fourth insulating layer 340 is located between the third gate 430 and the first active portion 210 to prevent the third gate 430 from being in direct contact with the first active portion 210 .

[0177] like Figures 1 to 7As shown, the embodiment of the first aspect of the present application further provides an array substrate, the array substrate comprising: a substrate 100; a first semiconductor layer 20a, located at one side of the substrate 100 and comprising a first active portion 210; a first insulating layer 310, located at a side of the first semiconductor layer 20a away from the substrate 100; a second semiconductor layer 20b, located at a side of the first insulating layer 310 away from the substrate 100, the second semiconductor layer 20b comprising a second active portion 220; a first gate 410, located at a side of the first semiconductor layer 20a away from the substrate 1 00, the first gate 410 and the first active portion 210 at least partially overlap in their orthographic projection on the substrate 100; the second gate 420 is located on the side of the second semiconductor layer 20b away from the substrate 100, and the orthographic projection of the second gate 420 and the second active portion 220 at least partially overlap in their orthographic projection on the substrate 100; wherein the materials of the first active portion 210 and the second active portion 220 both include indium, and the indium content of one of them is greater than that of the other.

[0178] In the array substrate provided in the embodiment of the present application, the array substrate includes a substrate 100, a first semiconductor layer 20a, a first insulating layer 310, a second semiconductor layer 20b, a first gate 410 and a second gate 420, the orthographic projection of the first gate 410 on the substrate 100 and the orthographic projection of the first active portion 210 of the first semiconductor layer 20a on the substrate 100 at least partially overlap, and the first gate 410 and the first active portion 210 are correspondingly arranged to turn on the first active portion 210. Similarly, the second gate 420 and the second active portion 220 are correspondingly arranged to turn on the second active portion 220. In the first active part 210 and the second active part 220, the materials of the first active part 210 and the second active part 220 both include indium, and the indium content of one of them is greater than that of the other, so that the carrier mobility of one of them is greater than that of the other, that is, the carrier mobilities of the first active part 210 and the second active part 220 are different, and a first insulating layer 310 is arranged between the first semiconductor layer 20a where the first active part 210 is located and the second semiconductor layer 20b where the second active part 220 is located, so that the carrier concentration of the first active part 210 can be adjusted through the first insulating layer 310, so as to achieve process compatibility between the first active part 210 and the second active part 220, and improve the process performance of the array substrate.

[0179] In some optional embodiments, the first active portion 210 is a single layer, or the first active portion 210 includes a plurality of stacked first sub-layers 211 , and the indium content of each first sub-layer 211 is greater than or less than the indium content of the second active portion 220 .

[0180] There are many ways to set the number of the first sublayers 211. The number of the first sublayers 211 can be two, and the indium contents of the two first sublayers 211 can be different to adjust the overall carrier mobility of the first active portion 210 to a suitable range.

[0181] Alternatively, the number of the first sublayers 211 may be three, and the indium content of the first sublayer 211 at the middle position is greater than the indium content of the other first sublayers 211. This maximizes the mobility of the first sublayer 211 at the middle position, improves the migration efficiency of carriers, and ensures the performance of the first active portion 210.

[0182] Optionally, when the number of first sublayers 211 is three or more, the multiple first sublayers 211 may include the above-mentioned first outer edge sublayer 211a, the first inner edge sublayer 211b and the first middle position layer 211c, and the indium content of the first outer edge sublayer 211a and the first inner edge sublayer 211b are both less than the indium content of the first middle position layer 211c.

[0183] In some optional embodiments, the number of first sublayers 211 can be more than four, and the more than four first sublayers 211 include the above-mentioned first outer edge sublayer 211a, the first inner edge sublayer 211b and the first middle position layer 211c, and any first sublayer 211 located between the first outer edge sublayer 211a and the first inner edge sublayer 211b can be the first middle position layer 211c.

[0184] In some optional embodiments, the second active portion 220 is a single layer, or the second active portion 220 includes a plurality of stacked second sub-layers 221 , and the indium content of each second sub-layer 221 is greater than or less than the indium content of the second active portion 220 .

[0185] There are many ways to set the number of the second sublayers 221. The number of the second sublayers 221 can be two, and the indium contents of the two second sublayers 221 can be different to adjust the overall carrier mobility of the second active portion 220 to an appropriate range.

[0186] Alternatively, the number of the second sublayers 221 may be three, and the indium content of the second sublayer 221 at the middle position is greater than the indium content of the other second sublayers 221. This maximizes the mobility of the second sublayer 221 at the middle position, improves the migration efficiency of carriers, and ensures the performance of the second active portion 220.

[0187] Optionally, when the number of second sublayers 221 is three or more, the multiple second sublayers 221 may include the above-mentioned second outer edge sublayer 221a, second inner edge sublayer 221b and second middle position layer 221c, and the indium content of the second outer edge sublayer 221a and the second inner edge sublayer 221b are both less than the indium content of the second middle position layer 221c.

[0188] In some optional embodiments, the number of second sublayers 221 can also be more than four, and the more than four second sublayers 221 include the above-mentioned second outer edge sublayer 221a, the second inner edge sublayer 221b and the second middle position layer 221c, and any second sublayer 221 located between the second outer edge sublayer 221a and the second inner edge sublayer 221b can be the second middle position layer 221c.

[0189] The display panel of the embodiment of the present application and the display panel of any of the above embodiments may be cross-referenced to each other.

[0190] The second aspect of the present application also provides a method for preparing an array substrate. The array substrate may be the array substrate provided by any of the first aspect embodiments described above. Figures 1 to 8 , the preparation method of the array substrate comprises:

[0191] Step S01: Fig. 9 As shown, a first active material layer is disposed on one side of a substrate 100 , and the first active material layer is patterned to form a first semiconductor layer 20 a having a first active portion 210 .

[0192] Step S02: Fig.10 As shown, a first insulating layer 310 is disposed on a side of the first semiconductor layer 20 a facing away from the substrate 100 .

[0193] Step S03: Fig.11 As shown, a second active material layer is disposed on a side of the first insulating layer 310 facing away from the substrate 100 , and the second active material layer is patterned to form a second semiconductor layer 20 b having a second active portion 220 .

[0194] Step S04: Fig.12 As shown, a first gate 410 and a second gate 420 are prepared on the side of the second semiconductor layer 20b facing away from the substrate, and the orthographic projection of the first gate 410 on the substrate 100 and the orthographic projection of the first active portion 210 on the substrate 100 at least partially overlap, and the orthographic projection of the second gate 420 on the substrate 100 and the orthographic projection of the second active portion 220 on the substrate 100 at least partially overlap.

[0195] Among them, the carrier mobility of one of the first active portion 210 and the second active portion 220 is greater than the carrier mobility of the other.

[0196] In the array substrate prepared in the embodiment of the present application, the array substrate includes a substrate 100, a first semiconductor layer 20a, a first insulating layer 310, a second semiconductor layer 20b, a first gate 410 and a second gate 420. The orthographic projection of the first gate 410 on the substrate 100 and the orthographic projection of the first active portion 210 of the first semiconductor layer 20a on the substrate 100 at least partially overlap, and the first gate 410 and the first active portion 210 are correspondingly arranged to make the first active portion 210 conductive. Similarly, the second gate 420 and the second active portion 220 are correspondingly arranged to make the second active portion 220 conductive. The carrier mobility of one of the first active portion 210 and the second active portion 220 is greater than the carrier mobility of the other, that is, the carrier mobility of the first active portion 210 and the second active portion 220 is different. Step S02 is provided between step S01 and step S03 to form the first insulating layer 310, so as to adjust the carrier concentration of the first active portion 210 through the first insulating layer 310, achieve process compatibility between the first active portion 210 and the second active portion 220, and improve the process performance of the array substrate.

[0197] In some optional embodiments, such as Fig.12 As shown, before step S04, the method may further include: preparing a second insulating layer 320 on the side of the second semiconductor layer 20b away from the substrate 100. Then in step S04, a first gate 410 and a second gate 420 may be prepared on the side of the second insulating layer 320 away from the substrate 100 to improve the short circuit connection problem between the second gate 420 and the second active part 220.

[0198] In some optional embodiments, please refer to Fig.13 The preparation method may further include:

[0199] Step S05: Fig.14 As shown, the second insulating layer 320 is patterned using the first gate 410 and the second gate 420 as masks, so that the second insulating layer 320 includes a first section 321 located on the side of the first gate 410 facing the substrate 100 and a second section 322 located on the side of the second gate 420 facing the substrate 100, and the first section 321 and the second section 322 are spaced apart.

[0200] In these optional embodiments, after preparing the first gate 410 and the second gate 420, the second insulating layer 320 can be directly patterned using the first gate 410 and the second gate 420 as masks to form the first section 321 and the second section 322, thereby simplifying the array substrate structure and reducing the overall distribution area of ​​the second insulating layer 320.

[0201] Optionally, in step S05, Fig.15As shown, the first insulating layer 310 is further patterned so that the first insulating layer 310 includes a third sub-portion 311 located on the side of the first sub-portion 321 facing the substrate 100 and a fourth sub-portion 312 located on the side of the second active portion 220 facing the substrate 100, and the third sub-portion 311 and the fourth sub-portion 312 are arranged at intervals. While simplifying the array substrate structure, the overall distribution area of ​​the second insulating layer 320 can be reduced.

[0202] Optionally, when the array substrate includes the third gate 430 and / or the fourth gate 440, before step S01, the third gate 430 and / or the fourth gate 440 are further prepared on one side of the substrate 100, and a fourth insulating layer 340 is provided on a side of the third gate 430 and / or the fourth gate 440 facing away from the substrate 100. In step S01, a first semiconductor layer 20a having a first active portion 210 may be prepared on the fourth insulating layer 340.

[0203] For example, before step S01, the method further includes: Fig.15 As shown, a gate material layer is disposed on one side of the substrate 100 , and the gate material layer is patterned to form a third gate 430 . In step S01 : the first active portion 210 is located on a side of the third gate 430 away from the substrate 100 .

[0204] Optionally, when the array substrate includes the fourth insulating layer 340 , the first active portion 210 is located on a side of the fourth insulating layer 340 facing away from the substrate 100 , and an orthographic projection of the first active portion 210 on the substrate 100 at least partially overlaps with an orthographic projection of the third gate 430 on the substrate 100 .

[0205] And / or, before step S03, the method further includes: Fig.15 As shown, a gate material layer is disposed on one side of the substrate 100 , and the gate material layer is patterned to form a fourth gate 440 . In step S03 : the second active portion 220 is located on a side of the fourth gate 440 away from the substrate 100 .

[0206] Optionally, when the array substrate includes a fourth insulating layer 340 , the second active portion 220 is located on the side of the fourth insulating layer 340 and the first insulating layer 310 facing away from the substrate 100 , and the orthographic projection of the second active portion 220 on the substrate 100 and the orthographic projection of the fourth gate 440 on the substrate 100 at least partially overlap.

[0207] Optionally, the third gate 430 and the fourth gate 440 can be prepared and formed in the same process step. For example, before step S01, the process further includes: disposing a gate material layer on one side of the substrate 100, and patterning the gate material layer to form the third gate 430 and the fourth gate 440. A fourth insulating layer 340 is disposed on the side of the third gate 430 and the fourth gate 440 facing away from the substrate 100.

[0208] The second aspect of the present application also provides a display panel, comprising any array substrate of the first aspect, or an array substrate prepared by any embodiment of the second aspect. The display panel of the embodiment of the present application can be a liquid crystal display panel, an organic light emitting diode display panel, or a micro light emitting diode display panel.

[0209] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises: substrate; A first semiconductor layer, located on one side of the substrate and including a first active portion; A first insulating layer, located on a side of the first semiconductor layer facing away from the substrate; A second semiconductor layer, located on a side of the first insulating layer away from the substrate, the second semiconductor layer comprising a second active portion; A first gate is located on a side of the first semiconductor layer facing away from the substrate, and an orthographic projection of the first gate on the substrate and an orthographic projection of the first active portion on the substrate at least partially overlap; A second gate is located on a side of the second semiconductor layer facing away from the substrate, and an orthographic projection of the second gate on the substrate and an orthographic projection of the second active portion on the substrate at least partially overlap; Among them, the carrier mobility of one of the first active portion and the second active portion is greater than the carrier mobility of the other.

2. The array substrate according to claim 1, characterized in that: The thickness of the first insulating layer is 10nm to 200nm; Preferably, the thickness of the first insulating layer is 50 nm to 100 nm.

3. The array substrate according to claim 1, characterized in that: The carrier mobility of the first active portion is smaller than the carrier mobility of the second active portion, and the material of the first active portion and / or the second active portion includes a metal oxide; Preferably, the material of the first active part includes at least one of indium oxide, gallium oxide, zinc oxide, tin oxide, indium gallium zinc oxide, and indium gallium oxide, the number of indium atoms accounts for 30% to 70% of the total number of metal atoms in the first active part, the number of gallium atoms accounts for 0 to 70% of the total number of metal atoms in the first active part, and the number of zinc atoms accounts for 0 to 70% of the total number of metal atoms in the first active part; Preferably, the thickness of the first active portion ranges from 3 nm to 100 nm; Preferably, the material of the second active portion includes at least one of indium oxide, gallium oxide, zinc oxide, tin oxide, indium gallium zinc oxide, and indium gallium oxide, the number of indium atoms accounts for 50% to 100% of the total number of metal atoms in the second active portion, the number of gallium atoms accounts for 0-50% of the total number of metal atoms in the second active portion, and the number of zinc atoms accounts for 0-50% of the total number of metal atoms in the second active portion; Preferably, the thickness of the second active portion ranges from 3 nm to 100 nm; Preferably, the proportion of metal atoms of indium in the first active portion is smaller than the proportion of metal atoms of indium in the second active portion.

4. The array substrate according to claim 1, characterized in that: The carrier mobility of the first active portion is greater than the carrier mobility of the second active portion, and the material of the first active portion and / or the second active portion includes a metal oxide; Preferably, the material of the second active portion includes at least one of indium oxide, gallium oxide, zinc oxide, tin oxide, indium gallium zinc oxide, and indium gallium oxide, the number of indium atoms accounts for 30% to 70% of the total number of metal atoms in the first active portion, the number of gallium atoms accounts for 0 to 70% of the total number of metal atoms in the first active portion, and the number of zinc atoms accounts for 0 to 70% of the total number of metal atoms in the first active portion; Preferably, the thickness of the second active portion ranges from 3 nm to 100 nm; Preferably, the material of the first active part includes at least one of indium oxide, gallium oxide, zinc oxide, tin oxide, indium gallium zinc oxide, and indium gallium oxide, the number of indium atoms accounts for 50% to 100% of the total number of metal atoms in the second active part, the number of gallium atoms accounts for 0-50% of the total number of metal atoms in the second active part, and the number of zinc atoms accounts for 0-50% of the total number of metal atoms in the second active part; Preferably, the thickness of the first active portion ranges from 3 nm to 100 nm; Preferably, the proportion of metal atoms of indium in the first active portion is greater than the proportion of metal atoms of indium in the second active portion.

5. The array substrate according to any one of claims 1 to 4, characterized in that: It also includes a second insulating layer located on a side of the second semiconductor layer away from the substrate, and the second gate is located on a side of the second insulating layer away from the substrate; Preferably, the first insulating layer and / or the second insulating layer are arranged as a whole layer; Preferably, the first insulating layer is in contact with the first active portion and the second active portion; Preferably, the second insulating layer is in contact with the second active portion.

6. The array substrate according to claim 5, characterized in that: The first gate is located on a side of the second insulating layer away from the substrate; Preferably, the first gate and the second gate are arranged in the same layer.

7. The array substrate according to claim 6, characterized in that: The second insulating layer comprises a first sub-portion located at a side of the first gate facing the substrate and a second sub-portion located at a side of the second gate facing the substrate, wherein the first sub-portion and the second sub-portion are arranged at intervals; Preferably, the orthographic projection of the first sub-portion on the substrate overlaps with the orthographic projection of the first gate on the substrate; Preferably, an orthographic projection of the second section on the substrate overlaps with an orthographic projection of the second gate on the substrate.

8. The array substrate according to claim 7, characterized in that: The first insulating layer comprises a third section located on a side of the first section facing the substrate and a fourth section located on a side of the second active section facing the substrate, wherein the third section and the fourth section are arranged at intervals; Preferably, the orthographic projection of the third section on the substrate overlaps with the orthographic projection of the first section on the substrate; Preferably, an orthographic projection of the fourth portion on the substrate overlaps with an orthographic projection of the second active portion on the substrate.

9. The array substrate according to claim 1, characterized in that: The first active portion is a single-layer arrangement, or the first active portion includes a plurality of first sub-layers arranged in a stacked manner, and the carrier mobility of each of the first sub-layers is greater than or less than the carrier mobility of the second active portion; Preferably, the first active portion includes two first sub-layers, and the two first sub-layers have different carrier mobilities; Alternatively, the first active portion includes three first sub-layers, and the carrier mobility of the first sub-layer located in the middle is greater than the carrier mobility of the other first sub-layers.

10. The array substrate according to claim 1, characterized in that: The second active portion is a single layer, or the second active portion includes a plurality of second sublayers stacked in layers, and the carrier mobility of each of the second sublayers is greater than or less than the carrier mobility of the first active portion; Preferably, the second active portion includes two second sub-layers, and the two second sub-layers have different carrier mobilities; Alternatively, the second active portion includes three second sub-layers, and the carrier mobility of the second sub-layer located in the middle is greater than the carrier mobility of the other second sub-layers.

11. The array substrate according to claim 1, characterized in that: The first active portion includes a first source electrode and a first drain electrode, the first active portion includes a first source region and a first drain region, the first source electrode is electrically connected to the first source region, the first drain electrode is electrically connected to the first drain region, and the first source electrode, the first drain electrode, the first gate electrode and the first active portion are combined to form a first transistor; Also includes a second source and a second drain, the second active portion includes a second source region and a second drain region, the second source is electrically connected to the second source region, the second drain is electrically connected to the second drain region, and the second source, the second drain, the second gate and the second active portion are combined to form a second transistor; Wherein, the absolute value of the difference between the threshold voltages of the first transistor and the second transistor is less than or equal to 0.4V; Preferably, the carrier mobility of the first active portion is smaller than the carrier mobility of the second active portion, the first transistor is a pixel circuit driving transistor, and the second transistor is a gate driving circuit transistor or a pixel circuit switching transistor; Alternatively, the carrier mobility of the first active portion is greater than the carrier mobility of the second active portion, the first transistor is a gate drive circuit transistor or a pixel circuit switch transistor, and the second transistor is a pixel circuit drive transistor.

12. The array substrate according to claim 1, characterized in that: Also includes: a third gate, located on a side of the first active portion facing the substrate; Preferably, the orthographic projection of the first grid on the substrate is located within the orthographic projection of the third grid on the substrate; Preferably, it further comprises a fourth gate located on a side of the second active portion facing the substrate; Preferably, the orthographic projection of the second grid on the substrate is located within the orthographic projection of the fourth grid on the substrate; Preferably, it further comprises a light shielding layer, and the light shielding layer is multiplexed as the third gate and / or the fourth gate.

13. An array substrate, characterized in that: The array substrate comprises: substrate; A first semiconductor layer, located on one side of the substrate and including a first active portion; A first insulating layer, located on a side of the first semiconductor layer facing away from the substrate; A second semiconductor layer, located on a side of the first insulating layer away from the substrate, the second semiconductor layer comprising a second active portion; A first gate is located on a side of the first semiconductor layer facing away from the substrate, and an orthographic projection of the first gate on the substrate and an orthographic projection of the first active portion on the substrate at least partially overlap; A second gate is located on a side of the second semiconductor layer facing away from the substrate, and an orthographic projection of the second gate on the substrate and an orthographic projection of the second active portion on the substrate at least partially overlap; The materials of the first active portion and the second active portion both include indium, and the indium content of one is greater than that of the other.

14. The array substrate according to claim 13, characterized in that: The first active portion is a single-layer arrangement, or the first active portion includes a plurality of first sub-layers arranged in a stacked manner, and the indium content of each of the first sub-layers is greater than or less than the indium content of the second active portion; Preferably, the first active portion includes two first sub-layers, and the indium contents of the two first sub-layers are different; Alternatively, the first active portion includes three first sub-layers, and the indium content of the first sub-layer located in the middle is greater than the indium content of the other first sub-layers.

15. The array substrate according to claim 13, characterized in that: The second active portion is a single-layer arrangement, or the second active portion includes a plurality of second sub-layers arranged in a stacked manner, and the indium content of each of the second sub-layers is greater than or less than the indium content of the first active portion; Preferably, the second active portion includes two second sub-layers, and the two second sub-layers have different indium contents; Alternatively, the second active portion includes three second sub-layers, and the indium content of the second sub-layer located in the middle is greater than the indium content of the other second sub-layers.

16. A method for preparing an array substrate, characterized in that: include: Disposing a first active material layer on one side of the substrate, and patterning the first active material layer to form a first semiconductor layer having a first active portion; Disposing a first insulating layer on a side of the first semiconductor layer facing away from the substrate; Disposing a second active material layer on a side of the first insulating layer away from the substrate, and patterning the second active material layer to form a second semiconductor layer having a second active portion; A first gate and a second gate are formed on a side of the second semiconductor layer facing away from the substrate, wherein an orthographic projection of the first gate on the substrate at least partially overlaps with an orthographic projection of the first active portion on the substrate, and an orthographic projection of the second gate on the substrate at least partially overlaps with an orthographic projection of the second active portion on the substrate; Among them, the carrier mobility of one of the first active portion and the second active portion is greater than the carrier mobility of the other.

17. The preparation method according to claim 16, characterized in that: Before the step of preparing the first gate and the second gate on the side of the second semiconductor layer facing away from the substrate, the step further includes: forming a second insulating layer on a side of the second semiconductor layer facing away from the substrate; In the step of preparing the first gate and the second gate on the side of the second semiconductor layer facing away from the substrate, the first gate and the second gate are prepared on the side of the second insulating layer facing away from the substrate.

18. The preparation method according to claim 17, characterized in that: Also includes: Using the first gate and the second gate as masks, patterning the second insulating layer so that the second insulating layer includes a first sub-portion located on a side of the first gate facing the substrate and a second sub-portion located on a side of the second gate facing the substrate, and the first sub-portion and the second sub-portion are arranged at intervals; Preferably, in the step of patterning the second insulating layer using the first gate and the second gate as mask plates, the first insulating layer is also patterned so that the first insulating layer includes a third division located on the side of the first division facing the substrate and a fourth division located on the side of the second active portion facing the substrate, and the third division and the fourth division are arranged at intervals.

19. The preparation method according to claim 16, characterized in that: Before the step of providing a first active material layer on one side of the substrate and patterning the first active material layer to form a first semiconductor layer having a first active portion, the method further includes: Disposing a gate material layer on one side of the substrate, and patterning the gate material layer to form a third gate; In the step of providing a first active material layer on one side of the substrate and patterning the first active material layer to form a first semiconductor layer having a first active portion: the first active portion is located on a side of the third gate away from the substrate; And / or, before the step of disposing a second active material layer on a side of the first insulating layer away from the substrate and patterning the second active material layer to form a second semiconductor layer having a second active portion, the method further includes: Disposing a gate material layer on one side of the substrate, and patterning the gate material layer to form a fourth gate; In the step of providing a second active material layer on a side of the first insulating layer away from the substrate, and patterning the second active material layer to form a second semiconductor layer having a second active portion: the second active portion is located on a side of the fourth gate away from the substrate; Preferably, before the step of providing a first active material layer on one side of the substrate and patterning the first active material layer to form a first semiconductor layer having a first active portion, the step further includes: A gate material layer is disposed on one side of the substrate, and the gate material layer is patterned to form the third gate and the fourth gate.

20. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 15, or the array substrate prepared by the method according to any one of claims 16 to 19.

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