High-voltage LED chip and preparation method thereof

Abstract

The invention discloses a high-voltage LED chip and a preparation method thereof. The preparation method comprises the following steps: coating one side, far away from a substrate, of an epitaxial layer with positive photoresist; providing a first mask plate, adjusting the position of the first mask plate to enable the preset position of the light-transmitting area of the first mask plate to correspond to the preset position of the non-bridging area, and performing exposure treatment to enable the non-bridging area to form an inclined plane with a steep angle; a second mask plate is provided, the second mask plate is provided with a plurality of light-transmitting areas of different sizes, the position of the second mask plate is adjusted so that the light-transmitting areas of the second mask plate can correspond to the preset positions of the bridging areas, n times of photoetching are carried out through the light-transmitting areas of the second mask plate of different sizes so that the bridging areas can form inclined planes with gentle angles, n is an integer greater than or equal to 1; and carrying out developing treatment and etching treatment. By implementing the preparation method disclosed by the invention, the light-emitting area is effectively increased, and meanwhile, electrode bridging is facilitated, so that the obtained high-voltage LED chip has good light-emitting efficiency and light-emitting brightness.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a high-voltage LED chip and a preparation method thereof. Background Art

[0002] LED (Light Emitting Diode) is a semiconductor light-emitting device that can convert electrical energy into light energy. With the development and progress of LED chip manufacturing technology, LED chips have gradually become a new mainstream lighting source after incandescent lamps and fluorescent lamps. They have the advantages of small size, fast response, long life, environmental protection and energy saving, and are widely used in lighting, display screens and other fields.

[0003] LED chips can be roughly divided into two categories: normal voltage LED chips and high voltage LED chips. In the limited packaging bracket space, it is difficult to connect multiple normal voltage chips in series to form high-power lamp beads, especially wire bonding. For this reason, high voltage LED chips came into being. High voltage LED chips are formed by connecting multiple PN junctions in series through chip technology. Normal voltage LED chips are generally called 3V chips, while high voltage LED chips are of various types such as 6V, 9V, 12V, and 18V. Its structure consists of a substrate, an epitaxial layer, and a chip layer. The epitaxy generally includes an N-type semiconductor, a quantum well layer, and a P-type semiconductor; the chip structure from bottom to top is a current blocking layer, a transparent conductive layer, an electrode, and a passivation layer. Specifically, the high voltage LED chip is formed by dividing the epitaxial layer into multiple PN junctions through an isolation groove, such as Figure 1 As shown, the isolation groove is formed by combining positive photoresist and mask, and has a gentle angle, generally <50°, such as Figure 2 As shown, the purpose is to facilitate electrode bridging, so as to realize the series connection between multiple PNs. However, the isolation groove process in the existing high-voltage LED chip is to make the bridge at the same time through a photoresist and a photolithography. In order to facilitate metal bridging, the bridge must be inclined enough, otherwise the electrode will break, which also leads to the isolation groove position angle of other non-bridge areas being relatively inclined, that is, the upper width of the isolation groove is larger, sacrificing the epitaxial layer, resulting in a small light-emitting area, affecting the brightness of the chip. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a high-voltage LED chip and a preparation method thereof, which can reduce the etching area of ​​the epitaxial layer during the isolation groove etching process, so that the formed isolation groove can take into account both the electrode connection and the light-emitting area.

[0005] In order to solve the above technical problems, the first aspect of the present invention provides a method for preparing a high-voltage LED chip, comprising:

[0006] Arranging an epitaxial layer on a substrate, wherein the epitaxial layer at least comprises an N-type semiconductor, a quantum well and a P-type semiconductor;

[0007] Etching the epitaxial layer to expose the N-type semiconductor layer and form a cutting path;

[0008] Performing photolithography and etching at the cutting path position to form an isolation groove, wherein the isolation groove includes a non-bridging area and a bridging area;

[0009] The photolithography and etching process is performed at the cutting path position to form the isolation groove, including:

[0010] (1) coating a positive photoresist on the side of the epitaxial layer away from the substrate;

[0011] (2) providing a first mask, adjusting the position of the first mask so that the light-transmitting area of ​​the first mask corresponds to the preset position of the non-bridging area, and performing exposure processing so that the non-bridging area forms an inclined surface with a steep angle;

[0012] (3) providing a second mask, adjusting the position of the second mask so that the light-transmitting area of ​​the second mask corresponds to the preset position of the bridge area, the light-transmitting area of ​​the second mask having a plurality of sub-light-transmitting areas of different sizes, performing n times of photolithography using the plurality of sub-light-transmitting areas of different sizes of the second mask so that the bridge area forms an inclined surface with a gentle angle, wherein n ≥ 1 and is an integer;

[0013] (4) performing a development process to form a non-bridging structure with a steep angle and a bridging structure with a gentle angle;

[0014] (5) Etching is performed to form a non-bridging area with a steep angle and a bridging area with a gentle angle.

[0015] As an improvement of the above solution, the value of n is positively correlated with the inclination angle of the bridging area.

[0016] As an improvement of the above solution, the non-bridge area passes through the center of the bridge area, and the width of the light-transmitting area of ​​the second mask during the first photolithography is d1; when n>1, the width of the light-transmitting area of ​​the second mask during the nth photolithography is d n , d n =2bn+d1, where b=1~3.

[0017] As an improvement of the above solution, when performing n times of photolithography, the horizontal distance between the bridge area and the non-bridge area formed by the first photolithography is c1;

[0018] When n>1, the horizontal distance between the bridge area and the non-bridge area formed by the nth photolithography is c n ,

[0019] cn =an+c1, where a=3~15.

[0020] As an improvement of the above scheme, 3≤c≤25μm; 10≤d≤50μm;

[0021] The width of the light-transmitting area of ​​the first mask is 1 μm to 10 μm.

[0022] As an improvement of the above scheme, in step (3), the exposure amount of the exposure process when performing n times of photolithography is J, and the value of J decreases as the value of n increases;

[0023] In step (2), the exposure amount of the exposure treatment is K, K>J.

[0024] As an improvement of the above solution, the coating thickness of the positive photoresist is T;

[0025] In step (3), when n>1, the exposure amount of the first photolithography exposure process is J1, and the exposure amount of the nth photolithography exposure process is J n , J n =J1-m(n-1), where m=20-300;

[0026] In step (2), the exposure amount of the exposure process is K, K>J1.

[0027] As an improvement of the above solution, J1<T*50; J n ≤T*100 / 5; K≥T*80;

[0028] The thickness of the epitaxial layer is H, satisfying T≥H*2.

[0029] As an improvement of the above solution, the angle of the isolation groove in the non-bridging area is θ1, θ1>70°, and the angle of the isolation groove in the bridging area is θ2, θ2≤50°.

[0030] The second aspect of the present invention also provides a high-voltage LED chip prepared according to the method for preparing the high-voltage LED chip.

[0031] The implementation of the present invention has the following beneficial effects:

[0032] In the present application, the isolation groove is divided into a bridging area and a non-bridging area, and the bridging area and the non-bridging area are exposed through different photolithography processes. Specifically, the epitaxial layer of the LED chip is photolithographically processed using the first mask plate and the second mask plate, so that the inclination angles of the bridging area and the non-bridging area can be controlled, forming an isolation groove structure with a relatively steep angle in the non-bridging area and a relatively gentle angle in the bridging area. Compared with the isolation groove structure of the traditional high-voltage LED chip, the light-emitting area is effectively increased, and at the same time it is conducive to electrode bridging, so that the obtained high-voltage LED chip has good luminous efficiency and luminous brightness.

[0033] In addition, the present application adopts a photolithography process of one-time photoresist coating, multiple exposure treatments, and unified development treatment, combined with an etching process to prepare isolation grooves. The preparation process is simple and at the same time avoids damage to the N-type semiconductor layer due to long-term use of the mask to a certain extent, and has little impact on the reliability of the high-voltage LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 : A schematic diagram of the planar structure of a high-voltage LED chip isolation groove in the prior art;

[0035] Figure 2 : A cross-sectional schematic diagram of a high-voltage LED chip isolation groove in the prior art;

[0036] Figure 3 : A schematic diagram of the planar structure of the high-voltage LED chip isolation groove in this application;

[0037] Figure 4 : A cross-sectional schematic diagram of the isolation groove of the non-bridge area of ​​the high-voltage LED chip in the present application;

[0038] Figure 5 : A cross-sectional schematic diagram of the isolation groove of the high-voltage LED chip bridge region in the present application;

[0039] Figure 6 : A schematic diagram of the structure of the first mask in this application;

[0040] Figure 7 : Schematic diagram of forming isolation trenches in non-bridging areas by photolithography;

[0041] Figure 8 : A schematic diagram of the structure of the second mask in this application;

[0042] Fig. 9 : Figure 8 A schematic diagram of the structure of the photolithography plate in the middle light transmission area;

[0043] Fig.10 : Schematic diagram of the first photolithography process to form the bridge area isolation groove;

[0044] Fig.11: Schematic diagram of forming the bridge area isolation groove by the second photolithography;

[0045] Fig.12 : Schematic diagram of the bridge structure after development;

[0046] Fig.13 : Schematic diagram of the non-bridging structure after development;

[0047] Reference numerals:

[0048] 1-substrate; 2-epitaxial layer; 3-isolation groove; 31-bridging area; 32-non-bridging area; 4-positive photoresist; 5-first mask; 6-second mask; 61-light-transmitting area; A1-first sub-light-transmitting area; A2-second sub-light-transmitting area; A3-third sub-light-transmitting area. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail with specific embodiments below.

[0050] In order to solve the above problems, the first aspect of the present invention provides a method for preparing a high-voltage LED chip, comprising:

[0051] An epitaxial layer 2 is provided on a substrate 1, wherein the epitaxial layer 2 at least comprises an N-type semiconductor, a quantum well and a P-type semiconductor;

[0052] Etching the epitaxial layer 2 to expose the N-type semiconductor layer and form a cutting path;

[0053] Performing photolithography and etching at the cutting path position to form an isolation groove 3, wherein the isolation groove 3 includes a non-bridging area 32 and a bridging area 31;

[0054] The photolithography and etching process is performed at the cutting path position to form the isolation groove 3, including:

[0055] (1) coating a positive photoresist 4 on the side of the epitaxial layer 2 away from the substrate 1;

[0056] (2) providing a first mask 5, adjusting the position of the first mask 5 so that the light-transmitting area of ​​the first mask 5 corresponds to the preset position of the non-bridge area 32, performing exposure processing so that the non-bridge area 32 forms an inclined surface with a steep angle;

[0057] (3) providing a second mask 6, adjusting the position of the second mask 6 so that the light-transmitting area 61 of the second mask 6 corresponds to the preset position of the bridge area 31, the light-transmitting area 61 of the second mask 6 has a plurality of sub-light-transmitting areas of different sizes, performing n times of photolithography using the plurality of sub-light-transmitting areas of different sizes of the second mask 6, so that the bridge area 31 forms an inclined surface with a gentle angle, wherein n ≥ 1 and is an integer;

[0058] (4) performing a development process to form a non-bridging structure with a steep angle and a bridging structure with a gentle angle;

[0059] (5) Etching is performed to form a non-bridging area 32 with a steep angle and a bridging area 31 with a gentle angle.

[0060] In the present application, the isolation groove 3 is divided into a bridge area 31 and a non-bridge area 32, and the bridge area 31 and the non-bridge area 32 are exposed by different photolithography processes. Specifically, the first mask plate 5 and the second mask plate 6 are used to perform photolithography on the epitaxial layer 2 of the LED chip, so that the inclination angles of the bridge area 31 and the non-bridge area 32 can be controlled respectively, forming an isolation groove 3 structure with a relatively steep angle of the non-bridge area 32 and a relatively gentle angle of the bridge area 31. Compared with the isolation groove 3 structure of the traditional high-voltage LED chip, the light-emitting area is effectively increased, and it is also conducive to electrode bridging. In addition, the present application adopts a photolithography process of one-time photoresist coating, multiple exposure processes, and unified development processes, combined with an etching process to prepare the isolation groove 3, the preparation process is simple, and at the same time, the damage to the N-type semiconductor layer caused by the long-term use of the mask plate is avoided to a certain extent, and the impact on the reliability of the high-voltage LED chip is small.

[0061] Each step is described in detail below:

[0062] S1, providing an epitaxial layer 2 on a substrate 1, wherein the epitaxial layer 2 at least includes an N-type semiconductor, a quantum well and a P-type semiconductor;

[0063] Preferably, the substrate 1 may be one of a sapphire substrate, a SiO2 sapphire composite substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a zinc oxide substrate; more preferably, a sapphire substrate.

[0064] Preferably, the N-type semiconductor layer includes but is not limited to an N-type GaN layer, the P-type semiconductor layer includes but is not limited to a P-type GaN layer, and the quantum well includes but is not limited to an InGaN / AlGaN superlattice structure, which can be reasonably adjusted according to actual needs.

[0065] Further, the thickness of the epitaxial layer 2 is H, 4≤H≤7μm, and the thickness of the epitaxial layer 2 is exemplarily 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm but not limited thereto.

[0066] S2, etching the epitaxial layer 2 to expose the N-type semiconductor layer and form a cutting path;

[0067] In this step, the epitaxial layer 2 can be etched by combining photolithography and dry etching. The etching depth is to expose the N-type semiconductor layer, which is convenient for preparing cutting paths and forming a negative electrode connection position. More preferably, the etching depth is 0.8 to 2 μm.

[0068] S3, performing photolithography and etching processing at the cutting path position to form an isolation groove 3, wherein the isolation groove 3 includes a non-bridging area 32 and a bridging area 31;

[0069] See also Figure 3-Figure 5 The isolation groove 3 can be set to divide the epitaxial layer 2 of the LED chip into multiple PN junctions, and use electrodes to realize the series connection between different PN junctions to form a high-voltage LED chip. The depth of the isolation groove 3 is equal to the depth of the epitaxial layer 2, so when performing photolithography and etching processing on the cutting path position, it is necessary to etch until the substrate 1 is exposed to ensure electrical isolation between each light-emitting unit, thereby improving the electrical performance and reliability of the LED chip.

[0070] Specifically, the photolithography and etching process is performed at the cutting path position to form the isolation groove 3, including:

[0071] (1) coating a positive photoresist 4 on the side of the epitaxial layer 2 away from the substrate 1;

[0072] In this step, the coating thickness of the positive photoresist 4 is related to the thickness of the epitaxial layer 2. In the photolithography process, the positive photoresist 4 of appropriate thickness is sufficient to provide good corrosion resistance and sufficient contrast during the development process, ensuring that the pattern can be accurately defined during the etching process and will not damage the underlying epitaxial layer 2. Preferably, the coating thickness of the positive photoresist 4 is T, satisfying T≥H*2. If the T value is too high, it will affect the penetration of light and the resolution of the pattern, and the accurate transfer of the pattern cannot be ensured. In some specific and preferred embodiments, 8≤T≤20μm, and the T value is exemplarily 8μm, 10μm, 12μm, 14μm, 16μm, 18μm, 20μm, but is not limited thereto.

[0073] (2) providing a first mask 5, adjusting the position of the first mask 5 so that the light-transmitting area of ​​the first mask 5 corresponds to the preset position of the non-bridge area 32, performing exposure processing so that the non-bridge area 32 forms an inclined surface with a steep angle;

[0074] In this step, use Figure 6 The first mask 5 shown in FIG. 1 (the shaded part is the light-shielding area, and the other part is the light-transmitting area) is subjected to exposure processing, such as Figure 7 As shown, the pattern on the first mask 5 can be transferred to the positive photoresist 4 layer.

[0075] Preferably, the width of the light-transmitting area of ​​the first mask 5 is 1 μm to 10 μm, that is, the upper width of the non-bridge area 32 in the isolation groove 3 is 1 μm to 10 μm. It should be noted that the steep angle of the non-bridge area 32 in the present application refers to the angle between the inclined surface and the horizontal line being greater than 60°. Preferably, the isolation groove angle of the non-bridge area 32 is θ1, θ1>70°, and the etching area of ​​the epitaxial layer 2 is relatively small, so that the light-emitting area of ​​the high-voltage LED chip is increased, and the light-emitting efficiency is improved.

[0076] Furthermore, when the exposure process is performed at the position of the isolation groove 3 in the non-bridging area 32, the purpose is to divide the epitaxial layer 2 into several PN junctions, thereby exposing the substrate 1. Therefore, the exposure amount during photolithography needs to be large enough to develop the positive photoresist 4. The exposure amount of the exposure process is K, and the value of K is related to the coating thickness T of the positive photoresist 4. In some specific and preferred embodiments, K≥T*80, and the unit of the exposure amount K value during the exposure process is millijoule (mJ).

[0077] (3) providing a second mask 6, adjusting the position of the second mask 6 so that the light-transmitting area 61 of the second mask 6 corresponds to the preset position of the bridge area 31, the light-transmitting area 61 of the second mask 6 has a plurality of sub-light-transmitting areas of different sizes, performing n times of photolithography using the plurality of sub-light-transmitting areas of different sizes of the second mask 6, so that the bridge area 31 forms an inclined surface with a gentle angle, wherein n ≥ 1 and is an integer;

[0078] In this step, the design of the second mask 6 is as follows: Figure 8 As shown (the shaded part is the shading area, and the other part is the light-transmitting area 61), the light-transmitting area 61 corresponds to the preset position of the bridge area 31, and the non-bridge area 32 passes through the center of the bridge area 31. Specifically, please refer to 9, each light-transmitting area 61 in the second mask 6 has a plurality of sub-light-transmitting areas of different sizes (each box is a complete light-transmitting area 61), such as the first sub-light-transmitting area A1, the second sub-light-transmitting area A2, and the third sub-light-transmitting area A3, and the size increases with equal gradients. By adjusting the size of the sub-light-transmitting areas 61 at the preset position of the bridge area 31 and performing exposure processing respectively, the bridge area 31 can be formed to form an inclined surface with a gentle angle. In the specific implementation process, as the n value increases, the size of the light-transmitting area 61 gradually increases, which is conducive to the formation of the inclined surface of the bridge area 31.

[0079] Further, when n=1, the wafer is subjected to one photolithography and etching with the second mask plate 6 as a shield to obtain the bridge area 31 of the isolation groove 3. At this time, the size of the light-transmitting area 61 of the second mask plate 6 can be selected according to actual needs. When n>1, it is necessary to perform multiple photolithography on the wafer with the second mask plate 6 as a shield, and finally perform etching to form the bridge area 31 of the isolation groove 3. The value of n is positively correlated with the inclination angle of the bridge area 31. The larger the n value, the larger the inclination angle of the bridge area 31, and the more inclined the inclined surface formed by the bridge area 31. It should be noted that the gentle angle of the bridge area 31 in the present application refers to the angle between the inclined surface and the horizontal line being less than 60°. Preferably, the angle of the isolation groove 3 of the bridge area 31 is θ2, and θ2≤50°. It can be understood that the inclination angle and the angle θ2 of the isolation groove 3 of the bridge area 31 are complementary angles.

[0080] Optionally, see Fig. 9 , the width of the first sub-light-transmitting area A1 of the second mask 6 is adjusted to d1 during the first photolithography, and when n>1, during the nth photolithography, the width of the light-transmitting area of ​​the second mask 6 during the nth photolithography is d n , d n =2bn+d1, wherein b=1-3, and b is exemplarily 1μm, 1.5μm, 2μm, 2.5μm, 3μm, etc. In some specific and preferred embodiments, 10≤d1≤50μm, and d1 can be exemplarily 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, etc.; the horizontal distance between the bridge area and the non-bridge area formed by the first photolithography is c1; when n>1, the horizontal distance between the bridge area and the non-bridge area formed by the nth photolithography is c n , c n =an+c1, wherein a=3-15, a is exemplarily 3μm, 5μm, 10μm, 15μm, etc. In some specific and preferred embodiments, 3≤c1≤25μm, c1 is exemplarily 3μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, etc. It should be noted that the length refers to the distance along the electrode bridging direction, and the width refers to the distance perpendicular to the electrode bridging direction.

[0081] Furthermore, in step (3), the isolation groove 3 of the bridge area 31 is subjected to multiple photolithography. During the exposure process, it is ensured that the positive photoresist 4 cannot be fully exposed, so that the remaining part of the positive photoresist 4 can protect the epitaxial layer 2. This is different from the purpose of the exposure process in step (2). Therefore, in step (3), the exposure amount of the exposure process when performing n times of photolithography is J, which satisfies K>J.

[0082] Furthermore, when n>1, the J value decreases as the n value increases, which may be a linear decrease, a gradient decrease, or an irregular decrease according to the thickness of the positive photoresist 4. More preferably, the exposure amount of the first photolithography exposure process is J1, K>J1, and the exposure amount of the nth photolithography exposure process is J n , J n =J1-m(n-1), where m=20~300(n-1), the exposure at the last photolithography is J n The value cannot be too large, to ensure that the thickness of the positive photoresist 4 is thick enough to protect the epitaxial layer 2 from being etched. For example, m can be 20, 50, 70, 100, 120, 150, 170, 200, 220, 250, 270, 300, etc. At the same time, the value of J is also related to the coating thickness T of the positive photoresist 4. In some specific and preferred embodiments, J1<T*50; J n ≤T*100 / 5. It should be noted that the unit of the exposure value J during the exposure process is millijoule (mJ).

[0083] See also Figure 10-11 , taking n=2 as an example for explanation.

[0084] In step (3), provide Figure 8 and Fig. 9 The second mask 6 shown in FIG. 1 determines the position of the isolation groove 3 in the bridge area 31 with the position of the isolation groove 3 in the non-bridge area 32 as the center, and then adjusts the position of the second mask 6 so that the smallest light-transmitting area A1 corresponds to the preset position of the bridge area 31, as shown in FIG. Fig.10 Then, the position of the second mask 6 is adjusted so that the second light-transmitting area A2 with a larger size corresponds to the preset position of the bridge area 31, as shown in FIG. Fig.11 As shown, a second exposure process is performed to complete the second photolithography, that is, the final photolithography.

[0085] (4) performing a development process to form a non-bridging structure with a steep angle and a bridging structure with a gentle angle;

[0086] In this step, the positive photoresist 4 layer that has been subjected to multiple exposure treatments in steps (2) and (3) is developed, so that the positive photoresist 4 in the light-transmitting portion of the first mask 5 and the second mask 6 generates a product that is soluble in a developer, and then is dissolved and removed after the development treatment, thereby forming a pattern on the epitaxial layer 2 with the first mask 5 and the second mask 6 as shielding, that is, a non-bridging structure with a steep angle and a bridging structure with a gentle angle. The bridging structure with a gentle angle after development is as shown in FIG. Fig.12 As shown, the non-bridging structure with a steep angle after development is as follows Fig.13 shown.

[0087] (5) Etching is performed to form a non-bridging area 32 with a steep angle and a bridging area 31 with a gentle angle.

[0088] In this step, the developed positive photoresist 4 is used as a mask for etching to expose the substrate 1, and the pattern on the positive photoresist 4 is transferred to the epitaxial layer 2 to form a non-bridge area 32 with a steep angle and a bridge area 31 with a gentle angle. The structure of the isolation groove 3 in the non-bridge area 32 with a steep angle is as shown in FIG. Figure 4 As shown, the structure of the isolation groove 3 of the bridge area 31 with a gentle angle is as follows Figure 5 As shown by Figure 4 and Figure 5 By comparison, it can be seen that the angle of the bridged isolation groove 3 is more inclined, which is convenient for the bridge area 31 to bridge the electrode. At the same time, the small inclination of the non-bridge area 32 is conducive to increasing the light-emitting area of ​​the high-voltage LED chip, thereby improving the light-emitting efficiency of the high-voltage LED chip. Optionally, dry etching can be selected for etching, and exemplary methods include reactive ion etching, high-density plasma etching, etc.

[0089] Optionally, the method for preparing the high-voltage LED chip further comprises: preparing a current blocking layer on the obtained high-voltage LED chip;

[0090] In this step, the method for preparing the current blocking layer includes: depositing a current blocking layer material on the obtained high-voltage LED chip, and then performing photolithography and etching to obtain the current blocking layer.

[0091] Preferably, the material of the current blocking layer includes but is not limited to SiO2, the thickness of the current blocking layer is 350-450 nm, the deposition method is preferably plasma enhanced chemical vapor deposition (PECVD), and the etching method is preferably wet etching.

[0092] Optionally, the method for preparing the high-voltage LED chip further comprises: preparing a transparent conductive layer on the obtained high-voltage LED chip;

[0093] In this step, the method for preparing the transparent conductive layer includes: depositing a transparent conductive material on the obtained high-voltage LED chip, and then performing photolithography and etching to obtain the transparent conductive layer.

[0094] Preferably, the material of the transparent conductive layer includes but is not limited to ITO, the thickness of the transparent conductive layer is 40-80 nm, the deposition method is preferably plasma enhanced chemical vapor deposition (PECVD), and the etching method is preferably wet etching.

[0095] Optionally, the method for preparing the high-voltage LED chip further comprises: preparing an electrode on the obtained high-voltage LED chip;

[0096] In this step, the preparation method of the electrode includes: performing coating on the high-voltage LED chip to obtain a metal electrode layer, and then performing photolithography to obtain the electrode.

[0097] Preferably, metal coating equipment may be used for coating.

[0098] Optionally, the method for preparing the high-voltage LED chip further comprises: preparing a passivation layer on the obtained high-voltage LED chip;

[0099] In this step, the method for preparing the passivation layer includes: depositing a passivation layer material on the high-voltage LED chip, and then performing photolithography and etching to obtain the passivation layer.

[0100] Preferably, the material of the passivation layer includes but is not limited to SiO2, the thickness of the passivation layer is 200-300 nm, the deposition method is preferably plasma enhanced chemical vapor deposition (PECVD), and the etching method is preferably wet etching.

[0101] Correspondingly, the present invention also provides a high-voltage LED chip prepared by the above preparation method.

[0102] The present invention will be further described below with specific embodiments:

[0103] Example 1

[0104] This embodiment provides a high-voltage LED chip, and the preparation method thereof is as follows:

[0105] S1. Depositing an epitaxial layer on a sapphire substrate, wherein the epitaxial layer includes an N-type semiconductor, a quantum well, and a P-type semiconductor; the thickness of the epitaxial layer is H=5.5 μm;

[0106] S2. Etching the epitaxial layer by photolithography and dry etching to a depth of 1 μm to expose the N-type semiconductor layer, forming a cutting path and a location for connecting the cathode electrode;

[0107] S3, performing photolithography and etching processing at the cutting path position to form an isolation groove, wherein the isolation groove includes a non-bridging area and a bridging area; the specific steps are as follows:

[0108] (1) coating a positive photoresist on the side of the epitaxial layer away from the substrate;

[0109] In this step, the coating thickness of the positive photoresist is T=11 μm;

[0110] (2) Figure 6 The first mask shown is shielded, so that the light-transmitting area of ​​the first mask corresponds to the preset position of the non-bridging area, and the exposure process is performed, such as Figure 7 As shown, the isolation groove in the non-bridging area is formed into an inclined surface with a steep angle;

[0111] In this step, the width of the light-transmitting area in the first mask is 3 μm, and the exposure amount K is 1100 mJ.

[0112] (3) Figure 8 and Fig. 9 The second mask shown is shielded so that the first sub-light-transmitting area A1 with the smallest size corresponds to the preset position of the bridge area, such as Fig.10 As shown, a first exposure process is performed to complete a first photolithography to form a first slope structure of the isolation groove in the bridge area;

[0113] In this step, the exposure amount of the first exposure treatment is J1=400mJ, c=6μm; d=25μm, the positive photoresist in this area is not fully photolithographic, and after development, there is still positive photoresist here to protect the epitaxial layer, but it is not enough to completely protect the epitaxial layer, and part of the epitaxial layer is etched during dry etching;

[0114] Then, the position of the second mask is adjusted so that the first light-transmitting sub-area A2 with a larger size corresponds to the preset position of the bridge area. Fig.11 As shown, a second exposure process is performed to complete the second photolithography, that is, the last photolithography, so that the isolation groove in the bridge area forms an inclined surface with a gentle angle;

[0115] In this step, the exposure amount of the second exposure treatment is J2=100mJ, where a=5μm and b=1μm. The photoresist in this area is not fully photolithographed, and there is still photoresist here after development. The photoresist is thick enough to completely protect the epitaxial layer from dry etching.

[0116] (4) The wafer after photolithography is developed. The structure of the non-bridging area with a steep angle after development is as follows: Fig.12 As shown, the structure of the non-bridging area with a steep angle after development is as follows Fig.13 As shown;

[0117] (5) The developed wafer is dry-etched to form a structure of an isolation groove in a non-bridging area with a steep angle as shown in FIG. Figure 4 As shown in FIG. 1 , the structure of the isolation groove in the bridge region with a gentle angle is as follows: Figure 5 shown.

[0118] S4, removing the positive photoresist, depositing SiO2 material on the above structure by PECVD to a thickness of 400nm, and then performing photolithography and wet etching to prepare a current blocking layer;

[0119] S5, depositing an ITO transparent conductive layer material on the above structure with a thickness of 60 nm, and preparing a transparent conductive layer by photolithography and wet etching;

[0120] S6. On the above structure, electrodes are prepared by photolithography and metal coating equipment;

[0121] S7. Deposit SiO2 material on the above structure by PECVD with a thickness of 230 nm, and then perform photolithography and wet etching to prepare a passivation layer.

[0122] Example 2

[0123] This embodiment provides a high-voltage LED chip, and its preparation method is basically the same as that of embodiment 1, except that:

[0124] by Figure 8 and Fig. 9 The second mask shown is shielded so that the first light-transmitting sub-area A1 with the smallest size corresponds to the preset position of the bridge area, and the first exposure process is performed to complete the first photolithography to form the first inclined surface structure of the isolation groove of the bridge area;

[0125] In this step, the exposure amount of the first exposure treatment is J1=400mJ, c=6μm; d=25μm, the positive photoresist in this area is not fully photolithographic, and after development, there is still positive photoresist here to protect the epitaxial layer, but it is not enough to completely protect the epitaxial layer, and part of the epitaxial layer is etched during dry etching;

[0126] Subsequently, the position of the second mask is adjusted so that the first light-transmitting sub-area A2 with a larger size corresponds to the preset position of the bridge area, and a second exposure process is performed to form a second inclined surface structure of the isolation groove in the bridge area;

[0127] In this step, the exposure amount of the second exposure treatment is J2=250mJ, a=5μm; b=1μm, the positive photoresist in this area is not fully photolithographic, and after development, there is still positive photoresist here to protect the epitaxial layer, but it is not enough to completely protect the epitaxial layer, and part of the epitaxial layer is etched during dry etching;

[0128] Finally, the position of the second mask is adjusted so that the first light-transmitting sub-area A3 with a larger size corresponds to the preset position of the bridge area, and a third exposure process is performed to complete the third photolithography, i.e., the last photolithography, so that the isolation groove of the bridge area forms an inclined surface with a gentle angle;

[0129] In this step, the exposure amount of the third exposure treatment is J3=100mJ, where a=5μm and b=1μm. The photoresist in this area is not fully photolithographic, and there is still photoresist here after development. The photoresist is thick enough to completely protect the epitaxial layer from dry etching.

[0130] Example 3

[0131] This embodiment provides a high-voltage LED chip, and its preparation method is basically the same as that of embodiment 1, except that:

[0132] The exposure amount of the first exposure process is J1=400mJ, c=6μm; d=25μm;

[0133] The exposure amount of the second exposure process is J2=200mJ, a=5μm; b=1μm.

[0134] Example 4

[0135] This embodiment provides a high-voltage LED chip, and its preparation method is basically the same as that of embodiment 1, except that:

[0136] In step (1), the coating thickness of the positive photoresist is T=13 μm.

[0137] Control group

[0138] by Figure 1 The high-voltage LED chip shown is a control group, that is, in this comparative example, the isolation grooves in the bridge area and the isolation grooves in the non-bridge area are completed by a photoresist and a photolithography process.

[0139] Performance Testing

[0140] The high-voltage LED chip obtained in the embodiment was tested for its luminous brightness, non-bridging area angle and bridging area angle under 30 mA. The test results are shown in Table 1 below.

[0141] Table 1 Performance test results of the embodiment and the control group

[0142]

[0143] It can be seen from the above results that compared with the control group, in Example 1, the angle of the flying bridge area is increased, and the luminous area is increased, so the luminous brightness is brighter than the control group; compared with Example 1, Example 2 adds a photolithography process, which can make the angle of the bridge area more oblique, so the luminous area in the bridge area is slightly reduced, and the brightness is slightly reduced; in Example 3, the exposure amount of J2 is increased, and it is easier to obtain a bridge area with a large inclination angle, thereby reducing the luminous area and reducing the brightness; in Example 4, the photoresist layer becomes thicker, but the exposure energy remains unchanged, which will make the photoresist angle more difficult to be oblique, so the angle of the bridge area is slightly increased, which prompts a slight increase in the luminous area, and then the luminous brightness is also slightly brighter.

[0144] It can be seen that in the present application, the isolation groove is divided into a bridging area and a non-bridging area, and the epitaxial layer of the LED chip is photolithographically processed using the first mask and the second mask. Combined with the design of the light-transmitting area of ​​the second mask, the thickness of the positive photoresist, the thickness of the epitaxial layer, and the exposure amount of the exposure treatment, an isolation groove structure with a relatively steep angle in the non-bridging area and a relatively gentle angle in the bridging area is formed, which effectively increases the light-emitting area and greatly improves the light-emitting efficiency. Moreover, the formed isolation groove structure is conducive to electrode bridging, so that the obtained high-voltage LED chip has a stable light-emitting brightness under the same current conditions.

[0145] The above disclosure is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for preparing a high-voltage LED chip, characterized in that: include: Arranging an epitaxial layer on a substrate, wherein the epitaxial layer at least comprises an N-type semiconductor, a quantum well and a P-type semiconductor; Etching the epitaxial layer to expose the N-type semiconductor layer and form a cutting path; Performing photolithography and etching at the cutting path position to form an isolation groove, wherein the isolation groove includes a non-bridging area and a bridging area; The photolithography and etching process is performed at the cutting path position to form the isolation groove, including: (1) coating a positive photoresist on the side of the epitaxial layer away from the substrate; (2) providing a first mask, adjusting the position of the first mask so that the light-transmitting area of ​​the first mask corresponds to the preset position of the non-bridging area, and performing exposure processing so that the non-bridging area forms an inclined surface with a steep angle; (3) providing a second mask, adjusting the position of the second mask so that the light-transmitting area of ​​the second mask corresponds to the preset position of the bridge area, the light-transmitting area of ​​the second mask having a plurality of sub-light-transmitting areas of different sizes, performing n times of photolithography using the plurality of sub-light-transmitting areas of different sizes of the second mask so that the bridge area forms an inclined surface with a gentle angle, wherein n ≥ 1 and is an integer; (4) performing a development process to form a non-bridging structure with a steep angle and a bridging structure with a gentle angle; (5) Etching is performed to form a non-bridging area with a steep angle and a bridging area with a gentle angle.

2. The method for preparing a high voltage LED chip according to claim 1, characterized in that: The value of n is positively correlated with the inclination angle of the bridge region.

3. The method for preparing a high voltage LED chip according to claim 1, characterized in that: The non-bridging area passes through the center of the bridging area, and the width of the light-transmitting area of ​​the second mask during the first photolithography is d1; When n>1, the width of the light-transmitting area of ​​the second mask during the nth photolithography is d n , d n =2bn+d1, where b=1~3.

4. The method for preparing a high voltage LED chip according to claim 3, characterized in that: The horizontal distance between the bridge area and the non-bridge area formed by the first photolithography is c1; When n>1, the horizontal distance between the bridge area and the non-bridge area formed by the nth photolithography is c n , c n =an+c1, where a=3~15.

5. The method for preparing a high-voltage LED chip according to claim 3 or 4, characterized in that: 3≤c≤25μm;10≤d≤50μm; The width of the light-transmitting area of ​​the first mask is 1 μm to 10 μm.

6. The method for preparing a high voltage LED chip according to claim 1, characterized in that: In step (3), the exposure amount of the exposure process when performing n times of photolithography is J, and the value of J decreases as the value of n increases; In step (2), the exposure amount of the exposure treatment is K, K>J.

7. The method for preparing a high voltage LED chip according to claim 6, characterized in that: The coating thickness of the positive photoresist is T; In step (3), when n>1, the exposure amount of the first photolithography exposure process is J1, and the exposure amount of the nth photolithography exposure process is J n , J n =J1-m(n-1), where m=20-300; In step (2), the exposure amount of the exposure process is K, K>J1.

8. The method for preparing a high voltage LED chip according to claim 7, characterized in that: J1<T*50;J n ≤T*100 / 5;K≥T*80; The thickness of the epitaxial layer is H, satisfying T≥H*2.

9. The method for preparing a high-voltage LED chip according to any one of claims 1 to 4, characterized in that: The angle of the isolation groove in the non-bridging area is θ1, θ1>70°, and the angle of the isolation groove in the bridging area is θ2, θ2≤50°.

10. A high-voltage LED chip prepared according to the method for preparing a high-voltage LED chip according to any one of claims 1 to 9.

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