Data processing method, storage medium and electronic equipment

Abstract

The invention discloses a data processing method, a storage medium and electronic equipment, and relates to the technical field of embedded systems.The data processing method comprises the steps that first to-be-processed data to be written into a simulated EEPROM storage space is determined; wherein the simulated EEPROM storage space is generated on the basis of a FLASH storage space; writing the first to-be-processed data into a buffer queue; wherein the buffer queue is preset in a storage space other than the FLASH storage space; and writing each data in the buffer queue into the simulated EEPROM storage space according to the queue sequence by periodically executing a writing command aiming at the buffer queue so as to improve the convenience of writing the data.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded systems, and in particular to a data processing method, a storage medium and an electronic device. Background Art

[0002] In embedded security applications, usually single-chip systems are used, which require EEPROM storage media that can be read and written by byte. However, EEPROM is expensive, and the internal storage medium of the chip is usually FLASH. The characteristics of FLASH are: it can only be erased by page and written by the smallest byte; when data needs to be modified, the entire page must be erased first, and then the data is written.

[0003] In this case, FLASH can be used to simulate EEPROM and frequently modified business data can be stored in the simulated EEPROM. However, there are problems with the writing of large amounts of data or multiple different data. FLASH can only wait until one is written before writing the next data, and it will continuously erase and write data page by page, which greatly causes inconvenience in writing data. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, one object of the present invention is to provide a data processing method, a storage medium and an electronic device to improve the convenience of writing data.

[0005] According to a first aspect of an embodiment of the present invention, a data processing method is provided, the method comprising: Determine first data to be processed to be written into the simulated EEPROM storage space; wherein the simulated EEPROM storage space is generated based on the FLASH storage space; Writing the first to-be-processed data into a buffer queue; wherein the buffer queue is preset in a storage space other than the FLASH storage space; By periodically executing a write command for the buffer queue, each data in the buffer queue is written into the simulated EEPROM storage space according to the queue order.

[0006] According to a second aspect of an embodiment of the present invention, there is provided a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned data processing method is implemented.

[0007] According to a third aspect of an embodiment of the present invention, there is provided an electronic device, comprising: a memory and a processor; a computer program is stored in the memory, and when the computer program is executed by the processor, the above-mentioned data processing method is implemented.

[0008] In the solution provided by the embodiment of the present invention, all the first data to be processed that need to be written into the simulated EEPROM are directly written into a buffer queue, so that after each data is written, there is no need to wait for a new write command, and the same write command can be directly and periodically executed to continuously complete the writing of data into the simulated EEPROM storage space. The buffer queue simplifies the execution of the write command, so that multiple data can be written in one execution of the write command, thereby improving the convenience of writing data.

[0009] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a flowchart of a first data processing method provided by an embodiment of the present invention; Figure 2 is a flow chart of a second data processing method provided by an embodiment of the present invention; Figure 3 is a flowchart of a third data processing method provided by an embodiment of the present invention; Figure 4 is a flowchart of a fourth data processing method provided by an embodiment of the present invention; Figure 5 is a flowchart of a fifth data processing method provided by an embodiment of the present invention; Figure 6 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0011] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0012] The data processing method, storage medium and electronic device according to the embodiments of the present invention are described below with reference to the accompanying drawings.

[0013] In one embodiment of the present invention, see Figure 1 , provides a data processing method, the method comprising: S101: Determine first data to be processed to be written into the simulated EEPROM storage space; wherein the simulated EEPROM storage space is generated based on the FLASH storage space; S102: writing the first to-be-processed data into a buffer queue; wherein the buffer queue is preset in a storage space other than the FLASH storage space; S103: By periodically executing the write command for the buffer queue, each data in the buffer queue is written into the simulated EEPROM storage space according to the queue order.

[0014] FLASH (flash memory) generally refers to flash memory, which has the following characteristics: it can only be erased by page and written by the minimum byte; when data needs to be modified, the entire page must be erased first, and then the data must be written. Each data written to FLASH must wait for the write operation to be completed before the next data can be written to the command. In the solution provided by the embodiment of the present invention, all the first data to be processed that needs to be written to the simulated EEPROM are directly written into a buffer queue. In this way, after each data is written, there is no need to wait for a new write command, and the same write command can be directly executed periodically to continuously complete the writing of data to the simulated EEPROM (Electrically Erasable Programmable read only memory) storage space. The buffer queue simplifies the execution of the write command, so that multiple data can be written in one execution of the write command, which improves the convenience of writing data.

[0015] The simulated EEPROM storage space is generated based on the FLASH storage space. When generating, the EEPROM starting address and size are configured for the FLASH storage space, so that the EEPROM starting address points to a certain address within the FLASH storage space. The FLASH storage space within the range specified by the configured starting address and size is set as the simulated EEPROM storage space.

[0016] Furthermore, the FLASH storage space may be integrated into the simulated EEPROM storage space in the following manner: the simulated EEPROM storage space is divided into at least two simulated EEPROM sectors, wherein each simulated EEPROM sector is generated based on a FLASH sector of at least one FLASH storage space.

[0017] The buffer queue is preset in a storage space other than the FLASH storage space so that the data processing process of the buffer queue does not directly affect the access process in the FLASH storage space. Specifically, a portion of the SRAM (Static Random-Access Memory) can be divided into a portion for the buffer queue of data that needs to be stored in the EEPROM.

[0018] When storing data in the simulated EEPROM storage space, the data is stored according to the regional storage sequence number.

[0019] A block is a unit for writing data. Each simulated EEPROM sector consists of multiple blocks. Each data item is written into at least one block, and each block has a storage area serial number. A block can be a storage area of ​​fixed size. Different blocks have different starting addresses. According to the size of the starting address, different storage area serial numbers of different sizes can be assigned to different blocks. For example, the larger the starting address, the larger the storage area serial number.

[0020] In addition to the data that needs to be stored, the content stored in FLASH also includes the block number, block data size, block check code and invalid flag, which are used to mark the validity of user data and verify the authenticity of data. A special storage space will be set in each block, for example, by setting a special starting address and size to specify such storage space to store the above information.

[0021] In one embodiment, when the first data to be processed is too large, for example, larger than a preset byte count threshold, a write command can be issued to package the block number of the first data to be processed and the check code and data calculated based on the first data to be processed together and write them into the SRAM buffer queue. At the same time, a periodic comparison operation is used to compare the data content of the SRAM buffer queue with the check data of the stored data in the FLASH storage space. The decision to write is made only when the check data is inconsistent. This can reduce the situation of writing duplicate data.

[0022] The verification data can be calculated using verification algorithms such as SUM, CRC, AES128, and SHA256.

[0023] Whenever a new block is written, it can be confirmed whether there is a block with the same storage area number in the current simulated EEPROM sector. If not, the writing is performed through the buffer queue in the above manner.

[0024] In one embodiment, the first data to be processed to be written into the simulated EEPROM storage space may be determined in the following manner, including: Obtain target data; compare the storage area serial number and verification data of the target data with the storage area serial number and verification code of the second data to be processed in the buffer queue respectively; if they are different, compare the storage area serial number and verification code of the target data with the storage area serial number and verification code of the stored data in the simulated EEPROM storage space respectively; if they are different, determine that the target data is the first data to be processed.

[0025] The target data may be user input on a user interface, or data generated by a system, which is not limited in the embodiment of the present invention.

[0026] When comparing with the second data to be processed in the buffer queue, if there is data to be processed with the same storage area serial number and the same verification data, the data in the SRAM buffer queue will not be updated. If they are different, the content of the target data will be updated to the SRAM buffer queue.

[0027] The specific comparison process can refer to the data writing steps A1-A10 shown below.

[0028] A1: After obtaining the target data, if it is determined that the buffer queue of the SRAM is full, then execute step A7. If the serial number of the storage area to be written exceeds the maximum serial number defined by the user, then execute step A8; otherwise, execute step A2.

[0029] A2: The storage area number to be written is searched in the buffer queue of the SRAM to see whether there is block data with the same storage area number. If so, execute step A3; if not, execute step A4.

[0030] A3: Compare the verification data of the target data with the verification data of the block data of the same storage area serial number in the SRAM. If they are the same, execute step A9; if they are different, execute step A4.

[0031] A4: For the storage area serial number of the block area to be written, check whether there is stored data with the same storage serial number in the FLASH serving as the simulated EEPROM. If so, execute step A5; if not, execute step A6.

[0032] A5: Compare the verification data with the verification data of the stored data with the same storage sequence number in the FLASH. If they are the same, execute step A9; if they are different, execute step A6.

[0033] A6: Write the target data as the first data to be processed into the buffer queue of the SRAM, increase the number of buffer queues by one, and increase the write buffer queue label by one. The current data already exists in the buffer queue of the SRAM, waiting for the execution of the write FLASH command, and execute step A10.

[0034] A7: The function ends and returns to the SRAM_FIFO_FULL state.

[0035] A8: The function ends and returns to ID_OUT_RANGE status.

[0036] A9: The function ends and returns to the DATA_SAME state.

[0037] A10: The function ends and returns the SUCC status.

[0038] In step A6, after obtaining the write FLASH command, the process of writing the FLASH command can be executed according to the following steps B1-B5.

[0039] B1: When executing the write command periodically, it is necessary to determine whether the buffer queue in the SRAM is empty. If it is empty, execute step B5, otherwise execute step B2.

[0040] B2: Obtain the second data to be processed that needs to be written from the SRAM, and perform a secondary judgment on the second data to be processed. If the storage area serial number exceeds the maximum serial number defined by the user, execute step B5, otherwise execute step B3.

[0041] B3: Write the second data to be processed pointed to by the current write pointer of the buffer queue in the SRAM into the FLASH, and determine whether the writing is completed. If it is completed, execute step B4; otherwise, execute step B6.

[0042] B4: If the writing is successful, the SRAM buffer queue is written to the FLASH sequence number plus one, and the number of the second data to be processed in the SRAM is reduced by one.

[0043] B5: Set the SRAM buffer queue to zero by writing the FLASH sequence number and the buffer queue number to zero, indicating resetting the buffer queue, which is equivalent to obtaining an empty buffer queue after resetting.

[0044] B6: Program execution ends and returns to ERR status.

[0045] Wherein, when executing the write command in step B1, if there is a simulated EEPROM sector that is full of data, the valid data in the simulated EEPROM sector is copied to the next simulated EEPROM sector; The simulated EEPROM sector is set to an invalid state, and the next simulated EEPROM sector is set to a valid state; and the storage space of the invalid data in the simulated EEPROM sector is set as the remaining storage space of the next simulated EEPROM sector.

[0046] The next simulated EEPROM sector is a sector that has not yet been used for data storage, and the starting address is one digit after the ending address of the previous sector.

[0047] In this way, the invalid data of the current simulated EEPROM sector will not be copied to the next simulated EEPROM sector, and the storage space occupied by the invalid data will be used as the remaining space of the next sector, which is equivalent to expanding the storage capacity of a single sector.

[0048] Invalid data is relative to valid data. If the data in the sector cannot correctly reflect the actual stored information, the data is considered invalid data, such as data with data entry errors or data conversion errors.

[0049] These invalid data can be deleted and their storage space can be reused as the remaining storage space of the next simulated EEPROM sector.

[0050] Specifically, in step B1, the implementation method of executing the write command refers to the following process C1-C13.

[0051] C1: Determine the size of the data to be written. If it is zero, execute step C13; otherwise, execute step C2.

[0052] C2: Determine the remaining space of the current simulated EEPROM sector. If the remaining space is sufficient to write new block data, execute step C3; otherwise, execute step C6.

[0053] C3: Find the end address of the block where the previous data is located, and start from the found end address, write the data to be written, the corresponding storage area serial number, the data size, the verification data in sequence, and determine whether the writing is successful. If the writing is successful, execute step C4, otherwise execute step C12.

[0054] C4: Search the directory in SRAM to see if there is a block with the same storage area number. If so, execute step C5; if not, execute step C10.

[0055] C5: Set the invalid flag of the previous block, update the directory in SRAM, and execute step 11.

[0056] C6: Determine whether the next sector is in a state after being completely erased. If it is in a state after being completely erased, execute step C8; otherwise, execute step C7.

[0057] C7: Erase the next simulated EEPROM sector, the address is the current sector start address plus a simulated EEPROM sector size, if all erased successfully, execute step C8, otherwise repeat the sector erase.

[0058] C8: Write the serial number and size of the next sector, and copy the valid block data of the simulated EEPROM recorded in the directory in the SRAM to the new simulated EEPROM sector. If the block data is copied successfully, execute step C9, otherwise execute step C12.

[0059] C9: Write the valid flag of the new simulated EEPROM sector to the valid flag area of ​​the starting address of the new simulated EEPROM sector, that is, set the next simulated EEPROM sector to a valid state, the current simulated EEPROM sector to an invalid state, set the invalid flag of the old simulated EEPROM sector to indicate that the old simulated EEPROM sector is invalid, enable the new simulated EEPROM sector to store data, and execute step C3.

[0060] C10: Update the SRAM directory information and execute step C11.

[0061] C11: The program ends execution and returns to SUCC status.

[0062] C12: The program ends execution and returns to the ERR status.

[0063] C13: The program ends execution and returns to NO_DATA_WRITE status.

[0064] In one embodiment, the data stored in the simulated EEPROM space may be read in the following manner.

[0065] Determine the third data to be processed to be taken out; if there is data with the same content as the third data to be processed in the second data to be processed in the buffer queue, obtain the data with the same content as the third data to be processed in the buffer queue as the third data to be processed; otherwise, obtain the third data to be processed from the simulated EEPROM storage space.

[0066] In this way, when the third data to be processed is actually in the buffer queue, it can be directly taken out from the buffer queue without storing in and taking out the simulated EEPROM storage space, thereby reducing unnecessary storage times and further extending the service life of FLASH.

[0067] If the data block area that needs to be read does not exist in the buffer queue, but there is a data block area that needs to be read in the simulated EEPROM storage space, the data in this data block area will be read from the simulated EEPROM storage space. The read data will be verified and compared with the verification data of the read data to ensure that the read data is correct and complete.

[0068] The verification data of the read data may be calculated when the data is stored, and the calculation method is the same as that of the verification data algorithms in the above embodiments.

[0069] In one embodiment of the present invention, the simulated EEPROM storage space for writing each data in the buffer queue in queue order includes: For each item of data in the buffer queue, the content of the data is written based on at least one cycle, wherein the number of bytes of the content written in each cycle does not exceed a preset maximum number of bytes.

[0070] Control the byte size written in a single cycle to prevent problems in periodic task scheduling due to long write operations, thereby reducing the problem of long write times affecting the main loop scheduling of the program due to writing a large amount of data at a time.

[0071] Each of the above data may refer to any first or second data to be processed in the aforementioned embodiments.

[0072] In one embodiment, if the number of bytes of the content written in a single cycle is less than a preset minimum number of bytes, the number of bytes written is increased to a number not less than the minimum number of bytes by supplementing the number of bytes.

[0073] This ensures that each access process is performed in multiples of the block area, ensuring that there is a corresponding relationship between each block area, data and storage area serial number.

[0074] In one embodiment, after writing each data in the buffer queue into the simulated EEPROM storage space in queue order, the method further includes: For each item of data in the buffer queue, determine whether the data is written successfully; If the writing is successful, then the preset directory is searched to see whether there is stored data with the same storage area serial number as the data; If it does not exist, the invalid flag of the previous storage area of ​​the data is set, and the directory is updated based on the invalid flag.

[0075] As in the aforementioned step C12, the directory can be stored in SRAM. The directory can record the storage area that has been written, and can record the serial number of each storage area that has been written. If the stored data with the same serial number of the storage area in the directory is not found, it means that a new block area has been written, and then the subsequent data is written in sequence in the address of the new block area. Correspondingly, the previous block area is invalidated by setting the invalid flag. The directory can traverse the current valid sectors of the FLASH as the simulated EEPROM during power-on initialization, record the serial number and address of the current valid data block area, and the simulated EEPROM information will be quickly read through this directory during subsequent reading. After the block data is successfully written into the FLASH, the address information of the corresponding block in the directory can also be updated.

[0076] The following Figure 2 The flowchart shown illustrates an implementation method of writing the first data to be processed into the buffer queue.

[0077] First, the FLASH is powered on and initialized to determine whether the data ID, data length, and FIFO (First Input First Output) data in the SRAM are out of range. FIFO data out of range means that after the FIFO maximum storage number is reached or there is a possibility that the next data or packet cannot be stored, the part that cannot be stored needs to be processed as needed, such as discarded.

[0078] If any item is out of range, it is not written into the buffer queue. In this embodiment, FIFO is used as a buffer queue. In other examples, queues with non-FIFO scheduling strategies may also be used, such as using a last-in-first-out strategy, which is not limited in the embodiment of the present invention.

[0079] Otherwise, it is further determined whether the FIFO has the same ID and the same data. If so, it means that the same data already exists in the queue, and it is not written into the buffer queue. Specifically, the above verification data can be used to determine whether the data is the same. ID represents the storage area serial number.

[0080] If the data is not the same, it is determined whether there is the same ID and data in the flash. If not, it is not written into the buffer queue. If so, it is written into the FIFO queue of the current put_index, that is, into the buffer queue. put_index represents the pointer number, that is, the index position pointed to by the current pointer.

[0081] And set the queue number current_size++, indicating that the data item in the queue increases by 1, and write the pointer label put_index++. After the data is stored, the pointer points to the next location that can be used to store data until it exceeds the range.

[0082] Accordingly, Figure 3 The illustrated embodiment shows an implementation method of data reading.

[0083] After power-on initialization, first determine whether the id and length are out of range, similar to Figure 2 In the embodiment shown, if the range is exceeded, an out of range ERR is returned, indicating an error occurs; If no error occurs, it is determined whether the same ID exists in the FIFO. Similarly, the ID can be used to represent the block number. If yes, the data is read from the FIFO. If not, the corresponding record information is read from the flash.

[0084] To determine whether the reading is successful, you can compare the length and ID of the read data with the preset length and ID. If the length and ID are consistent, the reading is considered successful. If the reading is not successful, ERR is returned to indicate an error.

[0085] Figure 4 The illustrated embodiment describes a method for implementing a write FLASH command.

[0086] Determine whether the FIFO is empty. If so, write the pointer labels put_index = 0 and get_index = 0. Among them, put_index is the pointer for putting data into the queue, pointing to the head of the queue (the position that enters later), get_index is the pointer for taking data out of the queue, pointing to the tail of the queue (the position that enters first), and return RESET.

[0087] If the FIFO is not empty in the above judgment, the data to be written into the FIFO is obtained to determine whether the ID and length of the data are out of range. If so, RESET is returned to reset the FIFO buffer queue. If not, the write FLASH operation is performed.

[0088] Determine whether the writing is successful. If not, return to the step of determining whether the data ID and length are out of range and re-write. If the writing is successful, get the pointer, set get_index++, current_size--, and return the SET flag to indicate that the setting is successful.

[0089] Figure 5 The illustrated embodiment is used to illustrate a specific implementation method of executing a write command.

[0090] The process includes: determining whether the data to be written is empty; if so, returning NO_DATA_WRITE, as in the aforementioned step C13, indicating an error occurs.

[0091] If it is not empty, it is determined whether the space of the current sector is sufficient. The determination method can be to obtain the number of bytes of the data to be written and the number of available bytes of the remaining space of the current simulated EEPROM sector for comparison.

[0092] If the space in the current sector is sufficient, the new data will be written from the end of the previous data. After writing, it will be determined whether the writing is successful. If not, ERR will be returned to indicate an error. If successful, it will be determined whether there is the same data block id in the directory, that is, the block data with the same area sequence number. If not, the directory will be updated in SRAM. If so, the invalid flag bit of the previous data block area will be written to the flag, and then the directory will be updated in SRAM. SUCC will be returned to indicate a successful write.

[0093] If the space of the current sector is insufficient, it is determined whether the next sector is in a state after being completely erased. If not, the sector is continuously erased.

[0094] When the next sector is completely erased, write the serial number and size of the next sector; copy the information of the EEPROM block data, that is, the valid data of the current sector to the next sector.

[0095] After the copy process is completed, it is determined whether the copy is successful. If not, ERR is returned to indicate an error. If so, the valid flag bit of the new EEPROM sector is written and the flag bit of the old sector is set to invalid.

[0096] In one embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any of the data processing methods described above is implemented.

[0097] In one embodiment of the present invention, there is further provided an electronic device, comprising: a memory and a processor; a computer program is stored in the memory, and when the computer program is executed by the processor, any of the data processing methods described above is implemented.

[0098] Figure 6 It is a structural block diagram of an electronic device according to an embodiment of the present invention.

[0099] like Figure 6 As shown, the electronic device 600 includes: a processor 601 and a memory 603. The processor 601 and the memory 603 are connected, such as through a bus 602. Optionally, the electronic device 600 may further include a transceiver 604. It should be noted that in actual applications, the transceiver 604 is not limited to one, and the structure of the electronic device 600 does not constitute a limitation on the embodiments of the present invention.

[0100] Processor 601 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of the present invention. Processor 601 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0101] The bus 602 may include a path to transmit information between the above components. The bus 602 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 602 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0102] The memory 603 is used to store a computer program corresponding to the data processing method of the above embodiment of the present invention, and the computer program is controlled and executed by the processor 601. The processor 601 is used to execute the computer program stored in the memory 603 to implement the content shown in the above method embodiment.

[0103] Among them, the electronic device 600 includes but is not limited to: mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 6 The electronic device 600 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0104] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0105] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0106] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0107] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0108] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0109] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0110] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0111] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A data processing method, characterized in that: The method comprises: Determine first data to be processed to be written into the simulated EEPROM storage space; wherein the simulated EEPROM storage space is generated based on the FLASH storage space; Writing the first to-be-processed data into a buffer queue; wherein the buffer queue is preset in a storage space other than the FLASH storage space; By periodically executing a write command for the buffer queue, each data in the buffer queue is written into the simulated EEPROM storage space according to the queue order.

2. The method according to claim 1, characterized in that The step of determining the first data to be processed to be written into the simulated EEPROM storage space comprises: Get target data; The storage area serial number and check code of the target data are compared with the storage area serial number and check code of the second data to be processed in the buffer queue respectively. If they are different, the storage area serial number and check code of the target data are compared with the storage area serial number and check code of the stored data in the simulated EEPROM storage space respectively. If they are different, the target data is determined to be the first data to be processed.

3. The method according to claim 1, characterized in that The simulated EEPROM storage space is divided into at least two simulated EEPROM sectors, wherein each simulated EEPROM sector is generated based on a FLASH sector of at least one FLASH storage space.

4. The method according to claim 1, characterized in that: When executing the write command, if there is a simulated EEPROM sector that is full of data, the valid data in the simulated EEPROM sector is copied to the next simulated EEPROM sector; Set the simulated EEPROM sector to an invalid state and set the next simulated EEPROM sector to a valid state; The storage space of invalid data in the simulated EEPROM sector is set as the remaining storage space of the next simulated EEPROM sector.

5. The method according to claim 1, characterized in that The method further comprises: Determining third data to be processed to be retrieved; If the second data to be processed in the buffer queue contains data with the same content as the third data to be processed, the data with the same content as the third data to be processed in the buffer queue is obtained as the third data to be processed; otherwise, the third data to be processed is obtained from the simulated EEPROM storage space.

6. The method according to claim 1, characterized in that The simulated EEPROM storage space for writing each data in the buffer queue in queue order includes: For each item of data in the buffer queue, the content of the data is written based on at least one cycle, wherein the number of bytes of the content written in each cycle does not exceed a preset maximum number of bytes.

7. The method according to claim 6, characterized in that If the number of bytes written in a single cycle is less than the preset minimum number of bytes, the number of bytes written is increased to a number not less than the minimum number of bytes by supplementing the number of bytes.

8. The method according to claim 1, characterized in that: After writing each data in the buffer queue into the simulated EEPROM storage space according to the queue order, the method further includes: For each item of data in the buffer queue, determine whether the data is written successfully; If the writing is successful, then the preset directory is searched to see whether there is stored data with the same storage area serial number as the data; If it does not exist, the invalid flag of the previous storage area of ​​the data is set, and the directory is updated based on the invalid flag.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data processing method according to any one of claims 1 to 8 is implemented.

10. An electronic device, characterized in that: include: Memory, processor; The memory stores a computer program, and when the computer program is executed by the processor, the data processing method according to any one of claims 1 to 8 is implemented.

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