Method and device for performing security verification on data in integrated circuit and medium

Abstract

The embodiment of the invention discloses a method and device for carrying out safety verification on data in an integrated circuit and a medium, and the method comprises the steps: determining a first address field of a first group of data written into a first memory in the integrated circuit according to an address corresponding to a write pointer; storing the first group of data into a storage space of the first address field in the first memory; determining target coded data based on the first group of data; storing the target coded data into a second memory located in the integrated circuit; the first memory is different from the second memory; and based on the target coded data, performing security verification on a second group of data read from the first memory. According to the embodiment of the invention, the data bit width during data transmission is reduced, the cost of data verification is reduced, and low-cost data verification is realized.

Description

Technical Field

[0001] The present disclosure relates to data processing technology in an integrated circuit, and in particular to a method, device and medium for performing security verification on data in an integrated circuit. Background Art

[0002] In vehicle applications, high-speed vehicle chips (e.g., vehicle SoC chips, single-chip microcomputer chips, Ethernet chips) have a large amount of data exchange, which requires a large amount of First Input First Output (FIFO) memory for temporary data caching and solving speed mismatch problems. FIFO memory is the buffering link of the system. Without FIFO memory, the entire high-speed vehicle chip will not work properly. The data in FIFO memory needs to be protected in the application, and how to achieve low-cost security protection of FIFO memory is a technical problem that needs to be solved urgently. Summary of the invention

[0003] In order to solve the above technical problems, the present disclosure is proposed. Embodiments of the present disclosure provide a method, device and medium for performing security verification on data in an integrated circuit.

[0004] According to one aspect of an embodiment of the present disclosure, a method for performing security verification on data in an integrated circuit is provided, comprising:

[0005] Determining, according to the address corresponding to the write pointer, a first address segment where the first group of data is written into a first memory located in the integrated circuit;

[0006] storing the first set of data into a storage space of the first address segment in the first memory;

[0007] Based on the first set of data, determining target encoding data;

[0008] storing the target encoded data in a second memory located in the integrated circuit; the first memory is different from the second memory;

[0009] Based on the target encoded data, a security check is performed on the second group of data read from the first memory.

[0010] According to another aspect of an embodiment of the present disclosure, there is provided a device for performing security verification on data in an integrated circuit, comprising:

[0011] An address determination module, for determining, according to an address corresponding to a write pointer, a first address segment where a first group of data is written into a first memory located in the integrated circuit;

[0012] A data storage module, used for storing the first set of data into a storage space of the first address segment in the first memory;

[0013] A data encoding module, used for determining target encoding data based on the first group of data;

[0014] A code writing module, used for storing the target code into a second memory located in the integrated circuit; the first memory is different from the second memory;

[0015] A security verification module is used to perform a security verification on a second set of data read from the first memory based on the target coded data.

[0016] According to another aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is used to execute the method for performing security verification on data in an integrated circuit as described in any one of the above embodiments.

[0017] According to another aspect of the embodiments of the present disclosure, an electronic device is provided, the electronic device comprising:

[0018] processor;

[0019] a memory for storing instructions executable by the processor;

[0020] The processor is used to read the executable instructions from the memory and execute the instructions to implement the method for security verification of data in an integrated circuit as described in any one of the above embodiments.

[0021] Based on a method, device and medium for performing security verification on data in an integrated circuit provided by the above-mentioned embodiments of the present disclosure, when a first group of data is stored in a storage space in a first memory, target coded data corresponding to the first group of data is stored in a second memory, and when the second group of data in the first memory is read, data verification is performed using the independently stored target coded data; since the target coded data used for data verification is stored in different memories from the first group of data, the first group of data and the target coded data are avoided from being stored together, thereby reducing the amount of data stored in the first memory, thereby reducing the data bit width during data transmission, reducing the cost of data verification, and achieving low-cost data verification.

[0022] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the drawings, the same reference numerals generally represent the same components or steps.

[0024] Figure 1 is a structural schematic diagram of a system for performing security verification on data in an integrated circuit provided by an exemplary embodiment of the present disclosure;

[0025] Figure 2 is a flowchart of a method for performing security verification on data in an integrated circuit provided by an exemplary embodiment of the present disclosure;

[0026] Figure 3 This disclosure Figure 2 A schematic flow chart of step 206 in the embodiment shown;

[0027] Figure 4 This disclosure Figure 3 A flow chart of step 2062 in the embodiment shown;

[0028] Figure 5 This disclosure Figure 2 A schematic flow chart of step 210 in the embodiment shown;

[0029] Figure 6 is a flowchart of a method for performing security verification on data in an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0030] Figure 7 is a schematic structural diagram of a device for performing security verification on data in an integrated circuit provided by an exemplary embodiment of the present disclosure;

[0031] Figure 8a is a schematic structural diagram of a device for performing security verification on data in an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0032] Figure 8b is a structural diagram of a data encoding module provided by another exemplary embodiment of the present disclosure;

[0033] Figure 9a is a structural schematic diagram of a device for performing security verification on data in an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0034] Figure 9b is a structural diagram of a security verification module provided by another exemplary embodiment of the present disclosure;

[0035] Fig.10 is a structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. It should be understood that the present disclosure is not limited to the example embodiments described herein.

[0037] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0038] Application Overview

[0039] In the process of implementing the present disclosure, the inventors found that there may be a large number of FIFO memories in integrated circuits (for example, high-speed vehicle-mounted chips, etc.) for data caching, transport, matching of operation speed, etc. The functions of FIFO memories include: 1) caching continuous data streams to prevent data loss during stacking and storage operations; 2) centralizing data for stacking and storage. Through centralized data processing, stacking and storage that originally required multiple bus operations to execute can be completed through one bus operation, which can avoid frequent bus operations and reduce the burden on the CPU; 3) allowing the system to perform direct memory access (DMA, Direct Memory Access) operations to increase the data transmission speed. Therefore, when reading data from the FIFO memory, a security check is required. When the bit width of the FIFO memory is relatively wide and the depth is very deep, if the traditional method is used to perform security checks on the data stored in the FIFO memory, a lot of data bit width needs to be occupied. In order to solve the above problems, the present disclosure provides a method for performing security checks on data in an integrated circuit, which reduces the bit width occupied when performing security checks on the data stored in the FIFO memory, and compresses the chip area and the cost of the integrated circuit.

[0040] Exemplary Methods

[0041] Figure 1 FIG. 1 is a schematic diagram of a system for performing security verification of data in an integrated circuit provided by an exemplary embodiment of the present disclosure. Figure 1 As shown, the system provided by the embodiment of the present disclosure includes:

[0042] The first memory 101 is a FIFO memory, which is used to store interactive data. When reading data, it is read out in the order in which the data is stored, that is, the data first stored in the FIFO memory is read out first. For example, the figure shows that the data flow direction is from top to bottom. At this time, the input data (input data) first input to the first memory 101 will be stored in the bottom (the storage space numbered 1 in the figure), and the subsequent stored data will be stored in the order of the storage space in the first memory 101 (to indicate the order, the storage addresses in the first memory 101 are sorted in the order of 1, 2, 3...n-2, n-1, n in the figure). When reading data from the first memory 101, it is read in the order of the storage space, and the data stored first is read out first.

[0043] The second memory 102 stores the coded data corresponding to the input data when the data is stored in the first memory 101. When the output data is read from the first memory 101, the coded data corresponding to the output data is read from the second memory 102 to verify the integrity of the output data.

[0044] Exemplary Methods

[0045] Figure 2 1 is a flow chart of a method for performing security verification of data in an integrated circuit provided by an exemplary embodiment of the present disclosure. This embodiment can be applied to electronic devices such as vehicle-mounted integrated circuits, such as Figure 2 As shown, the following steps are included:

[0046] Step 202: Determine, according to the address corresponding to the write pointer, a first address segment where a first group of data is written into a first memory in the integrated circuit.

[0047] Among them, the pointer describes the location of the data in the memory, and indicates the relative distance value of an entity occupying the storage space at the starting position of this space; the write pointer is the corresponding pointer when the data is written. In this embodiment, the first address segment is determined by the start address and the end address. Optionally, the start address of the first address segment of the data to be written in the first memory is indicated by the write pointer. Optionally, the size of the first address segment can be determined by the size of the first group of data, that is, the start address of the first address segment is determined by the write pointer, and the end address of the first address segment is obtained by accumulating the size of the first data from the start address to determine the first address segment.

[0048] Step 204: store the first set of data into the storage space of the first address segment in the first memory.

[0049] In one embodiment, the first memory may be a FIFO memory; there is a corresponding relationship between the storage space in the first memory and the address. For example, a corresponding storage space of a certain size may be found based on the start address and end address corresponding to the first address segment. For example, the first memory may store 256 bytes, and the first address segment is from 00000000 (start address) to 00000110 (end address), corresponding to the storage space from the 0th byte to the 6th byte. At this time, the first group of data is stored in the storage space based on the 0th byte to the 6th byte.

[0050] Step 206: Determine target coded data based on the first set of data.

[0051] Optionally, the first group of data is encoded at least once to obtain target encoded data, wherein the encoding method may include but is not limited to: cyclic redundancy check code method (Cyclic Redundancy Check, CRC), hash coding method, compression coding method, identification coding method, etc.; the obtained target encoded data may include but is not limited to: cyclic redundancy check code, hash coding, compression coding, identification coding, etc.

[0052] Step 208, storing the target encoded data into a second memory located in the integrated circuit.

[0053] The first memory is different from the second memory. The first memory and the second memory are used to store different data; the first memory and the second memory are independent of each other to achieve independent storage of the first group of data and the target coded data. Optionally, the memory type of the second memory can be the same as or different from that of the first memory, for example, the second memory can be a FIFO memory.

[0054] Step 210: Perform security verification on the second set of data read from the first memory based on the target encoded data.

[0055] In the prior art, data often faces various interferences and errors during transmission, such as data loss, data tampering, etc. If not effectively verified, these data errors may cause abnormal operation or even crash of the system. Therefore, data verification is particularly important in FIFO. The embodiment of the present disclosure implements effective security verification of data by performing security verification on the second set of data based on the target encoding data.

[0056] The data security check in this embodiment can be a data integrity check, which is implemented by adding a check code or a check value during data transmission. The sender calculates the check code when sending data, and the receiver recalculates the check code after receiving the data for comparison, thereby verifying the integrity of the data.

[0057] The method for performing security verification on data in an integrated circuit provided by the embodiment of the present disclosure stores target coded data corresponding to the first group of data in a second memory when storing the first group of data in a storage space in a first memory, and performs data verification through the independently stored target coded data when reading the second group of data in the first memory; since the target coded data used for data verification is stored in different memories from the first group of data, the first group of data and the target coded data are avoided from being stored together, thereby reducing the amount of data stored in the first memory, thereby reducing the data bit width during data transmission, reducing the cost of data verification, and achieving low-cost data verification.

[0058] like Figure 3 As shown in the above Figure 2 Based on the illustrated embodiment, step 206 may include the following steps:

[0059] Step 2061, performing encoding operation processing on the first group of data to obtain data encoding corresponding to the first group of data.

[0060] Optionally, the first set of data may include a preset number of data, and the value of the preset number can be set according to the specific application scenario to achieve data encoding processing with adjustable granularity. Optionally, the preset number of data included in the first set of data is encoded separately to obtain corresponding data encoding. Among them, the granularity represents the size or accuracy of the data unit (corresponding to the first set of data in this embodiment) that is concerned when observing or processing data. It can be coarse-grained (larger data unit) or fine-grained (smaller data unit). The larger the amount of data stored in the coarse-grained encoded data at one time, the more space compression.

[0061] Step 2062, determining target coded data based on a preset number of data codes.

[0062] In this embodiment, the data encoding granularity is adjusted by a preset number. Different preset numbers can be set in different application scenarios to meet the needs of the corresponding application scenarios. For example, when the amount of data is large, in order to improve the verification efficiency, the preset number is increased. By increasing the amount of data for performing data verification at one time, the efficiency of data verification is improved. For another example, when the amount of data is small and a higher accuracy is required, the preset number is reduced. By reducing the amount of data for performing data verification at one time, erroneous data can be quickly located, thereby improving the accuracy of data verification.

[0063] like Figure 4 As shown in the above Figure 3 Based on the illustrated embodiment, step 2062 may include the following steps:

[0064] Step 401, accumulate the value of the write pointer, and determine the number of data codes according to the accumulated value of the write pointer.

[0065] Optionally, after each write pointer determines the address for the corresponding write data, the write pointer corresponding to the next write data is determined based on the write pointer, that is, the amount of data stored can be determined based on the cumulative value of the write pointer; in one storage, the amount of data included in the first group of data can be determined based on the cumulative amount of the write pointer, and then the number of data codes can be determined.

[0066] Step 402: Process the preset number of data codes according to the relationship between the number of data codes and the preset number to obtain target coded data.

[0067] Optionally, the number of data codes may be counted by a counter, and the relationship between the number of data codes and a preset number may be determined based on the counting result of the counter. Optionally, by calculating whether the remainder obtained by dividing the counting result of the counter by the preset number is 0, it is determined whether to determine the target code data. For example, in response to the remainder being 0, the target code data is determined based on the preset number of data codes, and in response to the remainder not being 0, the target code data is not determined. For another example, when the number in the counter reaches the preset number, a reset process is performed, and it is determined whether to determine the target code data based on whether the data in the counter is 0. For example, in response to the data in the counter being 0, the target code data is determined based on the preset number of data codes, and in response to the data in the counter not being 0, the target code data is not determined.

[0068] Optionally, a preset number of data codes may be accumulated to obtain target coded data; or, a preset number of data codes may be encoded or processed by other data processing methods to obtain target coded data, for example, at least one of addition, subtraction, multiplication and division may be performed on a preset number of data codes, or, for example, hash processing may be performed on a preset number of data codes.

[0069] Step 403: store the target coded data into a preset storage space in the second memory.

[0070] Optionally, the determination of the preset storage space in the second memory may be similar to the determination of the storage space in the first memory, for example, the preset storage space is determined according to the corresponding write pointer.

[0071] In this embodiment, each time data is written to the first memory, the data is encoded, and each time data is stored, the write pointer is accumulated accordingly. When the accumulated value of the write pointer reaches a preset number each time, the target encoded data is obtained based on the preset number of encoded data, and the target encoded data is stored in the second memory. By storing only the target encoded data in the second memory, and the number of the target encoded data is much smaller than the encoded data (the number of the target encoded data is 1 / m of the encoded data, where m represents the preset number), the amount of data stored in the second memory is reduced, and therefore, the storage space of the second memory can be compressed to reduce its space occupation in the integrated circuit.

[0072] like Figure 5 As shown in the above Figure 2 Based on the illustrated embodiment, step 210 may include the following steps:

[0073] Step 2101, read a second set of data from a first memory.

[0074] Optionally, since the first memory is a FIFO memory, when reading data, the second set of data read is the earliest data stored in the first memory at the current moment. For example, the second set of data is Figure 1 The data in the first memory shown are located in the storage space numbered 1 to the storage space numbered m (m represents a preset number). For example, the second group of data may be the first group of data.

[0075] Optionally, according to the second address segment corresponding to the read pointer, data is read from the second address segment in the storage space of the first memory, and the value of the read pointer is accumulated.

[0076] In this embodiment, the read pointer can point to the second address segment corresponding to the earliest stored data in the first memory. The data stored in the storage space corresponding to the second address segment is the earliest stored data at the current moment. The data in the storage space is read to achieve first-in-first-out data reading. After the second group of data is read, the storage space corresponding to the second address segment is cleared and can continue to receive stored data. In addition, by accumulating the value of the read pointer, the address accuracy of the next data reading is guaranteed.

[0077] A preset number of read data is determined according to the result of numerical accumulation to obtain a second set of data.

[0078] Optionally, when reading data, since the target coded data stored in the second memory corresponds to a preset number of input data, in order to implement integrity verification of the read data based on the target coded data, a preset number of read data are read out continuously, and the second group of data is used as the verification granularity. The read data of the preset data is verified each time, thereby improving the efficiency of data verification.

[0079] Step 2102, based on the second set of data, determine the output encoded data.

[0080] Optionally, for all the read data included in the second group of data, the encoding method for encoding the input data may be used to encode the read data to obtain output encoded data obtained by encoding the second group of data.

[0081] Step 2103: Determine the integrity of the second group of data based on the relationship between the output coded data and the target coded data corresponding to the second group of data.

[0082] Optionally, the target coded data is the coded data obtained by encoding the second group of data and storing it in the second memory when the second group of data is input into the first memory.

[0083] In this embodiment, the output coded data is obtained by the same coding method as the target coded data, so if the data before coding is the same, the corresponding output coded data and the target coded data should be the same. In this embodiment, the output coded data obtained by encoding the second set of data when reading is matched with the target coded data obtained by encoding when inputting. When the output coded data and the target coded data are the same, it is determined that the second set of data is complete, otherwise, it is determined that the second set of data is incomplete, and in response to the incompleteness of the second set of data, an error is reported.

[0084] Optionally, step 2102 may include:

[0085] Perform at least one encoding operation on the second group of data to obtain at least one operation code; and determine output encoded data based on the at least one operation code.

[0086] In this embodiment, encoding processing is performed for each output data included in the second group of data. The encoding method used in the encoding processing is the same as the encoding method when the data is stored in the first memory, which ensures the comparability of the output coded data and the target coded data. Optionally, each time an output data is read out, encoding processing is performed on the read output data to obtain an operation code. Before the number of output data has not accumulated to a preset number, no output coded data is generated. Only when the number of output data reaches the accumulated preset number, at least one operation code is processed to obtain output coded data. Optionally, the processing of at least one operation code is the same as the processing of the data code when the data is stored in the first memory, for example, at least one operation code is accumulated to obtain output coded data; or, encoding or other data processing methods are performed on at least one operation code to obtain output coded data.

[0087] In some optional embodiments, step 2103 may include:

[0088] Determine the target coded data corresponding to the second group of data in the second memory.

[0089] Optionally, when the second memory is a FIFO memory, the earliest stored data is obtained from the second memory as the target coded data corresponding to the second group of data; or, when the second memory is a common memory, when the second group of data is stored in the first memory, an identification code is assigned to the second group of data and its corresponding target coded data, the second group of data plus the identification code is stored in the first memory, and the target coded data plus the identification code is stored in the second memory, and when the second group of data is read, the corresponding target coded data is obtained in the second memory according to the obtained identification code as an index.

[0090] The integrity of the second set of data is determined based on the difference between the read encoded data and the target encoded data.

[0091] Optionally, in response to a difference between the read coded data and the target coded data, it is determined that the second set of data is incomplete and an error message is issued; in response to no difference between the read coded data and the target coded data, it is determined that the second set of data is complete, and the data reading from the first memory continues, the read data in the next storage space in the first memory is read, and the integrity check of the read data continues. This embodiment protects the integrity of the data by comparing the read coded data with the target coded data to determine whether the data read from the first memory is complete during the storage process. In addition, since the target coded data is stored in the second memory, the storage space occupied in the first memory is reduced, and the cost of data integrity check is reduced.

[0092] In some optional embodiments, the comparison between the read coded data and the target coded data can be achieved through a comparator. For example, each bit of the code in the read coded data and the target coded data is compared by a comparator. When any bit of the code is different, it can be determined that there is a difference between the read coded data and the target coded data. Optionally, a multi-bit comparator can be used to compare multiple bits of code in the read coded data and the target coded data at the same time, or a unit comparator can be used to compare the codes in the read coded data and the target coded data in turn.

[0093] Figure 6 This is a flow chart of a method for performing security verification of data in an integrated circuit provided by another exemplary embodiment of the present disclosure. This embodiment is applied in vehicle-mounted applications. In vehicle-mounted applications, high-speed vehicle-mounted chips have a large amount of data exchange, which requires a large amount of FIFO memory for temporary data caching to solve problems such as speed mismatch. Figure 6 As shown, the following steps are included:

[0094] Step 601, pre-configure a threshold m of coding granularity, and determine a target coding data by storing m input data at a time through the value of coding granularity.

[0095] Step 602: Store the input data to be exchanged between chips into the first memory according to the storage address corresponding to the write pointer.

[0096] Step 603, each time a piece of input data is stored, the write pointer count is increased by 1, and a coding operation is performed on the input data to obtain a data code.

[0097] Step 604, each time a data code (CRC code) is obtained, the value of the first counter (counter) is increased by 1 (the first counter is aligned with the write pointer, and each time the write pointer counts by 1, the corresponding value of the first counter is increased by 1), and it is determined based on the accumulated value of the first counter whether the number of data codes reaches m. If so, execute step 605; otherwise, continue writing data and execute step 602.

[0098] Step 605, obtaining target coded data based on the m data codes, storing the target coded data in a second memory, and clearing the first counter.

[0099] Step 606: After the input data is stored in the first memory, in response to the demand for data from other chips, data is read out from the first memory according to the storage space corresponding to the read pointer.

[0100] Step 607, each time a piece of output data is read out, the read pointer count is increased by 1, and a coding operation is performed on the output data (the coding method is the same as the coding method used in step 603) to obtain the operation code.

[0101] Step 608, every time an operation code is obtained, the value of the second counter is increased by 1 (the second counter is aligned with the read pointer, and each time the read pointer counts by 1, the corresponding value of the second counter is increased by 1), and it is determined based on the accumulated value of the second counter whether the number of operation codes reaches m. If so, execute step 609; otherwise, continue data reading and execute step 606.

[0102] Step 609, obtaining output coded data based on the m operation codes, and clearing the second counter.

[0103] Step 610, read the earliest data stored in the second memory, compare the obtained target coding data with the output coding data, and determine whether the target coding data and the output coding data are consistent. If so, it means that the m output data corresponding to the output coding data are normal; otherwise, an error message is issued, indicating that there are errors in the m output data corresponding to the output coding data.

[0104] Any method for performing security verification on data in an integrated circuit provided in the embodiments of the present disclosure may be executed by any appropriate device with data processing capabilities, including but not limited to: a terminal device and a server, etc. Alternatively, any method for performing security verification on data in an integrated circuit provided in the embodiments of the present disclosure may be executed by a processor, such as the processor executing any method for performing security verification on data in an integrated circuit mentioned in the embodiments of the present disclosure by calling corresponding instructions stored in a memory. This will not be described in detail below.

[0105] Exemplary Devices

[0106] Figure 7 FIG. 1 is a schematic diagram of a device for performing security verification on data in an integrated circuit provided by an exemplary embodiment of the present disclosure. Figure 7 As shown, the device provided in this embodiment includes:

[0107] The address determination module 71 is used to determine the first address segment where the first group of data is written into the first memory in the integrated circuit according to the address corresponding to the write pointer.

[0108] The data storage module 72 is used to store the first set of data into the storage space of the first memory in the first address segment.

[0109] The data encoding module 73 is used to determine target encoding data based on the first set of data.

[0110] The code writing module 74 is used to store the target code into the second memory located in the integrated circuit.

[0111] The first memory is different from the second memory.

[0112] The security verification module 75 is used to perform a security verification on the second group of data read from the first memory based on the target coded data.

[0113] The device for performing security verification on data in an integrated circuit provided by the embodiment of the present disclosure stores target coded data corresponding to the first group of data in a second memory when storing the first group of data in the storage space in the first memory, and performs data verification through the independently stored target coded data when reading the second group of data in the first memory; since the target coded data used for data verification is stored in different memories from the first group of data, the first group of data and the target coded data are avoided from being stored together, thereby reducing the amount of data stored in the first memory, thereby reducing the data bit width during data transmission, reducing the cost of data verification, and achieving low-cost data verification.

[0114] Figure 8aFIG. 1 is a schematic diagram of a device for performing security verification on data in an integrated circuit provided by another exemplary embodiment of the present disclosure. Figure 8a As shown, the data encoding module 73 in the device provided in this embodiment includes:

[0115] The first encoding unit 731 is used to perform encoding operation processing on the first group of data to obtain data codes corresponding to the first group of data.

[0116] The data determination unit 732 is used to determine target coded data based on a preset number of data codes.

[0117] Figure 8b FIG. 1 is a schematic diagram of a data encoding module provided by another exemplary embodiment of the present disclosure. Figure 8b As shown, the data determination unit 732 in the data encoding module provided in this embodiment includes:

[0118] The first counter 81 is used to accumulate the value of the write pointer and determine the number of data codes according to the accumulated value of the write pointer.

[0119] The quantity comparison unit 82 is used to process the preset quantity of data codes according to the relationship between the quantity of data codes and the preset quantity to obtain target coded data.

[0120] The coding storage unit 83 is used to store the target coding data into a preset storage space in the second memory.

[0121] Figure 9a FIG. 1 is a schematic diagram of a device for performing security verification on data in an integrated circuit provided by another exemplary embodiment of the present disclosure. Figure 9a As shown, the security verification module 75 in the device provided in this embodiment may include:

[0122] The data reading unit 751 is used to read the second set of data from the first memory.

[0123] The output coding unit 752 is used to determine output coded data based on the second set of data.

[0124] The data verification unit 753 is used to determine the integrity of the second group of data according to the relationship between the output coded data and the target coded data corresponding to the second group of data.

[0125] Figure 9b FIG. 1 is a schematic diagram of a security verification module provided by another exemplary embodiment of the present disclosure. Figure 9b As shown, the data reading unit 751 in the security verification module provided in this embodiment may include:

[0126] The second counter 91 is used to read data from the storage space of the first memory from the second address segment according to the second address segment corresponding to the read pointer, and accumulate the value of the read pointer.

[0127] The data quantity determination unit 92 is used to determine a preset quantity of read data according to the result of numerical accumulation to obtain a second set of data.

[0128] Optionally, in Figure 9b In the illustrated embodiment, the output encoding unit 752 in the security verification module may include:

[0129] The second encoding unit 93 is used to perform at least one encoding operation on the second group of data to obtain at least one operation code.

[0130] The coded data output unit 94 is used to determine output coded data according to at least one operation code.

[0131] Optionally, in Figure 9b In the illustrated embodiment, the data verification unit 753 in the security verification module may include:

[0132] The storage coding determination unit 95 is used to determine the target coding data corresponding to the second group of data in the second memory.

[0133] The difference identification unit 96 is used to determine the integrity of the second set of data according to the difference between the read coded data and the target coded data.

[0134] The beneficial technical effects corresponding to the exemplary embodiment of the present device can be found in the corresponding beneficial technical effects of the above exemplary method section, which will not be repeated here.

[0135] Exemplary Electronic Devices

[0136] Fig.10 A structural diagram of an electronic device provided in an embodiment of the present disclosure includes at least one processor 11 and a memory 12.

[0137] The processor 11 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

[0138] The memory 12 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 11 may execute one or more computer program instructions to implement the method for performing security verification on data in an integrated circuit and / or other desired functions of the various embodiments of the present disclosure described above.

[0139] In one example, the electronic device 10 may further include: an input device 13 and an output device 14, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0140] The input device 13 may also include, for example, a keyboard, a mouse, etc.

[0141] The output device 14 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0142] Of course, to simplify, Fig.10 Only some of the components related to the present disclosure in the electronic device 10 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 10 may also include any other appropriate components.

[0143] Exemplary computer program products and computer-readable storage media

[0144] In addition to the above-mentioned methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the method for performing security verification on data in an integrated circuit of various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section.

[0145] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0146] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the processor executes the steps of the method for performing security verification on data in an integrated circuit of various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section.

[0147] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium is, for example, but not limited to, a system, device or device including electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0148] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and cannot be considered as necessary for each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, rather than limitation, and the above details do not limit the present disclosure to being implemented by adopting the above specific details.

[0149] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present disclosure claims and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A method for performing security verification on data in an integrated circuit, comprising: Determining, according to the address corresponding to the write pointer, a first address segment where the first group of data is written into a first memory located in the integrated circuit; storing the first set of data into a storage space of the first address segment in the first memory; Based on the first set of data, determining target encoding data; storing the target encoded data in a second memory located in the integrated circuit; The first memory is different from the second memory; Based on the target encoded data, a security check is performed on the second group of data read from the first memory.

2. The method according to claim 1, wherein: The step of determining target coded data based on the first set of data comprises: Performing encoding operation processing on the first group of data to obtain data encoding corresponding to the first group of data; Based on a preset number of the data codes, the target code data is determined.

3. The method according to claim 2, wherein: Determining the target coded data based on a preset number of the data codes includes: Accumulating the values ​​of the write pointers, and determining the number of the data codes according to the accumulated value of the write pointers; According to the relationship between the number of the data codes and the preset number, the preset number of data codes are processed to obtain the target coded data; The target encoded data is stored in a preset storage space in the second memory.

4. The method according to any one of claims 1 to 3, wherein the step of performing security verification on the second set of data read from the first memory based on the target coded data comprises: Reading a second set of data from the first memory; Based on the second set of data, determining output coded data; The integrity of the second group of data is determined based on a relationship between the output coded data and target coded data corresponding to the second group of data.

5. The method according to claim 4, wherein: The reading the second set of data from the first memory comprises: According to a second address segment corresponding to the read pointer, data is read from the second address segment in the storage space of the first memory, and a value of the read pointer is accumulated; A preset number of read data is determined according to the result of the numerical accumulation to obtain the second set of data.

6. The method according to claim 5, wherein: The step of determining output coded data based on the second set of data comprises: Performing at least one encoding operation process on the second group of data to obtain at least one operation code; The output coded data is determined based on the at least one operational code.

7. The method according to claim 5 or 6, wherein: The determining the integrity of the second set of data according to the relationship between the output coded data and the target coded data corresponding to the second set of data includes: Determining target coded data corresponding to the second group of data in the second memory; The integrity of the second set of data is determined based on the difference between the read encoded data and the target encoded data.

8. A device for performing security verification on data in an integrated circuit, comprising: An address determination module, for determining, according to an address corresponding to a write pointer, a first address segment where a first group of data is written into a first memory located in the integrated circuit; A data storage module, used for storing the first set of data into a storage space of the first address segment in the first memory; A data encoding module, used for determining target encoding data based on the first set of data; A code writing module, used for storing the target code into a second memory located in the integrated circuit; The first memory is different from the second memory; A security verification module is used to perform a security verification on a second set of data read from the first memory based on the target coded data.

9. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the method for performing security verification on data in an integrated circuit as described in any one of claims 1 to 7.

10. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the method for security verification of data in an integrated circuit as described in any one of claims 1-7 above.

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