Method for programming memory
The problem of hot carrier interference and programming interference during the programming process is solved by applying the common source line voltage and bit line voltage using incremental step pulse programming (ISPP) in multiple pre-charging stages of the memory. Achieve more stable and reliable memory operations.
Patent Information
- Application Number
- CN202311092159.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-21
- Filing Date
- 2023-08-29
- Publication Date
- 2025-02-21
AI Technical Summary
When multiple programming triggers of the memory, excessive common source line voltage may cause hot carrier interference and read interference, while reducing the common source line voltage will reduce the programmatic interference prevention of unselected memory cells. ability.
By applying common source line voltage and bit line voltage using incremental step pulse programming (ISPP) in multiple precharge stages, ensure that the channel level of the unselected memory cell is at a sufficiently large voltage level to avoid Hot carrier interference.
It effectively avoids hot carrier interference, reduces the possibility of programming interference in the memory, and ensures the stability and reliability of the memory.
Smart Images
Figure CN119495343A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an operating method of a semiconductor device, and more particularly to a method for programming a memory. Background Art
[0002] When performing a programming operation including multiple programming triggers on a memory, a specific common source line voltage may be applied to the common source line in the precharge stage of the programming trigger to increase the channel level of the unselected memory cell so that it can be at a sufficiently large voltage level to avoid the unselected memory cell from generating the FN tunneling effect (Fowler-Nordheim Tunneling Effect). However, an excessively large common source line voltage may easily generate a relatively large horizontal electric field on a specific word line (e.g., a selected word line) and induce hot carrier interference, causing the threshold voltage of the unselected memory cell to rise and increasing the possibility of generating read interference during a subsequent read operation.
[0003] If the common source line voltage applied to the common source line in the precharge phase is reduced to improve the above problem, the unselected memory cells will have reduced ability to prevent program disturbance due to a drop in channel level, increasing the possibility of program disturbance for the unselected memory cells. Summary of the invention
[0004] The invention provides a method for programming a memory, which can avoid inducing hot carrier interference and reduce the possibility of generating programming interference in the memory.
[0005] The method of programming a memory of the present invention comprises executing multiple programming triggers, wherein each programming trigger comprises a precharge phase and a programming phase, and comprises the following steps: first, in the precharge phase, a common source line voltage is applied to a common source line, wherein the common source line voltage is applied by using incremental step pulse programming (ISPP) in multiple precharge phases. Next, in the programming phase, a programming voltage is applied to a selected word line, wherein the programming voltage is applied by using ISPP in multiple programming phases.
[0006] The method for programming a memory of the present invention comprises performing multiple programming triggers, wherein each of the multiple programming triggers comprises a precharge phase and a programming phase, and comprises the following steps: first, in the precharge phase, a bit line voltage is applied to a bit line, wherein the bit line voltage is applied by using incremental step pulse programming (ISPP) in multiple precharge phases. Next, in the programming phase, a programming voltage is applied to a selected word line, wherein the programming voltage is applied in the form of incremental step pulse programming in multiple programming phases.
[0007] Based on the above, the method for programming a memory of the present invention applies a common source line voltage or a bit line voltage by using incremental step pulse programming (ISPP) in multiple precharge stages, which can avoid generating a relatively large horizontal electric field on a specific word line (e.g., a selected word line) to induce hot carrier interference. Furthermore, the method for programming a memory of the present invention applies a common source line voltage or a bit line voltage by using incremental step pulse programming (ISPP) in multiple precharge stages, which can reduce the possibility of program interference in the memory of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1A A partial three-dimensional schematic diagram of a memory according to an embodiment of the present invention is schematically shown.
[0009] Figure 1B Schematically shows Figure 1A A partial three-dimensional schematic diagram of a storage cell string in an embodiment of a memory.
[0010] Figure 2A as well as Figure 2B The voltage waveform diagram of the memory during programming operation according to one embodiment of the present invention is schematically shown.
[0011] Figure 3 The flowchart of a method for programming a memory according to an embodiment of the present invention is schematically shown.
[0012] Figure 4A The diagram schematically shows a schematic diagram of applying voltage to a ground selection line, a plurality of lower dummy word lines, a common source line, and a serial selection line during a precharge phase of a programming trigger according to an embodiment of the present invention.
[0013] Figure 4B , Figure 4C as well as Figure 4D The schematic diagram schematically shows a schematic diagram of applying voltage to a ground selection line, a serial selection line, a common source line, a selected word line, an unselected word line and a bit line during a programming phase of a one-time programming trigger according to an embodiment of the present invention, wherein Figure 4B The bit line in is the programming bit line. Figure 4C The bit line in is the inhibit bit line, and Figure 4D The bit lines in are quick pass write (QPW) bit lines.
[0014] Figure 5A as well as Figure 5B The voltage waveform diagram of the memory during programming operation according to another embodiment of the present invention is schematically shown.
[0015] Figure 6The flowchart of a method for programming a memory according to another embodiment of the present invention is schematically shown.
[0016] Fig. 7A The diagram schematically shows a schematic diagram of applying voltage to a serial selection line, a plurality of upper pseudo word lines, a bit line, a ground selection line and a shared source line during a precharge phase of a programming trigger according to another embodiment of the present invention.
[0017] Figure 7B , Figure 7C as well as Fig.7D A schematic diagram schematically shows a schematic diagram of applying voltages to a ground selection line, a serial selection line, a common source line, a selected word line, an unselected word line, and a bit line during a programming phase of a one-time programming trigger according to another embodiment of the present invention, wherein Figure 7B The bit line in is the programming bit line. Figure 7C The bit line in is the inhibit bit line, and Fig.7D The bit lines in are quick pass write (QPW) bit lines.
[0018] Figure 8 The block diagram schematically shows a memory system according to an embodiment of the present invention.
[0019] Description of Reference Numerals
[0020] 10: Memory
[0021] 10B: Memory block
[0022] 10S: Storage cell string
[0023] 100: Memory device
[0024] 200: Controller
[0025] 1000: Memory System
[0026] BL, BL0, BL1, BL2, BL3: bit lines
[0027] CH: Channel Layer
[0028] CSL: Common Source Line
[0029] CTL: Charge Trapping Layer
[0030] d1: first direction
[0031] d2: second direction
[0032] d3: normal direction of the base
[0033] DWL: pseudo word line stack
[0034] DBWL: Bottom Pseudo Word Line Stack
[0035] DBWL0-DBWL2: Lower pseudo word line
[0036] DC: Insulation column
[0037] DTWL: Top Pseudo Word Line Stack
[0038] DTWL0-DTWL2: Upper pseudo word line
[0039] GBL: Global Bit Line
[0040] GSL: Ground Select Line
[0041] S1, S2, S3: Programming trigger
[0042] S10, S10', S20: Steps
[0043] SB: Base
[0044] SSL: Serial Select Line
[0045] Tpgm, Tpgm1, Tpgm2, Tpgm3: Programming stage
[0046] Tpre, Tpre1, Tpre2, Tpre3: pre-charge stage
[0047] VBL_inhibit, VBL_pgm, VBL_pre, VBL_pre1, VBL_pre2, VBL_pre3, VBL_QPW: bit line voltage
[0048] VC: Multiple vertical channel structures
[0049] VCSL, VCSL_pre, VCSL_pre1, VCSL_pre2, VCSL_pre3: Common source line voltage
[0050] VDBWL, VDTWL: pass voltage
[0051] VDD: power supply voltage
[0052] VPASS_pre: pre-charge voltage
[0053] Vpgm: programming voltage
[0054] VSS: Ground voltage
[0055] VSSL: Serial Select Line Voltage
[0056] WL: word line stack
[0057] WL0-WL95: word lines DETAILED DESCRIPTION
[0058] Figure 1A A partial three-dimensional schematic diagram of a memory according to an embodiment of the present invention is schematically shown, and Figure 1B Schematically shows Figure 1A A partial three-dimensional schematic diagram of a storage cell string in an embodiment of a memory.
[0059] Please also refer to Figure 1A as well as Figure 1B The memory 10 of the present embodiment includes a substrate SB, a common source line CSL, a word line stack WL, a dummy word line stack DWL, a serial selection line SSL, a ground selection line GSL, a plurality of vertical channel structures VC, a plurality of bit lines BL, and a global bit line GBL. The memory 10 may be, for example, a three-dimensional memory, which may be, for example, a three-dimensional NAND flash memory, but the present invention is not limited thereto.
[0060] The substrate SB may be, for example, a semiconductor substrate. In some embodiments, the material of the substrate SB may include silicon, doped silicon, germanium, silicon germanium, semiconductor compounds, other suitable semiconductor materials, or a combination thereof. For example, the substrate SB may be a silicon substrate, but the present invention is not limited thereto. In some embodiments, a plurality of doped regions may be formed in the substrate SB according to design requirements. For example, a plurality of doped regions including a P-type well region (not shown) and an N-type deep well region (not shown) may be formed in the substrate SB, but the present invention is not limited thereto. In other embodiments, a buried oxide layer (not shown) may be further formed on the substrate SB.
[0061] The common source line CSL is, for example, disposed on the substrate SB, and may be, for example, a conductive layer or a plurality of conductive lines disposed on the substrate SB, but the present invention is not limited thereto. In the present embodiment, the common source line CSL further extends in the normal direction d3 of the substrate SB, and is used to define the memory block 10B of the memory 10. Specifically, the memory 10 of the present embodiment may also include Figure 1A A plurality of memory blocks and a plurality of common source lines are not shown, and the memory blocks are defined by two common source lines adjacent to each other.
[0062] A plurality of vertical channel structures VC are, for example, disposed on the substrate SB and electrically connected to the common source line CSL, wherein each of the plurality of vertical channel structures VC extends, for example, in the normal direction d3 of the substrate SB. In some embodiments, the plurality of vertical channel structures VC are disposed in a memory block 10B defined by two adjacent common source lines. In other words, the plurality of vertical channel structures VC may be disposed between adjacent common source lines.
[0063] One of the plurality of vertical channel structures VC includes a memory cell string 10S, such as Figure 1B In the present embodiment, each of the plurality of vertical channel structures VC may include an insulating column DC, a channel layer CH, and a charge trapping layer CTL, but the present invention is not limited thereto.
[0064] The insulating column DC is, for example, an internal structure of the vertical channel structure VC. In some embodiments, the material of the insulating column DC may include a suitable dielectric material. For example, the material of the insulating column DC may include silicon oxide, but the present invention is not limited thereto.
[0065] The channel layer CH is, for example, disposed around the insulating column DC. In some embodiments, the channel layer CH may include a suitable semiconductor material. For example, the material of the channel layer CH may include polysilicon, but the present invention is not limited thereto.
[0066] The charge capture layer CTL is, for example, disposed around the channel layer CH, which may be, for example, an external structure of the vertical channel structure VC. In some embodiments, the charge capture layer CTL may include a composite structure. In the present embodiment, the charge capture layer CTL may include three dielectric layers stacked in sequence on the side surface of the channel layer CH. For example, the charge capture layer CTL may include a composite layer of oxide-nitride-oxide (ONO), but the present invention is not limited thereto. In other embodiments, the charge capture layer CTL may include a composite layer of oxide-nitride-oxide-nitride-oxide (ONONO) or a composite layer including other structures.
[0067] The word line stack WL is, for example, disposed on a substrate SB. In some embodiments, the word line stack WL may include a plurality of word lines stacked in sequence in a normal direction d3 of the substrate SB, wherein the plurality of word lines may each extend on a plane defined by a first direction d1 and a second direction d2, and the first direction d1 and the second direction d2 are orthogonal to the normal direction d3 of the substrate SB. In detail, the plurality of word lines included in the word line stack WL may each be regarded as a layer of a memory cell page, wherein the memory block 10B includes multiple layers of memory cell pages. In the present embodiment, the word line stack WL includes 96 word lines WL0-WL95, wherein each memory cell in a memory cell string 10S is electrically connected to a corresponding word line, but the present invention is not limited thereto. In some embodiments, the material of the word line stack WL may include a suitable conductive material. For example, the material of the word line stack WL may include tungsten, but the present invention is not limited thereto.
[0068] The pseudo word line stack DWL is, for example, disposed on the substrate SB, and may, for example, include a lower pseudo word line stack DBWL and an upper pseudo word line stack DTWL. In some embodiments, the lower pseudo word line stack DBWL may include a plurality of lower pseudo word lines stacked in sequence in the normal direction d3 of the substrate SB, and the upper pseudo word line stack DTWL may also include a plurality of upper pseudo word lines stacked in sequence in the normal direction d3 of the substrate SB, wherein the plurality of lower pseudo word lines and the plurality of upper pseudo word lines may also each extend on a plane defined by the first direction d1 and the second direction d2. In the present embodiment, the lower pseudo word line stack DBWL includes three lower pseudo word lines DBWL0-DBWL2, and the upper pseudo word line stack DTWL also includes three upper pseudo word lines DTWL0-DTWL2, but the present invention is not limited thereto. In some embodiments, the material of the pseudo word line stack DWL may be the same or similar to the material of the word line stack WL.
[0069] In the present embodiment, the plurality of lower dummy word lines DBWL0-DBWL2 are disposed between the substrate SB and the plurality of word lines WL0-WL95 in the normal direction d3 of the substrate SB. From another perspective, the plurality of word lines WL0-WL95 are disposed between the plurality of lower dummy word lines DBWL0-DBWL2 and the plurality of upper dummy word lines DTWL0-DTWL2 in the normal direction d3 of the substrate SB.
[0070] The serial selection line SSL is, for example, disposed on the substrate SB. In some embodiments, the serial selection line SSL may be disposed on the plurality of upper pseudo word lines DTWL0-DTWL2 in the normal direction d3 of the substrate SB. In some embodiments, the material of the serial selection line SSL may be the same as or similar to the material of the word line stack WL. It is worth noting that although Figure 1A It is shown that the number of the serial selection line SSL included in the memory 10 is 1, but the present invention is not limited thereto.
[0071] The ground selection line GSL is, for example, disposed on the substrate SB. In some embodiments, the ground selection line GSL may be disposed between the plurality of lower dummy word lines DBWL0-DBWL2 and the substrate SB in the normal direction d3 of the substrate SB. In some embodiments, the material of the ground selection line GSL may be the same as or similar to the material of the word line stack WL.
[0072] The plurality of bit lines BL are, for example, disposed on the substrate SB, wherein the plurality of bit lines BL may, for example, each extend in the second direction d2. In some embodiments, the plurality of bit lines BL are disposed on the vertical channel structure VC in the normal direction d3 of the substrate SB. It is worth noting that although Figure 1AThe plurality of bit lines BL in the memory 10 are shown to include four bit lines BL0-BL3, but the present invention is not limited thereto. In addition, in the present embodiment, the corresponding bit lines (e.g., bit lines BL0-BL3) may be electrically connected to the channel layer CH in the corresponding vertical channel structure VC through a conductive structure such as a plug (not shown). Based on this, each memory cell string 10S in the memory block 10B may be electrically connected between the common source line CSL and the corresponding bit line (e.g., bit lines BL0-BL3). In some embodiments, the material of the plurality of bit lines BL may be the same or similar to the material of the word line stack WL.
[0073] The global bit line GBL is, for example, disposed on the substrate SB. In some embodiments, the global bit line GBL may be electrically connected to a plurality of bit lines BL. In this embodiment, the global bit line GBL may be electrically connected to the bit lines BL0-BL3. In some embodiments, the material of the global bit line GBL may be the same as or similar to the material of the word line stack WL.
[0074] Figure 2A as well as Figure 2B The following schematically shows a voltage waveform diagram of a memory device according to an embodiment of the present invention when performing a programming operation. Figure 3 The flowchart of a method for programming a memory according to an embodiment of the present invention is schematically shown. Figure 3 The memory described herein is based on the memory 10 mentioned above as an example, but it should be noted that the present invention is not limited thereto.
[0075] Please also refer to Figure 2A as well as Figure 3 First, the memory 10 of the present embodiment performs a programming operation with multiple programming shots, wherein the memory 10 performs a programming operation with 15 programming shots as an example, but the present invention is not limited thereto. Figure 3 Not shown in the figure, program verification may be performed between two program triggers.
[0076] It is worth noting that although the present embodiment takes the programming operation from the top of the memory 10 to the bottom of the memory 10 (from the word line WL95 to the word line WL0) as an example, the present invention is not limited thereto. That is, in other embodiments, the programming operation may be performed from the bottom of the memory 10 to the top of the memory 10 (from the word line WL0 to the word line WL95).
[0077] In step S10, during the pre-charge phase Tpre, a common source line voltage VCSL_pre is applied to the common source line CSL, wherein the common source line voltage VCSL_pre is applied in an incremental-step-pulse programming (ISPP) manner during the pre-charge phase Tpre of multiple programming triggers. Figure 2A As shown, during the pre-charging stage Tpre1 of the first programming trigger S1, the common source line voltage VCSL_pre1 is applied to the common source line CSL, during the pre-charging stage Tpre2 of the second programming trigger S2, the common source line voltage VCSL_pre2 is applied to the common source line CSL, and during the pre-charging stage Tpre3 of the third programming trigger S3, the common source line voltage VCSL_pre3 is applied to the common source line CSL, wherein the common source line voltage VCSL_pre1 is less than or equal to the common source line voltage VCSL_pre2, and the common source line voltage VCSL_pre2 is less than or equal to the common source line voltage VCSL_pre3 (VCSL_prel≤VCSL_pre2≤VCSL_pre3).
[0078] In this embodiment, the common source line voltage VCSL_pre applied in each pre-charging stage Tpre in 15 programming triggers may be as shown in the following Table 1 and will be described in detail below, but the present invention is not limited thereto.
[0079] [Table 1] Aspects of the common source line voltage applied during the precharge phase
[0080]
[0081]
[0082] In Embodiment 1, the common source line voltage applied in the precharge phase increases between one programming trigger and the subsequent programming trigger, and the common source line voltage increases by the same value between each one programming trigger and the subsequent programming trigger. In detail, the common source line voltage applied in the precharge stage of the first programming trigger (S1) is 1V, the common source line voltage applied in the precharge stage of the second programming trigger (S2) is 1.1V, the common source line voltage applied in the precharge stage of the third programming trigger (S3) is 1.2V, the common source line voltage applied in the precharge stage of the fourth programming trigger (S4) is 1.3V, the common source line voltage applied in the precharge stage of the fifth programming trigger (S5) is 1.4V, the common source line voltage applied in the precharge stage of the sixth programming trigger (S6) is 1.5V, the common source line voltage applied in the precharge stage of the seventh programming trigger (S7) is 1.6V, and the common source line voltage applied in the precharge stage of the eighth programming trigger (S8) is 1.6V. The common source line voltage is 1.7 V, the common source line voltage applied in the precharge stage of the ninth programming trigger (S9) is 1.8 V, the common source line voltage applied in the precharge stage of the tenth programming trigger (S10) is 1.9 V, the common source line voltage applied in the precharge stage of the eleventh programming trigger (S11) is 2.0 V, the common source line voltage applied in the precharge stage of the twelfth programming trigger (S12) is 2.1 V, the common source line voltage applied in the precharge stage of the thirteenth programming trigger (S13) is 2.2 V, the common source line voltage applied in the precharge stage of the fourteenth programming trigger (S14) is 2.3 V, and the common source line voltage applied in the precharge stage of the fifteenth programming trigger (S15) is 2.4 V. In addition, the value of the common source line voltage increased each time between one programming trigger and the subsequent programming trigger is 0.1 V.
[0083] In Embodiment 2, multiple programming triggers include a first period and a second period, the common source line voltage applied in the precharge stage remains unchanged between a programming trigger in the first period and a subsequent programming trigger, and the common source line voltage applied in the precharge stage increases between a programming trigger in the second period and a subsequent programming trigger. In detail, the first period of multiple programming triggers is from the first programming trigger to the tenth programming trigger (S1-S10), wherein the common source line voltage applied in the precharge stage maintains a precharge voltage of 1.0V. The second period of multiple programming triggers is from the tenth programming trigger to the fifteenth programming trigger (S10-S15), wherein the common source line voltage applied in the precharge stage increases between a programming trigger and a subsequent programming trigger, and the value of each increase in the common source line voltage between a programming trigger and a subsequent programming trigger is 0.1V.
[0084] In Embodiment 3, multiple programming triggers include a first period and a second period, the common source line voltage applied in the precharge stage remains unchanged between a programming trigger in the first period and a subsequent programming trigger, and the common source line voltage applied in the precharge stage increases between a programming trigger in the second period and a subsequent programming trigger. In detail, the first period of multiple programming triggers is from the first programming trigger to the tenth programming trigger (S1-S10), wherein the common source line voltage applied in the precharge stage maintains a precharge voltage of 1.0V. The second period of multiple programming triggers is from the tenth programming trigger to the fifteenth programming trigger (S10-S15), wherein the common source line voltage applied in the precharge stage increases between a programming trigger and a subsequent programming trigger, and the value of each increase in the common source line voltage between a programming trigger and a subsequent programming trigger is 0.3V.
[0085] In Embodiment 4, the multiple programming triggers include multiple first periods and multiple second periods, and one of the multiple second periods is arranged between two adjacent multiple first periods. Specifically, the multiple programming triggers include five first periods, which are respectively from the first programming trigger to the third programming trigger (S1-S3), from the fourth programming trigger to the sixth programming trigger (S4-S6), from the seventh programming trigger to the ninth programming trigger (S7-S9), from the tenth programming trigger to the twelfth programming trigger (S10-S12), and from the thirteenth programming trigger to the fifteenth programming trigger (S13-S15), wherein the common source line voltages applied in the precharge stage are respectively maintained at precharge voltages of 1.0V, 1.2V, 1.4V, 1.6V, and 1.8V. In addition, the multiple programming triggers include 4 second periods, which are the third programming trigger to the fourth programming trigger (S3-S4), the sixth programming trigger to the seventh programming trigger (S6-S7), the ninth programming trigger to the tenth programming trigger (S9-S10), and the twelfth programming trigger to the thirteenth programming trigger (S12-S13), respectively, wherein the common source line voltage applied in the pre-charging stage increases between one programming trigger and the subsequent programming trigger, and the value of each increase in the common source line voltage between one programming trigger and the subsequent programming trigger is 0.2V.
[0086] In Embodiment 5, the multiple programming triggers include two first periods and one second period arranged in sequence, and one second period is arranged between the two first periods. Specifically, the programming triggers of the two first periods are respectively the first programming trigger to the tenth programming trigger (S1-S10) and the eleventh programming trigger to the fifteenth programming trigger (S11-S15), wherein the common source line voltage applied in the precharge stage maintains the precharge voltage of 1.0V and 2.4V respectively. In addition, the programming trigger of the second period is the tenth programming trigger to the eleventh programming trigger (S10-S11), wherein the common source line voltage applied in the precharge stage increases between the tenth programming trigger and the eleventh programming trigger, and the value of the common source line voltage increased between the tenth programming trigger and the eleventh programming trigger is 1.4V.
[0087] In this embodiment, by applying the common source line voltage VCSL_pre by using incremental step pulse programming in each precharge stage Tpre of multiple programming triggers, the common source line voltage VCSL_pre with a relatively high voltage level can be applied to the common source line CSL in the last stage of the multiple programming triggers (e.g., the last five programming triggers S11 to S15). Based on this, it can be ensured that the channel level of the unselected memory cell is at a sufficiently large voltage level to avoid the unselected memory cell from generating the FN tunneling effect, thereby reducing the possibility of the memory 10 generating program interference.
[0088] Also, please refer to Figure 2A In the precharge phase Tpre, a ground voltage VSS is applied to the selected word line (in this embodiment, the word line WL24) of each memory cell string. In some embodiments, the ground voltage VSS is applied to the selected word line (in this embodiment, the word line WL24) of each memory cell string in the precharge phase Tpre of multiple programming triggers. Figure 2A The pre-charging stage Tpre1, the pre-charging stage Tpre2 and the pre-charging stage Tpre3 have the same voltage level. In this embodiment, the ground voltage VSS is 0V.
[0089] Please also refer to Figure 2A as well as Figure 3 In step S20, during the programming phase Tpgm, a programming voltage Vpgm is applied to the selected word line, wherein the programming voltage Vpgm is applied in the form of incremental step pulse programming during the programming phase Tpgm of multiple programming triggers. For example, Figure 2AAs shown, in the programming stage Tpgm1 of the first programming trigger S1, the programming voltage Vpgm1 is applied to the selected word line (which is the word line WL24 in this embodiment), in the programming stage Tpgm2 of the second programming trigger S2, the programming voltage Vpgm2 is applied to the selected word line, and in the programming stage Tpgm3 of the third programming trigger S3, the programming voltage Vpgm3 is applied to the selected word line, wherein the programming voltage Vpgm1 is less than or equal to the programming voltage Vpgm2, and the programming voltage Vpgm2 is less than or equal to the programming voltage Vpgm3 (Vpgm1≤Vpgm2≤Vpgm3).
[0090] The present embodiment is not limited to applying the programming voltage Vpgm in the programming phase Tpgm of multiple programming triggers in the form of incremental step pulses. For example, the programming voltage Vpgm applied in the programming phase may increase between one programming trigger and the subsequent programming trigger, and the value of the increase of the programming voltage Vpgm between each programming trigger and the subsequent programming trigger may be the same.
[0091] In the present embodiment, by applying the programming voltage Vpgm by using incremental step pulse programming in each programming stage Tpgm of multiple programming triggers, the programming voltage Vpgm may have a relatively low voltage level during the initial period of the multiple programming triggers (for example, the initial five programming triggers S1 to S5), so that during the initial period of the multiple programming triggers in step S10 (for example, the initial five programming triggers S1 to S5), a common source line voltage VCSL_pre having a relatively low voltage level may be applied to the common source line CSL, which may avoid generating a relatively large horizontal electric field on a specific word line (for example, word line WL24) and inducing hot carrier interference.
[0092] Also, please refer to Figure 2A , the common source line voltage VCSL_pre applied to the common source line CSL in the programming phase Tpgm may be raised to the power supply voltage VDD. For example, the common source line voltage VCSL_pre1 applied to the common source line CSL may be raised to the power supply voltage VDD in the programming phase Tpgm1 of the first programming trigger S1. In some embodiments, the power supply voltage VDD has the same voltage level in each programming phase Tpgm of multiple programming triggers.
[0093] The following will describe voltage waveforms of the lower dummy word line DBWL, the ground selection line GSL, the string selection line SSL, and the bit line BL when performing a programming operation according to an embodiment of the present invention.
[0094] Please refer to Figure 2B, in each precharge stage (including precharge stage Tpre1, precharge stage Tpre2 and precharge stage Tpre3), the precharge voltage VPASS_pre is applied to the lower pseudo word line DBWL. In detail, in each precharge stage, the voltage level of the lower pseudo word line DBWL may increase from the ground voltage VSS to the precharge voltage VPASS_pre, and then decrease from the precharge voltage VPASS_pre to the ground voltage VSS. Thereafter, in each programming stage (including programming stage Tpgm1, programming stage Tpgm2 and programming stage Tpgm3), the voltage level of the lower pseudo word line DBWL may increase from the ground voltage VSS to the pass voltage VDBWL, and then decrease from the pass voltage VDBWL to the ground voltage VSS.
[0095] Please refer to Figure 2B , in each precharge stage (including precharge stage Tpre1, precharge stage Tpre2, and precharge stage Tpre3), the precharge voltage VPASS_pre is applied to the ground selection line GSL. In detail, in each precharge stage, the voltage level of the ground selection line GSL may increase from the ground voltage VSS to the precharge voltage VPASS_pre, and then decrease from the precharge voltage VPASS_pre to the ground voltage VSS. Thereafter, in each programming stage (including programming stage Tpgm1, programming stage Tpgm2, and programming stage Tpgm3), the voltage level of the ground selection line GSL is maintained at the ground voltage VSS.
[0096] Please refer to Figure 2B , in each precharge stage (including precharge stage Tpre1, precharge stage Tpre2 and precharge stage Tpre3), the ground voltage VSS is applied to the serial selection line SSL. Thereafter, in each programming stage (including programming stage Tpgm1, programming stage Tpgm2 and programming stage Tpgm3), the serial selection line voltage VSSL is applied to the serial selection line SSL. In detail, the voltage level of the serial selection line SSL may increase from the ground voltage VSS to the serial selection line voltage VSSL, and then decrease from the serial selection line voltage VSSL to the ground voltage VSS. In the present embodiment, the serial selection line voltage VSSL is 3.6V, but the present invention is not limited thereto.
[0097] Please refer to Figure 2BIn each precharge stage (including precharge stage Tpre1, precharge stage Tpre2 and precharge stage Tpre3), the ground voltage VSS is applied to the programming bit line (BL0 in this embodiment). Thereafter, in each programming stage (including programming stage Tpgm1, programming stage Tpgm2 and programming stage Tpgm3), the bit line voltage VBL_pgm for programming the selected memory cell is applied to the programming bit line. In this embodiment, the bit line voltage VBL_pgm for programming the selected memory cell is 0V, but the present invention is not limited thereto.
[0098] Please refer to Figure 2B , in each precharge stage (including precharge stage Tpre1, precharge stage Tpre2 and precharge stage Tpre3), the bit line voltage VBL_inhibit for inhibiting the unselected memory cells from being programmed is applied to the inhibiting bit line (BL1 in this embodiment). In detail, in each precharge stage, the voltage level of the inhibiting bit line can be increased from the ground voltage VSS to the bit line voltage VBL_inhibit for inhibiting the unselected memory cells from being programmed, and the bit line voltage VBL_inhibit is maintained. Thereafter, in each programming stage (including programming stage Tpgm1, programming stage Tpgm2 and programming stage Tpgm3), the voltage level of the inhibiting bit line is reduced from the bit line voltage VBL_inhibit to the ground voltage VSS. In this embodiment, the bit line voltage VBL_inhibit for inhibiting the unselected memory cells from being programmed is the power supply voltage VDD, but the present invention is not limited thereto.
[0099] Please refer to Figure 2B , in each precharge stage (including precharge stage Tpre1, precharge stage Tpre2 and precharge stage Tpre3), the ground voltage VSS is applied to the quick pass write (QPW) bit line (BL2 in this embodiment). Thereafter, in each programming stage (including programming stage Tpgm1, programming stage Tpgm2 and programming stage Tpgm3), the bit line voltage VBL_QPW for quick pass writing the memory cell is applied to the quick pass writing bit line. In detail, the voltage level of the quick pass writing bit line may be increased from the ground voltage VSS to the bit line voltage VBL_QPW, and then decreased from the bit line voltage VBL_QPW to the ground voltage VSS.
[0100] Figure 4A The diagram schematically shows a schematic diagram of applying voltages to a ground selection line GSL, a plurality of lower dummy word lines DBWL0 - DBWL2 , a common source line CSL and a serial selection line SSL during a precharge phase of a one-time programming trigger according to an embodiment of the present invention.
[0101] Please refer to Figure 4A For the ground selection line GSL and the multiple lower pseudo word lines DBWL0-DBWL2, the precharge voltage VPASS_pre is applied to the ground selection line GSL and the multiple lower pseudo word lines DBWL0-DBWL2 in the precharge stage, so that the ground selection gate (not shown) coupled to the ground selection line GSL and the pseudo gate (not shown) coupled to the lower pseudo word lines DBWL0-DBWL2 can be opened. For the common source line CSL, the common source line voltage VCSL_pre is applied to the common source line CSL by using incremental step pulse programming in the precharge stage. Since the above-mentioned ground selection gate is turned on, the voltage level of the channel layer CH can be increased due to the application of the common source line voltage VCSL_pre. For the serial selection line SSL, the ground voltage VSS is applied to the serial selection line SSL in the precharge stage, so that the serial selection gate (not shown) coupled to the serial selection line SSL can be turned off and is in a closed state.
[0102] Figure 4B , Figure 4C as well as Figure 4D The schematic diagram shows a schematic diagram of applying voltage to the ground selection line GSL, the serial selection line SSL, the common source line CSL, the selected word line, the unselected word line and the bit lines BL0-BL2 during the programming stage of a one-time programming trigger according to an embodiment of the present invention, wherein Figure 4B The bit line BL0 in the program bit line is Figure 4C The bit line BL1 in the Figure 4D The bit line BL2 in is a fast-pass programming bit line.
[0103] Please refer to Figure 4B, for the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL in the programming phase, so that the ground selection gate coupled to the ground selection line GSL can be closed and in a closed state. For the serial selection line SSL, the serial selection line voltage VSSL is applied to the serial selection line SSL in the programming phase, so that the serial selection gate coupled to the serial selection line SSL can be turned on. For the common source line CSL, the power supply voltage VDD is applied to the common source line CSL in the programming phase. For the selected word line (in this embodiment, the word line WL24) and the unselected word lines (including the lower pseudo word lines DBWL0-DBWL2), the programming voltage Vpgm is applied to the selected word line by using incremental step pulse programming in the programming phase, and the pass voltage VDBWL is applied to the unselected word line in the programming phase. For the programming bit line (in this embodiment, the bit line BL0), the bit line voltage VBL_pgm is applied to the programming bit line in the programming phase to perform a programming operation. In detail, when a programming voltage Vpgm is applied to a selected word line, electrons can be tunneled from the channel layer CH to the charge trapping layer CTL (shown in FIG. 1 ) by a relatively high voltage difference between the programming voltage Vpgm and the bit line voltage VBL_pgm. Figure 1B ) and was captured by it.
[0104] Please refer to Figure 4C , for the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL in the programming phase. For the serial selection line SSL, the serial selection line voltage VSSL is applied to the serial selection line SSL in the programming phase. For the common source line CSL, the power supply voltage VDD is applied to the common source line CSL in the programming phase. For the selected word line (in this embodiment, the word line WL24) and the unselected word lines (including the lower pseudo word lines DBWL0-DBWL2), the programming voltage Vpgm is applied to the selected word line by using incremental step pulse programming in the programming phase, and the pass voltage VDBWL is applied to the unselected word lines in the programming phase. For the inhibited bit line (in this embodiment, the bit line BL1), the voltage level of the inhibited bit line in the programming phase is maintained at the bit line voltage VBL_inhibit, wherein the bit line voltage VBL_inhibit can be the power supply voltage VDD to increase the voltage level of the channel layer CH, thereby performing a programming inhibition operation.
[0105] Please refer to Figure 4D, for the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL in the programming phase. For the serial selection line SSL, the serial selection line voltage VSSL is applied to the serial selection line SSL in the programming phase. For the common source line CSL, the power supply voltage VDD is applied to the common source line CSL in the programming phase. For the selected word line (in this embodiment, the word line WL24) and the unselected word lines (including the lower pseudo word lines DBWL0-DBWL2), the programming voltage Vpgm is applied to the selected word line in the programming phase by using incremental step pulse programming, and the pass voltage VDBWL is applied to the unselected word line in the programming phase. For the fast pass programming bit line (in this embodiment, the bit line BL2), the bit line voltage VBL_QPW is applied to the fast pass programming bit line in the programming phase to perform a fast pass programming operation.
[0106] It is worth noting that, although the memory 10 of the present embodiment takes a three-dimensional memory as an example, the method for programming a memory of the present invention can be applied to a two-dimensional memory (e.g., a two-dimensional NAND flash memory). In addition, the method for programming a memory of the present invention can be applied to a memory cell including a single-level cell (SLC), a double-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).
[0107] Figure 5A as well as Figure 5B The following schematically shows a voltage waveform diagram of a memory device according to another embodiment of the present invention when performing a programming operation. Figure 6 A flowchart of a method for programming a memory according to another embodiment of the present invention is schematically shown, wherein Figure 6 The memory described herein is based on the memory 10 mentioned above as an example, but it should be noted that the present invention is not limited thereto.
[0108] Please also refer to Figure 5A as well as Figure 6 First, the memory 10 of the present embodiment performs a programming operation with multiple programming shots, wherein the memory 10 performs a programming operation with 15 programming shots as an example, but the present invention is not limited thereto. Figure 6 Not shown in the figure, program verification may be performed between two program triggers.
[0109] It is worth noting that although the present embodiment performs the programming operation from the bottom of the memory 10 to the top of the memory 10 (in the order from the word line WL0 to the word line WL95 ), the present invention is not limited thereto.
[0110] In step S10', during the precharge phase Tpre, a bit line voltage VBL_pre is applied to the bit line BL, wherein the bit line voltage VBL_pre is applied in an incremental-step-pulse programming (ISPP) manner during the precharge phase Tpre of multiple programming triggers. In this embodiment, the bit line BL includes a programming bit line (BL0), an inhibiting bit line (BL1), and a fast passing programming bit line (BL2). For example, Figure 5A As shown, during the pre-charging stage Tpre1 of the first programming trigger S1, the bit line voltage VBL_pre1 is applied to the bit line BL, during the pre-charging stage Tpre2 of the second programming trigger S2, the bit line voltage VBL_pre2 is applied to the bit line BL, and during the pre-charging stage Tpre3 of the third programming trigger S3, the bit line voltage VBL_pre3 is applied to the bit line BL, wherein the bit line voltage VBL_pre1 is less than or equal to the bit line voltage VBL_pre2, and the bit line voltage VBL_pre2 is less than or equal to the bit line voltage VBL_pre3 (VBL_pre1≤VBL_pre2≤VBL_pre3).
[0111] Please refer to Figure 5A , after the bit line voltage VBL_pre is applied, the voltage level of the programming bit line (BL0) in each precharge phase Tpre can be reduced from the bit line voltage VBL_pre to the ground voltage VSS, the voltage level of the inhibition bit line (BL1) in each precharge phase Tpre can be maintained at the bit line voltage VBL_pre, and the voltage level of the fast passing programming bit line (BL2) in each precharge phase Tpre can be reduced from the bit line voltage VBL_pre to the ground voltage VSS.
[0112] In this embodiment, the bit line voltage VBL_pre applied in each pre-charging stage Tpre in 15 programming triggers may be as shown in Table 2 below and will be described in detail below, but the present invention is not limited thereto.
[0113] [Table 2] Aspects of bit line voltage applied during precharge phase
[0114] Programming trigger Example 6 Example 7 Example 8 Example 9 Example 10 first 1V 1V 1V 1V 1V Second time 1.1V 1V 1V 1V 1V The third time 1.2V 1V 1V 1V 1V Fourth 1.3V 1V 1V 1.2V 1V Fifth 1.4V 1V 1V 1.2V 1V Sixth 1.5V 1V 1V 1.2V 1V Seventh 1.6V 1V 1V 1.4V 1V Eighth 1.7V 1V 1V 1.4V 1V Ninth 1.8V 1V 1V 1.4V 1V The tenth time 1.9V 1V 1V 1.6V 1V Eleventh 2.0V 1.1V 1.3V 1.6V 2.4V Twelfth 2.1V 1.2V 1.6V 1.6V 2.4V Thirteenth 2.2V 1.3V 1.9V 1.8V 2.4V Fourteenth 2.3V 1.4V 2.2V 1.8V 2.4V The fifteenth 2.4V 1.5V 2.5V 1.8V 2.4V
[0115] In Embodiment 6, the bit line voltage applied in the precharge stage increases between a programming trigger and a subsequent programming trigger, and the bit line voltage increases by the same value between each programming trigger and the subsequent programming trigger. Specifically, the bit line voltage applied in the precharge stage of the first programming trigger (S1) is 1V, the bit line voltage applied in the precharge stage of the second programming trigger (S2) is 1.1V, the bit line voltage applied in the precharge stage of the third programming trigger (S3) is 1.2V, the bit line voltage applied in the precharge stage of the fourth programming trigger (S4) is 1.3V, the bit line voltage applied in the precharge stage of the fifth programming trigger (S5) is 1.4V, the bit line voltage applied in the precharge stage of the sixth programming trigger (S6) is 1.5V, the bit line voltage applied in the precharge stage of the seventh programming trigger (S7) is 1.6V, and the bit line voltage applied in the precharge stage of the eighth programming trigger (S8) is 1.2V. The bit line voltage applied in the precharge stage of the ninth programming trigger (S9) is 1.7V, the bit line voltage applied in the precharge stage of the tenth programming trigger (S10) is 1.9V, the bit line voltage applied in the precharge stage of the eleventh programming trigger (S11) is 2.0V, the bit line voltage applied in the precharge stage of the twelfth programming trigger (S12) is 2.1V, the bit line voltage applied in the precharge stage of the thirteenth programming trigger (S13) is 2.2V, the bit line voltage applied in the precharge stage of the fourteenth programming trigger (S14) is 2.3V, and the bit line voltage applied in the precharge stage of the fifteenth programming trigger (S15) is 2.4V. In addition, the value of each increase in the bit line voltage between one programming trigger and the subsequent programming trigger is 0.1V.
[0116] In Embodiment 7, multiple programming triggers include a first period and a second period, the bit line voltage applied in the precharge stage remains unchanged between a programming trigger in the first period and a subsequent programming trigger, and the bit line voltage applied in the precharge stage increases between a programming trigger in the second period and a subsequent programming trigger. Specifically, the first period of multiple programming triggers is from the first programming trigger to the tenth programming trigger (S1-S10), wherein the bit line voltage applied in the precharge stage maintains a precharge voltage of 1.0V. The second period of multiple programming triggers is from the tenth programming trigger to the fifteenth programming trigger (S10-S15), wherein the bit line voltage applied in the precharge stage increases between a programming trigger and a subsequent programming trigger, and the value of each increase in the bit line voltage between a programming trigger and a subsequent programming trigger is 0.1V.
[0117] In Embodiment 8, multiple programming triggers include a first period and a second period, the bit line voltage applied in the precharge stage remains unchanged between a programming trigger in the first period and a subsequent programming trigger, and the bit line voltage applied in the precharge stage increases between a programming trigger in the second period and a subsequent programming trigger. Specifically, the first period of multiple programming triggers is from the first programming trigger to the tenth programming trigger (S1-S10), wherein the bit line voltage applied in the precharge stage maintains a precharge voltage of 1.0V. The second period of multiple programming triggers is from the tenth programming trigger to the fifteenth programming trigger (S10-S15), wherein the bit line voltage applied in the precharge stage increases between a programming trigger and a subsequent programming trigger, and the value of each increase in the bit line voltage between a programming trigger and a subsequent programming trigger is 0.3V.
[0118] In Embodiment 9, the multiple programming triggers include multiple first periods and multiple second periods, and one of the multiple second periods is arranged between two adjacent multiple first periods. Specifically, the multiple programming triggers include five first periods, which are respectively from the first programming trigger to the third programming trigger (S1-S3), from the fourth programming trigger to the sixth programming trigger (S4-S6), from the seventh programming trigger to the ninth programming trigger (S7-S9), from the tenth programming trigger to the twelfth programming trigger (S10-S12), and from the thirteenth programming trigger to the fifteenth programming trigger (S13-S15), wherein the bit line voltages applied in the precharge stage are respectively maintained at precharge voltages of 1.0V, 1.2V, 1.4V, 1.6V, and 1.8V. In addition, the multiple programming triggers include 4 second periods, which are the third programming trigger to the fourth programming trigger (S3-S4), the sixth programming trigger to the seventh programming trigger (S6-S7), the ninth programming trigger to the tenth programming trigger (S9-S10), and the twelfth programming trigger to the thirteenth programming trigger (S12-S13), respectively, wherein the bit line voltage applied in the precharge stage increases between one programming trigger and the subsequent programming trigger, and the value of each increase in the bit line voltage between one programming trigger and the subsequent programming trigger is 0.2V.
[0119] In Embodiment 10, the multiple programming triggers include two first periods and one second period arranged in sequence, and the second period is arranged between the two first periods. Specifically, the programming triggers of the two first periods are respectively the first programming trigger to the tenth programming trigger (S1-S10) and the eleventh programming trigger to the fifteenth programming trigger (S11-S15), wherein the bit line voltages applied in the precharge stage are respectively maintained at the precharge voltages of 1.0V and 2.4V. In addition, the programming triggers of the second period are the tenth programming trigger to the eleventh programming trigger (S10-S11), wherein the bit line voltage applied in the precharge stage increases between the tenth programming trigger and the eleventh programming trigger, and the value of the bit line voltage increased between the tenth programming trigger and the eleventh programming trigger is 1.4V.
[0120] In this embodiment, by applying the bit line voltage VBL_pre using an incremental step pulse program in each precharge stage Tpre of multiple programming triggers, the bit line voltage VBL_pre having a relatively high voltage level can be applied to the bit line BL in the last stage (e.g., the last five programming triggers S11 to S15) of the multiple programming triggers. Based on this, it can be ensured that the channel level of the unselected memory cell is at a sufficiently large voltage level to avoid the unselected memory cell from generating the FN tunneling effect, thereby reducing the possibility of the memory 10 generating program disturbance.
[0121] Also, please refer to Figure 5A , a ground voltage VSS is applied to a selected word line (in this embodiment, word line WL24) of each memory cell string in the precharge phase Tpre. In some embodiments, the ground voltage VSS has the same voltage level in each precharge phase Tpre of multiple programming triggers. In this embodiment, the ground voltage VSS is 0V.
[0122] Please also refer to Figure 5A as well as Figure 6 In step S20, during the programming phase Tpgm, a programming voltage Vpgm is applied to the selected word line, wherein the programming voltage Vpgm is applied in the form of incremental step pulse programming during the programming phase Tpgm of multiple programming triggers, which has been described in detail in the above-mentioned embodiments and will not be repeated here.
[0123] In the present embodiment, by applying the programming voltage Vpgm by using incremental step pulse programming in each programming stage Tpgm of multiple programming triggers, the programming voltage Vpgm may have a relatively low voltage level during the initial period of the multiple programming triggers (e.g., the first five programming triggers S1 to S5), so that a bit line voltage VBL_pre having a relatively low voltage level may be applied to the bit line BL during the initial period of the multiple programming triggers in step S10', which may avoid generating a relatively large horizontal electric field on a specific word line (e.g., word line WL24) and inducing hot carrier interference.
[0124] Also, please refer to Figure 5A , a bit line voltage VBL_pgm for programming the selected memory cell is applied to the programming bit line (BL0) in each programming phase Tpgm. In the present embodiment, the bit line voltage VBL_pgm is 0V, but the present disclosure is not limited thereto. The voltage level of the suppression bit line (BL1) is first increased from the bit line voltage VBL_pre to the power supply voltage VDD in each programming phase Tpgm, and then decreased from the power supply voltage VDD to the ground voltage VSS. The voltage level of the fast-through programming bit line (BL2) is first increased from the ground voltage VSS to the bit line voltage VBL_QPW for fast-through programming the memory cell in each programming phase Tpgm, and then decreased from the bit line voltage VBL_QPW to the ground voltage VSS.
[0125] The following will describe voltage waveforms of the upper dummy word line DTWL, the ground selection line GSL, the string selection line SSL, and the common source line CSL when performing a programming operation according to an embodiment of the present invention.
[0126] Please refer to Figure 5B , in each precharge stage (including precharge stage Tpre1, precharge stage Tpre2 and precharge stage Tpre3), the precharge voltage VPASS_pre is applied to the upper pseudo word line DTWL. In detail, in each precharge stage, the voltage level of the upper pseudo word line DTWL may increase from the ground voltage VSS to the precharge voltage VPASS_pre, and then decrease from the precharge voltage VPASS_pre to the ground voltage VSS. Thereafter, in each programming stage (including programming stage Tpgm1, programming stage Tpgm2 and programming stage Tpgm3), the voltage level of the upper pseudo word line DTWL may increase from the ground voltage VSS to the pass voltage VDTWL, and then decrease from the pass voltage VDTWL to the ground voltage VSS.
[0127] Please refer to Figure 5BIn each precharge phase (including precharge phase Tpre1, precharge phase Tpre2 and precharge phase Tpre3), the ground voltage VSS is applied to the ground selection line GSL. Thereafter, in each programming phase (including programming phase Tpgm1, programming phase Tpgm2 and programming phase Tpgm3), the voltage level of the ground selection line GSL is maintained at the ground voltage VSS.
[0128] Please refer to Figure 5B , in each precharge stage (including precharge stage Tpre1, precharge stage Tpre2 and precharge stage Tpre3), the precharge voltage VPASS_pre is applied to the serial selection line SSL. In detail, in each precharge stage, the voltage level of the serial selection line SSL may increase from the ground voltage VSS to the precharge voltage VPASS_pre, and then decrease from the precharge voltage VPASS_pre to the ground voltage VSS. Thereafter, in each programming stage (including programming stage Tpgm1, programming stage Tpgm2 and programming stage Tpgm3), the serial selection line voltage VSSL is applied to the serial selection line SSL. In detail, the voltage level of the serial selection line SSL may increase from the ground voltage VSS to the serial selection line voltage VSSL, and then decrease from the serial selection line voltage VSSL to the ground voltage VSS. In the present embodiment, the serial selection line voltage VSSL is 3.6V, but the present invention is not limited thereto.
[0129] Please refer to Figure 5B , in each precharge stage (including precharge stage Tpre1, precharge stage Tpre2 and precharge stage Tpre3), the common source line voltage VCSL is applied to the common source line CSL. In detail, in each precharge stage, the voltage level of the common source line CSL can be increased from the ground voltage VSS to the common source line voltage VCSL. In the present embodiment, the common source line voltage VCSL is the power supply voltage VDD, but the present invention is not limited thereto. Thereafter, in each programming stage (including programming stage Tpgm1, programming stage Tpgm2 and programming stage Tpgm3), the voltage level of the common source line CSL is maintained at the common source line voltage VCSL, and then is reduced from the common source line voltage VCSL to the ground voltage VSS.
[0130] Fig. 7A The diagram schematically shows a schematic diagram of applying voltages to the serial selection line SSL, a plurality of upper dummy word lines DTWL0 - DTWL2 , a bit line BL, a ground selection line GSL and a common source line CSL during a precharge phase of a one-time programming trigger according to another embodiment of the present invention.
[0131] Please refer to Fig. 7AFor the serial selection line SSL and the plurality of upper pseudo word lines DTWL0-DTWL2, the precharge voltage VPASS_pre is applied to the serial selection line SSL and the plurality of upper pseudo word lines DTWL0-DTWL2 in the precharge phase, so that the serial selection gate (not shown) coupled to the serial selection line SSL and the pseudo gate (not shown) coupled to the upper pseudo word lines DTWL0-DTWL2 can be turned on. For the bit line BL, the bit line voltage VBL_pre is applied to the bit line BL by programming with an incremental step pulse in the precharge phase. Since the serial selection gate is turned on, the voltage level of the channel layer CH can be increased due to the application of the bit line voltage VBL_pre. For the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL in the precharge phase, so that the ground selection gate (not shown) coupled to the ground selection line GSL can be turned off and is in a closed state. For the common source line CSL, the power supply voltage VDD can be applied to the common source line CSL in the precharge phase.
[0132] Figure 7B , Figure 7C as well as Fig.7D A schematic diagram schematically shows a schematic diagram of applying voltages to a ground selection line GSL, a serial selection line SSL, a common source line CSL, a selected word line, an unselected word line, and bit lines BL0-BL2 during a programming phase of a one-time programming trigger according to another embodiment of the present invention, wherein Figure 7B The bit line BL0 in the program bit line is Figure 7C The bit line BL1 in the Fig.7D The bit line BL2 in is a fast-pass programming bit line.
[0133] Please refer to Figure 7B , for the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL during the programming phase. For the serial selection line SSL, the serial selection line voltage VSSL is applied to the serial selection line SSL during the programming phase. For the common source line CSL, the voltage level of the common source line CSL is maintained at the power supply voltage VDD during the programming phase. For the selected word line (in this embodiment, the word line WL24) and the unselected word lines (including the upper pseudo word lines DTWL0-DTWL2), the programming voltage Vpgm is applied to the selected word line during the programming phase by using incremental step pulse programming, and the pass voltage VDTWL is applied to the unselected word lines during the programming phase. For the programming bit line (BL0), the bit line voltage VBL_pgm is applied to the programming bit line (BL0) during the programming phase to perform a programming operation. In detail, when a programming voltage Vpgm is applied to a selected word line, electrons can be tunneled from the channel layer CH to the charge trapping layer CTL (shown in FIG. 1 ) by a relatively high voltage difference between the programming voltage Vpgm and the bit line voltage VBL_pgm. Figure 1B) and was captured by it.
[0134] Please refer to Figure 7C , for the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL in the programming phase. For the serial selection line SSL, the serial selection line voltage VSSL is applied to the serial selection line SSL in the programming phase. For the common source line CSL, the voltage level of the common source line CSL is maintained at the power supply voltage VDD in the programming phase. For the selected word line (in this embodiment, the word line WL24) and the unselected word lines (including the upper pseudo word lines DTWL0-DTWL2), the programming voltage Vpgm is applied to the selected word line by using incremental step pulse programming in the programming phase, and the pass voltage VDTWL is applied to the unselected word line in the programming phase. For the inhibited bit line (BL1), the voltage level of the inhibited bit line (BL1) in the programming phase is maintained at the bit line voltage VBL_inhibit, wherein the bit line voltage VBL_inhibit can be the power supply voltage VDD to increase the voltage level of the channel layer CH, thereby performing a programming inhibition operation.
[0135] Please refer to Fig.7D , for the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL in the programming phase. For the serial selection line SSL, the serial selection line voltage VSSL is applied to the serial selection line SSL in the programming phase. For the common source line CSL, the voltage level of the common source line CSL is maintained at the power supply voltage VDD in the programming phase. For the selected word line (in this embodiment, the word line WL24) and the unselected word lines (including the upper pseudo word lines DTWL0-DTWL2), the programming voltage Vpgm is applied to the selected word line by using incremental step pulse programming in the programming phase, and the pass voltage VDTWL is applied to the unselected word line in the programming phase. For the fast pass programming bit line (BL2), the bit line voltage VBL_QPW is applied to the fast pass programming bit line (BL2) in the programming phase to perform a fast pass programming operation.
[0136] It is worth noting that, although the memory 10 of the present embodiment takes a three-dimensional memory as an example, the method for programming a memory of the present invention can be applied to a two-dimensional memory (e.g., a two-dimensional NAND flash memory). In addition, the method for programming a memory of the present invention can be applied to a memory cell including a single-level cell (SLC), a double-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).
[0137] Figure 8The block diagram schematically shows a memory system according to an embodiment of the present invention.
[0138] Please refer to Figure 8 , the memory system 1000 of this embodiment includes a memory device 100 and a controller 200 .
[0139] The memory device 100 may include at least the memory 10 of the aforementioned embodiment, but the present invention is not limited thereto. That is, the memory device 100 may include a two-dimensional memory or other three-dimensional memory. It is intended to be explained that: Figure 8 The schematic diagram is only a simplified block diagram. A person skilled in the art can appropriately design electronic components such as an address decoder, a voltage generator, a page buffer, a control logic and other functions in the memory device 100 based on the concept of the present invention.
[0140] The controller 200 is, for example, coupled to the memory device 100. The controller 200 may receive commands from a host device (not shown) to control the memory device 100. For example, the controller 200 may be used to issue a program command to the memory device 100 to perform a programming operation on the memory 10 in the memory device 100, but the present invention is not limited thereto. In other embodiments, the controller 200 may also be used to issue a read command or an erase command to the memory device 100.
[0141] In summary, the method for programming a memory of the present invention applies a common source line voltage to the common source line in a manner of incremental step pulse programming during multiple pre-charging stages, and can apply a common source line voltage with a relatively low voltage level during the initial period of multiple programming triggers (for example, the initial five programming triggers S1 to S5), which can avoid generating a relatively large horizontal electric field on a specific word line (for example, a selected word line) to induce hot carrier interference.
[0142] Furthermore, by applying a common source line voltage to the common source line in the above-mentioned incremental step pulse programming method, a common source line voltage with a relatively high voltage level can be applied during the last period of multiple programming triggers (for example, the last five programming triggers S11 to S15), thereby ensuring that the channel level of the unselected memory cells is at a sufficiently large voltage level to avoid the unselected memory cells from generating an FN tunneling effect, thereby reducing the possibility of programming interference in the memory of the present invention.
Claims
1. A method for programming a memory, comprising executing a plurality of programming triggers, wherein each programming trigger comprises a precharge phase and a programming phase, and comprising the following steps: During the precharge phase, applying a common source line voltage to the common source line, wherein the common source line voltage or the bit line voltage is applied by using incremental step pulse programming (ISPP) in a plurality of precharge phases; and During the programming phase, a program voltage is applied to a selected word line, wherein the program voltage is applied by using incremental step pulse programming (ISPP) in a plurality of programming phases.
2. The method for programming a memory according to claim 1 , wherein the common source line voltage applied in the precharge phase increases between a one-time programming trigger and a subsequent programming trigger, and the common source line voltage increases by the same value each time between the one-time programming trigger and the subsequent programming trigger.
3. The method for programming a memory according to claim 1, wherein the multiple programming triggers include a first period and a second period, the common source line voltage applied in the precharge stage remains unchanged between a programming trigger and a subsequent programming trigger in the first period, and the common source line voltage applied in the precharge stage increases between a programming trigger and a subsequent programming trigger in the second period.
4. The method for programming a memory according to claim 3, wherein the plurality of programming triggers include one first period and one second period arranged in sequence, and the common source line voltage increases by the same value between each programming trigger and the subsequent programming trigger in the second period. 5 . The method for programming a memory according to claim 3 , wherein the plurality of programming triggers comprises a plurality of the first periods and a plurality of the second periods, and one of the plurality of second periods is arranged between two adjacent ones of the plurality of first periods. 6 . The method for programming a memory according to claim 3 , wherein the plurality of programming triggers include two first periods and one second period arranged in sequence, and the one second period is arranged between the two first periods. 7 . The method for programming a memory according to claim 1 , further comprising applying a precharge voltage to a ground selection line and a plurality of lower dummy word lines during the precharge phase. 8 . The method for programming a memory according to claim 1 , further comprising applying a ground voltage to a string selection line during the precharge phase to turn off a string selection gate coupled to the string selection line.
9. The method for programming a memory according to claim 1, further comprising performing a fast-pass programming operation in the multiple programming triggers.
10. The method for programming a memory according to claim 1, wherein the memory comprises a memory cell of a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).
11. A method for programming a memory, comprising executing a plurality of programming triggers, wherein each programming trigger comprises a precharge phase and a programming phase, and comprising the following steps: During the precharge phase, applying a bit line voltage to the bit line, wherein the bit line voltage is applied in a manner of incremental step pulse programming in a plurality of the precharge phases; as well as During the programming phase, a programming voltage is applied to the selected word line, wherein the programming voltage is applied in a manner of incremental step pulse programming in a plurality of the programming phases.
12. The method for programming a memory according to claim 11, wherein the bit line voltage applied in the precharge phase increases between a programming trigger and a subsequent programming trigger, and the bit line voltage increases by the same value each time between the first programming trigger and the subsequent programming trigger.
13. The method for programming a memory according to claim 11, wherein the multiple programming triggers include a first period and a second period, the bit line voltage applied in the precharge phase remains unchanged between a programming trigger and a subsequent programming trigger in the first period, and the bit line voltage applied in the precharge phase increases between a programming trigger and a subsequent programming trigger in the second period.
14. The method for programming a memory according to claim 13, wherein the plurality of programming triggers include one first period and one second period arranged in sequence, and the bit line voltage increases by the same value between each programming trigger and the subsequent programming trigger in the second period. 15 . The method for programming a memory according to claim 13 , wherein the plurality of programming triggers comprises a plurality of the first periods and a plurality of the second periods, and one of the plurality of second periods is arranged between two adjacent ones of the plurality of first periods. 16 . The method for programming a memory according to claim 13 , wherein the plurality of programming triggers include two first periods and one second period arranged in sequence, and the one second period is arranged between the two first periods. 17 . The method for programming a memory according to claim 11 , further comprising applying a precharge voltage to a string selection line and a plurality of upper dummy word lines during the precharge phase. 18 . The method for programming a memory according to claim 11 , further comprising applying a ground voltage to a ground selection line during the precharge phase, so that a ground selection gate coupled to the ground selection line is in a closed state.
19. The method of programming a memory according to claim 11, further comprising performing a fast-pass programming operation in the multiple programming triggers.
20. The method for programming a memory according to claim 11, wherein the memory comprises a memory cell of a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).