Chip module packaging structure and forming method of chip cavity thereof
By providing through holes on the second carrier and forming a chip cavity, the problem of low reliability or high cost in the cavity formation method in the chip module packaging structure in the prior art is solved, and the cost reduction and reliability improvement are achieved Sexual effect.
Patent Information
- Application Number
- CN202411694951.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-25
- Publication Date
- 2025-02-21
AI Technical Summary
In the prior art, the method used to form a chip cavity in the chip module packaging structure has problems such as low reliability or high cost, and it is difficult to simultaneously improve the reliability and reduce costs of the surface acoustic filter module packaging.
By providing a through hole on the second carrier, the first insulating layer, the second carrier and the second insulating layer are sequentially combined, a chip cavity is formed, and the first line layer and the second line are connected through the electroplating through holes. The first carrier is removed and the insulating layer is packaged to obtain a chip module package structure with a chip cavity.
It effectively reduces the cost of chip module packaging, while improving the reliability of the packaging, ensuring that the filter chip is placed in the chip cavity.
Smart Images
Figure CN119496476A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip technology, and in particular to a chip module packaging structure and a method for forming a chip cavity thereof. Background Art
[0002] The RF front-end module is mainly composed of switches, multiplexers, power amplifiers, low-noise amplifiers and filters, among which the filter is the core of the entire module package and the most valuable device in the module package. Currently, surface acoustic wave filters (SAW) and bulk acoustic wave filters (BOW) are widely used. Among them, SAW focuses on the mid-to-low-end market, and BOW focuses on the high-end market. The characteristic of the surface acoustic wave filter (SAW) is to use the piezoelectric properties of piezoelectric materials and use input and output transducers to convert the input signal of the radio wave into mechanical energy.
[0003] In the prior art, in order to better transmit signals, a cavity is usually formed on the surface of the chip. At present, taking the filter chip as an example, the cavity on the chip surface is mainly realized by the following two methods: 1. A cavity structure is formed inside the filter wafer by using a wall film and a top film. This method can be directly used for RF modular packaging, but it has the disadvantages of complex manufacturing process and high cost; 2. During the modular packaging process, a cavity is formed on the surface of the filter chip by coating. Although this method can effectively reduce costs, the film is prone to breakage at the sharp edges and corners of the chip during the manufacturing process, which reduces the reliability of this method.
[0004] Therefore, how to provide a chip surface cavity formation method applied to a chip module packaging structure so as to improve the reliability of the surface acoustic wave filter module packaging while reducing the cost has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the invention
[0005] In view of the problem of low reliability or high cost in the method for forming a chip cavity in a chip module packaging structure in the prior art, an object of the present invention is to provide a chip module packaging structure and a method for forming a chip cavity thereof, so as to at least partially solve the above problems.
[0006] To achieve the above object, the technical solution of the present invention is: In a first aspect, the present invention provides a method for forming a chip cavity in a chip module packaging structure, the method comprising the following steps: Providing a first carrier and bonding a first insulating layer on the first carrier; forming a first circuit layer on the first insulating layer; Connecting at least one filter chip on the first circuit layer; A second carrier is combined on the first insulating layer, and the second carrier is provided with the same number of through holes respectively used to expose each filter chip; bonding a second insulating layer on the second carrier to form a chip cavity between the second insulating layer and the first insulating layer; forming a second circuit layer on the second insulating layer, and connecting the first circuit layer and the second circuit layer through electroplated through holes; The first carrier is removed, and the first insulating layer and the second insulating layer are packaged to obtain a chip module packaging structure with a chip cavity.
[0007] In some preferred embodiments, before packaging, the method further includes the following steps: performing a build-up layer process on the first insulating layer and / or the second insulating layer to form electrical connection pads on the build-up layer and its outer surface, and the electrical connection pads are connected to the filter chip through plated through holes.
[0008] In some preferred embodiments, the build-up process is continuously performed on the first insulating layer and the second insulating layer.
[0009] In some preferred embodiments, the method further comprises the following steps: a non-filter chip is mounted on the electrical connection pad.
[0010] In some preferred embodiments, the first circuit layer is further connected to a capacitor and / or an inductor, and the second carrier is correspondingly provided with through holes for exposing the capacitor and the inductor.
[0011] In some preferred embodiments, the first insulating layer and the second insulating layer are prepreg or film-like materials.
[0012] In some preferred embodiments, the filter chip is flip-chip connected to the first circuit layer.
[0013] In some preferred embodiments, a non-filter chip is mounted on the electrical connection pad.
[0014] In some preferred embodiments, LGA packaging or BGA packaging is used.
[0015] In a second aspect, the present invention further provides a chip module packaging structure obtained by the method described above.
[0016] By adopting the above technical solution, the present invention has the following effects: by providing a through hole on the second carrier, the present invention can form a chip cavity between the first insulating layer and the second insulating layer when the first insulating layer, the second carrier and the second insulating layer are sequentially combined, so that the filter chip mounted on the first insulating layer is placed in the chip cavity. Compared with the prior art, the present invention can effectively reduce costs and ensure reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a schematic diagram of the first bearing member in the present invention.
[0018] Figure 2 The diagram is a schematic diagram of combining a first insulating layer on a first carrier and forming a first circuit layer on the first insulating layer.
[0019] Figure 3 A schematic diagram of setting a filter on the first circuit layer.
[0020] Figure 4 It is a schematic diagram of the second supporting member in the present invention.
[0021] Figure 5 It is a schematic diagram of combining the second carrier onto the first insulating layer.
[0022] Figure 6 It is a schematic diagram of bonding the second insulating layer to the second carrier.
[0023] Figure 7 This is a schematic diagram of a chip module packaging structure with a chip cavity obtained by the method provided in Example 1 of the present invention.
[0024] Figure 8 This is a schematic diagram of a chip module packaging structure with a chip cavity obtained by the method provided in Example 3 of the present invention.
[0025] Fig. 9 A schematic diagram of a chip module packaging structure with a chip cavity obtained by the method provided in Example 4 of the present invention.
[0026] In the figure: 100-first carrier, 101-first insulating layer, 11-first circuit layer, 102-second insulating layer, 12-second circuit layer, 200-second carrier, 201-through hole, 21-filter chip, 31-first build-up layer, 120-first electrical connection pad, 32-second build-up layer, 130-second electrical connection pad, 41-electroplated through hole, 51-non-filter chip. DETAILED DESCRIPTION
[0027] The specific embodiments of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0028] Example 1 An embodiment of the present invention provides a method for forming a chip cavity in a chip module packaging structure.
[0029] See also Figure 1 , providing a first carrier 100, the first carrier 100 is configured as an insulating core board, a metal board or a circuit board, and the thickness of the first carrier 100 can be determined as needed.
[0030] See also Figure 2 , a first insulating layer 101 is bonded on the first carrier 100. The first insulating layer 101 is a prepreg or film material, such as epoxy resin, polyimide, LCP, BT, Bismaleimide triazine, ABF (Ajinomoto Build-up Film), PPE, PTFE, BCB, benzoncylobutene, etc. And a first circuit layer 11 is formed on the first insulating layer 101. The first circuit layer 11 is a conductive material and can be formed by any method such as physical filling, chemical plating, electroplating or vapor deposition.
[0031] See also Figure 3 , a flip-chip filter chip 21 is soldered on the first circuit layer 11 of the first insulating layer 101 , and there may be one or more filter chips 21 .
[0032] See also Figure 4 , providing a second carrier 200 having through openings 201. The second carrier 200 is configured as an insulating core board, a metal plate or a circuit board. The number of through openings 201 provided on the second carrier 200 is the same as the total number of filter chips 21, and the distribution mode of the through openings 201 on the second carrier 200 is the same as the distribution mode of the filter chips 21 on the first insulating layer 101.
[0033] See also Figure 5 ,Will Figure 4 The second carrier 200 in Figure 3 The filter chip 21 is exposed through the through hole 201 .
[0034] In addition, the thickness of the second carrier 200 is configured to be not less than the thickness of the filter chip 21 , so that the filter chip 21 does not protrude from the surface of the second carrier 200 .
[0035] See also Figure 6, a second insulating layer 102 is bonded to the second carrier 200. The second insulating layer 102 is configured as a prepreg or film material, such as epoxy resin, polyimide, LCP, BT, Bismaleimide triazine, ABF (Ajinomoto Build-up Film), polyphenylene ether (PPE), polytetrafluoroethylene (PTFE), BCB, benzoncylobutene, etc.
[0036] Thus, when the second insulating layer 102 is bonded to the second carrier 200 , the through opening 201 is closed, and a chip cavity is formed between the first insulating layer 101 , the second insulating layer 102 and the second carrier 200 , and the filter chip 21 is formed in the chip cavity.
[0037] See also Figure 7 , a second circuit layer 12 is formed on the second insulating layer 102. The second circuit layer 12 is a conductive material. The second circuit layer 12 can be formed by any method such as physical filling, chemical plating, electroplating or vapor deposition. In addition, the first circuit layer 11 and the second circuit layer 12 are connected by electroplated through holes 41. The position and number of the electroplated through holes 41 are set as needed, and there is not only one electroplated through hole shown in the figure.
[0038] Then, the first carrier 100 is removed, and the first insulating layer 101 and the second insulating layer 102 are packaged (not shown in the figure), and the packaging form can be LGA packaging form or BGA packaging form, so as to obtain a chip module packaging structure with a chip cavity.
[0039] Example 2 It is easy to understand that when the filter chip 21 is disposed on the first insulating layer 101 , a capacitor and / or an inductor (not shown in the figure) may also be disposed on the first insulating layer 101 according to circumstances.
[0040] Correspondingly, the number of through openings 201 set on the second carrier 200 is the same as the total number of filter chips 21, capacitors and inductors, and the distribution of the through openings 201 on the second carrier 200 is the same as the distribution of the filter chips 21, capacitors and inductors on the first insulating layer 101.
[0041] Accordingly, the thickness of the second carrier 200 is not less than the thickness of the filter chip 21 , the capacitor, and the inductor, so that the filter chip 21 , the capacitor, and the inductor do not protrude from the surface of the second carrier 200 .
[0042] Example 3 Based on the above embodiment, the method provided in the embodiment of the present invention further includes the following steps: See also Figure 8 Before packaging, a first build-up layer 31 and a first electrical connection pad 120 located on the outer surface of the first build-up layer 31 are provided on the first insulating layer 101 through a build-up process, and a second build-up layer 32 and a second electrical connection pad 130 located on the outer surface of the second build-up layer 32 are provided on the second insulating layer 102 through a build-up process.
[0043] In addition, the circuits on both sides of the second carrier 200 are electrically connected by plated through holes. The positions and number of the plated through holes referred to here are set according to needs, and there is not only one plated through hole shown in the figure, so that the first electrical connection pad 120 and the second electrical connection pad 130 can both be connected to the filter chip 21.
[0044] Example 4 See also Fig. 9 On the basis of Example 3, a flip-chip non-filter chip 51 can be attached to the second electrical connection pad 130 as needed, one or more chips can be attached as needed, and of course, a face-up non-filter chip 51 can be bonded as needed, and then connected to the second electrical connection pad 130 by wire bonding.
[0045] If LGA packaging is used, ball planting is not required, for example, ball planting is not required on the first electrical connection pad 120; if BGA packaging is used, ball planting and solder balls are required, for example, ball planting and solder balls are required on the first electrical connection pad 120.
[0046] Example 5 It is easy to understand that the method provided by the embodiment of the present invention can continue to perform the layer-adding process on the first insulating layer 101 and the second insulating layer 102, and connect the electrical connection pads through the plated through holes. The positions and number of the plated through holes referred to here are set according to needs, and there is not only one plated through hole shown in the figure, thereby forming a 2-layer, 4-layer, 6-layer, 8-layer, 10-layer, 12-layer or even more layer structure.
[0047] Example 6 An embodiment of the present invention further provides a chip module packaging structure, which is manufactured by the method disclosed in any of the above embodiments.
[0048] It should be noted that, in the description of the present invention, the directions or positional relationships indicated by the terms "up", "down", "left", "right", "front", "back", etc. are descriptions of the structure of the present invention based on the accompanying drawings, and are only for the convenience of describing the present invention, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.
[0049] The "first" and "second" in this technical solution are only used to distinguish the names of the same or similar structures, or corresponding structures with similar functions, and are not an arrangement of the importance of these structures, nor do they have a ranking, comparison of size, or other meanings.
[0050] In addition, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be a connection between the two structures. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood based on the overall idea of the present invention and the specific context of the present solution.
[0051] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions and variations of these embodiments are made without departing from the principles and spirit of the present invention, and still fall within the scope of protection of the present invention.
Claims
1. A method for forming a chip cavity in a chip module packaging structure, characterized in that: The method comprises the following steps: Providing a first carrier and bonding a first insulating layer on the first carrier; forming a first circuit layer on the first insulating layer; Connecting at least one filter chip on the first circuit layer; A second carrier is combined on the first insulating layer, and the second carrier is provided with the same number of through holes respectively used to expose each filter chip; bonding a second insulating layer on the second carrier to form a chip cavity between the second insulating layer and the first insulating layer; forming a second circuit layer on the second insulating layer, and connecting the first circuit layer and the second circuit layer through electroplated through holes; The first carrier is removed, and the first insulating layer and the second insulating layer are packaged to obtain a chip module packaging structure with a chip cavity.
2. The method according to claim 1, characterized in that Before packaging, the method further includes the following steps: performing a build-up layer process on the first insulating layer and / or the second insulating layer to form electrical connection pads on the build-up layer and its outer surface, and the electrical connection pads are connected to the filter chip through plated through holes.
3. The method according to claim 2, characterized in that: The build-up process is continued on the first insulating layer and the second insulating layer.
4. The method according to claim 2, characterized in that: The method further comprises the following steps: a non-filter chip is mounted on the electrical connection pad.
5. The method according to claim 1, characterized in that: The first circuit layer is also connected to a capacitor and / or an inductor, and the second carrier is correspondingly provided with a through hole for exposing the capacitor and the inductor.
6. The method according to claim 1, characterized in that: The first insulating layer and the second insulating layer are prepreg or film-like materials.
7. The method according to claim 1, characterized in that: The filter chip is flip-chip connected to the first circuit layer.
8. The method according to claim 4, characterized in that: The non-filter chip is flip-chip connected or face-up bonded on the electrical connection pad.
9. The method according to claim 1, characterized in that: Through LGA packaging or BGA packaging.
10. A chip module packaging structure, characterized in that: Obtained by the method according to any one of claims 1 to 9.