Level shift circuit based on current compensation

Abstract

According to the current compensation-based level shift circuit provided by the invention, one path of low-voltage pulse signal is accessed through the first level input end and the second level output end respectively, so that the two paths of low-voltage pulse signals are converted into two paths of high-voltage pulse signals; the signals are output to the current compensation circuit and the common-mode noise elimination circuit through the first level output end and the second level output end, and the output of the current compensation circuit and the output of the common-mode noise elimination circuit jointly influence the signal states of the R end and the S end in the latch. And the latch is used for restoring the high-voltage pulse signal into a floating square wave signal with the same phase as the input signal. The level shift circuit not only can resist high common-mode noise, but also has a good inhibition effect on differential-mode noise, and the stability and reliability of the level shift circuit are effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a level shift circuit based on current compensation. Background Art

[0002] In power integrated circuits, gate driver chips are used to receive control signals from external digital chips such as CPUs or MCUs, and provide gate signals required to control and drive power MOSFET devices or power IGBT devices. They are widely used in motor control, servo systems, 5G communications, wireless transmission, fast charging, etc. Usually, gate driver chips contain two parts, the high-voltage domain and the low-voltage domain. The level shift circuit acts as a transmission bridge between different voltage domains, moving the potential of the control logic from the low-voltage domain to the high-voltage domain or from the high-voltage domain to the low-voltage domain.

[0003] However, this high-to-low voltage conversion circuit requires the integration of a high-voltage resistant LDMOS tube. Due to the large parasitic capacitance of the LDMOS tube, when dv / dt occurs, its parasitic capacitance will generate a charging or discharging current, forming dv / dt noise, interfering with the normal operation of the level converter and causing errors in the driver's high-voltage domain logic signal.

[0004] like Figure 1 The circuit structure shown includes a level shift circuit and a gate driver chip. When the high-side power tube is turned on, V HS The voltage will quickly rise to VPVDD, dV HS / dt changes are coupled to the level shifter through the bootstrap capacitor, V HB With V HS Change, dV HB / dt is approximately equal to dV HS / dt; Since the input MOS device MH1 (MH2) of the level converter is a high-voltage LDMOS tube, there is a large parasitic capacitance C1 (C2) at point A (B), V HB The rapid change of the voltage will generate a large current on C1 (C2), which will lower the voltage at point A (B). When the noise amplitude (=R×C×dV HS / dt, where R is R1 or R2, and C is C1 or C2) is greater than V BOOT -V th When (where V BOOT Equal to V HB -V HS ), the subsequent circuit may be affected by the noise signal, resulting in driving logic errors. Especially in high-voltage application environments, the dv / dt noise of the level shift circuit seriously threatens the reliability of the gate driver.

[0005] In order to suppress the interference of dv / dt noise signals on the circuit, a common solution is to add a common mode noise elimination circuit with a cross-coupling structure to the level shifting circuit. Figure 2 As shown in the figure, the commonly used level shift circuit has the working principle that the input pulse signal triggers the high-voltage tubes MH1 and MH2, the control signal is copied to the latch input through the current mirror, and the pulse signal is restored to the original square wave signal through the latch; MP2~MP6 and MN1~MN4 form a cross-coupling structure. In theory, when dv / dt occurs, the noise current generated by the parasitic capacitance of the high-voltage tubes MH1 and MH2 will be offset in the cross-coupling structure, and its dv / dt noise is essentially input common-mode noise for the latch. Therefore, it has a good inhibitory effect on common-mode noise.

[0006] However, during the wafer taping process, due to process reasons, the parasitic capacitances of the high-voltage tubes MH1 and MH2 are not exactly the same, which will introduce differential mode noise into the circuit; in addition, differential mode noise may also be introduced during layout and wiring of the layout drawing. The level shift circuit with a cross-coupling structure cannot offset the noise current caused by the differential mode noise. Therefore, it is urgent to provide a new level shift circuit to process the differential mode noise. Summary of the invention

[0007] In view of the deficiencies in the prior art, the present invention provides a level shift circuit based on current compensation, which solves the problem in the prior art that the level shift circuit with a cross-coupling structure cannot handle differential mode noise, making the level shift circuit prone to signal distortion or circuit instability.

[0008] According to an embodiment of the present invention, a level shift circuit based on current compensation includes:

[0009] The level shift circuit includes a first level input terminal and a second level input terminal connected to a low voltage pulse signal, and also includes a first level output terminal and a second level output terminal for outputting a high voltage pulse signal;

[0010] a common mode noise elimination circuit, comprising a first mirror input terminal connected to the first level output terminal, a second mirror input terminal connected to the second level output terminal, a first current output terminal outputting a first current, a second current output terminal outputting a second current, a third current output terminal outputting a third current, and a fourth current output terminal outputting a fourth current;

[0011] a current compensation circuit, comprising a third mirror input terminal connected to the first level output terminal, a fourth mirror input terminal connected to the second level output terminal, a first compensation output terminal outputting a first compensation current, and a second compensation output terminal outputting a second compensation current;

[0012] A latch, including an R terminal, an S terminal and a latch output terminal;

[0013] When differential mode +dv / dt noise exists, the R terminal is 1 and the S terminal is 0, and a mismatch occurs in the level shift circuit so that the first current and the second current are smaller than the third current and the fourth current, then the first compensation output terminal, the first current output terminal, and the third current output terminal generate a first latch signal which is input to the R terminal, and in the first latch signal, the sum of the first current and the first compensation current is greater than or equal to the third current; the second compensation output terminal, the fourth current output terminal, and the second current output terminal generate a second latch signal which is input to the S terminal, and in the second latch signal, the fourth current minus the second compensation current is less than or equal to the second current;

[0014] The driver is connected to the output end of the latch and is used to enhance the square wave signal output by the latch end and output a logic control signal with driving capability.

[0015] Optionally, the first level input terminal and the second level input terminal are connected to the low voltage pulse signal through a cascade circuit including a high voltage LDMOS and a low voltage MOS.

[0016] Optionally, the level shift circuit includes a first NMOS transistor, a second NMOS transistor, a first LDMOS transistor, a second LDMOS transistor, a first PMOS transistor, a second PMOS transistor, a first Zener diode and a second Zener diode;

[0017] The first level input end is the gate of the first NMOS tube, which is used to collect the rising edge pulse signal in the low voltage pulse signal, and the second level input end is the gate of the second NMOS tube, which is used to collect the falling edge pulse signal in the low voltage pulse signal;

[0018] The source of the first NMOS tube and the source of the second NMOS tube are grounded, the drain of the first NMOS tube is connected to the source of the first LDMOS tube, and the drain of the second NMOS tube is connected to the source of the second LDMOS tube; the gates of the first LDMOS tube and the second LDMOS tube are both connected to an internal 5V bias voltage, the drain of the first LDMOS tube is connected to the drain of the first PMOS tube, and the drain of the second PMOS tube is connected to the drain of the first LDMOS tube; the gate of the first PMOS tube is connected to the drain of the first PMOS tube, the gate of the second PMOS tube is connected to the drain of the second PMOS tube, and the source of the first PMOS tube and the source of the second PMOS tube are both connected to a floating power supply; the positive end of the first Zener diode is connected to the drain of the first PMOS tube, the positive end of the second Zener diode is connected to the drain of the second PMOS tube, and the negative end of the first Zener diode and the negative end of the second Zener diode are both connected to a floating power supply;

[0019] The first level output end is the gate of the first PMOS tube; the second level output end is the gate of the second PMOS tube.

[0020] Optionally, the current compensation circuit further includes a first switch, a second switch and a third switch; the first switch and the second switch are connected to the S terminal, and the third switch is connected to the R terminal;

[0021] When differential mode +dv / dt noise exists, if the R terminal is 0 and the S terminal is 1, the current compensation circuit is turned off through the first switch, the second switch and the third switch.

[0022] Optionally, the current compensation circuit includes a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, and an eighth NMOS tube;

[0023] The seventh NMOS tube is the first switch, the eighth NMOS tube is the second switch, and the eighth PMOS tube is the third switch; the gate of the third PMOS tube is the third mirror input terminal, receiving the high-voltage pulse signal output by the first level output terminal, and the gate of the fourth PMOS tube is the fourth mirror input terminal, receiving the high-voltage pulse signal output by the second level output terminal;

[0024] The source of the fourth PMOS tube and the source of the third PMOS tube are both connected to a floating power supply, the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube, and the drain of the third PMOS tube is connected to the drain of the fourth NMOS tube; the gate and drain of the third NMOS tube are connected and connected to the gate of the fourth NMOS tube to form a current mirror, and the source of the third NMOS tube and the source of the fourth NMOS tube are both connected to a floating ground;

[0025] The gates of the fifth PMOS tube, the sixth PMOS tube, and the seventh PMOS tube and the drain of the fifth PMOS tube are connected to form a current mirror and connected to the drain of the fourth NMOS tube, and the source of the fifth PMOS tube, the source of the sixth PMOS tube, and the source of the seventh PMOS tube are all connected to a floating power supply;

[0026] The gate and drain of the fifth NMOS tube are connected and connected to the gate of the sixth NMOS tube to form a current mirror, and are connected to the drain of the sixth PMOS tube. The source of the fifth NMOS tube and the source of the sixth NMOS tube are both connected to the floating ground; the drain of the seventh PMOS tube is connected to the R terminal, and the drain of the sixth NMOS tube is connected to the S terminal; the gate of the eighth PMOS tube is connected to the R terminal, the drain of the eighth PMOS tube is connected to the gate of the seventh PMOS tube, and the source of the eighth PMOS tube and the source of the seventh PMOS tube are both connected to the floating power supply; the drain of the seventh NMOS tube is connected to the drain of the fourth NMOS tube, the drain of the eighth NMOS tube is connected to the gate of the sixth NMOS tube, the gate of the seventh NMOS tube and the gate of the eighth NMOS tube are both connected to the S terminal, and the source of the seventh NMOS tube and the source of the eighth NMOS tube are both connected to the floating ground.

[0027] Optionally, the common mode noise elimination circuit includes a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube;

[0028] The gate of the eleventh PMOS tube and the gate of the twelfth PMOS tube are both connected to the gate of the second PMOS tube in the level shift circuit, the source of the eleventh PMOS tube and the source of the twelfth PMOS tube are both connected to a floating power supply, the drain of the eleventh PMOS tube is connected to the drain of the tenth NMOS tube, and the drain of the twelfth PMOS tube is connected to the drain of the twelfth NMOS tube; the gate of the ninth PMOS tube and the gate of the tenth PMOS tube are both connected to the gate of the first PMOS tube in the level shift circuit, the source of the ninth PMOS tube and the source of the tenth PMOS tube are both connected to a floating power supply, the drain of the ninth PMOS tube is connected to the drain of the tenth NMOS tube, and the drain of the ninth PMOS tube is connected to the drain of the twelfth NMOS tube. The drain of the ninth NMOS tube is connected, and the drain of the tenth PMOS tube is connected to the drain of the eleventh NMOS tube; the gate of the tenth NMOS tube and the drain of the tenth NMOS tube are connected to the gate of the ninth NMOS tube, and the source of the tenth NMOS tube and the source of the tenth NMOS tube are both connected to the floating ground; the gate of the eleventh NMOS tube and the drain of the eleventh NMOS tube are connected to the gate of the twelfth NMOS tube, and the source of the eleventh NMOS tube and the source of the twelfth NMOS tube are both connected to the floating ground; the drain of the ninth PMOS tube is connected to the R terminal, and the drain of the twelfth PMOS tube is connected to the S terminal of the latch.

[0029] Optionally, the latch further includes a first inverter and a second inverter;

[0030] The first inverter and the second inverter are connected in series to form a loop, the R terminal is the input terminal of the first inverter and the output terminal of the second inverter, and the S terminal is the output terminal of the first inverter and the input terminal of the second inverter;

[0031] The latch output terminal comprises a first latch output terminal and a second latch output terminal;

[0032] The first latch output terminal is the input terminal of the first inverter and the output terminal of the second inverter, and the second latch output terminal is the output terminal of the first inverter and the input terminal of the second inverter.

[0033] Optionally, the driver includes a first drive circuit connected to the first latch output terminal, and a second drive circuit connected to the second latch output terminal.

[0034] The present invention has the following beneficial effects: the level shift circuit is connected to a low-voltage pulse signal through the first level input terminal and the second level output terminal respectively, thereby converting the two low-voltage pulse signals into two high-voltage pulse signals, and outputting them to the current compensation circuit and the common-mode noise elimination circuit through the first level output terminal and the second level output terminal. The outputs of the current compensation circuit and the common-mode noise elimination circuit jointly affect the signal states of the R terminal and the S terminal in the latch, and the latch is used to restore the high-voltage pulse signal to a floating square wave signal with the same phase as the input signal. Therefore, when there is differential mode noise, especially when there is a noise that affects the output of the latch, the embodiment of the present invention can effectively reduce the high-voltage pulse signal to a floating square wave signal with the same phase as the input signal. When there is differential mode + dv / dt noise, the first compensation current of the current compensation circuit compensates the first current of the common mode noise elimination circuit, and the second compensation current of the current compensation circuit compensates the fourth current of the common mode noise elimination circuit, so that the R end and the S end of the latch maintain the correct signal state, avoiding the differential mode noise from affecting the latch output state, thereby causing signal distortion or circuit instability. At the same time, the common mode noise elimination circuit is used to eliminate the common mode noise in the circuit, the latch is used to restore the high voltage pulse signal to a floating square wave signal with the same phase as the input signal, and the output stage driving circuit is used to enhance the driving ability of the logic control signal. Therefore, the present invention can not only resist high common mode noise, but also has a good inhibitory effect on differential mode noise, effectively improving the stability and reliability of the level shifting circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A circuit structure diagram including a level shift circuit and a gate drive chip;

[0036] Figure 2 The circuit structure diagram of the commonly used level shift circuit;

[0037] Figure 3 A circuit structure diagram of a level shift circuit based on current compensation provided by an embodiment of the present invention;

[0038] Figure 4 A detailed circuit structure diagram of a level shift circuit based on current compensation provided by an embodiment of the present invention;

[0039] Figure 5 This is a simulation waveform diagram of common mode noise interference before adding a current compensation circuit in an embodiment of the present invention;

[0040] Figure 6 This is a simulation waveform diagram of common mode noise interference after adding a current compensation circuit in an embodiment of the present invention;

[0041] Figure 7 This is a simulation waveform diagram of differential mode noise interference before adding a current compensation circuit in an embodiment of the present invention;

[0042] Figure 8 This is a simulation waveform diagram of differential mode noise interference after adding a current compensation circuit in an embodiment of the present invention.

[0043] Description of the drawings: 1. Level shift circuit; 2. Common mode noise elimination circuit; 3. Current compensation circuit; 4. Latch; 5. Driver. DETAILED DESCRIPTION

[0044] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0045] like Figure 3As shown, an embodiment of the present invention proposes a level shift circuit based on current compensation, including a level shift circuit, a common mode noise elimination circuit, a current compensation circuit, a latch and a driver. The detailed working process of this embodiment is that the level shift circuit is connected to a low-voltage pulse signal through the first level input terminal and the second level output terminal respectively, so as to convert the two low-voltage pulse signals into two high-voltage pulse signals, and output them to the current compensation circuit and the common-mode noise elimination circuit through the first level output terminal and the second level output terminal. The outputs of the current compensation circuit and the common-mode noise elimination circuit jointly affect the signal states of the R terminal and the S terminal in the latch, and the latch is used to restore the high-voltage pulse signal to a floating square wave signal with the same phase as the input signal. Therefore, in the embodiment of the present invention, when differential mode noise exists, the first compensation current of the common mode noise elimination circuit is compensated by the first compensation current of the current compensation circuit, and the fourth current of the common mode noise elimination circuit is compensated by the second compensation current of the current compensation circuit, so that the R terminal and the S terminal of the latch maintain the correct signal state, and avoid the differential mode noise affecting the output state of the latch, thereby causing signal distortion or circuit instability. At the same time, the common mode noise elimination circuit is used to eliminate the common mode noise in the circuit, the latch is used to restore the high-voltage pulse signal to a floating square wave signal with the same phase as the input signal, and the output stage driving circuit is used to enhance the driving capability of the logic control signal. Therefore, the present invention can not only resist high common mode noise, but also has a good inhibitory effect on differential mode noise, effectively improving the stability and reliability of the level shift circuit.

[0046] like Figure 3 As shown, the connection relationship of each part and the signal input and output relationship of the level shift circuit based on current compensation provided by the embodiment of the present invention are as follows:

[0047] The level shift circuit 1 includes a first level input terminal INN and a second level input terminal INP for receiving two low-voltage pulse signals, and also includes a first level output terminal W1 and a second level output terminal W2 for outputting high-voltage pulse signals.

[0048] The common mode noise elimination circuit 2 includes a first mirror input terminal J1 connected to the first level output terminal W1, a second mirror input terminal J2 connected to the second level output terminal W2, a first current output terminal A1 outputting a first current I1, a second current output terminal A2 outputting a second current I2, a third current output terminal A3 outputting a third current I3, and a fourth current output terminal A4 outputting a fourth current I4.

[0049] The current compensation circuit 3 includes a third mirror input terminal J3 connected to the first level output terminal W1, a fourth mirror input terminal J4 connected to the second level output terminal W2, and outputs a first compensation current I B1 The first compensation output terminal B1 and the output second compensation current I B2 The second compensation output terminal B2.

[0050] The latch 4 includes an R terminal, an S terminal and a latch output terminal C, and is used to restore the high-voltage pulse signal to a floating square wave signal in phase with the input signal.

[0051] In specific applications, differential mode noise is divided into two situations: rising (+dv / dt) and falling (-dv / dt). Among them, differential mode -dv / dt noise has no effect on the R and S terminals. When differential mode +dv / dt noise occurs, the high-voltage tube in the circuit is mismatched, causing the current in the two conversion paths in the level shift circuit to change, which may cause the first current, second current, third current, and fourth current in the common mode noise elimination circuit to be unequal; or it may not cause any effect, and the first current, second current, third current, and fourth current are still equal. However, if the above currents are unequal, it will affect the latch logic output.

[0052] Therefore, the level shift circuit based on current compensation provided by the embodiment of the present invention, when there is differential mode +dv / dt noise, at this time, the R terminal is 1, the S terminal is 0, and a mismatch occurs in the level shift circuit so that the first current I1 and the second current I2 are smaller than the third current I3 and the fourth current I4, then current compensation is performed, and the relevant circuit structure is: the first compensation output terminal B1, the first current output terminal A1 and the third current output terminal A3 generate a first latch signal input to the R terminal, and in the first latch signal, the sum of the first current I1 and the first compensation current is greater than or equal to the third current I3, thereby enhancing the pull-up capability of the R terminal and keeping the state of the R terminal at 1; the second compensation output terminal B2, the fourth current output terminal A4 and the second current output terminal A2 generate a second latch signal input to the S terminal, and in the second latch signal, the fourth current I4 minus the second compensation current is less than or equal to the second current I2, thereby enhancing the pull-down capability of the S terminal and keeping the state of the S terminal at 0.

[0053] The driver 5 is connected to the output terminal of the latch and is used to enhance the square wave signal output by the latch terminal and output a logic control signal with driving capability.

[0054] In one embodiment, the circuit structure of the first level input terminal INN and the second level output terminal W2 is optimized, and the first level input terminal INN and the second level input terminal INP are connected to the low voltage pulse signal through a cascade circuit including a high voltage LDMOS and a low voltage MOS, thereby isolating the high voltage domain from the low voltage domain and accelerating the signal transmission speed.

[0055] like Figure 4 As shown, the embodiment of the present invention also shows a detailed circuit structure of a level shift circuit, which is Figure 3 A way to implement a level shift circuit in the Figure 4The level shift circuit includes a first NMOS tube MN1, a second NMOS tube MN2, a first LDMOS tube MH1, a second LDMOS tube MH2, a first PMOS tube MP1, a second PMOS tube MP2, a first Zener diode D1 and a second Zener diode D2; the first level input terminal INN is the gate INN of the first NMOS tube MN1, the second level input terminal INP is the gate INP of the second NMOS tube MN2, the first level input terminal INN is used to collect the rising edge pulse signal in the low-voltage pulse signal, and the second level input terminal INP is used to collect the falling edge pulse signal in the low-voltage pulse signal. The source of the first NMOS tube MN1 and the source of the second NMOS tube MN2 are grounded, the drain of the first NMOS tube MN1 is connected to the source of the first LDMOS tube MH1, and the drain of the second NMOS tube MN2 is connected to the source of the second LDMOS tube MH2; the gates of the first LDMOS tube MH1 and the second LDMOS tube MH2 are both connected to the internal bias voltage of 5V, the drain of the first LDMOS tube MH1 is connected to the drain of the first PMOS tube MP1, and the drain of the second PMOS tube MP2 is connected to the drain of the first LDMOS tube MH1; the gate of the first PMOS tube MP1 is connected to the drain of the first PMOS tube MP1, the gate of the second PMOS tube MP2 is connected to the drain of the second PMOS tube MP2, and the source of the first PMOS tube MP1 and the source of the second PMOS tube MP2 are both connected to the floating power supply V HB The positive end of the first Zener diode D1 is connected to the drain of the first PMOS tube MP1, the positive end of the second Zener diode D2 is connected to the drain of the second PMOS tube MP2, and the negative end of the first Zener diode D1 and the negative end of the second Zener diode D2 are both connected to the floating power supply V HB It should be noted that, combined with Figure 3 and Figure 4 The first level output terminal W1 is the gate of the first PMOS transistor MP1; the second level output terminal W2 is the gate of the second PMOS transistor MP2.

[0056] In specific applications, when differential mode -dv / dt noise is generated, the R terminal is 0 and the S terminal is 1. At this time, no current compensation circuit is required for compensation, but in this case, the current compensation circuit may still be involved in the circuit operation.

[0057] Therefore, in one embodiment, the current compensation circuit further includes a first switch, a second switch and a third switch; the first switch and the second switch are connected to the S terminal, and the third switch is connected to the R terminal; when differential mode -dv / dt noise exists, the current compensation circuit is turned off by the first switch, the second switch and the third switch.

[0058] like Figure 4 As shown, the embodiment of the present invention also shows a detailed circuit structure of a current compensation circuit, which is Figure 3 A way to implement the current compensation circuit. Figure 4 The current compensation circuit includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8. The seventh NMOS transistor MN7 is a first switch, the eighth NMOS transistor MN8 is a second switch, and the eighth PMOS transistor MP8 is a third switch.

[0059] The gate of the third PMOS tube MP3 is the third mirror input terminal J3, which receives the high-voltage pulse signal output by the first level output terminal W1. The gate of the fourth PMOS tube MP4 is the fourth mirror input terminal J4, which receives the high-voltage pulse signal output by the second level output terminal W2. The source of the fourth PMOS tube MP4 and the source of the third PMOS tube MP3 are both connected to the floating power supply V HB , the drain of the fourth PMOS tube MP4 is connected to the drain of the third NMOS tube MN3, and the drain of the third PMOS tube MP3 is connected to the drain of the fourth NMOS tube MN4; the gate and drain of the third NMOS tube MN3 are connected and connected to the gate of the fourth NMOS tube MN4 to form a current mirror, and the source of the third NMOS tube MN3 and the source of the fourth NMOS tube MN4 are both connected to the floating ground VHS; the gates of the fifth PMOS tube MP5, the sixth PMOS tube MP6, and the seventh PMOS tube MP7 are connected to the drain of the fifth PMOS tube MP5 to form a current mirror and are connected to the drain of the fourth NMOS tube MN4, and the source of the fifth PMOS tube MP5, the source of the sixth PMOS tube MP6, and the source of the seventh PMOS tube MP7 are all connected to the floating power supply V HB The gate and drain of the fifth NMOS tube MN5 are connected and connected to the gate of the sixth NMOS tube MN6 to form a current mirror, and are connected to the drain of the sixth PMOS tube MP6. The source of the fifth NMOS tube MN5 and the source of the sixth NMOS tube MN6 are both connected to the floating ground VHS; the drain of the seventh PMOS tube MP7 is connected to the R terminal, and the drain of the sixth NMOS tube MN6 is connected to the S terminal; the gate of the eighth PMOS tube MP8 is connected to the R terminal, the drain of the eighth PMOS tube MP8 is connected to the gate of the seventh PMOS tube MP7, and the source of the eighth PMOS tube MP8 and the source of the seventh PMOS tube MP7 are both connected to the floating power supply V HBThe drain of the seventh NMOS tube MN7 is connected to the drain of the fourth NMOS tube MN4, the drain of the eighth NMOS tube MN8 is connected to the gate of the sixth NMOS tube MN6, the gate of the seventh NMOS tube MN7 and the gate of the eighth NMOS tube MN8 are both connected to the S terminal, and the source of the seventh NMOS tube MN7 and the source of the eighth NMOS tube MN8 are both connected to the floating ground VHS. When the R terminal is 0 and the S terminal is 1, the seventh NMOS tube MN7, the eighth NMOS tube MN8, and the eighth PMOS tube MP8 are turned on, and the current compensation circuit is turned off.

[0060] Embodiments of the present invention are combined Figure 4 , the current compensation circuit compensates the output of the common mode noise elimination circuit, and the signal state of the R and S terminals in the control latch is explained again. First, the differential mode -dv / dt noise has no effect on the R and S terminals. Only when the differential mode +dv / dt noise occurs, it may cause I1, I2 and I3, I4 to be unequal, and I1, I2 and I3, I4 to be unequal, will it affect the signal state of the R and S terminals. At present, the R terminal is 1 and the S terminal is 0. Figure 4 When differential mode +dv / dt noise occurs, MH1 and MH2 are mismatched, and IA>IB, there will be no impact, that is, I1, I2 and I3, I4 will not be unequal. When differential mode +dv / dt noise occurs, MH1 and MH2 are mismatched, and IA<IB, there will be an impact, that is, I1, I2 and I3, I4 are unequal, and the current flowing through MN9 and MN11 is less than the current flowing through MN10 and MN12. At this time, the logic signal may be affected by the noise, R suddenly changes to 0, S suddenly changes to 1, resulting in a drive logic error. However, the current compensation circuit added in the embodiment of the present invention works as follows in the above state: since IA<IB, the noise current is mirrored into I5 and I6 through MP3 and MP4, I5=I6+I7, and I7 is mirrored into a pull-up current I8 through MP7, and I7 is mirrored into a pull-down current I9 through MP6, MN5 and MN6; at this time, I8 is used to compensate I1, so that I1+I8≥I3, thereby enhancing the pull-up capability of the R terminal and keeping the state of the R terminal at 1; I9 is ​​used to compensate I4, so that I4-I9≤I2, thereby enhancing the pull-down capability of the S terminal and keeping the state of the S terminal at 0.

[0061] In addition, when differential mode -dv / dt noise exists, MP8, MN7, and MN8 are turned on, and the current compensation circuit is turned off.

[0062] like Figure 4 As shown, the embodiment of the present invention also shows a detailed circuit structure of a common mode noise elimination circuit, which is Figure 3 One implementation of a common mode noise elimination circuit. Figure 4The common mode noise elimination circuit includes a ninth PMOS tube MP9, a tenth PMOS tube MP10, an eleventh PMOS tube MP11, a twelfth PMOS tube MP12, a ninth NMOS tube MN9, a tenth NMOS tube MN10, an eleventh NMOS tube MN11 and a twelfth NMOS tube MN12.

[0063] The gate of the eleventh PMOS tube MP11 and the gate of the twelfth PMOS tube MP12 are both connected to the gate of the second PMOS tube MP2 in the level shift circuit, and the source of the eleventh PMOS tube MP11 and the source of the twelfth PMOS tube MP12 are both connected to the floating power supply V HB , the drain of the eleventh PMOS tube MP11 is connected to the drain of the tenth NMOS tube MN10, and the drain of the twelfth PMOS tube MP12 is connected to the drain of the twelfth NMOS tube MN12; the gate of the ninth PMOS tube MP9 and the gate of the tenth PMOS tube MP10 are both connected to the gate of the first PMOS tube MP1 in the level shift circuit, and the source of the ninth PMOS tube MP9 and the source of the tenth PMOS tube MP10 are both connected to the floating power supply V HB , the drain of the ninth PMOS tube MP9 is connected to the drain of the ninth NMOS tube MN9, the drain of the tenth PMOS tube MP10 is connected to the drain of the eleventh NMOS tube MN11; the gate of the tenth NMOS tube MN10 and the drain of the tenth NMOS tube MN10 are connected to the gate of the ninth NMOS tube MN9, and the source of the tenth NMOS tube MN10 and the source of the tenth NMOS tube MN10 are both connected to the floating ground V HS The gate of the eleventh NMOS tube MN11 and the drain of the eleventh NMOS tube MN11 are connected to the gate of the twelfth NMOS tube MN12, and the source of the eleventh NMOS tube MN11 and the source of the twelfth NMOS tube MN12 are both connected to the floating ground V HS The drain of the ninth PMOS tube MP9 is connected to the R terminal, and the drain of the twelfth PMOS tube MP12 is connected to the S terminal of the latch.

[0064] like Figure 4 As shown, the embodiment of the present invention also shows a detailed circuit structure of a latch, Figure 3 A way to implement a latch in . Figure 4 , the latch includes a first inverter and a second inverter.

[0065] The first inverter and the second inverter are connected in series to form a loop, the R terminal is the input terminal of the first inverter and the output terminal of the second inverter, and the S terminal is the output terminal of the first inverter and the input terminal of the second inverter;

[0066] The latch output terminal includes a first latch output terminal and a second latch output terminal;

[0067] The first latch output terminal is the input terminal of the first inverter and the output terminal of the second inverter, and the second latch output terminal is the output terminal of the first inverter and the input terminal of the second inverter.

[0068] like Figure 4 As shown, the embodiment of the present invention also shows a detailed circuit structure of a driver, Figure 3 See Figure 4 The driver includes a first driving circuit connected to the first latch output terminal, and a second driving circuit connected to the second latch output terminal. Exemplarily, since the square wave signal output by the latch terminal has a weak driving capability, the embodiment of the present invention uses a buffer as a driving circuit, and the power driving capability of the signal is gradually enhanced by the buffer, and a logic control signal with driving capability is output.

[0069] like Figures 5 to 8 As shown, the embodiment of the present invention shows the simulation results obtained by simulating the above-mentioned level shift circuit based on current compensation, so as to illustrate its ability to resist common-mode noise interference and differential-mode noise interference.

[0070] in, Figure 5 This is the simulation waveform of common mode noise interference before adding the current compensation circuit. Figure 6 This is the simulation waveform of the common mode noise interference after adding the current compensation circuit. The simulation conditions of the two simulations are the same: INN and INP are 5V pulse signal inputs, the frequency is 50K Hz, the gate bias of the high-voltage tube is connected to the bias voltage of 5V, and V is set HS It is a square wave of 0~100V, the frequency is the same as the input signal, and the signal delay is 100ns slower than the input signal. HB is V HS High 5V synchronous square wave signal; simulates V HS The waveform output of the rising edge time is swept from 2ns to 1ns, with a step length of 0.2ns. Figure 5 and Figure 6 , Figure 5 shows that no current compensation circuit V is added HS RV HS and OUT1-V HS The output waveform shows that when dv / dt is about 83V / ns, common-mode noise causes the signal to mutate, and there is a risk of output logic errors. Figure 6 V after adding current compensation circuit HS RV HS and OUT1-V HSThe output waveform of the circuit shows that when dv / dt is about 100V / ns, common mode noise causes the signal to change suddenly, and there is a risk of output logic errors. Figure 5 and Figure 6 According to the simulation results, the level shift circuit based on current compensation provided by the embodiment of the present invention has excellent ability to resist common mode noise.

[0071] in, Figure 7 This is the simulation waveform of differential mode noise interference before adding the current compensation circuit. Figure 7 This is the simulation waveform of differential mode noise interference after adding the current compensation circuit. The simulation conditions of the two simulations are the same, and the above Figure 5 and Figure 6 The simulation conditions are the same as those of , which will not be described here. In addition, when dv / dt is about 71V / ns, a wide mismatch ratio is set between MH1 and MH2 to simulate process errors and artificially introduce differential mode noise. Figure 7 and Figure 8 , Figure 7 shows that no current compensation circuit V is added HS RV HS and OUT1-V HS The output waveform shows that when the mismatch tolerance between MH1 and MH2 (1-MH1 / MH2) is about 10%, differential mode noise causes the signal to mutate, and there is a risk of output logic errors. Figure 8 The figure shows the V after adding the current compensation circuit. HS RV HS and OUT1-V HS The output waveform diagram shows that when the mismatch tolerance between MH1 and MH2 is greater than 30%, RV HS and OUT1-V HS The output waveform of the circuit changes suddenly, indicating that the current compensation circuit has a good suppression effect on differential mode noise and can effectively improve the stability and reliability of the level shift circuit.

[0072] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A level shift circuit based on current compensation, characterized in that: include: The level shift circuit includes a first level input terminal and a second level input terminal connected to a low voltage pulse signal, and also includes a first level output terminal and a second level output terminal for outputting a high voltage pulse signal; a common mode noise elimination circuit, comprising a first mirror input terminal connected to the first level output terminal, a second mirror input terminal connected to the second level output terminal, a first current output terminal outputting a first current, a second current output terminal outputting a second current, a third current output terminal outputting a third current, and a fourth current output terminal outputting a fourth current; a current compensation circuit, comprising a third mirror input terminal connected to the first level output terminal, a fourth mirror input terminal connected to the second level output terminal, a first compensation output terminal outputting a first compensation current, and a second compensation output terminal outputting a second compensation current; A latch, including an R terminal, an S terminal and a latch output terminal; When differential mode +dv / dt noise exists, the R terminal is 1 and the S terminal is 0, and a mismatch occurs in the level shift circuit so that the first current and the second current are smaller than the third current and the fourth current, then the first compensation output terminal, the first current output terminal, and the third current output terminal generate a first latch signal which is input to the R terminal, and in the first latch signal, the sum of the first current and the first compensation current is greater than or equal to the third current; the second compensation output terminal, the fourth current output terminal, and the second current output terminal generate a second latch signal which is input to the S terminal, and in the second latch signal, the fourth current minus the second compensation current is less than or equal to the second current; The driver is connected to the output end of the latch and is used to enhance the square wave signal output by the latch end and output a logic control signal with driving capability.

2. A level shift circuit based on current compensation as claimed in claim 1, characterized in that: The first level input terminal and the second level input terminal are connected to the low voltage pulse signal through a cascade circuit including a high voltage LDMOS and a low voltage MOS.

3. A level shift circuit based on current compensation as claimed in claim 1 or 2, characterized in that: The level shift circuit includes a first NMOS transistor, a second NMOS transistor, a first LDMOS transistor, a second LDMOS transistor, a first PMOS transistor, a second PMOS transistor, a first Zener diode and a second Zener diode; The first level input end is the gate of the first NMOS tube, which is used to collect the rising edge pulse signal in the low voltage pulse signal, and the second level input end is the gate of the second NMOS tube, which is used to collect the falling edge pulse signal in the low voltage pulse signal; The source of the first NMOS tube and the source of the second NMOS tube are grounded, the drain of the first NMOS tube is connected to the source of the first LDMOS tube, and the drain of the second NMOS tube is connected to the source of the second LDMOS tube; the gates of the first LDMOS tube and the second LDMOS tube are both connected to an internal 5V bias voltage, the drain of the first LDMOS tube is connected to the drain of the first PMOS tube, and the drain of the second PMOS tube is connected to the drain of the first LDMOS tube; the gate of the first PMOS tube is connected to the drain of the first PMOS tube, the gate of the second PMOS tube is connected to the drain of the second PMOS tube, and the source of the first PMOS tube and the source of the second PMOS tube are both connected to a floating power supply; the positive end of the first Zener diode is connected to the drain of the first PMOS tube, the positive end of the second Zener diode is connected to the drain of the second PMOS tube, and the negative end of the first Zener diode and the negative end of the second Zener diode are both connected to a floating power supply; The first level output end is the gate of the first PMOS tube; the second level output end is the gate of the second PMOS tube.

4. A level shift circuit based on current compensation as claimed in claim 1, characterized in that: The current compensation circuit further includes a first switch, a second switch and a third switch; the first switch and the second switch are connected to the S terminal, and the third switch is connected to the R terminal; When differential mode-dv / dt noise exists, the current compensation circuit is turned off through the first switch, the second switch and the third switch.

5. A level shift circuit based on current compensation as claimed in claim 4, characterized in that: The current compensation circuit includes a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, and an eighth NMOS tube; The seventh NMOS tube is the first switch, the eighth NMOS tube is the second switch, and the eighth PMOS tube is the third switch; the gate of the third PMOS tube is the third mirror input terminal, receiving the high-voltage pulse signal output by the first level output terminal, and the gate of the fourth PMOS tube is the fourth mirror input terminal, receiving the high-voltage pulse signal output by the second level output terminal; The source of the fourth PMOS tube and the source of the third PMOS tube are both connected to a floating power supply, the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube, and the drain of the third PMOS tube is connected to the drain of the fourth NMOS tube; the gate and drain of the third NMOS tube are connected and connected to the gate of the fourth NMOS tube to form a current mirror, and the source of the third NMOS tube and the source of the fourth NMOS tube are both connected to a floating ground; The gates of the fifth PMOS tube, the sixth PMOS tube, and the seventh PMOS tube and the drain of the fifth PMOS tube are connected to form a current mirror and connected to the drain of the fourth NMOS tube, and the source of the fifth PMOS tube, the source of the sixth PMOS tube, and the source of the seventh PMOS tube are all connected to a floating power supply; The gate and drain of the fifth NMOS tube are connected and connected to the gate of the sixth NMOS tube to form a current mirror, and are connected to the drain of the sixth PMOS tube. The source of the fifth NMOS tube and the source of the sixth NMOS tube are both connected to the floating ground; the drain of the seventh PMOS tube is connected to the R terminal, and the drain of the sixth NMOS tube is connected to the S terminal; the gate of the eighth PMOS tube is connected to the R terminal, the drain of the eighth PMOS tube is connected to the gate of the seventh PMOS tube, and the source of the eighth PMOS tube and the source of the seventh PMOS tube are both connected to the floating power supply; the drain of the seventh NMOS tube is connected to the drain of the fourth NMOS tube, the drain of the eighth NMOS tube is connected to the gate of the sixth NMOS tube, the gate of the seventh NMOS tube and the gate of the eighth NMOS tube are both connected to the S terminal, and the source of the seventh NMOS tube and the source of the eighth NMOS tube are both connected to the floating ground.

6. A level shift circuit based on current compensation as claimed in claim 5, characterized in that: The common mode noise elimination circuit includes a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube; The gate of the eleventh PMOS tube and the gate of the twelfth PMOS tube are both connected to the gate of the second PMOS tube in the level shift circuit, the source of the eleventh PMOS tube and the source of the twelfth PMOS tube are both connected to a floating power supply, the drain of the eleventh PMOS tube is connected to the drain of the tenth NMOS tube, and the drain of the twelfth PMOS tube is connected to the drain of the twelfth NMOS tube; the gate of the ninth PMOS tube and the gate of the tenth PMOS tube are both connected to the gate of the first PMOS tube in the level shift circuit, the source of the ninth PMOS tube and the source of the tenth PMOS tube are both connected to a floating power supply, the drain of the ninth PMOS tube is connected to the drain of the tenth NMOS tube, and the drain of the ninth PMOS tube is connected to the drain of the twelfth NMOS tube. The drain of the ninth NMOS tube is connected, and the drain of the tenth PMOS tube is connected to the drain of the eleventh NMOS tube; the gate of the tenth NMOS tube and the drain of the tenth NMOS tube are connected to the gate of the ninth NMOS tube, and the source of the tenth NMOS tube and the source of the tenth NMOS tube are both connected to the floating ground; the gate of the eleventh NMOS tube and the drain of the eleventh NMOS tube are connected to the gate of the twelfth NMOS tube, and the source of the eleventh NMOS tube and the source of the twelfth NMOS tube are both connected to the floating ground; the drain of the ninth PMOS tube is connected to the R terminal, and the drain of the twelfth PMOS tube is connected to the S terminal of the latch.

7. A level shift circuit based on current compensation as claimed in claim 1, characterized in that: The latch also includes a first inverter and a second inverter; The first inverter and the second inverter are connected in series to form a loop, the R terminal is the input terminal of the first inverter and the output terminal of the second inverter, and the S terminal is the output terminal of the first inverter and the input terminal of the second inverter; The latch output terminal comprises a first latch output terminal and a second latch output terminal; The first latch output terminal is the input terminal of the first inverter and the output terminal of the second inverter, and the second latch output terminal is the output terminal of the first inverter and the input terminal of the second inverter.

8. A level shift circuit based on current compensation as claimed in claim 7, characterized in that: The driver includes a first driving circuit connected to the first latch output terminal, and a second driving circuit connected to the second latch output terminal.

Images