Receiver equalizer module, transmitter equalizer module and electronic device

Abstract

A receiver equalizer module (14) is described. The equalizer module (14) comprises a signal input, a first signal processing channel, a second signal processing channel and a filter module. The first signal processing channel includes a first analog-to-digital converter and a first digital down converter disposed downstream of the first analog-to-digital converter. The second signal processing channel includes a second analog-to-digital converter and a second digital down converter disposed downstream of the second analog-to-digital converter. A filter module is connected to the signal processing channel downstream of the digital down converter. Furthermore, a transmitter equalizer module (18) and an electronic device (10) are described.

Description

Technical Field

[0001] The present invention generally relates to a receiver equalizer module. The present invention also relates to a transmitter equalizer module and an electronic device. Background Art

[0002] In the prior art, it is known to apply equalization to signals processed by parallel signal processing channels in order to resolve unwanted interference of the processed signals.

[0003] Typically, for two parallel signal processing channels, four real-valued filters are provided, each real-valued filter filtering one of the processed signals at a sampling rate corresponding to the sampling rate of an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC).

[0004] Furthermore, it is necessary to provide an additional radio frequency (RF) filter downstream of the four real-value filters, which filters the output signals of the real-value filters at the same sampling rate.

[0005] In other words, the signal is equalized at the high sampling rate of the ADC or DAC, which is quite resource-intensive because of the high computing power required.

[0006] Therefore, there is a need for a receiver equalizer module and a transmitter equalizer module that allow for more resource efficient equalization. Summary of the invention

[0007] According to the present invention, the problem is solved by a receiver equalizer module. The receiver equalizer module includes a signal input terminal, a first signal processing channel, a second signal processing channel and a filter module. The first signal processing channel and the second signal processing channel are connected to the signal input terminal respectively. The first signal processing channel includes a first analog-to-digital converter and a first digital down converter arranged downstream of the first analog-to-digital converter. The first analog-to-digital converter is configured to digitize the signal processed by the first signal processing channel, thereby obtaining a first digitized signal. The first digital down converter is configured to down-convert the first digitized signal or a processed version of the first digitized signal, thereby obtaining a first down-converted signal. The second signal processing channel includes a second analog-to-digital converter and a second digital down converter arranged downstream of the second analog-to-digital converter. The second analog-to-digital converter is configured to digitize the signal processed by the second signal processing channel, thereby obtaining a second digitized signal. The second digital down converter is configured to down-convert the second digitized signal or a processed version of the second digitized signal, thereby obtaining a second down-converted signal. The filter module is connected to the signal processing channel downstream of the digital down converter.

[0008] The invention is based on the concept of providing a filter module of a receiver equalizer module downstream of a digital downconverter. In this way, the filter module does not have to operate at the high sampling rate of the analog-to-digital converter (ADC), but at a small fraction of the sampling rate determined by the decimation factor of the digital downconverter.

[0009] In other words, the filter module of the receiver equalizer module according to the present invention is configured to process a signal having a bandwidth corresponding to the bandwidth actually used downstream of the receiver equalizer module.

[0010] In this way, the computing power required to filter the signals processed by the signal processing channel is significantly reduced, which allows saving power and / or using more cost-effective filter components.

[0011] Furthermore, it has been demonstrated that no additional RF filter, which is necessary in the prior art, is required in the receiver equalizer module according to the present invention. Therefore, the power consumption and cost of manufacturing the receiver equalizer module are further reduced.

[0012] According to one aspect of the invention, the filter module is configured to equalize the first down-converted signal and the second down-converted signal. In other words, the filter module is configured to perform post-equalization on the signals processed by the first signal processing channel and the second signal processing channel.

[0013] In an embodiment of the present invention, the filter module is configured to equalize the first down-converted signal and the second down-converted signal so that crosstalk between signal processing channels and / or imbalance between signal processing channels are eliminated. Therefore, undesirable interference of the signal processed by the signal processing channel is eliminated, thereby improving the quality of the down-converted signal for further processing downstream of the filter module.

[0014] According to another aspect of the present invention, the filter module comprises a first filter submodule connected to a first signal processing channel, wherein the filter module comprises a second filter submodule connected to a second signal processing channel. It has been demonstrated that if the filter module is arranged downstream of a digital down converter, two filter submodules are sufficient to equalize the signals processed by the signal processing channels. Therefore, a more resource-efficient and cost-effective receiver equalizer module is provided compared to the prior art that requires four filter submodules and additional RF filters for two parallel signal processing channels.

[0015] In particular, the first filter submodule is only connected to the first signal processing channel and not to the second signal processing channel.

[0016] The second filter submodule may be connected only to the second signal processing channel and not to the first signal processing channel.

[0017] In another embodiment of the present invention, the first filter submodule and the second filter submodule are respectively established as complex value filters. In other words, the filter coefficients of the first filter submodule and the second filter submodule are respectively complex numbers. It has been proved that if the first filter submodule and the second filter submodule are established as complex value filters, no additional filter submodule is needed to equalize the down-converted signal. Therefore, compared with the prior art of the additional RF filter downstream of the four filter submodules and four filter submodules for two parallel signal processing channels, a more resource-efficient and cost-effective receiver equalizer module is provided.

[0018] In particular, the filter module comprises a summing module connected to each of the first filter submodule and the second filter submodule, wherein the summing module is configured to superimpose the output signals of the filter submodules. Therefore, the output signal of the filter module is a superposition of the output signals of the filter submodules, i.e., a superposition of the filtered down-converted signal.

[0019] The output signal of the filter module can be forwarded to other electronic components or electronics for further processing, for example to an evaluation module or a signal processing module of a measuring instrument.

[0020] Another aspect of the present invention provides that the first signal processing channel is configured to process an in-phase signal (I signal), and wherein the second signal processing channel is configured to process a quadrature signal (Q signal).

[0021] Therefore, the receiver equalizer module according to the present invention can be configured to equalize in-phase and quadrature signals (IQ signals) such that crosstalk between a first signal processing channel processing the I signal and a second signal processing channel processing the Q signal is eliminated.

[0022] Alternatively or additionally, the receiver equalizer module according to the present invention may be configured to equalize the IQ signal so that an imbalance (ie, IQ imbalance) between a first signal processing channel processing the I signal and a second signal processing channel processing the Q signal is eliminated.

[0023] According to the present invention, the problem is further solved by a transmitter equalizer module. The transmitter equalizer module includes a signal input terminal, a first signal processing channel, a second signal processing channel and a filter module. The filter module is connected to the signal input terminal. The first signal processing channel includes a first digital up-converter and a first digital-to-analog converter arranged downstream of the first digital up-converter. The first digital up-converter is configured to up-convert the digital signal processed by the first signal processing channel, thereby obtaining a first up-converted signal. The first digital-to-analog converter is configured to convert the first up-converted signal or a processed version of the first up-converted signal into a first analog signal. The second signal processing channel includes a second digital up-converter and a second digital-to-analog converter arranged downstream of the second digital down-converter. The second digital up-converter is configured to up-convert the digital signal processed by the second signal processing channel, thereby obtaining a second up-converted signal. The second digital-to-analog converter is configured to convert the second up-converted signal or a processed version of the second up-converter signal into a second analog signal. The filter module is connected to the signal processing channel upstream of the digital up-converter.

[0024] The invention is based on the idea of ​​providing a filter module of a transmitter equalizer module upstream of a digital upconverter. In this way, the filter module does not have to operate at the high sampling rate of the digital-to-analog converter (DAC), but at a small fraction of the sampling rate determined by the interpolation factor of the digital upconverter.

[0025] In other words, the filter module of the transmitter equalizer module according to the present invention is configured to process a signal having a bandwidth corresponding to the bandwidth actually used upstream of the transmitter equalizer module.

[0026] In this way, the computing power required to filter the signals processed by the signal processing channel is significantly reduced, which allows saving power and / or using more cost-effective filter components.

[0027] Furthermore, it has been shown that in the transmitter equalizer module according to the present invention, no additional RF filter, which is necessary in the prior art upstream of the filter module, is required. Therefore, the power consumption and the cost of manufacturing the transmitter equalizer module are further reduced.

[0028] In an embodiment of the present invention, the filter module is configured to pre-equalize the digital signal processed by the signal processing channel. In other words, the signal forwarded to the signal processing channel is pre-adjusted so that undesired interference is not present in the output signal in the signal processing channel.

[0029] According to one aspect of the present invention, the filter module is configured to pre-equalize the digital signals processed by the signal processing channels so that the crosstalk between the signal processing channels and / or the imbalance between the signal processing channels are eliminated. In other words, the signals forwarded to the signal processing channels are pre-adjusted so that the crosstalk between the signal processing channels and / or the imbalance between the signal processing channels are not present in the output signals of the signal processing channels.

[0030] In particular, the filter module comprises a first filter submodule connected to the first signal processing channel, and wherein the filter module comprises a second filter submodule connected to the second signal processing channel. It has been demonstrated that if the filter module is arranged upstream of the digital upconverter, two filter submodules are sufficient to pre-equalize the signals processed by the signal processing channels. Thus, a more resource efficient and cost-effective transmitter equalizer module is provided compared to the prior art which requires four filter submodules for two parallel signal processing channels and an RF filter upstream of the filter module.

[0031] In particular, the first filter submodule is only connected to the first signal processing channel and not to the second signal processing channel.

[0032] The second filter submodule may be connected only to the second signal processing channel and not to the first signal processing channel.

[0033] In another embodiment of the present invention, the first filter submodule and the second filter submodule are respectively established as complex value filters. In other words, the filter coefficients of the first filter submodule and the second filter submodule are respectively complex numbers. It has been proved that if the first filter submodule and the second filter submodule are established as complex value filters, no additional filter submodule is needed to pre-equalize the signal processed by the signal processing channel. Therefore, compared with the prior art of the four filter submodules and the RF filter upstream of the filter module for two parallel signal processing channels, a more resource-efficient and cost-effective transmitter equalizer module is provided.

[0034] The filter module may include a splitter module connected to each of the first filter submodule and the second filter submodule, wherein the splitter module is configured to forward a signal received via the signal input terminal to the filter submodule. Thus, the input signal received by the filter module is separated and forwarded to the first signal processing channel and the second signal processing channel.

[0035] The input signal of the filter module may be an output signal of another electronic component or another electronic device, for example an output signal of an analysis module or a signal processing module of a measuring instrument.

[0036] According to one aspect of the invention, the first signal processing channel is configured to process an in-phase signal, wherein the second signal processing channel is configured to process a quadrature signal.

[0037] Therefore, the transmitter equalizer module according to the present invention can be configured to pre-equalize the IQ signal so that the crosstalk between the first signal processing channel processing the I signal and the second signal processing channel processing the Q signal is eliminated.

[0038] Alternatively or additionally, the transmitter equalizer module according to the present invention may be configured to pre-equalize the IQ signal so that an imbalance (ie, IQ imbalance) between a first signal processing channel processing the I signal and a second signal processing channel processing the Q signal is eliminated.

[0039] According to the present invention, this problem is further solved by an electronic device comprising a receiver equalizer module according to any one of the above variants and / or a transmitter equalizer module according to any one of the above variants.

[0040] With regard to advantages and further properties of the electronic device, reference is made to the explanations given above with regard to the receiver equalizer module and with regard to the transmitter equalizer module, which also apply to the electronic device and vice versa.

[0041] According to one aspect of the invention, the electronic device is established as a measuring instrument. For example, the electronic device can be an oscilloscope, in particular a digital oscilloscope, a signal analyzer, a spectrum analyzer or a vector network analyzer.

[0042] However, it should be understood that the electronic device may be set up as any other type of measuring instrument.

[0043] Another aspect of the invention provides that the electronic device is established as a radio frequency (RF) receiver and / or an RF transmitter. In particular, the electronic device may be an RF transceiver or an RF front end, in particular an external RF front end. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The foregoing aspects and many of the attendant advantages of the claimed subject matter will become more readily understood as the same become better appreciated by reference to the following detailed description when taken in conjunction with the accompanying drawings, in which:

[0045] - Figure 1 Schematically shows an electronic device according to the present invention;

[0046] - Figure 2 schematically illustrates a receiver equalizer module according to the present invention; and

[0047] - Figure 3A transmitter equalizer module according to the present invention is schematically shown. DETAILED DESCRIPTION

[0048] The detailed description set forth below in conjunction with the accompanying drawings, in which like reference numerals refer to like elements, is intended as a description of various embodiments of the disclosed subject matter and is not intended to represent the only embodiments. Each embodiment described in the present disclosure is provided only as an example or illustration and should not be construed as preferred or superior to other embodiments. The illustrative examples provided herein are not intended to be exhaustive or to limit the claimed subject matter to the precise form disclosed.

[0049] For purposes of this disclosure, the phrase "at least one of A, B, and C," for example, means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all other possible permutations when more than three elements are listed. In other words, the term "at least one of A and B" generally means "A and / or B," i.e., "A" alone, "B" alone, or "A and B."

[0050] Figure 1 Schematically illustrated is an electronic device 10. Generally, the electronic device 10 is configured to receive, process and / or transmit electrical signals, in particular radio frequency (RF) signals.

[0051] For example, the electronic device 10 may be an oscilloscope, in particular a digital oscilloscope, a signal analyzer, a spectrum analyzer, a vector network analyzer or any other type of measuring instrument.

[0052] As another example, the electronic device 10 may be an RF receiver and / or an RF transmitter. In particular, the electronic device 10 may be an RF transceiver or an RF front end, in particular an external RF front end.

[0053] exist Figure 1 In the exemplary embodiment shown, the electronic device comprises a signal input terminal 12 and a receiver equalizer module 14 connected to the signal input terminal 12 .

[0054] Here and in the following, the term "module" is understood to describe suitable hardware, suitable software or a combination of hardware and software configured to have a certain functionality.

[0055] The hardware may include, among other things, a CPU, a GPU, an FPGA, an ASIC, or other types of electronic circuitry.

[0056] Typically, the signal input 12 is configured to receive an electrical signal and forward the received electrical signal to the receiver equalizer module 14 , wherein the received electrical signal is an analog RF signal.

[0057] For example, the signal input terminal 12 may be connected to the device under test so that the signal input terminal 12 receives an output signal of the device under test.

[0058] As another example, the signal input 12 may be connected to an RF antenna such that the signal input 12 receives an electrical signal generated by the RF antenna based on a wireless signal picked up by the RF antenna.

[0059] The receiver equalizer module 14 is configured to pre-process the signal received via the signal input 12 , as will be described in more detail below.

[0060] The receiver equalizer module 14 is also configured to forward the pre-processed signal to the analysis and / or processing module 16 for further processing.

[0061] The analysis and / or processing module 16 is configured to analyze and / or process signals received from the receiver equalizer module 14, for example, in order to evaluate the performance of the device under test.

[0062] The analysis and / or processing module 16 is also configured to generate an output signal, which is forwarded to the transmitter equalizer module 18 .

[0063] The transmitter equalizer module 18 is configured to process signals received from the analysis and / or processing module 16, as will be described in more detail below.

[0064] The transmitter equalizer module 18 is connected to a signal output 20 of the electronic device 10 .

[0065] For example, the signal output 20 may be connected to the device under test, such that the output signal of the transmitter equalizer module 18 may be sent to the device under test via the signal output 20 .

[0066] As another example, the signal output terminal 20 may be connected to an RF antenna, so that the output signal of the transmitter equalizer module 18 may be converted into a wireless signal by means of the RF antenna.

[0067] Figure 2 An exemplary embodiment of receiver equalizer module 14 is shown in greater detail.

[0068] The receiver equalizer module 14 includes a signal input terminal 22, which is configured to receive the RF signal s from the signal input terminal 12 of the electronic device 10. HF (f).

[0069] Without limiting the generality, the following assumes that the RF signal s HF (f) is the simulated IQ signal.

[0070] The receiver equalizer module 14 also includes a first signal processing path 24 and a second signal processing path 26 connected to the signal input 22 .

[0071] The signal input 22 is configured to forward the RF signal to the processing channels 24 , 26 .

[0072] like Figure 2 As shown, the signal input terminal 22 may have a transfer function H RF (f), the transfer function H RF (f) According to H RF (f) s HF (f) to change the received RF signal.

[0073] The receiver equalizer module 14 also includes an IQ demodulation module 28 having a first IQ mixer 30 and a second IQ mixer 32 .

[0074] The first IQ mixer 30 is provided in the first signal processing channel 24 and is configured to convert the RF signal s HF (f) and cos(ω c t) to obtain the in-phase signal I1, where ω c is the carrier frequency.

[0075] Therefore, the first signal processing channel 24 is configured to process the in-phase signal I1 .

[0076] The second IQ mixer 32 is provided in the second signal processing channel 26 and is configured to convert the RF signal s HF (f) and -sin(ω c t) to obtain the orthogonal signal Q1.

[0077] Therefore, the second signal processing channel 26 is configured to process the quadrature signal Q1.

[0078] The receiver equalizer module 14 also includes an RF filter module 32 that is configured to filter the analog I signal I1 and the analog Q signal Q1 to at least partially eliminate crosstalk between the signal processing channels 24 , 26 and / or eliminate imbalance between the signal processing channels 24 , 26 .

[0079] This type of RF filters is well known in the art and therefore will not be explained in further detail.

[0080] Each of the signal processing channels 24 , 26 further includes a low pass filter 34 disposed downstream of the RF filter module 32 .

[0081] The output signal of the low-pass filter 34 of the first signal processing channel 24 is an analog I signal I2.

[0082] The output signal of the low-pass filter 34 of the second signal processing channel 26 is the analog Q signal I2.

[0083] The first signal processing channel 24 includes a first analog-to-digital converter (ADC) 36 downstream of the low-pass filter 34 , wherein the first ADC 36 is configured to digitize the analog I signal I2 to obtain a first digitized signal.

[0084] In fact, the first ADC 36 is configured to digitize the analog I signal I2 at a certain sampling rate.

[0085] For example, the sampling rate may be between 5 GS / s (Gigasamples per second) and 50 GS / s, in particular between 10 GS / s and 40 GS / s.

[0086] In a specific example, the sampling rate may be equal to 20 GS / s.

[0087] The first signal processing channel 24 further includes a first digital down-converter (DDC) 38, which is configured to down-convert the first digitized signal to obtain a first down-converted signal I3.

[0088] More specifically, the first digital down converter 38 includes a mixer submodule 40 configured to combine the first digitized signal with an intermediate frequency -ω IF mixing.

[0089] In fact, the mixer submodule 40 includes a first branch and a second branch, wherein the first branch is configured to combine the first digitized signal with cos(-ω IF t), the second branch is configured to multiply the first digitized signal by -sin(-ω IF t) are multiplied.

[0090] The digital down converter 38 further includes a decimation module 42 configured to decimate the first digitized signal by a decimation factor N.

[0091] For example, the decimation factor N may be equal to 2, 3, 4, or any other suitable number.

[0092] Therefore, the sampling rate of the first down-converted signal I3 is equal to the sampling rate of the first ADC 36 divided by the decimation factor N.

[0093] For example, if the sampling rate of the first ADC 36 is equal to 20 GS / s, and if the decimation factor N is equal to 4, the sampling rate of the first down-converted signal I3 is equal to 5 GS / s.

[0094] The second signal processing channel 26 includes a second ADC 44 downstream of the low-pass filter 34 , wherein the second ADC 44 is configured to digitize the analog Q signal Q2 to obtain a second digitized signal.

[0095] In fact, the second ADC 44 is configured to digitize the analog I-signal I2 at a certain sampling rate, in particular wherein the sampling rate of the second ADC 44 is equal to the sampling rate of the first ADC 36 .

[0096] The second signal processing channel 26 further includes a second digital down converter 46 configured to down-convert the second digitized signal to obtain a second down-converted signal Q3.

[0097] The second digital down converter 46 is configured similarly to the first digital down converter 38 described above.

[0098] Therefore, the sampling rate of the second down-converted signal Q3 is equal to the sampling rate of the second ADC 44 divided by the decimation factor N.

[0099] The receiver equalizer module 14 also includes a filter module 48 that is disposed downstream of the digital down converters 38 , 46 .

[0100] The filter module 48 includes a first filter submodule 50 disposed in the first signal processing channel 24 and a second filter submodule 52 disposed in the second signal processing channel 26 .

[0101] The filter coefficients of the first filter submodule 50 and the second filter submodule may be derived based on the following equalizer conditions:

[0102]

[0103] The filter coefficients can be calculated according to the following equation:

[0104]

[0105] C(ω)=H -1 (ω)

[0106] S BB (ω)=I3(ω)·(C I (ω′)+j·C IQ (ω′)+Q3(ω)·(C QI (ω′)+j·C Q (ω′)

[0107] It can be seen from these equations that two complex-valued filters are sufficient to equalize the first down-converted signal I3 and the second down-converted signal Q3, thereby obtaining the output signal sBB (ω).

[0108] The first filter submodule 50 is a filter having filter coefficients c I (f)+jc IQ (f) Complex-valued filter.

[0109] The second filter submodule 52 is a filter having filter coefficients c QI (f)+jc Q (f) Complex-valued filter.

[0110] Typically, the filter coefficients of the filter submodules 50 , 52 are selected such that crosstalk between the signal processing channels 24 , 26 and / or imbalance between the signal processing channels 24 , 26 are eliminated.

[0111] In other words, the filter module 48 is configured to post-equalize the signal processing channels 24 , 26 by filtering the down-converted signals I3 and Q3 .

[0112] The filter module 48 also includes a summing module 54 connected to the first filter sub-module 50 and the second filter sub-module 52 .

[0113] The summing module 54 is configured to add the output signals of the filter submodules 50 and 52 to obtain the output signal s of the receiver equalizer module 14. BB (f).

[0114] In fact, the output signal s of the receiver equalizer module 14 is BB (f) may be a baseband signal.

[0115] The output signal may be forwarded to the analysis and / or processing module 16 for further analysis and / or processing.

[0116] Figure 3 An exemplary embodiment of transmitter equalizer module 18 is shown in greater detail.

[0117] The transmitter equalizer module 18 includes a signal input terminal 56, which is configured to receive the digital baseband signal s from the analysis and / or processing module 16. BB (f).

[0118] The transmitter equalizer module 18 also includes a filter module 58 having a splitter module 60 connected to the signal input terminal 56 for receiving the digital baseband signal s BB (f).

[0119] Downstream of the splitter module, a first filter submodule 62 is disposed in the first signal processing path 64 , and a second filter submodule 66 is disposed in the second signal processing path 68 .

[0120] The splitter module 60 is configured to divide the digital baseband signal s BB (f) is forwarded to the first filter submodule 62 and the second filter submodule 66.

[0121] Typically, the filter module 58 is configured to pre-equalize the digital signals processed by the signal processing channels 64 , 68 so as to eliminate crosstalk between the signal processing channels 64 , 68 and / or imbalance, ie, IQ imbalance, between the signal processing channels 64 , 68 .

[0122] The filter coefficients of the filter submodules 62, 66 may be determined similarly to the above-described variations.

[0123] The first filter submodule 62 is a filter having filter coefficients c I (f)+jc IQ (f) Complex-valued filter.

[0124] The output signal of the first filter submodule 62 is a digital I signal I3 .

[0125] The second filter submodule 66 is a filter having filter coefficients c QI (f)+jc Q (f) Complex-valued filter.

[0126] The output signal of the second filter submodule 66 is a digital Q signal Q3.

[0127] The filter coefficients of the filter submodules 62 , 66 are selected such that crosstalk between the signal processing channels 64 , 68 and / or imbalance between the signal processing channels 64 , 68 , ie, IQ imbalance, is eliminated.

[0128] The first signal processing channel 64 further includes a first digital up-converter (DUC) 70 configured to up-convert the digital I signal I3 to obtain a first up-converted signal.

[0129] More specifically, the first digital up-converter 70 comprises an interpolation module 72 configured to interpolate the digital I signal I3 with an interpolation factor N.

[0130] For example, the interpolation factor N may be equal to 2, 3, 4, or any other suitable number.

[0131] The first digital up-converter 70 includes a mixer submodule 74 configured to mix the first up-converted signal with an intermediate frequency -ωIF mixing.

[0132] In fact, the mixer submodule 74 includes a first branch and a second branch, wherein the first branch is configured to combine the first up-converted signal with cos(-ω IF t), the second branch is configured to multiply the first up-converter signal by -sin(-ω IF t) are multiplied.

[0133] The first signal processing channel 64 further includes a first digital-to-analog converter (DAC) 76 configured to convert the first up-converted signal into a first analog signal I2 having a specific sampling rate.

[0134] For example, the sampling rate may be between 5 GS / s and 50 GS / s, in particular between 10 GS / s and 40 GS / s.

[0135] In a specific example, the sampling rate may be equal to 20 GS / s.

[0136] In fact, the sampling rate of the first digital-to-analog converter 76 is equal to the baseband signal s BB The sampling rate of (f) is multiplied by the interpolation factor N.

[0137] For example, if the baseband signal s BB The sampling rate of (f) is equal to 5 GS / s, and if the interpolation factor N is equal to 4, the sampling rate of the first digital-to-analog converter 76 is equal to 20 GS / s.

[0138] The second signal processing channel 68 further includes a second digital up-converter (DUC) 78 configured to up-convert the digital Q signal Q3 to obtain a second up-converted signal.

[0139] More specifically, the second digital up-converter 78 comprises an interpolation module 72 configured to interpolate the digital Q signal Q3 with an interpolation factor N.

[0140] For example, the interpolation factor N may be equal to 2, 3, 4, or any other suitable number.

[0141] The second digital up-converter 78 further includes a mixer submodule 74 configured to mix the second up-converted signal with the intermediate frequency -ω IF mixing.

[0142] In fact, the mixer submodule 74 includes a first branch and a second branch, wherein the first branch is configured to combine the second up-converted signal with cos(-ω IF t), the second branch is configured to multiply the second up-converted signal by -sin(-ω IF t) are multiplied.

[0143] The second signal processing channel 68 further includes a second digital-to-analog converter (DAC) 80 configured to convert the second up-converted signal into a second analog signal Q2 having a specific sampling rate.

[0144] The sampling rate of the second digital-to-analog converter 80 may be equal to the sampling rate of the first digital-to-analog converter 76 .

[0145] The signal processing channels 64 , 68 each include a low pass filter 82 disposed downstream of the respective digital-to-analog converter 76 , 80 .

[0146] The transmitter equalizer module 18 also includes an RF filter module 84 , which is disposed downstream of the low-pass filter 82 .

[0147] This type of RF filter is well known in the art and will not be explained in further detail.

[0148] Downstream of the RF filter module 84, an IQ modulation module 86 having a first IQ mixer 88 and a second IQ mixer 90 is arranged.

[0149] The first IQ mixer 88 is provided in the first signal processing channel 64 and is configured to combine the output signal I1 of the RF filter module 84 with cos(ω c t) multiplied by ω c is the carrier frequency.

[0150] The second IQ mixer 90 is provided in the second signal processing channel 68 and is configured to combine the output signal Q1 of the RF filter module 84 with -sin(ω c t) are multiplied.

[0151] The transmitter equalizer module 18 also includes a summing module 92 downstream of the IQ modulation module 86 .

[0152] The summing module 92 is configured to add the output signals of the IQ mixers 88 and 90 to obtain the RF output signal s HF (f).

[0153] RF output signal HF (f) can be forwarded to the signal output terminal 20 of the electronic device 10.

[0154] Certain embodiments disclosed herein, in particular corresponding modules and / or units, utilize circuits (e.g., one or more circuits) to implement the standards, protocols, methods or techniques disclosed herein, operably couple two or more components, generate information, process information, analyze information, generate signals, encode / decode signals, convert signals, send and / or receive signals, control other devices, etc. Any type of circuit may be used.

[0155] In an embodiment, the circuit includes one or more computing devices, such as a processor (e.g., a microprocessor), a central processing unit (CPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a system on a chip (SoC), etc., or any combination thereof, and may include discrete digital or analog circuit elements or electronic devices, or a combination thereof. In an embodiment, the circuit includes a hardware circuit implementation (e.g., an implementation in an analog circuit, an implementation in a digital circuit, etc., and a combination thereof).

[0156] In an embodiment, the circuit includes a combination of a circuit and a computer program product having software or firmware instructions stored on one or more computer-readable memories that work together to cause a device to perform one or more protocols, methods, or techniques described herein. In an embodiment, the circuit includes circuits that require software, firmware, etc. to operate, such as, for example, a microprocessor or portion of a microprocessor. In an embodiment, the circuit includes one or more processors or portions thereof and accompanying software, firmware, hardware, etc.

[0157] The present application may quote quantities and numbers. Unless otherwise specified, these quantities and numbers are not considered to be restrictive, but examples of possible quantities or numbers associated with the present application. Also in this regard, the present application may use the term "plurality" to refer to quantities or numbers. In this regard, the term "plurality" refers to any number greater than one, for example, two, three, four, five, etc. The terms "approximately", "approximately", "close to", etc. refer to plus or minus 5% of the value.

Claims

1. A receiver equalizer module, the receiver equalizer module (14) comprising a signal input terminal (22), a first signal processing channel (24), a second signal processing channel (26) and a filter module (48), wherein: The first signal processing channel (24) and the second signal processing channel (26) are respectively connected to the signal input terminal (22). The first signal processing channel (24) comprises a first analog-to-digital converter (36) and a first digital down-converter (38) arranged downstream of the first analog-to-digital converter (36), wherein the first analog-to-digital converter (36) is configured to digitize the signal processed by the first signal processing channel (24) to obtain a first digitized signal, and wherein the first digital down-converter (38) is configured to down-convert the first digitized signal or a processed version of the first digitized signal to obtain a first down-converted signal, The second signal processing channel (26) comprises a second analog-to-digital converter (44) and a second digital down-converter (46) arranged downstream of the second analog-to-digital converter (44), wherein the second analog-to-digital converter (44) is configured to digitize the signal processed by the second signal processing channel (26) to obtain a second digitized signal, and wherein the second digital down-converter (46) is configured to down-convert the second digitized signal or a processed version of the second digitized signal to obtain a second down-converted signal, and The filter module (48) is connected to the signal processing channel downstream of the digital down converter.

2. The receiver equalizer module according to claim 1, wherein: The filter module (48) is configured to equalize the first down-converted signal and the second down-converted signal.

3. The receiver equalizer module of claim 2, wherein: The filter module (48) is configured to equalize the first down-converted signal and the second down-converted signal such that crosstalk between the signal processing channels (24, 26) and / or imbalance between the signal processing channels (24, 26) are eliminated.

4. A receiver equalizer module according to any one of the preceding claims, wherein: The filter module (48) comprises a first filter submodule (50) connected to the first signal processing channel (24), and wherein the filter module (48) comprises a second filter submodule (52) connected to the second signal processing channel (26), in particular wherein the first filter submodule (50) and the second filter submodule (52) are respectively established as complex-valued filters.

5. The receiver equalizer module of claim 4, wherein: The filter module (48) includes a summing module (54) connected to each of the first filter submodule (50) and the second filter submodule (52), wherein the summing module (54) is configured to add output signals of the filter submodules (50, 52).

6. A receiver equalizer module according to any one of the preceding claims, wherein: The first signal processing channel (24) is configured to process an in-phase signal, and wherein the second signal processing channel (26) is configured to process a quadrature signal.

7. A transmitter equalizer module, the transmitter equalizer module (18) comprising a signal input terminal (56), a first signal processing channel (64), a second signal processing channel (68) and a filter module (58), wherein: The filter module (58) is connected to the signal input terminal (56), The first signal processing channel (64) comprises a first digital up-converter (70) and a first digital-to-analog converter (76) arranged downstream of the first digital up-converter (70), wherein the first digital up-converter (70) is configured to up-convert a digital signal processed by the first signal processing channel (64) to obtain a first up-converted signal, and wherein the first digital-to-analog converter (76) is configured to convert the first up-converted signal or a processed version of the first up-converted signal into a first analog signal, The second signal processing path (68) comprises a second digital up-converter (78) and a second digital-to-analog converter (80) arranged downstream of the second digital up-converter (78), wherein the second digital up-converter (78) is configured to up-convert the digital signal processed by the second signal processing path (68) to obtain a second up-converted signal, and wherein the second digital-to-analog converter (80) is configured to convert the second up-converter signal or a processed version of the second up-converted signal into a second analog signal, and Wherein the filter module (58) is connected to the signal processing path (64, 68) upstream of the digital up-converter (70, 78).

8. The transmitter equalizer module according to claim 7, wherein: The filter module (58) is configured to pre-equalize digital signals processed by the signal processing channel (64, 68).

9. The transmitter equalizer module according to claim 8, wherein: The filter module (58) is configured to pre-equalize the digital signals processed by the signal processing channels (64, 68) so that crosstalk between the signal processing channels (64, 68) and / or imbalance between the signal processing channels (64, 68) are eliminated.

10. The transmitter equalizer module according to any one of claims 7 to 9, wherein: The filter module (58) comprises a first filter submodule (62) connected to the first signal processing channel (64), and wherein the filter module (58) comprises a second filter submodule (66) connected to the second signal processing channel (68), in particular wherein the first filter submodule (62) and the second filter submodule (66) are respectively established as complex-valued filters.

11. The transmitter equalizer module of claim 10, wherein: The filter module (58) includes a splitter module (60) connected to each of the first filter sub-module (62) and the second filter sub-module (66), wherein the splitter module (60) is configured to forward a signal received via the signal input terminal (56) to the filter sub-modules (62, 66).

12. The transmitter equalizer module according to any one of claims 7 to 11, wherein: The first signal processing channel (64) is configured to process an in-phase signal, and wherein the second signal processing channel (68) is configured to process a quadrature signal.

13. An electronic device, the electronic device (10) comprising a receiver equalizer module (14) according to any one of claims 1 to 6 and / or a transmitter equalizer module (18) according to any one of claims 7 to 12.

14. The electronic device according to claim 13, wherein: The electronic device (10) is constructed as a measuring instrument.

15. The electronic device according to claim 13, wherein: The electronic device (10) is established as a radio frequency (RF) receiver and / or an RF transmitter.

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