Memory, preparation method thereof and electronic equipment

Abstract

The invention relates to a memory and a preparation method thereof, and electronic equipment. The memory comprises a substrate; the stacking structure is located on the substrate, the stacking structure comprises conductive layers and dielectric layers, and the conductive layers and the dielectric layers are alternately stacked; the word line structure penetrates through the conductive layer and the dielectric layer; the semiconductor layer comprises a semiconductor part and an insulating part, the semiconductor part is located between the word line structure and the conducting layer, and the insulating part is located between the word line structure and the dielectric layer. A semiconductor layer is formed on the hole wall of a word line hole, a protection layer covers the part, located at a conducting layer, of the semiconductor layer, in the annealing process, an insulating layer is formed on the part, located at a dielectric layer, of the semiconductor layer, and meanwhile the oxygen vacancy concentration of the semiconductor layer covered by the protection layer is kept unchanged through the protection layer. And the properties of the semiconductor are still retained.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a memory and a preparation method thereof, and an electronic device. Background Art

[0002] Among semiconductor devices, semiconductor devices with vertical word line structures are prone to parasitic transistors, and the channel region of the parasitic transistors may cause leakage problems, thus affecting the normal operation of the semiconductor device.

[0003] However, as semiconductor devices shrink, it becomes increasingly difficult to remove parasitic transistors. Summary of the invention

[0004] Based on this, it is necessary to provide a memory and a method for preparing the memory to address the difficulty of removing parasitic transistors in the prior art.

[0005] In order to achieve the above objectives, on the one hand, the present application provides a memory, including:

[0006] substrate;

[0007] A stacking structure, located on the substrate, comprising a conductive layer and a dielectric layer, wherein the conductive layer and the dielectric layer are alternately stacked in a direction away from the substrate;

[0008] A word line structure, running through the conductive layer and the dielectric layer;

[0009] The semiconductor layer comprises a semiconductor portion and an insulating portion which are connected to each other. The semiconductor portion is located between the word line structure and the conductive layer, and the insulating portion is located between the word line structure and the dielectric layer.

[0010] In one embodiment, the semiconductor portion has an oxygen vacancy concentration greater than that of the insulating portion.

[0011] In one embodiment, the oxygen vacancy concentration of the semiconductor portion is greater than 15%, and the oxygen vacancy concentration of the insulating portion is less than 5%.

[0012] In one embodiment, the material of the semiconductor layer includes indium gallium zinc oxide.

[0013] In one embodiment, the memory includes a word line hole, the word line structure is located in the word line hole, the word line hole includes a word line through hole and a word line side hole, the word line through hole passes through the conductive layer and the dielectric layer, the word line side hole is connected to the word line through hole, the word line side hole is located in the conductive layer, and the semiconductor part is located on the hole wall of the word line side hole.

[0014] In one embodiment, the memory comprises:

[0015] An etch stop layer is located between the semiconductor layer and the word line structure, and the material of the etch stop layer includes silicon oxide.

[0016] In one embodiment, the etch stop layer covers the surface of the semiconductor layer, and the etch stop layer forms a first protrusion at the position of the conductive layer, and the first protrusion protrudes in a direction away from the word line structure.

[0017] In one embodiment, the word line structure forms a second protrusion at the conductive layer, and the second protrusion is at least partially located within the first protrusion.

[0018] In one embodiment, a capacitor region and a device region are provided on the substrate, and the word line hole is located in the device region.

[0019] The memory comprises:

[0020] The capacitor structure includes a capacitor dielectric layer and a capacitor outer plate, wherein the capacitor dielectric layer surrounds the surface of the conductive layer located in the capacitor area, the conductive layer serves as a capacitor inner plate, and the capacitor outer plate surrounds the surface of the capacitor dielectric layer.

[0021] In one embodiment, the capacitor dielectric layer and the capacitor outer plate are also located above the stacked structure;

[0022] The memory comprises:

[0023] The filling dielectric layer is located in the device region and penetrates the capacitor dielectric layer and the capacitor outer plate.

[0024] In one embodiment, the stacking structure includes a main body and a branch portion, the main body extends along a first direction, the branch portion extends along a second direction, the second direction intersects the first direction, a plurality of the branch portions are arranged on the main body along the first direction, and two of the branch portions are symmetrically arranged on both sides of the main body along the second direction;

[0025] The device region includes a first sub-region and a second sub-region located on both sides of the first sub-region, the branch portion includes a first sub-portion and a second sub-portion, the first sub-portion is located in the second sub-region, the second sub-portion is located in the capacitor region, and the main portion is located in the first sub-region;

[0026] The conductive layer of the trunk portion forms a bit line structure.

[0027] In one embodiment, the word line structure comprises:

[0028] word line;

[0029] The gate dielectric layer is located between the word line and the semiconductor layer.

[0030] On the other hand, the present application also provides a method for preparing a memory, comprising the following steps:

[0031] providing a substrate;

[0032] Alternating conductive material layers and dielectric material layers on the substrate to form a stacked structure;

[0033] Etching the stacked structure to form a word line hole, the remaining conductive material layer forms a conductive layer, and the remaining dielectric material layer forms a dielectric layer, the word line hole includes a word line through hole, and the word line through hole penetrates the conductive material layer and the dielectric material layer;

[0034] forming a semiconductor layer on the hole wall of the word line hole, and forming a protection layer covering the semiconductor layer at the position of the conductive layer;

[0035] Performing thermal annealing on the structure after the protective layer is formed, so that the portion of the semiconductor layer located at the position of the dielectric layer forms an insulating portion;

[0036] The protection layer is removed, and a word line structure is formed in the word line hole.

[0037] In one embodiment, the word line hole further comprises a word line side hole;

[0038] The etching of the stack structure to form a word line hole comprises:

[0039] Etching the conductive layer and the dielectric layer to form the word line through hole;

[0040] From the side wall of the word line through hole, etching back the conductive layer to form the word line side hole;

[0041] The semiconductor layer is formed on the hole wall of the word line hole, and a protection layer covering the semiconductor layer and located at the position of the conductive layer is formed, including:

[0042] forming the semiconductor layer on the hole wall of the word line through hole and the hole wall of the word line side hole;

[0043] The protection layer is filled in the word line side hole where the semiconductor layer is formed.

[0044] In one embodiment, before the protective layer is filled in the word line side hole formed with the semiconductor layer, the method includes:

[0045] forming an etching stop layer on the surface of the semiconductor layer;

[0046] Filling the protective layer in the word line side hole formed with the semiconductor layer comprises:

[0047] forming the protective material layer on the surface of the etch stop layer;

[0048] The protection material layer outside the word line side hole is removed, and the remaining protection material layer forms the protection layer.

[0049] In one embodiment, removing the protection material layer outside the word line side hole includes:

[0050] Thinning the protection material layer outside the word line side hole by a first etching;

[0051] The thinned protection material layer outside the word line side hole is removed by a second etching, wherein the etching accuracy of the second etching is greater than the etching accuracy of the first etching.

[0052] In one embodiment, a capacitor region and a device region are provided on the substrate, and the word line hole is located in the device region.

[0053] Before etching the stack structure to form a word line hole, the method includes:

[0054] removing the dielectric material layer located in the capacitor region;

[0055] A capacitor dielectric layer and a capacitor outer plate are formed in sequence on the surface of the conductive material layer located in the capacitor region, and the conductive material layer serves as a capacitor inner plate, thereby forming a capacitor structure.

[0056] In one embodiment, while forming the capacitor dielectric layer and the capacitor outer plate in sequence on the surface of the conductive material layer located in the capacitor region, the capacitor dielectric layer and the capacitor outer plate are formed on the upper surface of the structure obtained after removing the dielectric material layer;

[0057] Before etching the stack structure to form a word line hole, the method further includes:

[0058] Removing the capacitor dielectric layer and the capacitor outer plate located in the device area and on the upper surface of the obtained structure to form a groove;

[0059] Filling the trench to form a filling dielectric material layer;

[0060] The etching of the stack structure to form a word line hole comprises:

[0061] In the device region, the filling dielectric material layer, the conductive layer and the dielectric layer are sequentially etched to form the word line through hole, and the remaining filling dielectric material layer forms a filling dielectric layer.

[0062] In one embodiment, the stacking structure includes a main body and a branch portion, the main body extends along a first direction, the branch portion extends along a second direction, the second direction intersects the first direction, a plurality of the branch portions are arranged on the main body along the first direction, and two of the branch portions are symmetrically arranged on both sides of the main body along the second direction.

[0063] The device region includes a first sub-region and a second sub-region located on both sides of the first sub-region, the branch portion includes a first sub-portion and a second sub-portion, the first sub-portion is located in the second sub-region, the second sub-portion is located in the capacitor region, and the main portion is located in the first sub-region.

[0064] The conductive layer of the trunk portion forms a bit line structure.

[0065] In one embodiment, removing the protection layer and forming a word line structure in the word line hole includes:

[0066] forming a gate dielectric layer on the hole wall of the word line hole after removing the protective layer;

[0067] A word line is formed on the surface of the gate dielectric layer, and the word line fills the word line hole.

[0068] On the other hand, the present application also provides an electronic device, including: a logic circuit and the aforementioned memory, wherein the word line structure is connected to the logic circuit.

[0069] In the memory and its preparation method, and electronic device of the present invention, a semiconductor layer is formed on the hole wall of the word line hole, and a protective layer is formed covering the portion of the semiconductor layer located at the position of the conductive layer. During the annealing process, the oxygen vacancy concentration of the portion of the semiconductor layer located at the position of the dielectric layer gradually decreases, and finally an insulating portion is formed. At the same time, the protective layer keeps the oxygen vacancy concentration of the semiconductor layer covered by it unchanged, and the semiconductor properties are still retained. The process steps for eliminating parasitic transistors in the present application are simple, and the remaining structures will not be damaged during the process, so a semiconductor device without parasitic transistors can be easily obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0071] Figure 1 is a flow chart of a method for preparing a memory provided in an embodiment;

[0072] Figure 2A schematic diagram of a conductive original layer and a dielectric original layer of a memory provided in an embodiment;

[0073] Figure 3a is a three-dimensional diagram of a stacked structure of a memory provided in an embodiment;

[0074] Figure 3b is a cross-sectional view of a stacked structure of a memory provided in an embodiment along the BB' direction;

[0075] Figure 4a and Figure 4b A schematic diagram of a capacitor region and a device region of a memory provided in different embodiments;

[0076] Figure 5a A three-dimensional diagram of a stacked structure of a memory provided in an embodiment after filling;

[0077] Figure 5b A cross-sectional view of a structure obtained after filling a stacked structure of a memory provided in an embodiment along the AA' direction;

[0078] Figure 5c A cross-sectional view of a structure obtained after filling the stacked structure of a memory provided in an embodiment along the BB' direction;

[0079] Figure 6a A three-dimensional diagram of a structure obtained after etching a dielectric material layer of a memory provided in an embodiment;

[0080] Figure 6b It is a cross-sectional view along the AA' direction of a structure obtained after etching the dielectric material layer of a memory provided in an embodiment;

[0081] Figure 6c It is a cross-sectional view along the BB' direction of a structure obtained after etching the dielectric material layer of a memory provided in an embodiment;

[0082] Figure 7a A three-dimensional diagram of a structure obtained after preparing a capacitor structure of a memory provided in an embodiment;

[0083] Figure 7b A cross-sectional view of a structure obtained after preparing a capacitor structure of a memory provided in an embodiment along the AA' direction;

[0084] Figure 7c A cross-sectional view of a structure obtained after preparing a capacitor structure of a memory provided in an embodiment along the BB' direction;

[0085] Figure 8a A three-dimensional diagram of a structure obtained after forming a word line hole of a memory provided in an embodiment;

[0086] Figure 8bis a cross-sectional view of a structure obtained after forming a word line hole of a memory provided in an embodiment along the AA' direction;

[0087] Figure 8c A cross-sectional view of a structure obtained after forming a word line hole of a memory provided in an embodiment along the BB' direction;

[0088] Figure 9a A three-dimensional diagram of a structure obtained after forming a protective material layer of a memory provided in an embodiment;

[0089] Figure 9b A cross-sectional view of a structure obtained after forming a protective material layer of a memory provided in an embodiment along the AA' direction;

[0090] Fig.9c A cross-sectional view of a structure obtained after forming a protective material layer of a memory provided in an embodiment along the BB' direction;

[0091] Fig.10a is a three-dimensional diagram of a structure obtained after annealing of a memory provided in an embodiment;

[0092] Fig.10b is a cross-sectional view along the AA' direction of a structure obtained after annealing of a memory provided in an embodiment;

[0093] Fig.10c is a cross-sectional view along the BB' direction of a structure obtained after annealing of a memory provided in an embodiment;

[0094] Fig.11a A three-dimensional diagram of a structure obtained after forming a word line structure of a memory provided in an embodiment;

[0095] Fig.11b A cross-sectional view of a structure along the AA' direction obtained after forming a word line structure of a memory provided in an embodiment;

[0096] Fig.11c It is a cross-sectional view of the structure along the BB' direction obtained after forming the word line structure of the memory provided in one embodiment.

[0097] Description of reference numerals: substrate-10; capacitor region-11; device region-12; first sub-region-121; second sub-region-122; stacked structure-20; conductive material layer-21; conductive layer-210; conductive original layer-2100; dielectric material layer 22; dielectric layer-220; dielectric original layer-2200; trunk portion-23; branch portion-24; first sub-portion 241; second sub-portion 242; isolation layer-30; support structure-31; word line hole-40; word line through hole-41; word line side hole- 42; semiconductor layer-50; insulating portion-51; semiconductor portion 52; protective layer-60; protective material layer-600; word line structure-70; gate dielectric layer-71; word line-72; etching barrier layer-80; capacitor structure-90; capacitor dielectric layer-91; capacitor external plate-92; titanium layer-921; polysilicon layer-922; filling dielectric material layer 110; filling dielectric layer 111; bit line structure-120; first mask layer-300; second mask layer-310; fourth mask layer-320. DETAILED DESCRIPTION

[0098] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0099] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0100] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, or connected to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0101] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0102] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0103] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of idealized embodiments (and intermediate structures) of the invention, and variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.

[0104] In one embodiment, see Figure 1 , a method for preparing a memory is provided, comprising the following steps:

[0105] Step S100: providing a substrate 10 .

[0106] Step S200 : alternately arranging conductive material layers 21 and dielectric material layers 22 on the substrate 10 to form a stacked structure 20 .

[0107] Step S400 : etching the stacked structure to form a word line hole 40 , the remaining conductive material layer 21 forms a conductive layer 210 , and the remaining dielectric material layer 22 forms a dielectric layer 220 . The word line hole 40 includes a word line through hole 41 , and the word line through hole 41 penetrates the conductive material layer 21 and the dielectric material layer 22 .

[0108] Step S500 : forming a semiconductor layer 50 on the hole wall of the word line hole 40 , and forming a protection layer 60 covering the semiconductor layer 50 at a position of the conductive layer 21 .

[0109] Step S600 : performing a thermal annealing process on the structure after the protective layer 60 is formed, so that the portion of the semiconductor layer 50 located at the position of the dielectric layer 31 forms an insulating portion 51 .

[0110] Step S700 : removing the protection layer 60 , and forming a word line structure 70 in the word line hole 40 .

[0111] In step S100, refer to Figure 2 The substrate 10 may be made of semiconductor material, insulating material or any combination thereof. The substrate 10 may be a single-layer structure or a multi-layer structure. As an example, the substrate 10 may include a silicon substrate, a silicon germanium substrate, a silicon germanium carbon substrate or other III / V semiconductor substrates or II / VI semiconductor substrates.

[0112] In step S200, refer to Figure 3a to Figure 3b , the material of the conductive material layer 21 can be metal. For example, the material of the conductive material layer 21 can be copper, tungsten or alloy and other conductive materials. Multiple layers of conductive material layers 21 are arranged on the substrate 10, and the thickness of the multiple layers of conductive material layers 21 can be 40nm-60nm. The above data are only used as examples, and the thickness of the conductive material layer 21 in actual embodiments is not limited to the above data.

[0113] The material of the dielectric material layer 22 is an insulating material. For example, the material of the dielectric material layer 22 can be silicon dioxide, silicon nitride, silicon oxynitride, or the like. Similarly, a plurality of dielectric material layers 22 are provided on the substrate 10, and the thickness of the plurality of dielectric material layers 22 can be 40nm-60nm. It can be understood that the thickness of the dielectric material layer 22 can be consistent with the thickness of the conductive material layer 21. Of course, the thickness of the dielectric material layer 22 can also be inconsistent with the thickness of the conductive material layer 21.

[0114] Multiple conductive material layers 21 and multiple dielectric material layers 22 are alternately stacked on the substrate 10 to form a stacked structure 20. As an example, a bottom dielectric material layer may be first deposited on the substrate 10, and then the bottom conductive material layer 21 may be deposited on the bottom dielectric material layer. The deposition process for forming the conductive material layer 21 and the dielectric material layer 22 may include, but is not limited to, one or more of a chemical vapor deposition process, an atomic layer deposition process, a high-density plasma deposition process, a plasma enhanced deposition process, and a spin-coating dielectric material layer.

[0115] The above process is repeated until the number of conductive material layers 21 and dielectric material layers 22 meet the requirements. At this time, the top film layer can be the dielectric material layer 22 to protect the underlying film layers.

[0116] In step S400, refer to Figures 8a to 8c When etching the stacked structure 20, a first mask layer 300 may be formed on the stacked structure 20, the first mask layer 300 exposes the word line hole 40, and the stacked structure 20 is etched based on the first mask layer 300. When etching, dry etching or wet etching may be used. For example, any one of reactive ion etching, inductively coupled plasma etching or high concentration plasma etching may be used during dry etching.

[0117] After etching the conductive material layer 21 and the dielectric material layer 22, a word line hole 40 is formed in the stacked structure 20. The word line hole 40 is used to form a word line structure in subsequent steps. At the same time, the remaining conductive material layer 21 and the dielectric material layer 22 form a conductive layer 210 and a dielectric layer 220 respectively.

[0118] The word line hole 40 includes a word line through hole 41. The word line through hole 41 extends from the top surface of the stacked structure 20 in the stacking direction until the substrate 10 is exposed. As an example, the aperture of the word line through hole 41 can be 60nm-80nm. For example, the aperture of the word line through hole 41 can be 70nm. The above data is only for example, and the width of the word line through hole 41 in the actual embodiment is not limited to the above data.

[0119] There may be a plurality of word line through holes 41. The plurality of word line through holes 41 are arranged at intervals. As an example, two word line through holes 41 may be formed in the stacked structure 20 in the same region.

[0120] In step S500, refer to Figures 9a to 9c as well as Figures 10a to 10c A semiconductor layer 50 may be deposited on the hole wall of the word line hole 40 , so that the semiconductor layer 50 covers the conductive layer 210 and the dielectric layer 220 exposed on the side wall of the word line through hole 41 .

[0121] The material of the semiconductor layer 50 may be a metal oxide. For example, the material of the semiconductor layer 50 may be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10-15A), thereby ensuring a low refresh rate of the memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0122] At this time, the thickness of IGZO can be 5nm-8nm. For example, the thickness of IGZO can be 6nm.

[0123] After the semiconductor layer 50 is formed, a protective layer 60 is formed at the position of the semiconductor layer 50 located at the conductive layer 210. The portion of the semiconductor layer 50 located at the conductive layer 210 includes the portion of the semiconductor layer 50 opposite to the conductive layer 210. At the same time, it can be understood that the portion of the semiconductor layer 50 located at the dielectric layer 220 includes the portion of the semiconductor layer 50 opposite to the dielectric layer 220, which is not covered by the protective layer 60.

[0124] The material of the protective layer 60 may be aluminum oxide, etc. At this time, as an example, the thickness of the aluminum oxide may be 15 nm to 19 nm. For example, the thickness of the aluminum oxide may be 17 nm.

[0125] In step S600, the structure after the protective layer 60 is formed is placed in an annealing process chamber, and a thermal annealing process is performed on the structure after the protective layer 60 is formed. For example, a rapid thermal annealing process is performed on the structure after the protective layer 60 is formed.

[0126] At this time, an oxygen-containing gas may be introduced into the annealing process chamber, and the temperature of the annealing process chamber may be controlled at a relatively low temperature (e.g., below 500°C), so that the oxygen vacancy concentration of the portion of the semiconductor layer 50 not covered by the protective layer 60 is reduced while protecting other portions of the semiconductor layer 50 from damage. For example, ozone gas may be introduced into the annealing process chamber, and the temperature of the annealing process chamber may be controlled at 400°C-500°C. Specifically, the temperature of the annealing process chamber may be 450°C. The above data are for example only, and the preset annealing temperature in the actual embodiment is not limited to the above data.

[0127] During the thermal annealing process, the portion of the semiconductor layer 50 located at the dielectric layer 220 (i.e., the portion of the semiconductor layer 50 not covered by the protective layer 60) is more easily oxidized. When the oxygen vacancy concentration is low enough, the semiconductor layer 50 in this portion becomes an insulating portion 51 having insulating properties. For example, referring to 10c, the C region represents the portion of the semiconductor layer 50 located at the conductive layer 210, and the D region represents the portion of the semiconductor layer 50 located at the dielectric layer 220. When the oxygen vacancy concentration is low enough, the semiconductor layer 50 in the D region becomes an insulating portion 51 having insulating properties.

[0128] At the same time, since the portion of the semiconductor layer 50 located at the conductive layer 210 is covered by the protective layer 60, the protective layer 60 prevents external oxygen atoms from entering the semiconductor layer 50, so that the oxygen vacancy concentration of this portion remains unchanged, and the semiconductor layer 50 of this portion still retains the semiconductor properties and forms a semiconductor portion 52. For example, referring to 10c, the semiconductor layer 50 in the C region still has semiconductor properties, and the C region is set as the semiconductor portion 52.

[0129] At this time, the oxygen vacancy concentration of the semiconductor portion 50 is greater than the oxygen vacancy concentration of the insulating portion 51. For example, the oxygen vacancy concentration of the film layer can be measured using X-ray photoelectron spectroscopy. When the material of the semiconductor layer 50 is IGZO, it can be considered that the oxygen vacancy concentration of the IGZO covered by the protective layer 60 is greater than 15% (for example, the oxygen vacancy concentration of the IGZO covered by the protective layer 60 is greater than 20%), and the oxygen vacancy concentration of the IGZO not covered by the protective layer 60 is less than 8% (for example, the oxygen vacancy concentration of the IGZO not covered by the protective layer 60 is less than 5%), the IGZO not covered by the protective layer 60 becomes the insulating portion 51 having insulating properties.

[0130] Of course, the oxygen vacancy concentration of the film layer can also be measured using methods such as hot wire measurement, thermal desorption spectroscopy or electron paramagnetic resonance.

[0131] In step S700, refer to Figures 11a to 11cThe protective layer 60 can be removed by dry etching or wet etching. For example, when wet etching is used, ammonia or hydrogen chloride is used to remove the protective layer 60, exposing the semiconductor layer 50 and the insulating portion 51.

[0132] The word line structure 70 may include a gate dielectric layer 71 and a word line 72. At this time, the gate dielectric layer 71 and the word line 72 may be sequentially deposited in the word line hole 40 after the protection layer 60 is removed to form the word line structure 70.

[0133] For example, see Figure 11a to Figure 11b , the word line structure 70 includes a gate dielectric layer 71 and a word line 72. At this time, step S700 includes:

[0134] Step S710 : forming a gate dielectric layer 71 on the hole wall of the word line hole 40 after removing the protection layer 60 .

[0135] Step S720 : forming a word line 72 on the surface of the gate dielectric layer 71 , and the word line 72 fills the word line hole 40 .

[0136] In step S710, a gate dielectric layer 71 is disposed at the bottom and sidewalls of the word line hole 40. As an example, the gate dielectric layer 71 may be formed by chemical vapor deposition.

[0137] The gate dielectric layer 71 may be made of a high-K material, such as aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, or tantalum oxide.

[0138] In step S720, the word line 40 forming the gate dielectric layer 71 is filled with a conductive material to form a word line 72. As an example, the material of the word line 72 is platinum, tungsten or titanium.

[0139] When the word line structure 70 has a voltage, the semiconductor layer 50 between the word line structure 70 and the conductive layer 210 retains semiconductor properties, so the part of the semiconductor layer 50 can form a vertical annular channel device structure (CAA, Channel-All-Around) transistor with the word line structure 70. At the same time, the two ends of the CAA transistor are connected to two parts of the same conductive layer 210 (the two parts of the conductive layer 210 can be used as the source and drain of the CAA transistor respectively), so as to have a horizontal channel. At the same time, the semiconductor layer 50 between the word line structure 70 and the dielectric layer 220 becomes an insulating part 51 with insulating properties, so the part of the semiconductor layer 50 will not form a parasitic transistor with the word line structure 70, so that a vertical channel will not be formed between adjacent conductive layers 210, so that leakage between adjacent conductive layers 210 can be prevented, and leakage between adjacent transistors can be effectively prevented.

[0140] In this embodiment, a semiconductor layer 50 is formed on the hole wall of the word line hole 40, and a protective layer 60 covering the semiconductor layer 50 and located at the position of the conductive material layer 21 is formed, and then a thermal annealing treatment is performed. During the thermal annealing process, the oxygen vacancy concentration of the portion of the semiconductor layer 50 located at the position of the dielectric layer 220 gradually decreases until it becomes the insulating portion 51. At the same time, the protective layer 60 keeps the oxygen vacancy concentration of the semiconductor layer 50 covered by it unchanged, and the semiconductor properties are still retained. In this embodiment, the process steps for eliminating the parasitic transistor are simple, and the remaining structures will not be damaged during the process, so that a semiconductor device without a parasitic transistor can be easily obtained.

[0141] In one embodiment, see Figures 10a to 10c , the word line hole 40 further includes a word line side hole 42, at this time, step S400 includes:

[0142] Step S410 : etching the conductive material layer 21 and the dielectric material layer 22 to form a word line through hole 41 .

[0143] Step S420 : etching back the conductive material layer 21 from the sidewall of the word line through hole 41 to form a word line side hole 42 .

[0144] Meanwhile, step S500 includes:

[0145] Step S510 : forming a semiconductor layer 50 on the hole wall of the word line through hole 41 and the hole wall of the word line side hole 42 .

[0146] Step S530 : forming a protection layer 60 in the word line side hole 42 where the semiconductor layer 50 is formed, and the protection layer 60 fills the word line side hole 42 .

[0147] In step S410 , the conductive material layer 21 and the dielectric material layer 22 are etched to form a word line through hole 41 .

[0148] In step S420 , the hole wall of the word line through hole 41 exposes the conductive material layer 21 and the dielectric material layer 22 . In the word line through hole 41 , the conductive material layer 21 exposed by the word line through hole 41 is etched back to form a word line side hole 42 in the conductive material layer 21 .

[0149] Furthermore, it can be considered that the word line side hole 42 is recessed into the conductive layer 210 .

[0150] Since the stacked structure 20 includes multiple conductive material layers 21 , a plurality of word line side holes 42 spaced apart may be formed when forming the word line side holes 42 . It can be understood that the word line through hole 41 is connected to the plurality of word line side holes 42 .

[0151] Meanwhile, as an example, the word line side hole 42 surrounds the word line through hole 41. At this time, the conductive material layer 21 can be cut through the word line side hole 42, so that the semiconductor layer 50 subsequently formed in the annular word line side hole 42 serves as the channel region of the transistor, and the conductive material layer 21 (i.e., the conductive layer 210) cut on both sides of the word line side hole 42 serves as the source and drain of the transistor respectively.

[0152] As an example, the diameter of the word line side hole 42 may be 40 nm-60 nm. For example, the diameter of the word line side hole 42 may be 50 nm. The above data are only examples, and in actual embodiments, the width of the word line side hole 42 is not limited to the above data.

[0153] In step S510 , the semiconductor layer 50 may be deposited simultaneously on the hole walls of the word line through hole 41 and the hole walls of the word line side hole 42 .

[0154] In step S530 , a protection layer 60 is formed in the word line side hole 42 where the semiconductor layer 50 is formed, and the protection layer 60 fills up the word line side hole 42 .

[0155] During the thermal annealing process, the performance of the semiconductor layer 50 in the word line side hole 42 does not change because the protection layer 60 is filled in the word line side hole 42. Outside the word line side hole 42, there is no protection of the protection layer 60, and the oxygen vacancy concentration of the semiconductor layer 50 gradually decreases. When the oxygen vacancy concentration is low enough, the semiconductor layer 50 in this part becomes the insulating portion 51.

[0156] In this embodiment, by forming the word line side hole 42 , it is convenient to form the protection layer 60 in the word line side hole 42 , thereby reducing the difficulty of preparing the protection layer 60 .

[0157] In one embodiment, see Figures 9a to 9c as well as Figures 10a to 10c , before step S530, including:

[0158] Step S520 : forming an etch stop layer 80 on the surface of the semiconductor layer 50 , wherein the material of the etch stop layer 80 includes silicon oxide.

[0159] Step S530 includes:

[0160] Step S531 : forming a protection material layer 600 on the surface of the etching stop layer 80 .

[0161] Step S532 : removing the protection material layer 600 outside the word line side hole 42 , and the remaining protection material layer 600 forms a protection layer 60 .

[0162] In step S520, an etch stop layer 80 may be deposited on the surface of the semiconductor layer 50. Similar to the semiconductor layer 50, the etch stop layer 80 is also formed in the word line through hole 41 and the word line side hole 42 at the same time.

[0163] The material of the etch stop layer 80 may also include silicon dioxide, etc. The thickness of the etch stop layer 80 may be 1 nm-3 nm. For example, the thickness of the etch stop layer 80 is 2 nm. The above data are only used as examples, and the thickness of the etch stop layer 80 in actual embodiments is not limited to the above data.

[0164] In step S531, a protective material layer 600 is deposited on the entire surface of the etching stop layer 80. The thickness of the protective material layer 600 may be 15 nm to 20 nm. As an example, when the material of the protective material layer 600 is aluminum oxide, its thickness is 17 nm.

[0165] At this time, the word line through hole 41 retains an opening with a certain aperture, that is, the protection material layer 600 does not fill the word line through hole 41. As an example, the word line through hole 41 may retain an opening of 20 nm.

[0166] In step S532 , the protection material layer 600 outside the word line side hole 42 is removed from the opening of the word line through hole 41 , and the protection material layer 600 in the word line side hole 42 is retained to form a protection layer 60 .

[0167] At this time, the hole wall of the word line side hole 42 is sequentially formed with the semiconductor layer 50, the etching stop layer 80 and the protection layer 60. At the same time, the hole wall of the word line through hole 41 opposite to the dielectric layer 220 is sequentially formed with the semiconductor layer 50 and the etching stop layer 80.

[0168] In this embodiment, since the etching stop layer 80 is formed, when removing the protection material layer 600 outside the word line side hole 42 , the etching gas or etching liquid stops etching when it contacts the etching stop layer 80 , thereby protecting the semiconductor layer 50 .

[0169] As an example, when the protective material layer 600 is deposited, the protective material layer 600 may be located not only on the surface of the semiconductor layer 50 but also on the top surface of the entire structure. At this time, when the protective material layer 600 outside the word line side hole 42 is removed, the protective material layer 600 on the top surface is also removed.

[0170] In one embodiment, step S532 includes:

[0171] Step S5321 : thinning the protection material layer 600 outside the word line side hole 42 through the first etching.

[0172] Step S5322: removing the thinned protection material layer 600 outside the word line side hole 42 through a second etching, wherein the etching accuracy of the second etching is greater than the etching accuracy of the first etching.

[0173] In step S5321 , most of the protective material layer 600 is removed first, and a thinner protective material layer 600 is retained.

[0174] As an example, the material of the protective material layer 600 is aluminum oxide, the thickness of the protective material layer 600 located on the hole wall of the word line through hole 41 is 14nm-20nm, and the first etching thins the protective material layer 600 to 3nm-7nm. For example, when the thickness of the protective material layer 600 located on the hole wall of the word line through hole 41 is 17nm, the first etching can thin the protective material layer 600 to 5nm.

[0175] In step S5322, the etching accuracy can be a controllable minimum etching thickness.

[0176] A more precise etching method is used for the second time to remove the remaining protection material layer 600 , thereby accurately removing the protection material layer 600 outside the word line side hole 42 .

[0177] As an example, the second etching method is an atomic layer etching process, and the remaining protection material layer 600 is etched until the hole wall of the word line through hole 41 is exposed.

[0178] In this embodiment, by using the step-by-step etching method, the etching efficiency can be improved through the first etching, and the damage to other parts during etching can be reduced through the second etching.

[0179] Of course, this embodiment only exemplifies a two-step etching method to remove the protective material layer 600 outside the word line side holes 42 . In actual embodiments, one or more etching steps may be used to remove the protective material layer 600 outside the word line side holes 42 .

[0180] In one embodiment, see Figure 4a to Figure 4b , a capacitor region 11 and a device region 12 are provided on the substrate 10, and the word line hole 40 is located in the device region 12. The capacitor region 11 is used to prepare a capacitor structure 90, and the device region 12 is used to prepare a transistor (not shown).

[0181] Also, see Figures 6a to 6c as well as Figures 7a to 7c , before step S400, including:

[0182] Step S300 : removing the dielectric material layer 22 located in the capacitor region 11 .

[0183] Step S310 : forming a capacitor dielectric layer 91 and a capacitor outer plate 92 surrounding each other in sequence on the surface of the conductive material layer 21 located in the capacitor region 11 , with the conductive material layer 21 serving as a capacitor inner plate, thereby forming a capacitor structure 90 .

[0184] In step S300, as an example, on the substrate 10, the capacitor region 11 is located on both sides of the device region 12. In a subsequent step, two word line holes 40 are formed in the device region 12 by etching.

[0185] Of course, the capacitor region 11 may also be located on a single side of the device region 12. At this time, a word line hole 40 may be formed in the device region 12 in subsequent steps.

[0186] When removing the dielectric material layer 22 located in the capacitor region 11, a second mask layer 310 may be formed on the upper surface of the obtained structure, and the second mask layer 310 exposes the device region 12. Based on the second mask layer 310, the dielectric material layer 22 located in the capacitor region 11 is removed, and the conductive material layer 21 located in the capacitor region 11 is retained.

[0187] In step S310, one or more of a chemical vapor deposition process, an atomic layer deposition process, a high-density plasma deposition process or a plasma enhanced deposition process can be used to sequentially deposit a capacitor dielectric layer 91 and a capacitor external electrode plate 92 on the surface of the conductive material layer 21 located in the capacitor area 11 to form a capacitor structure 90 in which the capacitor dielectric layer 91 and the capacitor external electrode plate 92 surround the conductive material layer 21 located in the capacitor area 11.

[0188] In the capacitor structure 90 , the conductive material layer 21 (or the conductive layer 210 ) located in the capacitor region 11 may be an inner capacitor plate, the outer capacitor plate 92 may be an upper capacitor plate, and the capacitor dielectric layer 91 may be located between the lower capacitor plate and the upper capacitor plate.

[0189] The material of the capacitor dielectric layer 91 can be a high-K material, and the material of the capacitor outer plate 92 can be titanium, titanium nitride or polysilicon. The capacitor dielectric layer 91 and the capacitor outer plate 92 can each include one layer or multiple layers. For example, the capacitor outer plate 92 includes two layers, namely a titanium nitride layer 921 and a polysilicon layer 922.

[0190] In one embodiment, during step S310 , a capacitor dielectric layer 91 and a capacitor outer plate 92 are formed on the upper surface of the structure obtained after removing the dielectric material layer 21 .

[0191] Before step S400, the method further includes:

[0192] Step S330: removing the capacitor dielectric layer 91 and the capacitor outer plate 92 located in the device region 12 and on the upper surface of the obtained structure to form a groove.

[0193] Step S331 : filling the trench to form a filling dielectric material layer 110 .

[0194] Step S400 includes:

[0195] Step S4100 : in the device region 12 , the filling dielectric material layer 110 , the conductive material layer 21 and the dielectric material layer 22 are sequentially etched to form a word line through hole 41 , and the remaining filling dielectric material layer 110 forms a filling dielectric layer 111 .

[0196] In step S330, a fourth mask layer may be formed on the upper surface of the obtained structure, and the third mask layer exposes the device region 12. Based on the third mask layer, the capacitor dielectric layer 91 and the capacitor outer plate 92 are etched to form a groove.

[0197] In step S331, the trench is filled with an insulating material to form a filling dielectric material layer 110. As an example, the material of the filling dielectric material layer 110 may include silicon or silicide.

[0198] The upper surface of the filling dielectric material layer 110 may be flush with the remaining capacitor dielectric layer 91 and the capacitor outer plate 92 located on the upper surface of the obtained structure. The flush surface can facilitate the formation of other structures thereon.

[0199] In step S4100, the word line via 41 is formed in the device region 12. At this time, the formation of the word line via 41 requires sequentially etching the filling dielectric layer 111, the conductive material layer 21 and the dielectric material layer 22 until the substrate is exposed.

[0200] In this embodiment, the filling dielectric layer 111 is formed first, so that in the subsequent steps, the word line structure 70 and the capacitor outer plate 92 located on the upper surface of the stacked structure are isolated by the filling dielectric layer 111 to prevent short circuit.

[0201] Of course, in this embodiment, the trench may be located in the device region 12 or may extend beyond the device region 12 , that is, the sidewall of the trench may be located in the capacitor region 11 .

[0202] In one embodiment, see Figure 4a to Figure 4b , the first direction is the X direction, and the second direction is the Y direction. As an example, the first direction is perpendicular to the second direction.

[0203] The stacking structure 20 includes a main body 23 and a branch 24. The branch 24 connects the main body 23. The main body 23 extends along a first direction, and the branch 24 extends along a second direction, the second direction intersects the first direction, and a plurality of branch 24 are arranged on the main body 23 along the first direction, and two branch 24 are symmetrically arranged on both sides of the main body 23 along the second direction.

[0204] At the same time, the device area 12 includes a first sub-area 121 and a second sub-area 122 located on both sides of the first sub-area 121, the branch portion 24 includes a first sub-portion 241 and a second sub-portion 242, the first sub-portion 241 is located in the second sub-portion 122, the second sub-portion 242 is located in the capacitor area 11, and the main body 23 is located in the first sub-region 121.

[0205] When the device region 12 is prepared as a transistor structure, the conductive layer 210 in the trunk 23 forms the bit line structure 120 of the transistor. The conductive layer 210 in the first sub-portion 241 forms the source and drain of the transistor. Meanwhile, the conductive layer 210 in the second sub-portion 242 forms the lower plate of the capacitor structure 90.

[0206] As an example, in step S200, a conductive original layer 2100 and a dielectric original layer 2200 that are alternately stacked can be formed on the substrate 10. The conductive original layer 2100 and the dielectric original layer 2200 can be formed on the entire surface of the substrate 10. Then, a fourth mask layer 320 is formed by etching on the conductive original layer 2100 and the dielectric original layer 2200, and the fourth mask layer 320 covers the film layer that needs to form the main body 23 and the branch part 24. Based on the fourth mask layer 320, the film layer in the uncovered area is removed to form a stacked structure 20.

[0207] Thereafter, an insulating material may be used to fill the removed area to form an isolation material layer. Thereafter, in the second direction, the isolation material layer located on both sides of the stacked structure 20 and a portion of the isolation material layer located at the end of the conductive material layer 21 are removed to form a support hole, and the remaining isolation material layer forms an isolation layer 30. The support hole is filled to form a support structure 31 located on both sides of the stacked structure 20, and the support structure 31 can support the conductive material layer 21.

[0208] As an example, the isolation layer 30 may include an oxide layer and a nitride layer. The material of the support structure 31 may include silicon oxide, silicon nitride or silicon oxynitride.

[0209] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0210] Based on the same inventive concept, in one embodiment, please refer to Figure 11a to Figure 11b , providing a memory. Fig.11b for Fig.11a The cross-sectional view of the structure along the AA' direction, Fig.11c for Fig.11a Cross-sectional view of the structure obtained along the BB' direction.

[0211] The memory includes a substrate 10 , a stack structure 20 , a semiconductor layer 50 and a word line structure 70 .

[0212] The substrate 10 may be made of semiconductor material, insulating material or any combination thereof.

[0213] The stacked structure 20 includes conductive layers 210 and dielectric layers 220 alternately stacked and arranged in a direction away from the substrate 10. The conductive layers 210 are made of metal, and the dielectric layers 220 are made of insulating materials.

[0214] A plurality of conductive layers 210 are disposed on the substrate 10, and the thickness of the plurality of conductive layers 210 can be 40 nm to 60 nm. Similarly, a plurality of dielectric layers 220 are disposed on the substrate 10, and the thickness of the plurality of dielectric layers 220 can be 40 nm to 60 nm. The above data are only used as examples, and the thickness of each layer in the actual embodiment is not limited to the above data.

[0215] The top film layer may be a dielectric layer 220 to protect the underlying film layers.

[0216] The word line structure 70 extends from the top surface of the stack structure 20 in the stacking direction to the substrate 10 .

[0217] The semiconductor layer 50 includes an insulating portion 51 and a semiconductor portion 52 connected to each other. The insulating portion 51 is located between the word line structure 70 and the dielectric layer 220. The semiconductor portion 52 is located between the word line structure 70 and the conductive layer 210.

[0218] The material of the semiconductor layer 50 may be a metal oxide. For example, the material of the semiconductor layer 50 may be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10-15A), thereby ensuring a low refresh rate of the memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0219] The IGZO may be a semiconductor material such as IGZO. At this time, the thickness of the IGZO may be 5 nm to 8 nm. For example, the thickness of the IGZO may be 6 nm.

[0220] The insulating portion 51 covers the dielectric layer 220 exposed by the sidewall of the word line through hole 41 . As an example, the material of the insulating portion 51 may also be IGZO or other materials. At this time, the oxygen vacancy concentration of the material of the insulating portion 51 is less than the oxygen vacancy concentration of the material of the semiconductor layer 50 .

[0221] For example, the oxygen vacancy concentration of the film layer can be measured using X-ray photoelectron spectroscopy. When the material of the semiconductor layer 50 is IGZO, it can be considered that when the oxygen vacancy concentration of the IGZO covered by the protective layer 60 is greater than 15% (for example, the oxygen vacancy concentration of the IGZO covered by the protective layer 60 is greater than 20%), and the oxygen vacancy concentration of the IGZO not covered by the protective layer 60 is less than 8% (for example, the oxygen vacancy concentration of the IGZO not covered by the protective layer 60 is less than 5%), the IGZO not covered by the protective layer 60 becomes an insulating portion 51 having insulating properties.

[0222] Of course, the oxygen vacancy concentration of the film layer can also be measured by hot wire measurement, thermal desorption spectroscopy or electron paramagnetic resonance.

[0223] The memory further includes a word line hole 40, and the word line structure 70 is located in the word line hole 40. As an example, the aperture of the word line hole 41 can be 60nm-80nm. For example, the aperture of the word line hole 41 can be 70nm. The above data is only used as an example, and in actual embodiments, the width of the word line hole 41 is not limited to the above data.

[0224] There may be a plurality of word line through holes 41. The plurality of word line through holes 41 are arranged at intervals. As an example, two word line through holes 41 may be formed in the stacked structure 20 in the same region.

[0225] The word line structure 70 includes a gate dielectric layer 71 and a word line 72 . The gate dielectric layer 71 is located between the word line 72 and the semiconductor layer 50 .

[0226] As an example, the material of the gate dielectric layer 71 may be a high-K material, such as aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, etc. The material of the word line 72 may be platinum, tungsten, or titanium, etc.

[0227] In this embodiment, when the word line structure 70 has a voltage, the semiconductor layer 50 between the word line structure 70 and the conductive layer 210 retains semiconductor properties, so the portion of the semiconductor layer 50 can form a CAA transistor with the word line structure 70. At the same time, since the semiconductor layer 50 between the word line structure 70 and the dielectric layer 220 becomes an insulating portion 51 with insulating properties, the portion of the semiconductor layer 50 will not form a parasitic transistor with the word line structure 70, and thus will not form a vertical channel between adjacent conductive layers 210, thereby preventing leakage between adjacent conductive layers 210, and further effectively preventing leakage between adjacent transistors.

[0228] In one embodiment, the word line hole 40 further includes a word line side hole 42 .

[0229] The word line side hole 42 is connected to the word line through hole 41. The word line side hole 42 is located in the conductive layer 210. Alternatively, it can be considered that the word line side hole 42 is recessed in the conductive layer 210. At this time, the semiconductor layer 50 is located on the hole wall of the word line side hole 42.

[0230] As an example, the diameter of the word line side hole 42 may be 40 nm-60 nm. For example, the diameter of the word line side hole 42 may be 50 nm. The above data are only examples, and in actual embodiments, the width of the word line side hole 42 is not limited to the above data.

[0231] In this embodiment, it can be considered that the protection layer 60 is recessed in the conductive layer 210. At this time, by forming the word line side hole 42, it is convenient to form the protection layer 60 in the word line side hole 42, and the difficulty of preparing the protection layer 60 is reduced.

[0232] In one embodiment, the memory includes an etch stop layer 80 .

[0233] The etch stop layer 80 is located between the insulating portion 51 and the word line structure 70 , and is also located between the semiconductor layer 50 and the word line structure 70 .

[0234] The etch stop layer 80 covers the surface of the semiconductor layer 50, and the etch stop layer 80 forms a first protrusion at the conductive layer 210, and the first protrusion protrudes in a direction away from the word line structure 70. At the same time, the word line structure 70 forms a second protrusion at the conductive layer 210, and the second protrusion is at least partially located in the first protrusion. Alternatively, the second protrusion is entirely located in the first protrusion.

[0235] For example, the first protrusion and the second protrusion may be located in the word line side hole 42 at the same time.

[0236] The material of the etch stop layer 80 may include silicon oxide or silicon dioxide. The thickness of the etch stop layer 80 may be 1 nm-3 nm. For example, the thickness of the etch stop layer 80 is 2 nm. The above data are only used as examples, and the thickness of the etch stop layer 80 in actual embodiments is not limited to the above data.

[0237] In one embodiment, a capacitor region 11 and a device region 12 are provided on the substrate 10, and the word line hole 40 is located in the device region 12. The capacitor region 11 is used to prepare a capacitor structure 90, and the device region 12 is used to prepare a transistor (not shown).

[0238] At this time, the memory further includes a capacitor structure 90. The capacitor structure 90 includes a capacitor dielectric layer 91 and a capacitor outer plate 92. The capacitor dielectric layer 91 and the capacitor outer plate 92 are sequentially surrounded on the surface of the conductive layer 210 located at 11.

[0239] The material of the capacitor dielectric layer 91 can be a high-K material, and the material of the capacitor outer plate 92 can be titanium, titanium nitride or polysilicon. The capacitor dielectric layer 91 and the capacitor outer plate 92 can each include one layer or multiple layers. For example, the capacitor outer plate 92 includes two layers, namely a titanium oxide layer 921 and a polysilicon layer 922.

[0240] In the capacitor structure 90 , the conductive material layer 21 (or the conductive layer 210 ) located in the capacitor region 11 is the inner plate of the capacitor, the outer plate 92 of the capacitor is the upper plate, and the capacitor dielectric layer 91 is located between the lower plate and the upper plate.

[0241] In one embodiment, the capacitor dielectric layer 91 and the capacitor outer plate 92 are also located on the upper surface of the obtained structure. At this time, the memory includes a groove and a filling dielectric layer 111 .

[0242] The trench is located in the device region 12 , and the trench penetrates the capacitor dielectric layer 91 and the capacitor outer plate 92 from the upper surface of the obtained structure.

[0243] The filling dielectric layer 111 is located in the trench. Meanwhile, the word line through hole 41 is formed in the device region 12, and the word line through hole 41 also penetrates the filling dielectric layer 111. The filling dielectric layer 111 can isolate the word line structure 70 from the capacitor outer plate 92 located on the upper surface of the obtained structure to prevent short circuit.

[0244] In one embodiment, see Figure 4a to Figure 4b , the first direction is the X direction, and the second direction is the Y direction. As an example, the first direction is perpendicular to the second direction. The stacked structure 20 includes a main body 23 and a branch 24, the main body 23 extends along the first direction, the branch 24 extends along the second direction, the second direction intersects the first direction, a plurality of branch 24 are arranged on the main body 23 along the first direction, and two branch 24 are symmetrically arranged on both sides of the main body 23 along the second direction.

[0245] At the same time, the device area 12 includes a first sub-area 121 and a second sub-area 122 located on both sides of the first sub-area 121, the branch portion 24 includes a first sub-portion 241 and a second sub-portion 242, the first sub-portion 241 is located in the second sub-portion 122, the second sub-portion 242 is located in the capacitor area 11, and the main body 23 is located in the first sub-region 121.

[0246] When the device region 12 is prepared as a transistor structure, the conductive layer 210 provided in the main body 23 forms the bit line structure 120 of the transistor. The conductive layer 210 provided in the first sub-portion 241 forms the source and drain of the transistor. At the same time, the conductive layer 210 provided in the second sub-portion 242 forms the lower plate of the capacitor structure 90.

[0247] This embodiment also provides an electronic device, which includes a logic circuit and the aforementioned memory. The logic circuit is connected to the word line structure 70. Of course, the logic circuit can also be connected to the bit line structure 120 and the like.

[0248] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0249] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A memory, characterized in that: include: substrate; A stacking structure, located on the substrate, comprising a conductive layer and a dielectric layer, wherein the conductive layer and the dielectric layer are alternately stacked in a direction away from the substrate; A word line structure, running through the conductive layer and the dielectric layer; The semiconductor layer comprises a semiconductor portion and an insulating portion which are connected to each other. The semiconductor portion is located between the word line structure and the conductive layer, and the insulating portion is located between the word line structure and the dielectric layer.

2. The memory according to claim 1, characterized in that: The semiconductor portion has an oxygen vacancy concentration greater than that of the insulating portion.

3. The memory according to claim 2, characterized in that: The semiconductor portion has an oxygen vacancy concentration greater than 15%, and the insulating portion has an oxygen vacancy concentration less than 5%.

4. The memory according to claim 3, characterized in that: The material of the semiconductor layer includes indium gallium zinc oxide.

5. The memory according to claim 1, characterized in that: The memory includes a word line hole, the word line structure is located in the word line hole, the word line hole includes a word line through hole and a word line side hole, the word line through hole penetrates the conductive layer and the dielectric layer, the word line side hole is connected to the word line through hole, the word line side hole is located in the conductive layer, and the semiconductor part is located on the hole wall of the word line side hole.

6. The memory according to claim 5, characterized in that: The memory comprises: An etch stop layer is located between the semiconductor layer and the word line structure, and the material of the etch stop layer includes silicon oxide.

7. The memory according to claim 6, characterized in that: The etch stop layer covers the surface of the semiconductor layer, and the etch stop layer forms a first protrusion at the position of the conductive layer, and the first protrusion protrudes in a direction away from the word line structure.

8. The memory according to claim 7, characterized in that: The word line structure forms a second protrusion at the conductive layer position, and the second protrusion is at least partially located inside the first protrusion.

9. The memory according to claim 1, characterized in that: The substrate is provided with a capacitor region and a device region, and the word line hole is located in the device region. The memory comprises: A capacitor dielectric layer and a capacitor outer plate, wherein the capacitor dielectric layer surrounds the surface of the conductive layer located in the capacitor region, the conductive layer serves as a capacitor inner plate, and the capacitor outer plate surrounds the surface of the capacitor dielectric layer.

10. The memory according to claim 9, characterized in that: The capacitor dielectric layer and the capacitor outer plate are also located above the stacked structure; The memory comprises: The filling dielectric layer is located in the device region and penetrates the capacitor dielectric layer and the capacitor outer plate.

11. The memory according to claim 9, characterized in that: The stacking structure comprises a main body and a branch part, wherein the main body extends along a first direction, and the branch part extends along a second direction, the second direction intersects the first direction, a plurality of the branch parts are arranged on the main body along the first direction, and two branch parts are symmetrically arranged on both sides of the main body along the second direction; The device region includes a first sub-region and a second sub-region located on both sides of the first sub-region, the branch portion includes a first sub-portion and a second sub-portion, the first sub-portion is located in the second sub-region, the second sub-portion is located in the capacitor region, and the main portion is located in the first sub-region; The conductive layer of the trunk portion forms a bit line structure.

12. The memory according to claim 1, characterized in that: The word line structure comprises: word line; The gate dielectric layer is located between the word line and the semiconductor layer.

13. A method for preparing a memory, characterized in that: The steps include: providing a substrate; Alternating conductive material layers and dielectric material layers on the substrate to form a stacked structure; Etching the stacked structure to form a word line hole, the remaining conductive material layer forms a conductive layer, and the remaining dielectric material layer forms a dielectric layer, the word line hole includes a word line through hole, and the word line through hole penetrates the conductive material layer and the dielectric material layer; forming a semiconductor layer on the hole wall of the word line hole, and forming a protection layer covering the semiconductor layer and located at the position of the conductive layer; Performing thermal annealing on the structure after the protective layer is formed, so that the portion of the semiconductor layer located at the position of the dielectric layer forms an insulating portion; The protection layer is removed, and a word line structure is formed in the word line hole.

14. The method for preparing a memory according to claim 13, characterized in that: The word line hole also includes a word line side hole; The etching of the stack structure to form a word line hole comprises: Etching the conductive layer and the dielectric layer to form the word line through hole; From the side wall of the word line through hole, etching back the conductive layer to form the word line side hole; The semiconductor layer is formed on the hole wall of the word line hole, and a protection layer covering the semiconductor layer and located at the position of the conductive layer is formed, including: forming the semiconductor layer on the hole wall of the word line through hole and the hole wall of the word line side hole; The protection layer is filled in the word line side hole where the semiconductor layer is formed.

15. The method for preparing a memory according to claim 14, characterized in that: Before the protective layer is filled in the word line side hole formed with the semiconductor layer, the method includes: forming an etch stop layer on the surface of the semiconductor layer, wherein the material of the etch stop layer includes silicon oxide; Filling the protective layer in the word line side hole formed with the semiconductor layer comprises: forming the protective material layer on the surface of the etch stop layer; The protection material layer outside the word line side hole is removed, and the remaining protection material layer forms the protection layer.

16. The method for preparing a memory according to claim 15, characterized in that: The removing of the protection material layer outside the word line side hole comprises: Thinning the protection material layer outside the word line side hole by a first etching; The thinned protection material layer outside the word line side hole is removed by a second etching, wherein the etching accuracy of the second etching is greater than the etching accuracy of the first etching.

17. The method for preparing a memory according to claim 13, characterized in that: The substrate is provided with a capacitor region and a device region, and the word line hole is located in the device region. Before etching the stack structure to form a word line hole, the method includes: removing the dielectric material layer located in the capacitor region; A capacitor dielectric layer and a capacitor outer plate are formed in sequence on the surface of the conductive material layer located in the capacitor region, and the conductive material layer serves as a capacitor inner plate, thereby forming a capacitor structure.

18. The method for preparing a memory according to claim 17, characterized in that: While forming the capacitor dielectric layer and the capacitor outer plate in sequence on the surface of the conductive material layer located in the capacitor region, the capacitor dielectric layer and the capacitor outer plate are formed on the upper surface of the structure obtained after removing the dielectric material layer; Before etching the stack structure to form a word line hole, the method further includes: Removing the capacitor dielectric layer and the capacitor outer plate located in the device area and on the upper surface of the obtained structure to form a groove; Filling the trench to form a filling dielectric material layer; The etching of the stack structure to form a word line hole comprises: In the device region, the filling dielectric material layer, the conductive layer and the dielectric layer are sequentially etched to form the word line through hole, and the remaining filling dielectric material layer forms a filling dielectric layer.

19. The method for preparing a memory according to claim 17, characterized in that: The stacking structure includes a main body and a branch part, wherein the main body extends along a first direction, and the branch part extends along a second direction, the second direction intersects the first direction, a plurality of the branch parts are arranged on the main body along the first direction, and two of the branch parts are symmetrically arranged on both sides of the main body along the second direction. The device region includes a first sub-region and a second sub-region located on both sides of the first sub-region, the branch portion includes a first sub-portion and a second sub-portion, the first sub-portion is located in the second sub-region, the second sub-portion is located in the capacitor region, and the main portion is located in the first sub-region. The conductive layer of the trunk portion forms a bit line structure.

20. The method for preparing a memory according to claim 13, characterized in that: The protective layer is removed, and a word line structure is formed in the word line hole, including: forming a gate dielectric layer on the hole wall of the word line hole after removing the protective layer; A word line is formed on the surface of the gate dielectric layer, and the word line fills the word line hole.

21. An electronic device, characterized in that: include: A logic circuit and a memory as claimed in any one of claims 1 to 12, wherein the word line structure is connected to the logic circuit.

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