Semiconductor memory structure and forming method thereof
By forming a multi-layer high-dielectric material structure in the DRAM device and performing an annealing process, the short-circuit problem caused by high tensile stress of the capacitive dielectric film is solved, and the manufacturing yield and device density are improved.
Patent Information
- Application Number
- CN202410002130.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-15
- Filing Date
- 2024-01-02
- Publication Date
- 2025-02-21
AI Technical Summary
The existing DRAM devices have shortcomings in device density and overall performance, and during the miniaturization of device size, the high tension stress of the capacitor leads to a short circuit that reduces the manufacturing yield.
By forming a multi-layer high-dielectric dielectric material structure in the semiconductor memory structure, including depositing a first high-dielectric dielectric material, a second high-dielectric dielectric material and a third high-dielectric dielectric material, And annealing process is performed during this process to release the tension stress of the dielectric film.
It effectively reduces the risk of short circuits between capacitors, improves the manufacturing yield of semiconductor memory devices, and improves device density and overall performance.
Smart Images
Figure CN119497375A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor memory structure and a forming method thereof, and in particular to a dynamic random access memory and a forming method thereof. Background Art
[0002] In order to increase the device density in a dynamic random access memory (DRAM) device and improve its overall performance, the current DRAM device manufacturing technology continues to strive towards miniaturization of device size. Therefore, improving the manufacturing method of DRAM devices is an important issue that must be faced at present. Summary of the invention
[0003] The present invention provides a method for forming a semiconductor memory structure. The method includes forming a bottom electrode layer on an active region, depositing a first high-k dielectric material on the bottom electrode layer, depositing a second high-k dielectric material on the first high-k dielectric material, performing an annealing process on the first high-k dielectric material and the second high-k dielectric material, and after the annealing process, depositing a third high-k dielectric material on the second high-k dielectric material; and forming a top electrode layer on the third high-k dielectric material.
[0004] An embodiment of the present invention provides a semiconductor memory structure. The semiconductor memory structure includes a transistor disposed on a substrate, a bottom electrode layer disposed on the transistor and electrically connected to a first source / drain region of the transistor, and a capacitor dielectric film. The capacitor dielectric film includes a first zirconium oxide layer, an aluminum oxide layer, and a second zirconium oxide layer sequentially disposed on the bottom electrode layer. The grains of the zirconium oxide layer have a first average size, the grains of the second zirconium oxide layer have a second average size, and the first average size is greater than the second average size. The semiconductor memory structure also includes a top electrode layer disposed on the capacitor dielectric film.
[0005] The present invention can reduce the risk of short circuit between capacitors, thereby improving the manufacturing yield of semiconductor memory devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] In order to make the features and advantages of the present invention more clearly understood, different embodiments are described in detail below with reference to the accompanying drawings:
[0007] Figure 1A FIG. 4 is a schematic plan view showing a semiconductor memory structure according to some embodiments of the present invention.
[0008] Figure 1B is a cross-sectional schematic diagram showing a semiconductor memory structure according to some embodiments of the present invention.
[0009] Figures 2 to 5 and Figure 7 Schematic cross-sectional views showing some intermediate stages of forming a semiconductor memory structure according to some embodiments of the present invention.
[0010] FIG. 6A to FIG. 6C Some details of forming a capacitor dielectric film are described according to some embodiments of the present invention.
[0011] Figure Number:
[0012] 100:Semiconductor memory structure
[0013] 102: Base
[0014] 104: Active Zone
[0015] 110: Contact plug
[0016] 112: Conductive pad
[0017] 114: Dielectric structure
[0018] 116: Sacrificial layer
[0019] 118: Opening
[0020] 120: bottom electrode layer
[0021] 122: Capacitor dielectric film
[0022] 122S1: Inner surface
[0023] 122S2: Outer surface
[0024] 124: The first high dielectric constant dielectric material
[0025] 124G, 124G', 128G: Grain
[0026] 126: Second highest dielectric constant dielectric material
[0027] 128: The third highest dielectric constant dielectric material
[0028] 130: Top electrode layer
[0029] 132: Protective layer
[0030] 1000: Annealing process
[0031] BL: Bit Line Structure
[0032] CA: Capacitor structure
[0033] D1: First direction
[0034] D2: Second direction
[0035] D3: Third direction
[0036] WL: Word Line DETAILED DESCRIPTION
[0037] Figure 1A and Figure 1B are respectively a plan view and a cross-sectional view showing a semiconductor memory structure 100, wherein Figure 1B Corresponds to Figure 1A Line II in the middle. For the sake of brevity and clarity, Figure 1A Only some components of the semiconductor memory structure 100 are shown, and other components of the semiconductor memory structure 100 can be seen in Figure 1B .
[0038] A semiconductor memory structure 100 is provided, which may be or include a dynamic random access memory (DRAM) device. The semiconductor memory structure 100 includes a substrate 102. The substrate 102 may be or include a semiconductor substrate, which may be an elemental semiconductor substrate (eg, a silicon substrate) or a compound semiconductor substrate.
[0039] For ease of explanation, Figure 1A Indicates the reference direction. Directions D1, D2 and D3 are horizontal directions. The second direction D2 is substantially perpendicular to the third direction D3. An acute angle is formed between the first direction D1 and the second direction D2. Line II is parallel to the second direction D2.
[0040] The semiconductor memory structure 100 further includes a plurality of active regions 104 extending in a first direction D1. Each active region 104 can be defined as a plurality of channel regions and a plurality of source / drain regions, and the channel regions and the source / drain regions are alternately arranged in the first direction D1. For example, two first source / drain regions are located at two ends of the active region 104, a second source / drain region is located in the center of the active region 104, and the two channel regions are sandwiched between the first source / drain region and the second source / drain region.
[0041] The semiconductor memory structure 100 further includes a plurality of word lines WL buried in the substrate 102. The word lines WL extend in the second direction D2 and pass through the channel region of the active region 104. The word lines WL function as gate structures, which are combined with the source / drain regions of the active region 104 to form transistors.
[0042] The semiconductor memory structure 100 further includes a plurality of bit line structures BL disposed on the substrate 102. The bit line structures BL extend in the third direction D3 and are electrically connected to the second source / drain region in the center of the active region 104. Each bit line structure BL includes a contact plug (not shown) corresponding to and falling on the second source / drain region of the active region 104.
[0043] The semiconductor memory structure 100 further includes a contact plug 110 disposed on the first source / drain region at the end of the active region 104, and a conductive pad (or landing pad) 112 disposed on the contact plug 110. The semiconductor memory structure 100 further includes a dielectric structure 114, which surrounds the active region 104, the word line WL, the bit line structure BL, the contact plug 110, and the conductive pad 112. The dielectric structure 114 may include one or more dielectric layers, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), multiple layers thereof, and / or combinations thereof.
[0044] The semiconductor memory structure 100 further includes a plurality of capacitor structures CA disposed on the conductive pads 112, and a protective layer 132 surrounding the capacitor structures CA. The capacitor structures CA are coupled to the transistors below to function as unit cells of a dynamic random access memory device. The capacitor structures CA include a bottom electrode layer 120, a capacitor dielectric film 122 disposed on the bottom electrode layer 120, and a top electrode layer 130 disposed on the capacitor dielectric film 122. The bottom electrode layer 120 is electrically connected to the first source / drain region of the active region 104 through the conductive pads 112 and the contact plugs 110.
[0045] The bottom electrode layer 120 has a cup-shaped profile. In a plan view, the bottom electrode layer 120 is annular (e.g., circular), and in a cross-sectional view, the bottom electrode layer 120 is U-shaped. The bottom electrode layer 120 of a portion of the capacitor structure CA overlaps with the first source / drain region electrically connected thereto, while the bottom electrode layer 120 of another portion of the capacitor structure CA does not overlap with (or is offset by a distance from) the first source / drain region electrically connected thereto.
[0046] The bottom electrode layer 120 has an inner surface 122S1 within the plane and an outer surface 122S2 outside the plane. The capacitor dielectric film 122 and the top electrode layer 130 extend along the inner surface 122S1 and the outer surface 122S2 of the bottom electrode layer 120. Thus, in a plan view, the capacitor structure CA has a concentric circle structure, which is top electrode layer 130 / capacitor dielectric film 122 / bottom electrode layer 120 / capacitor dielectric film 122 / top electrode layer 130 in sequence from inside to outside or from outside to inside. The capacitor dielectric film 122 and the top electrode layer 130 partially fill the inside of the cup-shaped outline of the bottom electrode layer 120. The protective layer 132 has a portion extending into the bottom electrode layer 120 to fill the remaining portion inside the cup-shaped outline.
[0047] The capacitor dielectric film 122 is a multilayer structure of a high-k dielectric material. In some embodiments, the multilayer structure of the capacitor dielectric film 122 may be or include zirconium oxide (ZrO2) / aluminum oxide (Al2O3) / zirconium oxide (ZrO2) to have the characteristics of high permittivity and low leakage current. However, the multilayer structure of zirconium oxide (ZrO2) / aluminum oxide (Al2O3) / zirconium oxide (ZrO2) will produce high tensile stress, which may cause the capacitor to twist or fall. In this way, the risk of short circuits between capacitors is increased, thereby reducing the manufacturing yield of semiconductor memory devices.
[0048] The embodiments of the present invention provide a semiconductor memory structure and a method for forming the same, so as to reduce the tensile stress of a capacitor dielectric film, thereby reducing the risk of the capacitor being distorted or tipped over. Figures 2 to 5 and Figure 7 1 is a schematic cross-sectional view showing some intermediate stages of forming a semiconductor memory structure 100 according to some embodiments of the present invention. Figures 2 to 5 and Figure 7 Corresponds to Figure 1A Line II.
[0049] A sacrificial layer 116 is formed on the dielectric structure 114 and the conductive pad 112. Figure 2 In some embodiments, the sacrificial layer 116 may include one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), multiple layers thereof, other suitable materials, and / or combinations thereof.
[0050] The sacrificial layer 116 is patterned to form an opening 118. The patterning process may include forming a patterned mask layer (not shown) on the sacrificial layer 116 by a photolithography process, followed by an etching process. The opening 118 corresponds to and exposes the conductive pad 112. In a plan view, the opening 118 has a circular profile.
[0051] A bottom electrode layer 120 is formed in the opening 118, such as Figure 3 As shown. The bottom electrode layer 120 extends along the bottom and sidewalls of the opening 118. The bottom electrode layer 120 can be made of a conductive material, such as a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)), a metal material (e.g., tungsten (W), aluminum (Al), copper (Cu), cobalt (Co) or ruthenium (Ru)), a multilayer thereof, and / or a combination thereof. The formation of the bottom electrode layer 120 includes conformally depositing a conductive material for the bottom electrode layer 120, and then performing an etch-back process on the bottom electrode layer 120.
[0052] The sacrificial layer 116 is removed to expose the outer surface 122S2 of the bottom electrode layer 120 and the upper surface of the dielectric structure 114. Figure 4 The removal process may be an etching process.
[0053] A capacitor dielectric film 122 is formed on the bottom electrode layer 120. Figure 5 As shown. The capacitor dielectric film 122 conformably extends to the upper surface of the dielectric structure 114, and the outer surface 122S2, the top surface, the inner surface 122S1 and the lower surface of the bottom electrode layer 120. In some embodiments, the capacitor dielectric film 122 is a three-layer structure of zirconium oxide (ZrO2) / aluminum oxide (Al2O3) / zirconium oxide (ZrO2).
[0054] FIG. 6A to FIG. 6C FIG. 1 is a diagram illustrating some details of forming the capacitor dielectric film 122 according to some embodiments of the present invention. The semiconductor memory structure 100 is placed in a deposition device, and a first high-k dielectric material 124 and a second high-k dielectric material 126 are sequentially deposited on the bottom electrode layer 120. Fig. 6A As shown. The first high-k dielectric material 124 is a zirconium oxide (ZrO2) layer, and the second high-k dielectric material 126 is an aluminum oxide (Al2O3) layer. In some embodiments, the deposition process may be an atomic layer deposition (ALD) process. The step of depositing the first high-k dielectric material 124 and the step of depositing the second high-k dielectric material may be performed continuously in the same deposition equipment.
[0055] For example, the step of depositing the first high-k dielectric material 124 includes using a zirconium-containing precursor (e.g., CpZr(NMe2)3 and / or ZrCl4) and an oxygen-containing precursor (e.g., O3), and performing 25 to 150 deposition cycles. The step of depositing the second high-k dielectric material 126 includes using an aluminum-containing precursor (e.g., trimethylaluminum (TMA)) and an oxygen-containing precursor (e.g., O3), and performing 3 to 20 deposition cycles.
[0056] In some embodiments, the first high-k dielectric material 124 as deposited has a crystalline portion and an amorphous portion. The crystalline portion is composed of grains 124G. For example, the grains 124G have an average size of about 0.1 nanometers. In some other embodiments, the first high-k dielectric material 124 as deposited has only an amorphous portion.
[0057] Once the step of depositing the second high-k dielectric material 126 is completed, the semiconductor memory structure 100 is removed from the deposition equipment. Next, the semiconductor memory structure 100 is placed in a thermal treatment equipment to perform an annealing process 1000 on the first high-k dielectric material 124 and the second high-k dielectric material 126. Figure 6B The annealing process 1000 can fully release the tensile stress between the first high-k dielectric material 124 and the second high-k dielectric material 126. Therefore, the risk of short circuit between capacitors can be reduced, thereby improving the manufacturing yield of the semiconductor memory device.
[0058] In some embodiments, the annealing process 1000 is performed at a temperature ranging from 400° C. to about 600° C. and in a process atmosphere containing N2. If the annealing temperature is too low or the annealing time is too short, the stress between the first high-k dielectric material 124 and the second high-k dielectric material 126 may not be sufficiently released. If the annealing temperature is too high or the annealing time is too long, aluminum atoms from the second high-k dielectric material 126 and zirconium atoms from the first high-k dielectric material 124 may be excessively inter-diffused, which may significantly increase the leakage rate of the capacitor dielectric film 122 and reduce the reliability of the semiconductor memory device.
[0059] During the annealing process 1000, the first high-k dielectric material 124 undergoes grain growth and increases the crystallinity of the first high-k dielectric material 124. The grown grains 124G' have an average size ranging from about 0.1 nm to about 1 nm.
[0060] Once the annealing process 1000 is completed, the semiconductor memory structure 100 is removed from the thermal treatment equipment. The semiconductor memory structure 100 is placed in a deposition equipment to deposit a third high-k dielectric material 128, such as Figure 6C As shown. The third high-k dielectric material 128 is a zirconium oxide layer. In some embodiments, the deposition process may be an atomic layer deposition (ALD) process.
[0061] For example, depositing the third high-k dielectric material 128 includes using a zirconium-containing precursor (e.g., CpZr(NMe2)3 and / or ZrCl4) and an oxygen-containing precursor (e.g., O3), and performing 10 to 65 deposition cycles. The number of cycles for depositing the third high-k dielectric material 128 may be less than the number of cycles for depositing the first high-k dielectric material 124. The thickness of the third high-k dielectric material 128 may be less than the thickness of the first high-k dielectric material 124.
[0062] In some embodiments, the just-deposited third high-k dielectric material 128 has a crystalline portion and an amorphous portion. The crystalline portion is composed of grains 128G. For example, the grains 128G have an average size of about 0.1 nanometers. In some other embodiments, the just-deposited third high-k dielectric material 128 has only an amorphous portion.
[0063] The crystallinity of the third high-k dielectric material 128 is lower than that of the annealed first high-k dielectric material 124, and the average size of grains 128G is smaller than the average size of grains 124G'. In some embodiments, the ratio of the average size of grains 128G to the average size of grains 124G' is in a range of about 0.1 to about 0.8.
[0064] During the aforementioned heat treatment process, zirconium atoms from the first high-k dielectric material 124 diffuse into the second high-k dielectric material 126, so that the second high-k dielectric material 126 contains zirconium. Therefore, the concentration of zirconium in the second high-k dielectric material 126 at the interface between the first high-k dielectric material 124 and the second high-k dielectric material 126 is higher than the concentration at the interface between the third high-k dielectric material 128 and the second high-k dielectric material 126.
[0065] Please refer to Figure 7 Once the deposition of the third high-k dielectric material 128 is completed, a top electrode layer 130 is conformably formed on the third high-k dielectric material 128 of the capacitor dielectric film 122. The top electrode layer 130 may be made of a conductive material, such as a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)), a metal material (e.g., tungsten (W), aluminum (Al), copper (Cu), cobalt (Co) or ruthenium (Ru)), a multilayer thereof, and / or a combination thereof.
[0066] It is worth noting that after depositing the third high-k dielectric material 128, no additional heat treatment (e.g., annealing process) is performed on the capacitor dielectric film 122. This is because the additional heat treatment may cause cross-diffusion at the two interfaces of the three-layer structure of the capacitor dielectric film 122 (i.e., the interface between the second high-k dielectric material 126 and the first high-k dielectric material 124, and the interface between the second high-k dielectric material 126 and the third high-k dielectric material 128). This may cause the leakage rate of the capacitor dielectric film 122 to increase significantly.
[0067] Afterwards, the formation Figure 1B The protective layer 132 is shown above the top electrode layer 130. In some embodiments, the protective layer 132 is a semiconductor material, such as SiGe.
[0068] According to the above, the embodiment of the present invention provides a semiconductor memory structure and a method for forming the same. By performing an annealing process after forming the second high-k dielectric material 126, the tensile stress of the capacitor dielectric film can be fully released. Therefore, the risk of short circuit between capacitors is reduced, thereby improving the manufacturing yield of the semiconductor memory device.
[0069] Although the present invention is disclosed in the above embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor memory structure, characterized in that: include: forming a bottom electrode layer on an active region; Depositing a first high-k dielectric material on the bottom electrode layer; Depositing a second high-k dielectric material on the first high-k dielectric material; Performing an annealing process on the first high-k dielectric material and the second high-k dielectric material; After the annealing process, depositing a third high-k dielectric material on the second high-k dielectric material; and A top electrode layer is formed on the third high-k dielectric material.
2. The method for forming a semiconductor memory structure according to claim 1, wherein: During the annealing process, zirconium atoms in the first high-k dielectric material diffuse into the second high-k dielectric material.
3. The method for forming a semiconductor memory structure according to claim 1, wherein: The grains of the first high-k dielectric material before the annealing process have a first average size, and the grains of the first high-k dielectric material after the annealing process have a second average size, the second average size being greater than the first average size.
4. The method for forming a semiconductor memory structure according to claim 3, wherein: The grains of the third high-k dielectric material have a third average size, and the third average size is smaller than the second average size.
5. The method for forming a semiconductor memory structure according to claim 1, wherein: Depositing the first high-k dielectric material and depositing the second high-k dielectric material are performed continuously in the same deposition equipment.
6. The method for forming a semiconductor memory structure according to claim 1, wherein: The annealing process is performed in a thermal treatment apparatus, and during the annealing process, the surface of the second high-k dielectric material is exposed to a process atmosphere.
7. The method for forming a semiconductor memory structure according to claim 1, wherein: Also includes: forming a dielectric structure surrounding the active region; forming a sacrificial layer on the dielectric structure, wherein the sacrificial layer has an opening, and the bottom electrode layer is formed in the opening; removing the sacrificial layer to expose the side surface of the bottom electrode layer; and A protection layer is formed around the top electrode layer.
8. The method for forming a semiconductor memory structure according to claim 1, wherein: Forming the first high-k dielectric material includes: performing a first atomic layer deposition using a first deposition cycle, and forming the third high-k dielectric material includes: performing a second atomic layer deposition using a second deposition cycle, wherein the number of the first deposition cycle is greater than the number of the second deposition cycle.
9. A semiconductor memory structure, characterized in that: include: A transistor is disposed on a substrate: a bottom electrode layer disposed on the transistor and electrically connected to a first source / drain region of the transistor; a capacitor dielectric film, comprising a first zirconium oxide layer, an aluminum oxide layer, and a second zirconium oxide layer sequentially disposed on the bottom electrode layer, wherein the grains of the first zirconium oxide layer have a first average size, the grains of the second zirconium oxide layer have a second average size, and the first average size is larger than the second average size; and A top electrode layer is disposed on the capacitor dielectric film.
10. The semiconductor memory structure according to claim 9, characterized in that: In a plan view, the bottom electrode layer has a ring-shaped profile.
11. The semiconductor memory structure according to claim 10, wherein: The capacitor dielectric film extends on an inner surface and an outer surface of the annular contour of the bottom electrode layer.
12. The semiconductor memory structure according to claim 10, wherein: Also includes: A protection layer surrounds the top electrode layer, wherein the protection layer includes a portion located within the annular contour of the bottom electrode layer.
13. The semiconductor memory structure according to claim 9, wherein: The aluminum oxide layer contains zirconium and has: a first zirconium concentration at the interface between the first zirconium oxide layer and the aluminum oxide layer; and A second zirconium concentration is provided, wherein the first zirconium concentration is higher than the second zirconium concentration at an interface between the second zirconium oxide layer and the aluminum oxide layer.
14. The semiconductor memory structure according to claim 9, wherein: Also includes: a contact plug disposed on the first source / drain region of the transistor; and A conducting pad is disposed on the contact plug, wherein the bottom electrode is disposed on the conducting pad.
15. The semiconductor memory structure according to claim 9, wherein: The first zirconium oxide layer has a first crystallinity, and the second zirconium oxide layer has a second crystallinity smaller than the first crystallinity.
16. The semiconductor memory structure according to claim 9, wherein: Also includes: A bit line structure extends above the substrate in a first direction and is electrically connected to a second source / drain region of the transistor, wherein the transistor has a gate structure located in the substrate and extending in a second direction that is perpendicular to the first direction.