Semiconductor structure and manufacturing method thereof, memory and memory system

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, a memory and a memory system. The semiconductor structure comprises a stacking structure and a channel structure, the stacked structure comprises gate layers, interlayer insulating layers and top selection gate layers, the gate layers and the interlayer insulating layers are alternately stacked in the first direction, the top selection gate layers are located on one side of the multiple gate layers in the first direction, and the interlayer insulating layers are arranged between the top selection gate layers and the gate layers; the channel structure comprises a channel layer, a functional layer and a gate dielectric layer; wherein the channel layer penetrates through the stacked structure, the gate dielectric layer is located between the channel layer and the top selection gate layer, the functional layer is located between the channel layer and the gate layer, and the functional layer comprises a ferroelectric storage layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof, a memory, and a memory system. Background Art

[0002] Ferroelectric RAM (FRAM) uses the ferroelectric effect of ferroelectric materials under the action of an external electric field to store information. Since ferroelectric memory has the ability to quickly read / write data and save data after power failure, and can store data quickly with very low power requirements, it is expected to be widely used in small devices in the consumer field.

[0003] At present, the development of ferroelectric memory is still relatively slow, and how to improve the storage density and reliability of ferroelectric memory is still a topic that requires long-term research. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, a memory, and a memory system.

[0005] According to a first aspect of the present disclosure, there is provided a semiconductor structure, comprising:

[0006] A stacked structure, comprising a gate layer, an interlayer insulating layer and a top selection gate layer, wherein the gate layer and the interlayer insulating layer are alternately stacked along a first direction, the top selection gate layer is located on one side of the plurality of gate layers along the first direction, and the interlayer insulating layer is provided between the top selection gate layer and the gate layer;

[0007] A channel structure comprises a channel layer, a functional layer and a gate dielectric layer; wherein the channel layer runs through the stacked structure, the gate dielectric layer is located between the channel layer and the top selection gate layer, the functional layer is located between the channel layer and the gate layer, and the functional layer comprises a ferroelectric storage layer.

[0008] According to a second aspect of the present disclosure, there is provided yet another semiconductor structure, comprising:

[0009] A stacked structure, comprising a gate layer, an interlayer insulating layer and a top selection gate layer, wherein the gate layer and the interlayer insulating layer are alternately stacked along a first direction, the top selection gate layer is located on one side of the plurality of gate layers along the first direction, and the interlayer insulating layer is provided between the top selection gate layer and the gate layer;

[0010] A channel structure, comprising a channel layer and a functional layer, wherein the channel layer runs through the stacked structure, and the functional layer is located between the channel layer and the top selection gate layer, and between the channel layer and the gate layer; the functional layer comprises a ferroelectric storage layer;

[0011] A first array common source layer is further provided on a side of the stack structure away from the top selection gate layer, and the first array common source layer is in contact with the channel layer; or a substrate is further provided on a side of the stack structure away from the top selection gate layer, and the channel structure extends into the substrate and is electrically isolated from the substrate, and the stack structure also includes a second array common source layer, which is located between the gate layer and the substrate, and passes through the functional layer and is in contact with the channel layer.

[0012] According to a third aspect of the present disclosure, a memory is provided, comprising: a semiconductor structure as described in any one of the first aspect and the second aspect of the present disclosure.

[0013] According to a fourth aspect of the present disclosure, a memory system is provided, the memory comprising:

[0014] One or more memories as described in the third aspect of the present disclosure;

[0015] A memory controller is coupled to the memory and configured to control the memory.

[0016] According to a fifth aspect of the present disclosure, there is provided a method for manufacturing a semiconductor structure, comprising:

[0017] A stacking structure is formed on a substrate; wherein the stacking structure comprises a third sublayer and first and second sublayers alternately stacked; the third sublayer is located on a side of the plurality of second sublayers away from the substrate, and the first sublayer is disposed between the third sublayer and the second sublayer;

[0018] forming a channel hole penetrating the stacked structure and extending into the substrate;

[0019] forming a functional material layer on the sidewall of the channel hole, and forming a channel layer on the surface of the functional material layer; wherein the functional material layer comprises a ferroelectric material layer;

[0020] Removing at least part of the functional material layer between the third sublayer and the channel layer to form a gap; wherein the at least part of the functional material layer includes the ferroelectric material layer, and the remaining ferroelectric material layer forms the ferroelectric storage layer;

[0021] A dielectric material is deposited in the gap to form a gate dielectric layer between the top selection gate layer and the channel layer.

[0022] According to a sixth aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0023] A first sub-stack structure is formed on a substrate; wherein the first sub-stack structure comprises a first sub-layer and a second sub-layer alternately stacked; the first sub-layer is exposed on a front side of the first sub-stack structure, and the front side is away from the substrate;

[0024] forming a first sub-channel structure in the first sub-stack structure; wherein the first sub-channel structure comprises a first sub-channel layer penetrating the first sub-stack structure and extending into the substrate, a functional layer is provided between the first sub-channel layer and the second sub-layer, and the functional layer comprises a ferroelectric storage layer;

[0025] forming a second sub-stack structure on the first sub-stack structure; wherein the second sub-stack structure comprises a top selection gate layer; and the first sub-stack structure and the second sub-stack structure form a stack structure;

[0026] A second sub-channel structure is formed in the second sub-stack structure; wherein the second sub-channel structure includes a second sub-channel layer that penetrates the second sub-stack structure, the second sub-channel layer is electrically connected to the first sub-channel layer, and a gate dielectric layer is provided between the second sub-channel layer and the top selection gate layer; the first sub-channel layer and the second sub-channel layer form a channel layer.

[0027] In the semiconductor structure provided by the embodiment of the present disclosure, the functional layer between the top selection gate layer and the channel layer is replaced by a gate dielectric layer, so that the top selection transistor composed of the top selection gate layer, the gate dielectric layer, and the channel layer is a MOS transistor, and the MOS transistor has a uniquely determined threshold voltage. When an activation voltage greater than the threshold voltage is applied to the top selection gate layer, the top selection transistor is turned on, and when the activation voltage is canceled, the top selection transistor is turned off. Compared with transistors using ferroelectric storage layers that require a turn-on voltage and a turn-off voltage to control the transistor, the top selection transistor using a gate dielectric layer only requires one voltage, so it is easier to control. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of a semiconductor structure including a memory string provided in an embodiment of the present disclosure;

[0029] Figure 2 A schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figure 3 A schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0031] Figure 4 A schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0032] Figure 5A schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0033] Figure 6 A schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0034] Figure 7a , Figure 7b and Figure 7c Schematic diagrams of some channel structures provided for embodiments of the present disclosure;

[0035] Figure 8 A schematic diagram of another channel structure provided in an embodiment of the present disclosure;

[0036] Fig. 9 A schematic diagram of another channel structure provided in an embodiment of the present disclosure;

[0037] Fig.10a and Fig.10b Schematic diagrams of some further channel structures provided for embodiments of the present disclosure;

[0038] Fig.11 A schematic diagram of another channel structure provided in an embodiment of the present disclosure;

[0039] Figures 12a to 12d Schematic diagrams of some further channel structures provided for embodiments of the present disclosure;

[0040] Fig.13 A schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0041] Fig.14 A schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0042] Fig.15a and Fig.15b Schematic diagrams of some other semiconductor structures provided for embodiments of the present disclosure;

[0043] Fig.16 A schematic diagram of a second wafer provided in an embodiment of the present disclosure;

[0044] Fig.17 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0045] Figures 18a to 18i A schematic diagram of the structure of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0046] Figures 19a to 19i A schematic diagram of the structure of another semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0047] Fig. 20A schematic flow chart of another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0048] Figures 21a to 21g A schematic diagram of the structure of another semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the accompanying drawings show exemplary implementation methods of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that the technical solutions recorded in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0050] The memory cell array of the three-dimensional ferroelectric memory includes a plurality of memory strings, each memory string extending in the vertical direction and including a top select gate TSG (Top Select Gate), a plurality of memory cells and a bottom select gate BSG (Bottom Select Gate) coupled in series in sequence. The top select gate TSG is configured to connect the memory string to the bit line via a bit line contact, and the bottom select gate BSG is configured to connect the memory string to the array common source ACS (Array Common Source). The corresponding memory string can be activated or deactivated by applying appropriate voltages to the top select gate TSG and the bottom select gate BSG. Each memory cell in the memory string is a ferroelectric memory cell, which uses the ferroelectric effect of the ferroelectric memory layer to store data.

[0051] Figure 1 A schematic diagram of a semiconductor structure including a memory string provided in an embodiment of the present disclosure, such as Figure 1 As shown, the semiconductor structure includes a first wafer 10 and a second wafer 20 connected to each other, the first wafer 10 includes a memory cell array, and the second wafer 20 includes a peripheral circuit. The first wafer 10 and the second wafer 20 are connected through a pad to realize an electrical connection between the peripheral circuit and the memory cell array, and the peripheral circuit is used to control the memory cell array to perform write, read and erase operations. For example, the first wafer 10 and the second wafer 20 are bonded to each other or welded together through a pad.

[0052] Continue to see Figure 1 , the first wafer 10 includes: a stacking structure 100 and a channel structure 200;

[0053] The stacked structure 100 includes a gate layer 110, an interlayer insulating layer 120 and a top selection gate layer 130. The gate layer 110 and the interlayer insulating layer 120 are alternately stacked along a first direction (e.g., a Z direction). The top selection gate layer 130 is located on one side of the plurality of gate layers 110 along the first direction, and an interlayer insulating layer 120 is provided between the top selection gate layer 130 and the gate layer 110.

[0054] The channel structure 200 includes a channel layer 210 and a functional layer 220 . The channel layer 210 runs through the stacked structure 100 . The functional layer 220 is partially located between the channel layer 210 and the gate layer 110 , and partially located between the channel layer 210 and the top selection gate layer 130 . The functional layer 220 includes a ferroelectric storage layer 221 .

[0055] In the disclosed embodiment, the material of the gate layer 110 may include at least one of metal, metal nitride, metal silicide or silicon. The metals mentioned here and below include but are not limited to tungsten, aluminum, copper, gold, silver, titanium, tantalum, etc. The metal nitrides mentioned here and below include but are not limited to titanium nitride, tantalum nitride, etc. The metal silicides mentioned here and below include but are not limited to titanium silicide, tantalum silicide, tungsten silicide, cobalt silicide, nickel silicide, etc. The silicon mentioned here and below includes but is not limited to polycrystalline silicon, doped polycrystalline silicon, amorphous silicon, doped amorphous silicon, etc.

[0056] In this embodiment, the gate layer 110 includes a metal layer and a metal nitride layer, wherein the metal nitride layer covers the top surface, the bottom surface and part of the sidewall surface of the metal layer. The material of the metal layer is, for example, tungsten, and the metal nitride layer is used to prevent tungsten from diffusing into the interlayer insulating layer 120.

[0057] The material of the top selection gate layer 130 may be the same as that of the gate layer 110. The top selection gate layer and the gate layer may be formed in the same process and have the same material composition. In other embodiments, the material of the top selection gate layer 130 may also be different from that of the gate layer 110.

[0058] Continue to see Figure 1 The channel structure 200 includes a channel layer 210 and a functional layer 220. The channel layer 210 extends along the first direction (Z direction) and penetrates the stacked structure 100. The material of the channel layer includes but is not limited to polysilicon, doped polysilicon, etc. The functional layer 220 surrounds the outer wall of the channel layer 210. The functional layer 220 includes a ferroelectric storage layer 221, and the ferroelectric storage layer is composed of a ferroelectric material. The ferroelectric storage layer uses the ferroelectric effect of ferroelectric materials to achieve data storage. Under the action of an external electric field, the polarization characteristics of the ferroelectric material change. When the external electric field is removed, the polarization state of the ferroelectric material can still be preserved. Ferroelectric materials have two stable polarization states, so they can be used as storage units to store the two states of "0" and "1".

[0059] The material of the ferroelectric storage layer includes but is not limited to at least one of hafnium oxide, zirconium oxide, hafnium zirconium oxide, zirconium bismuth oxide, hafnium bismuth oxide, and hafnium zirconium bismuth oxide. In addition, the ferroelectric material may be doped to adjust the performance of the ferroelectric material, and the doping atoms may include at least one of the following: magnesium, yttrium, strontium, niobium, tantalum, lanthanum, gadolinium, vanadium, phosphorus, potassium, scandium, ruthenium, selenium, calcium, barium, aluminum, arsenic, and indium.

[0060] Continue to see Figure 1 The semiconductor structure further includes: a plurality of first gate contact plugs 310; wherein the first gate contact plugs 310 include a lead portion 311 and a connection portion 312, the connection portion 312 is located between adjacent interlayer insulating layers 120 and contacts one gate layer 110; the lead portion 311 contacts the connection portion 312 and the lead portion 311 extends along the first direction (Z direction) to the front side exposed to the stacked structure 100. Here, the stacked structure 100 includes a front side and a back side arranged opposite to each other along the first direction (Z direction), and the front side is closer to the top selection gate layer 130.

[0061] In some embodiments, the lead-out portion 311 and the connecting portion 312 may be an integral whole, and the lead-out portion and the connecting portion are formed simultaneously in the same process step.

[0062] In the semiconductor structure having the first gate contact plug 310, as Figure 1 As shown, the sidewalls of different gate layers 110 may be flush with each other. Different first gate contact plugs 310 extend from different positions on the front of the stack structure into the stack structure, and stop at different gate layers 110 respectively, and are connected to the corresponding gate layer 110 through the connecting portion 312. The material of the first gate contact plug may be the same as or different from that of the gate layer.

[0063] In this embodiment, the bottoms of different first gate contact plugs 310 stop at different gate layers, thereby leading out the corresponding gate layers. Each gate layer has substantially the same shape and area, which can avoid problems such as pressure caused by film changes of the gate layer or the interlayer insulating layer in the three-dimensional memory, and the process steps in the manufacturing process of the first gate contact plug are relatively simple.

[0064] Continue to see Figure 1 The semiconductor structure also includes a first array common source layer 410, a first conductive plug 420 and a first interconnect structure 430; wherein the first array common source layer 410 is arranged on the back side of the stack structure and contacts the channel layer 210; the first conductive plug 420 penetrates the stack structure 100; and the first interconnect structure 430 is used to connect the first conductive plug 420 and the first array common source layer 410.

[0065] In some embodiments, Figure 1As shown, the first interconnect structure 430 includes a first interlayer dielectric layer 431, a first conductive via 432, a second conductive via 433 and a first interconnect layer 434. The first interlayer dielectric layer 431 covers the first array common source layer 410. The first conductive via 432 penetrates the first interlayer dielectric layer 431 and contacts the first array common source layer 410. The second conductive via 433 penetrates the first interlayer dielectric layer 431 and the first array common source layer 410 and contacts the first conductive plug 420. A first gap insulating layer is provided between the second conductive via 433 and the first array common source layer 410 to isolate the second conductive via 433 from the first array common source layer 410.

[0066] The first interconnection layer 434 covers the side of the first interlayer dielectric layer 431 away from the first array common source layer 410, and the first interconnection layer 434 contacts the first conductive via 432 and the second conductive via 433, so that the first array common source layer 410 is connected to the peripheral circuit through the first conductive via 432, the first interconnection layer 434, the second conductive via 433 and the first conductive plug 420 in sequence. In addition, the surface of the first interconnection layer 434 away from the first interlayer dielectric layer 431 may also be covered with a protective layer 450.

[0067] In some embodiments, the semiconductor structure further includes a second conductive plug 440 , which penetrates the stack structure 100 and has an end in contact with the first array common source layer 410 . That is, the first array common source layer 410 can also be connected to a peripheral circuit through the second conductive plug 440 .

[0068] like Figure 1 As shown, the first gate contact plug 310, the first conductive plug 420 and the second conductive plug 440 may include a metal layer and a metal nitride layer, wherein the metal nitride layer covers the outer sidewall and the bottom (the end away from the top selection gate) of the metal layer. A filling layer may also be provided in the metal layer.

[0069] The first conductive via 432 and the second conductive via 433 may also include a metal layer and a metal nitride layer, and the metal nitride layer covers the outer sidewall and the top (the end near the top selection gate) of the metal layer. The material of the first array common source layer 410 may include polysilicon, doped polysilicon, etc. The material of the first interconnect layer 434 may include metal.

[0070] Continue to see Figure 1The semiconductor structure also includes a gate line isolation structure 500, which penetrates the stacked structure 100 and contacts the first array common source layer 410. The gate line isolation structure 500 is used to divide the stacked structure 100 into multiple storage blocks (Blocks), and can also be used to divide the storage blocks into multiple storage areas (Fingers). In some embodiments, the gate line isolation structure 500 can also be used as an array common source ACS of multiple channel structures. The gate line isolation structure 500 includes a gate line contact layer 510 in contact with the first array common source layer 410, and a gate line isolation layer 520 located between the gate line contact layer 510 and the stacked structure. The material of the gate line contact layer 510 includes polysilicon or doped polysilicon.

[0071] In addition, the stacked structure 100 further includes: an etch stop layer 140, which is located on one side of the plurality of gate layers away from the top selection gate layer (i.e., located below the plurality of gate layers), and an interlayer insulating layer 120 is provided between the etch stop layer 140 and the gate layer, and the channel layer 210 penetrates the etch stop layer 140. In the manufacturing process of the semiconductor structure, the etch stop layer 140 is located between the substrate and the gate layer, and the channel structure 200 and the gate line isolation structure 500 penetrate the etch stop layer and extend into the substrate. The etch stop layer 140 is used to define the size range of the functional layer to be removed and the gate line isolation layer to be removed along the first direction (Z direction) when removing the substrate, the functional layer 220 in the channel structure, and the gate line isolation layer 520 of the gate line isolation structure. The etch stop layer 140 is also used as an etch stop layer when forming a conductive plug (a first conductive plug 420, a second conductive plug 440), and defines the position of the bottom of the conductive plug.

[0072] In this embodiment, the method of removing the substrate and redepositing the first array common source layer 410 can reduce the difficulty of connecting the bottom of the channel structure 200 and the array common source ACS, thereby facilitating the three-dimensional memory to increase the number of stacking layers to improve integration.

[0073] Figure 2 A schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure. Figure 1 compared to, Figure 2 The material of the gate layer 110 and the top selection gate layer 130 includes polysilicon or doped polysilicon. Figure 2 The gate layer 110 and the top selection gate layer 130 are directly deposited when forming the stacked structure, that is, the polysilicon gate layer 110 and the interlayer insulating layer 120, and the polysilicon top selection gate layer 130 are directly formed in the process. Figure 1 The gate layer 110 shown is obtained by first forming alternately stacked dummy gate layers 111 and interlayer insulating layers 120, and then partially replacing the dummy gate layer 111 with the gate layer 110 based on the gate line gap structure (for forming a gate line isolation structure). Therefore, Figure 1A dummy gate layer 111 still remains in the substrate. Figure 1 The top selection gate layer 130 is formed simultaneously with the gate layer 110 .

[0074] like Figure 2 As shown, in this embodiment, the first gate contact plug 310 extends from the front side of the stack structure into the stack structure, and the bottom of the first gate contact plug 310 contacts a gate layer 110 for applying a voltage signal to the gate layer 110. A second gap insulating layer is further provided between the first gate contact plug 310 and the stack structure for isolating the first gate contact plug 310 from other gate layers 110.

[0075] also, Figure 2 The semiconductor structure shown includes Figure 1 The channel structure 200 , the etch stop layer 140 , the first array common source layer 410 , the first conductive plug 420 , the second conductive plug 440 , the first interconnect structure 430 , etc. are the same, so they are not described in detail.

[0076] Figure 3 A schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure. Figure 1 The difference is, Figure 3 The stacked structure 100 in the embodiment includes a core region and a step region surrounding the core region, and the channel structure 200 is located in the core region. The step region includes a plurality of steps formed in the stacked structure, and each step includes a gate layer 110 (or a top selection gate layer 130) and an interlayer insulating layer 120 located on the gate layer. Along the direction from the front to the back of the stacked structure, the next step protrudes from the sidewall of the previous step. That is, when the stacked structure is viewed from the front of the stacked structure, the step surface of each step parallel to the plane where the stacked structure is located can be seen.

[0077] A first dielectric cover layer 150 is formed on the stacked structure in the step region. The semiconductor structure further includes a plurality of second gate contact plugs 320, which are located in the step region, penetrate the first dielectric cover layer 150, and contact the top surface of a gate layer 110. The plurality of second gate contact plugs 320 contact the plurality of gate layers 110, respectively.

[0078] For example, the second gate contact plug 320 includes a metal layer and a metal nitride layer covering the outer sidewall and the bottom of the metal layer. In some embodiments, the first conductive plug 420 penetrates the first dielectric cover layer 150 and the etch stop layer 140. The first conductive plug 420 and the second gate contact plug 320 can be formed simultaneously in the same process step, and the first conductive plug 420 and the second gate contact plug 320 have the same material.

[0079] In some embodiments, the semiconductor structure further includes a first buffer layer 160 located in the step region and covering a step top surface and a step sidewall of each step.

[0080] also, Figure 3 The semiconductor structure shown includes Figure 1 The channel structure 200 , gate line isolation structure 500 , first array common source layer 410 , first interconnect structure 430 , etc. are the same, so they are not described in detail.

[0081] Figure 4 A schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure. Figure 3 compared to, Figure 4 The material of the gate layer 110 and the top selection gate layer 130 includes polysilicon or doped polysilicon. Figure 4 The polysilicon gate layer 110 and the polysilicon top selection gate layer are obtained by first forming alternately stacked polysilicon gate material layers and interlayer insulating layers 120, and polysilicon top selection gate material layers, and then trimming the multiple gate material layers and the top selection gate material layers into a step shape after forming the channel structure 200. Figure 3 The gate layer 110 shown is obtained by first forming alternately stacked dummy gate material layers and interlayer insulating layers 120 , and then trimming the dummy gate layer into a step shape and partially replacing the stepped dummy gate layer 111 with the gate layer 110 .

[0082] also, Figure 4 The semiconductor structure shown includes Figure 3 The same channel structure 200 , gate line isolation structure 500 , second gate contact plug 320 , first conductive plug 420 , first array common source layer 410 , first interconnect structure 430 , etc. are not described in detail.

[0083] Figure 5 A schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure. Figure 1 The difference is, Figure 5 Different channel structures and array common source connection methods are used. Figure 5 As shown, a second array common source layer 170 is further provided in the stack structure 100, and the second array common source layer 170 is located on a side of the plurality of gate layers away from the top selection gate layer, and an interlayer insulating layer 120 is provided between the second array common source layer 170 and the gate layer; wherein the second array common source layer 170 passes through the functional layer 220 of the channel structure 200 and contacts the channel layer 210;

[0084] The semiconductor structure further includes: a substrate 11 and a third conductive plug 460, wherein the substrate 11 is located on the back side of the stack structure 100, and the channel structure 200 extends into the substrate 11 and a barrier layer is provided between the channel structure 200 and the substrate 11 to achieve electrical isolation. The third conductive plug 460 extends from the front side of the stack structure to the second array common source layer 170 and contacts the second array common source layer 170. That is, the second array common source layer 170 contacts the peripheral circuit through the third conductive plug 460.

[0085] In this embodiment, the second array common source layer 170 directly contacts the channel layer 210 from the side wall of the channel layer 210, which can reduce the risk of bottom etching of the functional layer 220 due to the increase in the number of layers, such as etching consistency, alignment margin and large pressure changes, etc., and the connection method of the channel layer 210 and the second array common source layer 170 provided in this embodiment is conducive to increasing the number of stacked layers of the three-dimensional memory to improve the integration. For example, the material of the second array common source layer 170 may include N-type doped polysilicon, and the connection method of the second array common source layer 170 and the channel layer 210 may be called a SWNN (Side Wall N-poly / N-Sub) structure.

[0086] In some embodiments, a portion of peripheral circuits (not shown) are disposed on a side of the substrate 11 away from the stacking structure. Figure 5 As shown, the semiconductor structure may further include a fourth conductive plug 470 and a second interconnect structure 480 . The second interconnect structure 480 is connected to the portion of the peripheral circuit and is electrically connected to the peripheral circuit in the second wafer 20 through the fourth conductive plug 470 .

[0087] Figure 5 In the embodiment, the fourth conductive plug 470 extends from the front of the stacked structure to the second array common source layer 170, and the fourth conductive plug 470 can be formed in the same process step as the third conductive plug 460. The second interconnect structure 480 includes: a second interconnect layer 481 and a third conductive via 482, the third conductive via 482 penetrates the substrate 11 and contacts the fourth conductive plug 470, and a third gap insulating layer is provided between the third conductive via 482 and the substrate 11 to achieve electrical isolation. The second interconnect layer 481 covers the surface of the substrate 11 away from the stacked structure, and the second interconnect layer 481 is in contact with the third conductive via 482. The surface of the second interconnect layer can also be partially covered with a protective layer 450.

[0088] also, Figure 5 The semiconductor structure shown includes Figure 1 The channel structure 200 and the first gate contact plug 310 are the same, so they are not described again.

[0089] Figure 6A schematic diagram of another semiconductor structure provided in accordance with an embodiment of the present disclosure. Figure 6 The semiconductor structure shown includes Figure 3 The same channel structure 200, top selection gate layer 130, gate layer 110 and first gate contact plug 310; and includes Figure 5 The same second array common source layer 170 , third conductive plug 460 , fourth conductive plug 470 , second interconnect structure 480 , gate line isolation structure 500 , etc. are not described in detail in this disclosure.

[0090] It should be understood that Figure 5 and Figure 6 The gate layer 110 and the top selection gate layer 130 in the embodiment may also be replaced by Figure 2 and Figure 4 The polysilicon (or doped polysilicon) gate layer 110 and the top selection gate layer 130 are formed to obtain another semiconductor structure, which will not be described in detail in the present disclosure.

[0091] Figure 7a , Figure 7b and Figure 7c Schematic diagrams of various channel structures provided in the embodiments of the present disclosure, such as Figure 7a As shown, in the channel structure 200, the functional layer 220 may further include: a first dielectric layer 222 disposed between the gate layer 110 and the ferroelectric storage layer 221, and between the top selection gate layer 110 and the ferroelectric storage layer 221. By way of example, the first dielectric layer surrounds the outer sidewall of the ferroelectric storage layer 221.

[0092] The first dielectric layer 222 is provided between the gate layer 110 (or the top selection gate layer 130) and the ferroelectric storage layer 221, so as to improve the interface characteristics, reduce the defects in the interface, and improve the adhesion between the gate layer and the ferroelectric storage layer.

[0093] like Figure 7b As shown, the functional layer 220 may further include a second dielectric layer 223 disposed between the ferroelectric memory layer 221 and the channel layer 210 . For example, the second dielectric layer 223 surrounds the outer sidewall of the channel layer 210 , and the ferroelectric memory layer 221 surrounds the outer sidewall of the second dielectric layer 223 .

[0094] A second dielectric layer 223 is provided between the ferroelectric storage layer 221 and the channel layer 210, which can not only improve the interface characteristics, reduce defects in the interface, and improve the adhesion between the ferroelectric storage layer and the channel layer, but also reduce leakage current, so as to improve the data retention capability of the storage unit composed of the gate layer 110 - ferroelectric storage layer 221 - second dielectric layer 223 - channel layer 210.

[0095] like Figure 7cAs shown, the functional layer 220 may include a first dielectric layer 222 and a second dielectric layer 223, wherein the second dielectric layer 223, the ferroelectric storage layer 221 and the first dielectric layer 222 are sequentially stacked in a direction outward from the channel layer 210. The first dielectric layer 222 and the second dielectric layer 223 are arranged in the functional layer 220 to form a composite functional layer 220, which can improve the interface characteristics, reduce the leakage current to improve the data retention capability, and improve the breakdown voltage of the storage unit.

[0096] Figure 8 A schematic diagram of another channel structure 200 provided in an embodiment of the present disclosure is shown as follows: Figure 8 As shown, in the channel structure 200, a second dielectric layer 223 is provided between the ferroelectric storage layer 221 and the channel layer 210, and the functional layer 220 may also include: a conductive layer 224, located between the ferroelectric storage layer 221 and the second dielectric layer 223, constituting a storage unit of a gate layer 110-ferroelectric storage layer 221-conductive layer 224-second dielectric layer 223-channel layer 210 structure.

[0097] The conductive layer 224 and the second dielectric layer 223 improve the interface characteristics between the ferroelectric storage layer and the channel layer and the gate layer, reduce oxygen vacancy defects on the interface, effectively avoid the formation of an oxide layer between the channel layer and the ferroelectric storage layer, increase the reliability of the storage unit, and also improve the adhesion of the interface. In addition, the conductive layer 224 and the second dielectric layer 223 can reduce leakage current to improve data retention capability, can increase breakdown voltage and thus improve device reliability. Furthermore, the storage performance of the storage unit can be adjusted by adjusting the thickness ratio of the conductive layer 224 in the functional layer 220.

[0098] Fig. 9 A schematic diagram of another channel structure provided in an embodiment of the present disclosure is shown in FIG. Fig. 9 As shown, the ferroelectric storage layer 221 includes a plurality of ferroelectric units 2211 spaced apart along a first direction (Z direction), and an interlayer insulating layer 120 is provided between two adjacent ferroelectric units 2211; each ferroelectric unit 2211 is located between a channel layer 210 and a gate layer 110 (or a top selection gate layer 130).

[0099] Fig. 9 In the embodiment, the sidewalls of the gate layer 110 and the top selection gate layer 130 close to the channel layer are retracted by a certain distance relative to the sidewalls of the interlayer insulating layer 120 to form a groove, and the ferroelectric unit 2211 is located in the groove, and adjacent ferroelectric units 2211 are isolated by the interlayer insulating layer 120. In this embodiment, the ferroelectric storage layer 221 is made into separate ferroelectric units 2211, which can reduce the mutual series connection between adjacent ferroelectric units 2211, reduce the probability of data error caused by crosstalk, and thus improve the reliability of the storage device.

[0100] In some embodiments, Fig. 9 As shown, a first dielectric layer 222 may be further disposed between each ferroelectric unit 2211 and the gate layer 110 (or the top selection gate layer 130) to improve the interface characteristics between the ferroelectric unit 2211 and the gate layer 110 (or the top selection gate layer 130).

[0101] In some other embodiments, a second dielectric layer may be provided between each ferroelectric unit 2211 and the channel layer 210. For example, the second dielectric layer may penetrate the interlayer insulating layer and cover the entire outer side wall of the channel layer; or the second dielectric layer may be located between adjacent interlayer insulating layers, that is, the ferroelectric unit 2211 and the second dielectric layer are sequentially arranged in the groove formed by the gate layer retracting relative to the interlayer insulating layer. In some other embodiments, a first dielectric layer 222 may be provided between each ferroelectric unit 2211 and the gate layer 110, and a second dielectric layer may be provided between each ferroelectric unit 2211 and the channel layer 210.

[0102] Fig.10a and Fig.10b Schematic diagrams of some other channel structures provided in the embodiments of the present disclosure, such as Fig.10a As shown, the conductive layer includes a plurality of conductive units 2241 spaced apart along a first direction (Z direction); wherein an interlayer insulating layer 120 is disposed between two adjacent conductive units 2241; and each conductive unit 2241 is located between a ferroelectric unit 2211 and a second dielectric layer 223. For example, the second dielectric layer 223 penetrates the interlayer dielectric layer and covers the outer side wall of the entire channel layer 210.

[0103] In this embodiment, the conductive layer 224 is made into separate conductive units 2241, each of which can adjust the storage performance of the storage unit, and the separated conductive units 2241 can also reduce the mutual series connection between adjacent storage units, reducing the probability of data errors due to crosstalk, thereby improving the reliability of the storage device.

[0104] In some embodiments, Fig.10b As shown, the ferroelectric unit 2211 may include a first portion A extending along the first direction (Z direction) and disposed on the side wall of the gate layer 110, and a second portion B and a third portion C disposed on the surface of the interlayer insulating layer 120 and disposed opposite to each other along the first direction. The first portion A, the second portion B and the third portion C of the ferroelectric unit 2211 are collectively disposed in a "concave" shape. The conductive unit 2241 is filled in the concave of the "concave" ferroelectric unit 2211. Compared to Fig.10a The storage unit shown, Fig.10b The proportion of the conductive unit 2241 in the storage unit is smaller, which can improve the storage window.

[0105] It should be understood that Figures 7a to 7c , Figure 8 , Fig. 9 , Fig.10a and Fig.10b The channel structure 200 shown may replace any of the semiconductor structures described above (eg Figures 1 to 6 ) to obtain other semiconductor structures. According to actual use requirements, any of the above semiconductor structures can be used. Figures 7a to 10b Any of the channel structures 200 shown is used to improve the performance of the semiconductor structure, which will not be described in detail here.

[0106] Fig.11 A schematic diagram of another channel structure provided in an embodiment of the present disclosure. Fig.11 As shown, the channel structure 200 includes a channel layer 210, a functional layer 220 and a gate dielectric layer 230; wherein the channel layer 210 extends along a first direction and penetrates the stacked structure 100, the gate dielectric layer 230 is located between the channel layer 210 and the top selection gate layer 130, the functional layer 220 is located between the channel layer 210 and the gate layer 110, and the functional layer 220 includes a ferroelectric storage layer 221.

[0107] In some embodiments, the size of the gate dielectric layer 230 along the second direction is equal to the size of the functional layer 220 along the second direction. The second direction is perpendicular to the first direction. The second direction is any direction in a plane perpendicular to the first direction. The second direction may be, for example, the X direction. Fig.11 As shown, the orthographic projection of the gate dielectric layer 230 in a plane parallel to the second direction (X direction) overlaps with the orthographic projection of the functional layer 220 in the plane. For example, the gate dielectric layer 230 is formed by filling the position where a portion of the functional material layer is removed by etching back.

[0108] Compared to Figure 1 In the semiconductor structure shown in FIG. 1 , in this embodiment, the functional layer between the top selection gate layer 130 and the channel layer 210 is replaced by the gate dielectric layer 230, so that the top selection transistor composed of the top selection gate layer 130, the gate dielectric layer 230, and the channel layer 210 is a MOS transistor, and the MOS transistor has a unique threshold voltage. When an activation voltage greater than the threshold voltage is applied to the top selection gate layer 130, the top selection transistor is turned on, and when the activation voltage is canceled, the top selection transistor is turned off. Compared with the transistor using the ferroelectric storage layer, which requires a turn-on voltage and a turn-off voltage to control the transistor, the top selection transistor using the gate dielectric layer 230 only needs one voltage, so it is easier to control.

[0109] It should be understood that Fig.11 The channel structure 200 shown may replace any of the semiconductor structures described above (eg, Figures 1 to 6) in order to obtain other semiconductor structures. These have Fig.11 In the semiconductor structure of the channel structure 200 shown, the top selection transistor can be turned on or off by applying an activation voltage to the top selection transistor or canceling the application of the activation voltage. The control method is simpler and the programming steps can be reduced.

[0110] Figures 12a to 12d Schematic diagrams of some further channel structures provided by embodiments of the present disclosure. Fig.12a As shown, in the channel structure 200, the gate dielectric layer 230 is composed of a single material. The functional layer 220 includes a second dielectric layer 223, a ferroelectric storage layer 221, and a first dielectric layer 222 arranged in sequence from the channel layer 210 outward. The size of the gate dielectric layer 230 along the second direction is equal to the sum of the sizes of the second dielectric layer 223, the ferroelectric storage layer 221, and the first dielectric layer 222 along the second direction. During the manufacturing process, the gate dielectric layer 230 is formed by filling the gate dielectric material at the position where part of the first dielectric layer, the second dielectric layer, and the ferroelectric material layer are removed by back etching.

[0111] It should be understood that in another embodiment, the functional layer 220 may also include a first dielectric layer and a ferroelectric storage layer, or a second dielectric layer and a ferroelectric storage layer, or a second dielectric layer, a conductive layer and a ferroelectric storage layer.

[0112] See also Figure 12b , the first dielectric layer 222 may also extend between the top selection gate layer 130 and the channel layer 210. The gate dielectric layer 230 further includes: a third dielectric layer 231, the third dielectric layer 231 is in contact with the ferroelectric storage layer 221, the third dielectric layer 231 is located between the first dielectric layer 222 and the channel layer 210, and the size of the third dielectric layer 231 along the second direction is equal to the size of the ferroelectric storage layer 221 along the second direction. In this embodiment, the first dielectric layer 222 and the third dielectric layer 231 together constitute the gate dielectric layer 230.

[0113] See also Fig.12c , the second dielectric layer 223 also extends between the top selection gate layer 130 and the channel layer 210. Similarly, the gate dielectric layer 230 also includes a third dielectric layer 231, which is located between the top selection gate layer 130 and the second dielectric layer 223, and the size of the third dielectric layer 231 along the second direction is equal to the size of the ferroelectric storage layer 221 along the second direction. In this embodiment, the second dielectric layer 223 and the third dielectric layer 231 together constitute the gate dielectric layer 230.

[0114] It should be understood that in another embodiment, the first dielectric layer 222 and the second dielectric layer 223 both extend between the top selection gate layer and the channel layer, and the gate dielectric layer 230 includes the second dielectric layer 223, the third dielectric layer 231 and the first dielectric layer 222 stacked in sequence along the channel layer.

[0115] See also Fig.12d In the channel structure 200, the functional layer 220 includes a second dielectric layer 223, a conductive layer 224, and a ferroelectric storage layer 221 which are sequentially arranged from the channel layer 210 outward. The second dielectric layer 223 also extends between the top selection gate layer 130 and the channel layer 210. The gate dielectric layer 230 includes a second dielectric layer 223 and a third dielectric layer 231. The size of the third dielectric layer 231 along the second direction is equal to the sum of the sizes of the conductive layer 224 and the ferroelectric storage layer 221 along the second direction. During the manufacturing process, the gate dielectric layer 230 is formed by filling the gate dielectric material at the position where part of the conductive material layer and the ferroelectric material layer are removed by etching back.

[0116] Figures 12a to 12d The channel structure 200 shown may replace any of the semiconductor structures described above (eg, Figures 1 to 6 ) in the channel structure 200 to obtain other semiconductor structures, which will not be described in detail here.

[0117] Fig.13 A schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure, such as Fig.13 As shown, in some embodiments, the stacking structure 100 includes a first sub-stack structure 101 and a second sub-stack structure 102; the first sub-stack structure 101 includes alternatingly stacked gate layers 110 and interlayer insulating layers 120, wherein the interlayer insulating layer 120 is located at the top of the first sub-stack structure 101; the second sub-stack structure 102 includes a top selection gate layer 130, which is located on the top interlayer insulating layer 120 in the first sub-stack structure 101.

[0118] The top selection gate layer 130 may be made of different materials from the gate layer 110. In the present embodiment, the gate layer 110 includes a metal layer 112 and a metal nitride layer 113 surrounding the top surface, the bottom surface and a portion of the sidewall of the metal layer, and the top selection gate layer 130 includes a stacked polysilicon layer 131 and a metal silicide layer 132. The polysilicon layer 131 is located between the metal silicide layer 132 and the first sub-stack structure 101. By way of example, the top selection gate layer and the gate layer are formed in different process steps, which will be described in detail in the subsequent manufacturing method of the present disclosure.

[0119] Continue to see Fig.13, the channel structure 200 includes a first sub-channel structure 201 and a second sub-channel structure 202; wherein the first sub-channel structure 201 includes a first sub-channel layer 211 penetrating the first sub-stack structure 101, and a functional layer 220 is provided between the first sub-channel layer 211 and the gate layer 110. By way of example, the functional layer 220 surrounds the outer sidewall of the first sub-channel layer 211. The second sub-channel structure 202 includes a second sub-channel layer 212 penetrating the second sub-stack structure 102, the second sub-channel layer 212 and the first sub-channel layer 211 are electrically connected, and a gate dielectric layer 230 is provided between the second sub-channel layer 212 and the top selection gate layer 130. By way of example, the gate dielectric layer 230 surrounds the second sub-channel layer 212.

[0120] The second sub-channel structure 202 and the first sub-channel structure 201 are formed in different process steps. The size of the second sub-channel structure 202 along the second direction (X direction) may be different from the size of the first sub-channel structure 201 along the second direction. Fig.13 As shown, the size of the first sub-channel structure 201 along the second direction is larger than that of the second sub-channel structure 202. The size of the first sub-channel layer 211 along the second direction is larger than that of the second sub-channel layer 212. A filling layer 213 may be further provided in the first sub-channel layer 211.

[0121] The material of the second sub-channel layer 212 may be the same as or different from that of the first sub-channel layer 211. For example, the second sub-channel layer 212 and the first sub-channel layer 211 are polysilicon doped with different atoms, or one of the second sub-channel layer 212 and the first sub-channel layer 211 is doped polysilicon and the other is intrinsic polysilicon.

[0122] In some embodiments, the first sub-channel structure 201 further includes a connection contact 214 disposed on the filling layer 213 and in contact with the first sub-channel layer 211. The second sub-channel layer 212 is disposed on and in contact with the connection contact 214, and the second sub-channel layer 212 and the first sub-channel layer 211 are electrically connected via the connection contact 214.

[0123] In this embodiment, the top selection gate layer 130 is set independently of the gate layer 110, so that the top selection transistor composed of the top selection gate layer 130, the gate dielectric layer 230, and the second sub-channel layer 212 is a MOS transistor. Using a MOS transistor as a switch makes it easier to control the on and off of the top selection transistor. In addition, since the gate layer 110 and the top selection gate layer 130 are independent of each other, it is not necessary to consider the performance of the top selection transistor when adjusting the functional layer 220 between the gate layer 110 and the first sub-channel layer 211. Therefore, it is easier to flexibly set the functional layer in the first sub-channel structure 201 to obtain a storage unit that meets different needs. For example, Fig.13The functional layer 220 may be the above Figures 7a to 7c , Figure 8 , Fig. 9 , Fig.10a and Fig.10b Any of the functional layers described above can be used to obtain other semiconductor structures.

[0124] That is to say, Fig.13 The functional layer 220 in the embodiment may also include a first dielectric layer and a ferroelectric storage layer 221, or a second dielectric layer and a ferroelectric storage layer 221, or a first dielectric layer, a ferroelectric storage layer 221 and a second dielectric layer, or a second dielectric layer, a conductive layer and a ferroelectric storage layer. Fig.14 As shown, in the functional layer of the first sub-channel structure 201, the ferroelectric storage layer 221 may include a plurality of ferroelectric units 2211 spaced apart along the first direction (Z direction), and an interlayer insulating layer 120 is provided between two adjacent ferroelectric units 2211; each ferroelectric unit 2211 is located between the first sub-channel layer 211 and a gate layer 110. A first dielectric layer 222 may also be provided between the ferroelectric unit 2211 and the gate layer 110. In some other embodiments, a conductive unit and a second dielectric layer may also be provided between the ferroelectric unit 2211 and the first sub-channel layer 211.

[0125] It should be understood that Fig.13 and Fig.14 The stack structure 100 and the channel structure 200 are shown, and Fig.13 The functional layer is Figures 7a to 10b The channel structure obtained by replacing the functional layer can replace any of the above semiconductor structures (for example, Figures 1 to 6 ) in the stacked structure 100 and the channel structure 200 to obtain other semiconductor structures.

[0126] For example, Fig.13 The stacked structure 100 and the channel structure 200 shown replace Figure 1 The stacked structure 100 and the channel structure 200 in the semiconductor structure shown in FIG. Fig.15a The semiconductor structure shown. Fig.15a The semiconductor structure includes Figure 1The same first gate contact plug 310, first array common source layer 410, etch stop layer 140, first conductive plug 420, second conductive plug 440 and first interconnect structure 430. The first gate contact plug 310, the first conductive plug 420 and the second conductive plug 440 all penetrate the second sub-stack structure 102 and the first sub-stack structure 101, and the etch stop layer 140 is disposed on a side of the plurality of gate layers 110 away from the second sub-stack structure 102. The detailed description of the first gate contact plug 310, the first array common source layer 410, the etch stop layer 140, the first conductive plug 420, the second conductive plug 440 and the first interconnect structure 430 is as described above, and will not be repeated here.

[0127] For example, Fig.14 The stacked structure 100 and the channel structure 200 shown replace Figure 3 The stacked structure 100 and the channel structure 200 in the semiconductor structure shown in FIG. Fig.15b The semiconductor structure shown. Fig.15b In the embodiment, the first sub-stack structure 101 includes a core region and a step region, and the first dielectric cover layer 150 covers the step region of the first sub-stack structure 101. Figure 3 The same second gate contact plug 320 and first conductive plug 420 both penetrate the second sub-stack structure 102 and the first sub-stack structure 101, and the etch stop layer 140 is disposed on a side of the plurality of gate layers 110 away from the second sub-stack structure 102. The detailed description of the second gate contact plug 320, the first array common source layer 410, the etch stop layer 140, the first conductive plug 420 and the first interconnect structure 430 is as described above and will not be repeated here.

[0128] In addition, you can Fig.13 and Fig.14 The channel structure 200 and the stacked structure 100 are replaced Figure 2 , Figure 4 , Figure 5 and Figure 6 The channel structure 200 and the stacked structure 100 are used to obtain other semiconductor structures, which will not be described in detail in the present disclosure.

[0129] In some embodiments, the semiconductor structure further includes a dummy channel structure 200', which does not have a storage function but supports the stacked structure 100 to enhance the structural stability. Figure 1 or Fig.15a As shown, the dummy channel structure 200' may have the same structure as the channel structure 200, and the dummy channel structure 200' may be formed simultaneously with the channel structure 200. Also, as an example, Figure 3 or Fig.15bAs shown, the dummy channel structure 200' may have a structure different from that of the channel structure 200. For example, the dummy channel structure 200' may include a single insulating material. In this case, the dummy channel structure 200' and the channel structure 200 are formed in different processes.

[0130] In some embodiments, Figure 1 or Fig.15a As shown, the first wafer 10 further includes a bit line (not shown) and a back-end interconnect structure 610. The bit line is located on the channel contact plug 490 and is connected to a plurality of channel contact plugs 490. The corresponding channel structure 200 is activated or deactivated by applying an appropriate voltage to the bit line. The extension direction of the bit line and the extension direction of the gate line isolation structure 500 may be perpendicular to each other.

[0131] The back-end interconnect structure 610 is located on the conductive plugs (including at least one of the first conductive plug 420, the second conductive plug 440, the third conductive plug and the fourth conductive plug), the gate contact plugs (including the first gate contact plug 310 or the second gate contact plug) and the bit lines, and is in contact with the conductive plugs, the gate contact plugs and the bit lines. The back-end interconnect structure 610 may include interconnect vias and metal interconnect layers, etc.

[0132] In some embodiments, a first pad lead-out layer 620 is formed on the back-end interconnect structure 610, including a first passivation layer 621 and a first pad 622 located in the first passivation layer, the first pad 622 is connected to the back-end interconnect structure 610, and the first passivation layer can be used as the outermost layer for passivating and protecting the first wafer 10. The top surface of the first pad 622 can be exposed from the first passivation layer to lead out the conductive plug, the gate contact plug, the bit line, etc. The first pad may include at least one of a metal, a metal silicide, or a metal nitride.

[0133] Fig.16 Schematic diagram of a second wafer provided by an embodiment of the present disclosure. Fig.16 As shown, the second wafer 20 includes: a peripheral substrate 21, in which a peripheral transistor 710 is formed. By way of example, the number of the peripheral transistors is multiple, and the multiple peripheral transistors may include NMOS transistors and PMOS transistors. A shallow trench isolation structure 720 is provided between adjacent peripheral transistors 710 to isolate the adjacent peripheral transistors 710.

[0134] The peripheral transistor 710 includes a first source-drain doped region 711, a channel region 712, and a second source-drain doped region 713, which are sequentially arranged in a direction parallel to the surface of the peripheral substrate. The peripheral gate 714 is arranged opposite to the channel region 712 via a peripheral gate dielectric layer. The second wafer 20 also includes a first source-drain plug 731, a second source-drain plug 732, and a peripheral gate plug 733, which are respectively in contact with the first source-drain doped region 711, the second source-drain doped region 713, and the peripheral gate 714, so as to control the peripheral transistor by applying an electrical signal to the peripheral transistor 710.

[0135] The second wafer also includes a peripheral interconnect structure 740, which is connected to the first source-drain plug 731, the second source-drain plug 732 and the peripheral gate plug 733, and a second pad 741 is provided on the side of the peripheral interconnect structure 740 away from the peripheral substrate 21, and the second pad 741 is bonded to the first pad 622 on the first wafer 10, thereby realizing the electrical connection between the peripheral circuit and the memory cell array, so that the peripheral circuit can control the memory cell array to access data.

[0136] For example, the peripheral interconnect structure 740 may include peripheral conductive vias and a peripheral metal interconnect layer, etc.

[0137] It should be understood that the second wafer 20 in any of the above semiconductor structures may be Fig.16 A second wafer 20 is shown.

[0138] The above embodiments of the present disclosure provide a variety of structures of three-dimensional ferroelectric memory. Compared with three-dimensional NAND memory, ferroelectric memory cells can be programmed at a lower voltage, so the spacing between gate layers along the Z direction can be reduced, so that the number of effective layers in a chip of the same thickness can be increased, thereby improving the storage density of the three-dimensional ferroelectric memory. In addition, the above-mentioned various solutions of adding the first dielectric layer, the second dielectric layer and / or the conductive layer, the solution of using an independent top selection gate layer, the solution of using a gate dielectric layer, and the solution of using a ferroelectric unit and a conductive unit can all increase the reliability of the three-dimensional ferroelectric memory and improve its performance.

[0139] The present disclosure also provides a method for manufacturing a semiconductor structure. Fig.17 Schematic diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. Fig.17 As shown, the method for manufacturing the semiconductor structure includes:

[0140] S110: forming a stacking structure on a substrate; wherein the stacking structure includes a third sublayer and first sublayers and second sublayers stacked alternately; the third sublayer is located on a side of the plurality of second sublayers away from the substrate, and the first sublayer is disposed between the third sublayer and the second sublayer;

[0141] S210: forming a channel hole penetrating the stacked structure and extending into the substrate;

[0142] S310: forming a functional material layer on the sidewall of the channel hole, and forming a channel layer on the surface of the functional material layer; wherein the functional material layer includes a ferroelectric material layer;

[0143] S410: removing at least part of the functional material layer between the third sub-layer and the channel layer to form a gap; wherein at least part of the functional material layer includes a ferroelectric material layer, and the remaining ferroelectric material layer forms a ferroelectric storage layer;

[0144] S510: depositing a dielectric material in the gap to form a gate dielectric layer between the third sub-layer and the channel layer.

[0145] Figures 18a to 18i A schematic diagram of a semiconductor structure in a manufacturing process provided by an embodiment of the present disclosure is shown below. Fig.17 , Figures 18a to 18i The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0146] like Fig.18a As shown, step S110 is performed to form a stacked structure 100 on the substrate 11, and the stacked structure 100 includes a first sublayer and a second sublayer alternately stacked, and a third sublayer located on the topmost first sublayer. In this embodiment, the first sublayer is an interlayer insulating layer 120, the second sublayer is a dummy gate layer 111, and the third sublayer is a dummy top selection gate layer 133.

[0147] The stacked structure 100 further includes an etch stop layer 140 located between the substrate 11 and the bottommost dummy gate layer 111 , and an interlayer insulating layer 120 is disposed between the substrate 11 and the bottommost dummy gate layer 111 .

[0148] In some embodiments, the material of the interlayer insulating layer 120 includes silicon oxide, and the materials of the dummy gate layer 111 and the dummy top selection gate layer include silicon nitride.

[0149] See also Fig.18b , perform step S210 to form a channel hole 20 that penetrates the stacked structure 100 and extends into the substrate 11. For example, the channel hole 20 may be formed by a dry etching process.

[0150] See also Fig.18c , perform step S310 to form a functional material layer 810 on the sidewall and bottom of the channel hole 20 , and form a channel layer 210 on the surface of the functional material layer 810 ; wherein the functional material layer 810 includes a ferroelectric material layer 811 .

[0151] like Fig.18cAs shown, in this embodiment, the functional material layer 810 only includes a ferroelectric material layer 811 , and the ferroelectric material layer 811 is located on the sidewall and the bottom of the channel hole 20 .

[0152] For example, before forming the ferroelectric material layer 811, a barrier layer 820 may be formed on the sidewalls and bottom of the channel hole 20, and the ferroelectric material layer 811 may be formed on the surface of the barrier layer 820. The barrier layer 820 can improve the surface characteristics of the channel hole 20, so that the surface of the channel hole 20 is composed of a single material, thereby improving the deposition quality of the ferroelectric material layer 811.

[0153] In some embodiments, the ferroelectric material layer 811 can be used as the ferroelectric storage layer 221, and the barrier layer 820 can be removed in a subsequent process, so that the functional layer 220 only includes the ferroelectric storage layer 221, forming a Figure 1 In another embodiment, the barrier layer 820 may not be provided, and a ferroelectric material may be directly deposited on the sidewall and bottom of the channel hole 20 to form a ferroelectric storage layer 221, so as to obtain Figure 1 A channel structure 200 is shown.

[0154] In some other embodiments, a first dielectric layer 222 may be formed on the sidewall and bottom of the channel hole 20, and a ferroelectric material layer may be formed on the surface of the first dielectric layer 222. The ferroelectric material layer may serve as the ferroelectric storage layer 221. Figure 7a The channel structure shown in FIG. 8 , wherein the first dielectric layer 222 can be used as a blocking layer 820 and is retained in subsequent processes.

[0155] In some other embodiments, after forming the ferroelectric material layer, a second dielectric layer 223 may be formed on the surface of the ferroelectric material layer, and a channel layer 210 may be formed on the surface of the second dielectric layer 223. Figure 7b In the channel structure, the second dielectric layer 223 is located between the ferroelectric storage layer 221 and the channel layer 210 .

[0156] In other embodiments, a first dielectric layer 222 may be formed on the sidewall and bottom of the channel hole 20, a ferroelectric material layer may be formed on the surface of the first dielectric layer, a second dielectric layer 223 may be formed on the surface of the ferroelectric material layer, and a channel layer 210 may be formed on the surface of the second dielectric layer, so as to form a Figure 7c The channel structure shown.

[0157] In some other embodiments, after forming the ferroelectric material layer, a conductive material layer may be formed on the surface of the ferroelectric material layer 811, a second dielectric layer 223 may be formed on the surface of the conductive material layer, and then a channel layer 210 may be formed on the surface of the second dielectric layer; wherein the conductive material layer may be used as the final conductive layer 224 to form a conductive layer such as Figure 8 The channel structure shown.

[0158] Continue to see Fig.18d , step S410 is performed to etch back the ferroelectric material layer until the top surface of the remaining ferroelectric material layer is lower than the bottom surface of the pseudo top selection gate layer 133, so as to form a gap 830 between the pseudo top selection gate layer 133 and the channel layer 210, and the remaining ferroelectric material layer forms a ferroelectric storage layer 221. For example, the ferroelectric material layer can be etched by a dry etching process or a wet etching process.

[0159] See also Fig.18e , step S510 is performed to fill the gap with dielectric material to form a gate dielectric layer 230 . The top surface of the gate dielectric layer 230 is flush with the top surface of the stacked structure 100 .

[0160] In some embodiments, when the functional material layer 810 includes the first dielectric layer 222, in the step of etching back the ferroelectric material layer 811, the first dielectric layer 222 may not be etched but remain intact. When the dielectric material is filled in the gap, the dielectric material forms a third dielectric layer 231. The gate dielectric layer 230 includes the third dielectric layer 231 and the first dielectric layer 222 extending between the pseudo top selection gate layer 133 and the channel layer 210, forming a gate dielectric layer 230 as shown in FIG. Fig.11 b shows the channel structure 200.

[0161] In other embodiments, when the functional material layer 810 includes the second dielectric layer 223, in the step of etching back the ferroelectric material layer 811, the second dielectric layer 223 may not be etched but completely retained. When the dielectric material is filled in the gap, the dielectric material forms a third dielectric layer 231. The gate dielectric layer 230 includes the third dielectric layer 231 and the second dielectric layer 223 extending between the pseudo top selection gate layer 133 and the channel layer 210, forming a gate dielectric layer 230 having a gate dielectric layer 231 and a gate dielectric layer 230 extending between the pseudo top selection gate layer 133 and the channel layer 210. Fig.11 c shows the channel structure 200.

[0162] In other embodiments, when the functional material layer 810 includes the first dielectric layer 222 and the second dielectric layer 223, in the step of etching back the ferroelectric material layer 811, the first dielectric layer 222 and the second dielectric layer 223 may not be etched and remain intact. When the dielectric material is filled in the gap, the dielectric material forms a third dielectric layer 231. The gate dielectric layer 230 includes the third dielectric layer 231 and the first dielectric layer 222 and the second dielectric layer 223 extending between the pseudo top selection gate layer 133 and the channel layer 210.

[0163] In other embodiments, when the functional material layer 810 includes a conductive material layer and a second dielectric layer 223, in step S410, the ferroelectric material layer and the conductive material layer are simultaneously etched back until the top surface of the remaining ferroelectric material layer and the conductive material layer are lower than the bottom surface of the pseudo top selection gate layer 133, so as to remove the ferroelectric material layer and the conductive material layer between the pseudo top selection gate layer 133 and the channel layer 210 to form a gap 830; then the gap is filled with dielectric material to form a third dielectric layer 231. The gate dielectric layer 230 includes a third dielectric layer 231 and a second dielectric layer 223; the remaining ferroelectric material layer and the conductive material layer respectively form a ferroelectric storage layer 221 and a conductive layer 224, forming a gap 830 as shown in FIG. Fig.12d A channel structure 200 is shown.

[0164] It should be understood that in other embodiments, no matter the functional material layer 810 further includes the first dielectric layer, the second dielectric layer and / or the conductive material layer, in step S410, the entire functional material layer 810 may be etched back until the top surface of the functional material layer 810 is lower than the bottom surface of the pseudo top selection gate layer 133 to form a gap 830; in step S510, the dielectric material is filled in the gap 830 to form a gate dielectric layer 230 composed of a single material. For example, in the case where the functional material layer 810 includes the first dielectric layer 222 and the second dielectric layer 223, the following may be formed: Fig.12a A channel structure 200 is shown.

[0165] In some embodiments, after step S510, the manufacturing method further includes:

[0166] See also Fig.18f , forming a gate line gap structure penetrating the stacked structure 100 and extending into the substrate 11, removing at least a portion of the dummy gate layer 111 and at least a portion of the dummy top selection gate layer 133 based on the gate line gap structure, until all outer side walls of the section of each channel structure 200 located in the dummy gate layer 111 and the dummy top selection gate layer 133 are exposed. Here, when a barrier layer 820 is formed on the outer surface of the channel structure 200, the barrier layer 820 needs to be further removed based on the gate line gap structure to expose all outer side walls of the section of the channel structure 200 located in the dummy gate layer 111.

[0167] Then, based on the gate line gap structure, the gate layer 110 is formed at the position where the dummy gate layer 111 is removed, and the top selection gate layer 130 is formed at the position where the dummy top selection gate layer is removed. By way of example, by way of example, a metal nitride may be first deposited at the position where the dummy gate layer 111 or the dummy top selection gate layer 133 is removed, and then a metal filling the first cavity between adjacent interlayer insulating layers 120 is formed on the surface of the metal nitride, so that the finally formed gate layer 110 and the top selection gate layer 130 include a metal layer and a metal nitride layer.

[0168] Finally, the gate line gap structure is filled to form a gate line isolation structure 500. For example, a gate line isolation layer 510 may be formed at the bottom and sidewalls of the gate line gap structure, and then a gate line contact layer 520 may be formed to fill the remaining space in the gate line gap structure. The gate line contact layer may be used to form an array common source.

[0169] It should be noted that, in some embodiments, the second sublayer may also be a gate layer 110. The material of the gate layer 110 includes polysilicon or doped polysilicon. In this way, the step of replacing the dummy gate layer 110 with the gate layer 110 can be omitted.

[0170] See also Figure 18g , a first gate contact plug 310 , conductive plugs (eg, a first conductive plug 420 , a second conductive plug 440 ) and a channel contact plug 490 are formed.

[0171] In some embodiments, the step of forming the first gate contact plug 310 includes:

[0172] An extraction hole is formed extending from the top surface of the stacked structure 100 to the top surface of a gate layer 110; a gap insulating material is deposited on the sidewalls and bottom of the extraction hole; the gap insulating material at the bottom of the extraction hole is removed, and the remaining gap insulating material located on the sidewalls of the extraction hole forms a second gap insulating layer; a wet etching process is used to laterally (in a direction parallel to the surface of the substrate 11) etch the pseudo gate layer 111 at the bottom of the through hole until the gate layer 110 is exposed to form a second cavity; and then a first gate contact plug 310 is formed in the remaining space in the extraction hole and the second cavity.

[0173] For example, a first gate contact plug is formed in the lead-out hole and the second cavity, including: depositing metal nitride on the surface of the lead-out hole and the second cavity, depositing metal on the surface of the metal nitride, and depositing filling material in the remaining space of the lead-out hole; etching back the filling material (or the filling material and the metal), and depositing metal at the position where the filling material (or the filling material and the metal) is removed to form a first gate contact plug 310.

[0174] In some embodiments, the first conductive plug 420 and the second conductive plug 440 are formed simultaneously. The steps of forming the conductive plugs (including the first conductive plug 420 and the second conductive plug 440) include:

[0175] A through hole extending from the top surface of the stacked structure 100 to the etch stop layer 140 is formed; a gap insulating material is deposited on the sidewall and bottom of the through hole; the gap insulating material at the bottom of the through hole is removed, and the remaining gap insulating material forms a fourth gap insulating layer; and a conductive plug is formed in the remaining space in the through hole. The step of forming the conductive plug in the through hole is the same as the step of forming the first gate contact plug in the lead-out hole and the second cavity, so it will not be repeated.

[0176] In some embodiments, the step of forming the channel contact plug 490 includes:

[0177] The stacked structure 100 is etched to form a contact hole exposing the top surface of the channel structure 200; a metal nitride layer is deposited in the contact hole, and a metal filling the contact hole is formed on the surface of the metal nitride layer to form a channel contact plug.

[0178] In some embodiments, the first gate lead-out plug, the conductive plug, and the channel contact plug are formed in different process steps.

[0179] See also Figure 18h , a back-end interconnect structure 610 and a first pad lead-out layer 620 are formed on the stack structure 100 ; the first pad lead-out layer 620 includes a first passivation layer 621 and a first pad 622 located in the first passivation layer 621 .

[0180] A second wafer 20 on which a peripheral circuit has been formed is provided, and the second wafer 20 includes a second pad 741 .

[0181] The first pad 622 and the second pad 741 are bonded to achieve electrical connection between the first wafer 10 and the second wafer 20. Then, the substrate 11 of the first wafer 10 in the bonded semiconductor structure is placed upward.

[0182] See also Fig.18i , forming a first interconnect structure 430. For example, a dry etching or wet etching process is used to sequentially remove the substrate 11 and an interlayer insulating layer 120 of the first wafer 10 until the etching stop layer 140 is exposed, remove the functional layer 220 in the channel structure 200 until the channel layer 210 is exposed, and remove the gate line isolation layer 510 of the gate line isolation structure 500 until the gate line contact layer 520 is exposed.

[0183] A first array common source layer 410 is formed to cover the etch stop layer 140, the exposed channel layer 210 and the polysilicon layer. Then, a first interlayer dielectric layer 431 is formed to cover the first array common source layer 410. After that, a first via hole is formed to penetrate the first interlayer dielectric layer 431 and expose the first array common source layer 410, and the first via hole is filled to form a first conductive via 432. A second via hole is formed to penetrate the first interlayer dielectric layer 431 and the first array common source layer 410 and expose the first conductive plug 420, and a first gap insulating layer is formed on the sidewall of the first via hole, and the remaining space of the first via hole is filled to form a second conductive via 433. Finally, a first interconnect layer 434 is formed to cover the first interlayer dielectric layer 431, the first conductive via 432 and the second conductive via 433. By way of example, a protective layer 450 may be formed on the surface of the first interconnect layer 434. Finally, a structure such as the one shown in FIG. 4 is formed. Figure 1 The semiconductor structure shown.

[0184] Figures 19a to 19d A schematic diagram of the structure of another semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure. Fig.19a In the embodiment, a stacked structure 100 is formed on a substrate 11, and a step of forming a channel hole 20 in the stacked structure 100 is similar to that in the embodiment of the present invention. Fig.18a and Fig.18b So I won’t go into details.

[0185] See also Fig.19b After forming the channel hole 20, the second sublayer (e.g., the dummy gate layer 110) and the third sublayer (e.g., the dummy top selection gate layer 131) are etched laterally along the channel hole 20, so that the sidewalls of the second sublayer and the third sublayer are laterally recessed relative to the sidewalls of the interlayer insulating layer 120 to form a groove 30;

[0186] See also Fig.19c , a barrier layer 820 or a first dielectric layer is formed in the groove 30 and located on the sidewalls of the second sub-layer and the third sub-layer.

[0187] For example, in this embodiment, the material of the dummy gate layer 111 includes silicon nitride, and a thermal oxidation process can be used to oxidize the sidewalls of the dummy gate layer 111 exposed in the groove to form a silicon oxide barrier layer 820 or a silicon oxide first dielectric layer.

[0188] In some other embodiments, a deposition process such as chemical vapor deposition may be used to deposit the barrier layer 820 or the first dielectric layer on all surfaces of the channel hole 20. Then, the barrier layer 820 or the first dielectric layer located on the sidewalls of the interlayer insulating layer 120 in the channel hole 20, the sidewalls of the substrate 11, and the bottom of the channel hole 20 is removed.

[0189] See also Fig.19d , a ferroelectric material layer is formed on the sidewalls and bottom of the channel hole 20; then the ferroelectric material layer located on the sidewalls of the interlayer insulating layer, the sidewalls of the substrate and the bottom of the channel hole is removed, and the remaining ferroelectric material layer located in the groove 30 forms a ferroelectric unit 2211.

[0190] For example, a dry etching process may be used to remove the ferroelectric material layer located on the sidewalls of the interlayer insulating layer, the sidewalls of the substrate and the bottom of the channel hole.

[0191] In some embodiments, the size of the groove 30 along the second direction can be controlled to match the size of the ferroelectric unit 2211 along the second direction so that the ferroelectric unit 2211 completely fills the groove 30, thereby obtaining Fig. 9 A channel structure 200 is shown.

[0192] In other embodiments, the size of the groove 30 along the second direction may be controlled to be larger than the size of the ferroelectric unit 2211 along the second direction, so that the ferroelectric unit 2211 does not fill the groove 30. In the case where the ferroelectric unit 2211 does not fill the groove, in one example, the ferroelectric material layer 811 in the groove may be completely retained by controlling the dry etching process to form Fig.10b The ferroelectric unit 2211 is shown as a "concave" shape. In this embodiment, the dry etching process can also be controlled so that the ferroelectric material layer 811 in the groove is partially etched to form Fig.10a The ferroelectric unit 2211 is shown.

[0193] See also Fig.19e , a conductive material layer is formed on the sidewall and bottom of the channel hole 20; then the conductive material layer located on the sidewall of the interlayer insulating layer 120, the sidewall of the substrate 11 and the bottom of the channel hole 20 is removed, and the remaining conductive material layer located in the groove forms a conductive unit 2241. For example, the conductive unit 2241 can fill the groove so that the sidewall of the conductive unit 2241 is flush with the sidewall of the interlayer insulating layer 120.

[0194] See also Fig.19f A second dielectric layer 223 is formed on the sidewall and bottom of the channel hole 20, a channel material layer 840 is formed on the surface of the second dielectric layer 223, and the channel material layer 840 is filled with a filling material to form a filling material layer 850. The channel material layer 840 can be used as Fig. 9 , Fig.10a and Fig.10b The channel layer 210 or Fig.14 and Fig.15b The first sub-channel layer 211 in the embodiment of the present invention.

[0195] See also Figure 19g , etching back the filling material layer 850 ; forming a conductive contact 250 at the position where the filling material layer is removed, and the remaining filling material layer forms a filling layer 240 .

[0196] See also Figure 19h Based on the gate gap structure, the dummy gate layer 111 , the dummy top selection gate layer 133 and the blocking layer 820 are removed to form a first cavity 860 .

[0197] See also Fig.19i , filling the first cavity 860 , forming the gate layer 110 and the top selection gate layer 130 .

[0198] The subsequent steps of the semiconductor structure provided in this embodiment can refer to the above Figure 18g to Figure 18i , so I will not go into details.

[0199] Fig. 20 A schematic diagram of a process flow of another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. Fig. 20 As shown, the manufacturing method includes:

[0200] S120: forming a first sub-stack structure on a substrate; wherein the first sub-stack structure comprises a first sub-layer and a second sub-layer alternately stacked; the first sub-layer is exposed on a front side of the first sub-stack structure, and the front side is away from the substrate;

[0201] S220: forming a first sub-channel structure in the first sub-stack structure; wherein the first sub-channel structure includes a first sub-channel layer penetrating the first sub-stack structure, a functional layer is provided between the first sub-channel layer and the second sub-layer, and the functional layer includes a ferroelectric storage layer;

[0202] S330: forming a second sub-stack structure on the first sub-stack structure; wherein the second sub-stack structure includes a top selection gate layer; and the first sub-stack structure and the second sub-stack structure form a stack structure;

[0203] S420: forming a second sub-channel structure in the second sub-stack structure; wherein the second sub-channel structure includes a second sub-channel layer penetrating the second sub-stack structure, the second sub-channel layer and the first sub-channel layer are electrically connected, and a gate dielectric layer is provided between the second sub-channel layer and the top selection gate; the first sub-channel layer and the second sub-channel layer form a channel layer.

[0204] Figures 21a to 21f A schematic diagram of the structure of another semiconductor structure in the process of preparation provided by the embodiment of the present disclosure. Fig. 20 , Figures 21a to 21f Another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is described in detail.

[0205] See also Fig.21a , step S120 is performed to form a first sub-stack structure 101 on the substrate 11, wherein the first sub-stack structure 101 includes a first sub-layer and a second sub-layer alternately stacked. In this embodiment, the first sub-layer is an interlayer insulating layer 120, and the second sub-layer is a dummy gate layer 111. The interlayer insulating layer 120 is exposed on the front side of the first sub-stack structure 101. The front side of the first sub-stack structure 101 is away from the substrate 11.

[0206] The first sub-stack structure 101 further includes a sacrificial layer 171 located between the substrate 11 and the bottommost dummy gate layer 111 , and an interlayer insulating layer 120 is provided between the substrate 11 and the bottommost dummy gate layer 111 .

[0207] See also Figure 21b, perform step S220 to form a first sub-channel structure 201 in the first sub-stacked structure 101. By way of example, forming the first sub-channel structure 201 may specifically include: forming a first sub-channel hole penetrating the first sub-stacked structure 101, forming a functional layer 220 on a sidewall of the first sub-channel hole, and forming a first sub-channel layer 211 on a surface of the functional layer 220; wherein the functional layer 220 includes a ferroelectric storage layer 221.

[0208] In some embodiments, the step of forming the functional layer 220 on the sidewall of the first channel hole can be the same as the above step S310, that is, forming the functional material layer 810 on the sidewall and bottom of the channel hole 20, and the functional material layer 810 serves as the functional layer 220. The functional layer 220 can also include any one of the four combinations of the first dielectric layer 222, the second dielectric layer 223, the first dielectric layer 222 and the second dielectric layer 223, and the conductive layer 224 and the second dielectric layer 223. No further description is given here.

[0209] In some other embodiments, the step of forming the functional layer 220 on the sidewall of the first sub-channel hole can also be the same as the above Figures 19a to 19g The steps shown form the separated ferroelectric unit 2211, or the separated ferroelectric unit 2211 and the conductive unit 2241, which will not be described in detail here. The steps of forming the connecting contact 214 are the same as the steps of forming the conductive contact 250, which will not be described in detail here.

[0210] See also Fig.21c , executing step S320 , forming a second sub-stack structure 102 on the first sub-stack structure 101 , and the first sub-stack structure 101 and the second sub-stack structure 102 form a stack structure 100 .

[0211] In some embodiments, the step of forming the second sub-stack structure 102 may specifically include:

[0212] forming a second buffer layer 180 on the first sub-stack structure 101;

[0213] forming a second dielectric cover layer 190 on the second buffer layer 180;

[0214] A polysilicon layer 131 and a metal silicide layer 132 are sequentially stacked in the second dielectric cover layer 190 , and the polysilicon layer 131 and the metal silicide layer 132 constitute a top selection gate layer 130 .

[0215] For example, the metal silicide layer 132 may be formed by depositing a metal on the polysilicon layer 131 and then performing an annealing process.

[0216] Continue to see Fig.21c, perform step S420 to form a second sub-channel structure 202 in the second sub-stack structure 102. For example, forming the second sub-channel structure 202 may specifically include: forming a second sub-channel hole that penetrates the second sub-stack structure 102 and exposes the connection contact 214 of the first sub-channel structure 201, forming a gate dielectric layer 230 on the sidewall of the second sub-channel hole, forming a second sub-channel layer 212 on the surface of the gate dielectric layer 230, and the second sub-channel layer 212 fills the second sub-channel hole. Here, the first sub-channel layer 211 and the second sub-channel layer 212 form a channel layer.

[0217] After forming the first sub-channel structure 201 and the second sub-channel structure 202 in step S420, see Fig.21d The stacked structure 100 (including the first sub-stacked structure 101 and the second sub-stacked structure 102) is etched to form a step region at the edge of the stacked structure 100. Each step in the step region includes a dummy gate layer 111 and an interlayer insulating layer 120 stacked in sequence.

[0218] In some embodiments, a first buffer layer 160 may be formed on the step region to cover a top surface and sidewalls of the step.

[0219] After forming the step region, a first dielectric cover layer 150 is formed to cover the step region, and the top surface of the first dielectric cover layer 150 is flush with the top surface of the core region. Then, a dummy channel structure 200' is formed that penetrates the stacked structure 100 and the first dielectric cover layer.

[0220] Continue to see Fig.21d , forming a gate line gap structure penetrating the stacked structure 100 and extending into the substrate 11, removing the sacrificial layer 171 based on the gate line gap structure, and removing the functional layer 220 located in the sacrificial layer 171 until the channel layer 210 is exposed. Then, through the gate line gap structure, a second array common source layer 170 is formed in the third cavity formed by removing the sacrificial layer and part of the functional layer 220. That is, the sacrificial layer 171 is replaced by the second array common source layer 170, so that the second array common source layer 170 is electrically connected through the side wall of the channel layer 210, and the second array common source layer 170 is in contact with the subsequently formed third conductive plug 460 and electrically connected to the third conductive plug 460.

[0221] In this embodiment, the second array common source layer 170 directly contacts the channel layer 210 from the sidewall of the channel layer 210, which can reduce the risk of bottom etching of the channel structure due to the increase in the number of layers, thereby facilitating the three-dimensional memory to increase the number of stacked layers to improve integration.

[0222] Continue to see Fig.21dBased on the gate line gap structure, all the dummy gate layers 111 are replaced with the gate layer 110 , and then the gate line gap structure is filled to form a gate line isolation structure 500 .

[0223] See also Fig.21e , a second gate contact plug 320 , conductive plugs (including a third conductive plug 460 and a fourth conductive plug 470 ) and a channel contact plug 490 are formed.

[0224] In some embodiments, the second gate contact plug 320, the conductive plug and the channel contact plug 490 are formed in the same process step. For example, a lead hole penetrating the dielectric layer and the interlayer insulating layer 120 and extending to the first gate layer 110 is formed on the step region, a through hole penetrating the dielectric layer and extending to the substrate 11 is formed, and a contact hole penetrating the dielectric layer and exposing the channel structure 200 is formed in the core region; the lead hole, the through hole and the channel contact hole are filled to form the second gate contact plug 320, the conductive plug and the channel contact plug 490.

[0225] Continue to see Fig.21e , forming a bit line (not shown in the figure) on the stacked structure, and a back-end interconnect structure 610 contacting the second gate contact plug 320, the third conductive plug 460, the fourth conductive plug 470 and the channel contact plug 490. The specific steps can be referred to above Figure 18g The corresponding steps are not described in detail.

[0226] See also Fig.21f , forming a first pad lead-out layer 620 on the first wafer 10, providing a second wafer 20, and bonding the first wafer and the second wafer. The specific steps can refer to the above Figure 18h The corresponding steps are not described in detail.

[0227] See also Figure 21g , a second interconnect structure 480 is formed on the first wafer 10. For example, a third via hole is formed that penetrates the substrate 11 of the first wafer and exposes the fourth conductive plug 470, a third gap insulating layer is formed on the sidewall of the third via hole, and then the third via hole is filled to form a third conductive via hole 482. Next, a second interconnect layer 481 is formed to cover a side of the substrate away from the stacking structure, and the second interconnect layer 481 is in contact with the third conductive via hole 482.

[0228] The three-dimensional memory prepared by the semiconductor structure manufacturing method provided in the embodiment of the present disclosure has high storage density and reliability.

[0229] The embodiments of the present disclosure further provide a memory, which includes: one or more semiconductor structures as described in any of the above embodiments.

[0230] The present disclosure also provides a memory system, the memory system comprising:

[0231] One or more memories according to any of the above embodiments;

[0232] The memory controller is coupled to the memory and configured to control the memory.

[0233] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A stacked structure, comprising a gate layer, an interlayer insulating layer and a top selection gate layer, wherein the gate layer and the interlayer insulating layer are alternately stacked along a first direction, the top selection gate layer is located on one side of the plurality of gate layers along the first direction, and the interlayer insulating layer is provided between the top selection gate layer and the gate layer; A channel structure comprises a channel layer, a functional layer and a gate dielectric layer; wherein the channel layer runs through the stacked structure, the gate dielectric layer is located between the channel layer and the top selection gate layer, the functional layer is located between the channel layer and the gate layer, and the functional layer comprises a ferroelectric storage layer.

2. The semiconductor structure according to claim 1, characterized in that: The size of the gate dielectric layer along the second direction is equal to the size of the functional layer along the second direction; and the second direction is perpendicular to the first direction.

3. The semiconductor structure according to claim 1, characterized in that: The stack structure includes a first sub-stack structure and a second sub-stack structure; the first sub-stack structure includes the gate layers and the interlayer insulating layers stacked alternately, and the second sub-stack structure includes the top selection gate layer; The channel structure includes a first sub-channel structure and a second sub-channel structure; Wherein, the first sub-channel structure comprises a first sub-channel layer penetrating the first sub-stacked structure, and the functional layer is provided between the first sub-channel layer and the gate layer; The second sub-channel structure includes a second sub-channel layer that penetrates the second sub-stack structure, the second sub-channel layer is electrically connected to the first sub-channel layer, and the gate dielectric layer is arranged between the second sub-channel layer and the top selection gate; wherein the size of the second sub-channel structure along the second direction is different from the size of the first sub-channel structure along the second direction; and the second direction is perpendicular to the first direction.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: A first dielectric layer is provided between the gate layer and the ferroelectric storage layer; and / or, A second dielectric layer is provided between the ferroelectric storage layer and the channel layer.

5. The semiconductor structure according to claim 4, characterized in that: The first dielectric layer is also located between the top selection gate layer and the channel layer; and / or, the second dielectric layer is also located between the top selection gate layer and the channel layer; The gate dielectric layer further includes: a third dielectric layer, the third dielectric layer is in contact with the ferroelectric storage layer, the dimension of the third dielectric layer along a second direction is equal to the dimension of the ferroelectric storage layer along the second direction, and the second direction is perpendicular to the first direction.

6. The semiconductor structure according to claim 1, characterized in that The ferroelectric memory layer penetrates the interlayer insulating layer between adjacent gate layers; or, The ferroelectric storage layer comprises a plurality of ferroelectric units spaced apart along the first direction, and the interlayer insulating layer is arranged between two adjacent ferroelectric units; each of the ferroelectric units is located between the channel layer and one of the gate layers.

7. The semiconductor structure according to claim 6, characterized in that: A second dielectric layer is provided between the ferroelectric storage layer and the channel layer; The functional layer further includes: a conductive layer located between the ferroelectric storage layer and the second dielectric layer.

8. The semiconductor structure according to claim 7, characterized in that: The conductive layer includes a plurality of conductive units spaced apart along the first direction; Wherein, the interlayer insulating layer is provided between two adjacent conductive units; and each conductive unit is located between the ferroelectric unit and the second dielectric layer.

9. The semiconductor structure according to claim 1, characterized in that: The material of the gate layer includes at least one of metal, metal nitride and silicon.

10. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a plurality of first gate contact plugs; Wherein, the first gate contact plug comprises a lead-out portion and a connecting portion, the connecting portion is located between adjacent interlayer insulating layers and contacts one of the gate layers; the lead-out portion contacts the connecting portion and extends along the first direction to be exposed on the front side of the stacked structure; the front side is close to the top selection gate layer; or, The first gate contact plug extends from the front side of the stack structure into the stack structure and contacts one of the gate layers. A plurality of the first gate contact plugs contact a plurality of the gate layers respectively.

11. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A first array common source layer is located at the back of the stack structure, and the back of the stack structure is far away from the top selection gate layer; the first array common source layer is in contact with the channel layer; A first conductive plug, penetrating the stack structure; A first interconnect structure comprises a first interlayer dielectric layer, a first conductive via, a second conductive via and a first interconnect layer; wherein the first interlayer dielectric layer covers the first array common source layer; The first conductive via penetrates the first interlayer dielectric layer and contacts the first array common source layer; The second conductive via penetrates the first interlayer dielectric layer and the first array common source layer and contacts the first conductive plug, and a gap insulating layer is provided between the second conductive via and the first array common source layer; The first interconnection layer covers the first interlayer dielectric layer and contacts the first conductive via and the second conductive via.

12. The semiconductor structure according to claim 11, characterized in that: The semiconductor structure further comprises: A second conductive plug penetrates the stack structure and an end of the second conductive plug contacts the first array common source layer.

13. The semiconductor structure according to claim 1, characterized in that The stacking structure further comprises: A second array common source layer, located at a side of the plurality of gate layers away from the top selection gate layer, the interlayer insulating layer being provided between the second array common source layer and the gate layer; wherein the second array common source layer passes through the functional layer and contacts the channel layer; The semiconductor structure further comprises: A substrate is located at the back side of the stack structure, and the back side is far away from the top selection gate layer; the channel structure extends into the substrate and is electrically isolated from the substrate; A third conductive plug extends from the front side of the stack structure to the second array common source layer and contacts the second array common source layer; the front side and the back side are arranged opposite to each other along the first direction.

14. A semiconductor structure, characterized in that: include: A stacked structure, comprising a gate layer, an interlayer insulating layer and a top selection gate layer, wherein the gate layer and the interlayer insulating layer are alternately stacked along a first direction, the top selection gate layer is located on one side of the plurality of gate layers along the first direction, and the interlayer insulating layer is provided between the top selection gate layer and the gate layer; A channel structure, comprising a channel layer and a functional layer, wherein the channel layer runs through the stacked structure, the functional layer is partially located between the channel layer and the top selection gate layer, and partially located between the channel layer and the gate layer; the functional layer comprises a ferroelectric storage layer; A first array common source layer is further provided on a side of the stack structure away from the top selection gate layer, and the first array common source layer is in contact with the channel layer; or a substrate is further provided on a side of the stack structure away from the top selection gate layer, and the channel structure extends into the substrate and is electrically isolated from the substrate, and the stack structure also includes a second array common source layer, which is located between the gate layer and the substrate, and passes through the functional layer and is in contact with the channel layer.

15. A memory, characterized in that: The memory comprises: a semiconductor structure as claimed in any one of claims 1 to 14.

16. A memory system, characterized in that: The memory system comprises: One or more memories as claimed in claim 15; A memory controller is coupled to the memory and configured to control the memory.

17. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: A stacking structure is formed on a substrate; wherein the stacking structure comprises a third sublayer and first and second sublayers alternately stacked; the third sublayer is located on a side of the plurality of second sublayers away from the substrate, and the first sublayer is disposed between the third sublayer and the second sublayer; forming a channel hole penetrating the stacked structure and extending into the substrate; forming a functional material layer on the sidewall of the channel hole, and forming a channel layer on the surface of the functional material layer; wherein the functional material layer comprises a ferroelectric material layer; Removing at least part of the functional material layer between the third sublayer and the channel layer to form a gap; wherein the at least part of the functional material layer includes the ferroelectric material layer, and the remaining ferroelectric material layer forms a ferroelectric storage layer; A dielectric material is deposited in the gap to form a gate dielectric layer between the third sub-layer and the channel layer.

18. The method for manufacturing a semiconductor structure according to claim 17, characterized in that: The functional material layer further includes: a first dielectric layer, and / or a second dielectric layer; The forming of the functional material layer comprises: The first dielectric layer is formed on the sidewall of the channel hole; the ferroelectric material layer is formed on the surface of the first dielectric layer; wherein the ferroelectric material layer is located between the first dielectric layer and the channel layer; and / or, The second dielectric layer is formed on the surface of the ferroelectric material layer; wherein the second dielectric layer is located between the ferroelectric material layer and the channel layer.

19. The method for manufacturing a semiconductor structure according to claim 17, characterized in that: The functional material layer further includes: a second dielectric layer and a conductive layer; The forming of the functional material layer comprises: forming the conductive material layer on the surface of the ferroelectric storage layer; forming a second dielectric layer on the surface of the conductive material layer; wherein the second dielectric layer is located between the conductive material layer and the channel layer; The removing at least part of the functional layer between the third sub-layer and the channel layer further includes: The conductive material layer between the third sub-layer and the channel layer is removed to form the gap; and the remaining conductive material layer forms a conductive layer.

20. The method for manufacturing a semiconductor structure according to claim 17, characterized in that: The first sub-layer is an interlayer insulating layer, the second sub-layer is a gate layer, and the third sub-layer is a top selection gate layer.

21. The method for manufacturing a semiconductor structure according to claim 17, characterized in that: The first sub-layer is an interlayer insulating layer, the second sub-layer is a dummy gate layer, the third sub-layer is a dummy top selection gate layer, and the manufacturing method further includes: forming a gate line gap structure penetrating the stacked structure; Based on the gate line gap structure, removing at least a portion of the dummy gate layer and at least a portion of the dummy top selection gate layer until the sidewall of the channel structure is exposed; forming a gate layer at a position where the dummy gate layer is removed, and forming a top selection gate layer at a position where the dummy top selection gate layer is removed; The gate line gap structure is filled to form a gate line isolation structure.

22. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: A first sub-stack structure is formed on a substrate; wherein the first sub-stack structure comprises a first sub-layer and a second sub-layer alternately stacked; the first sub-layer is exposed on a front side of the first sub-stack structure, and the front side is away from the substrate; forming a first sub-channel structure in the first sub-stack structure; wherein the first sub-channel structure comprises a first sub-channel layer penetrating the first sub-stack structure and extending into the substrate, a functional layer is provided between the first sub-channel layer and the second sub-layer, and the functional layer comprises a ferroelectric storage layer; forming a second sub-stack structure on the first sub-stack structure; wherein the second sub-stack structure comprises a top selection gate layer; and the first sub-stack structure and the second sub-stack structure form a stack structure; A second sub-channel structure is formed in the second sub-stack structure; wherein the second sub-channel structure includes a second sub-channel layer that penetrates the second sub-stack structure, the second sub-channel layer is electrically connected to the first sub-channel layer, and a gate dielectric layer is provided between the second sub-channel layer and the top selection gate layer; the first sub-channel layer and the second sub-channel layer form a channel layer.

23. The method for manufacturing a semiconductor structure according to claim 22, characterized in that: The forming of a first sub-channel structure in the first sub-stack structure includes: forming a first sub-channel hole penetrating the first sub-stack structure and extending into the substrate; Etching the second sub-layer along the lateral direction of the first sub-channel hole so that the sidewall of the second sub-layer is laterally recessed relative to the sidewall of the first sub-layer to form a groove; forming a ferroelectric material layer on the sidewalls and bottom of the first sub-channel hole; The ferroelectric material layer on the side wall of the first sub-layer in the first sub-channel hole is removed, and the remaining ferroelectric material layer in the groove forms a ferroelectric unit; wherein the functional layer includes the ferroelectric unit; A first channel layer is formed on the sidewalls and the bottom of the first sub-channel hole.

24. The method for manufacturing a semiconductor structure according to claim 23, characterized in that: The forming of a first sub-channel structure in the first sub-stack structure further includes: After forming the ferroelectric unit, forming a conductive material layer on the sidewalls and bottom of the first sub-channel hole; The conductive material layer on the side wall of the first sub-layer in the first sub-channel hole is removed, and the remaining conductive material layer in the groove forms a conductive unit; wherein the functional layer also includes the conductive unit; A second dielectric layer is formed on the sidewall of the channel hole; wherein the second dielectric layer is located between the conductive unit and the channel layer.

25. The method for manufacturing a semiconductor structure according to claim 22, characterized in that: The first sub-layer is an interlayer insulating layer, and the second sub-layer includes a gate layer.

26. The method for manufacturing a semiconductor structure according to claim 22, characterized in that: The first sub-layer includes an interlayer insulating layer, the second sub-layer includes a dummy gate layer, and the manufacturing method further includes: forming a gate line gap structure penetrating the first sub-stack structure and the second sub-stack structure; removing at least a portion of the dummy gate layer based on the gate line gap structure until the sidewall of the first sub-channel structure is exposed; forming a gate layer at a position where the dummy gate layer is removed; The gate line gap structure is filled to form a gate line isolation structure.

27. The method for manufacturing a semiconductor structure according to claim 20 or 25, characterized in that: The second sub-layer includes a gate layer, and the manufacturing method further includes: A plurality of first gate contact plugs are formed; wherein the first gate contact plugs extend from a surface of the stack structure away from the substrate into the stack structure and contact one of the second sub-layers; and the plurality of first gate contact plugs contact the plurality of second sub-layers respectively.

28. The method for manufacturing a semiconductor structure according to claim 21 or 26, characterized in that: The manufacturing method further comprises: A plurality of first gate contact plugs are formed; wherein the first gate contact plugs include a lead portion and a connecting portion, the connecting portion is located between adjacent first sub-layers and contacts one of the gate layers; the lead portion contacts the connecting portion and extends in a direction away from the substrate to a surface exposed on the stacked structure.

29. The method for manufacturing a semiconductor structure according to claim 17 or 22, characterized in that: The stacked structure further includes an etch stop layer located between the second sub-layer and the substrate; The manufacturing method further comprises: forming a first conductive plug in the stack structure; wherein the first conductive plug extends from a surface of the stack structure away from the substrate to the etch stop layer; removing the substrate and a portion of the stacked structure until the etch stop layer is exposed; removing part of the functional layer to expose the channel layer; forming a first array common source layer covering the etch stop layer and the channel layer; forming a first interlayer dielectric layer covering the first array common source layer; forming a first conductive via penetrating the first interlayer dielectric layer and contacting the first array common source layer; forming a second conductive via penetrating the first interlayer dielectric layer and the first array common source layer and contacting the first conductive plug; wherein a gap insulating layer is provided between the second conductive via and the first array common source layer; A first interconnection layer is formed covering the first interlayer dielectric layer and contacting the first conductive via and the second conductive via.

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